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Expand PMF_FN_* macros.
[netbsd-mini2440.git] / sys / dev / pci / trm.c
blob43e0474370a92a1052d7e30967203aa6ccce353d
1 /* $NetBSD: trm.c,v 1.29 2008/04/12 08:35:22 tsutsui Exp $ */
2 /*-
3 * Copyright (c) 2002 Izumi Tsutsui. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 */
25
26 /*
27 * Device Driver for Tekram DC395U/UW/F, DC315/U
28 * PCI SCSI Bus Master Host Adapter
29 * (SCSI chip set used Tekram ASIC TRM-S1040)
30 *
31 * Copyright (c) 2001 Rui-Xiang Guo
32 * All rights reserved.
33 *
34 * Redistribution and use in source and binary forms, with or without
35 * modification, are permitted provided that the following conditions
36 * are met:
37 * 1. Redistributions of source code must retain the above copyright
38 * notice, this list of conditions and the following disclaimer.
39 * 2. Redistributions in binary form must reproduce the above copyright
40 * notice, this list of conditions and the following disclaimer in the
41 * documentation and/or other materials provided with the distribution.
42 * 3. The name of the author may not be used to endorse or promote products
43 * derived from this software without specific prior written permission.
44 *
45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
46 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
47 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
48 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
49 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
50 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
51 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
52 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
53 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
54 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
55 */
56 /*
57 * Ported from
58 * dc395x_trm.c
59 *
60 * Written for NetBSD 1.4.x by
61 * Erich Chen (erich@tekram.com.tw)
62 *
63 * Provided by
64 * (C)Copyright 1995-1999 Tekram Technology Co., Ltd. All rights reserved.
65 */
66
67 #include <sys/cdefs.h>
68 __KERNEL_RCSID(0, "$NetBSD: trm.c,v 1.29 2008/04/12 08:35:22 tsutsui Exp $");
69
70 /* #define TRM_DEBUG */
71 #ifdef TRM_DEBUG
72 int trm_debug = 1;
73 #define DPRINTF(arg) if (trm_debug > 0) printf arg;
74 #else
75 #define DPRINTF(arg)
76 #endif
77
78 #include <sys/param.h>
79 #include <sys/systm.h>
80 #include <sys/malloc.h>
81 #include <sys/buf.h>
82 #include <sys/kernel.h>
83 #include <sys/device.h>
84 #include <sys/queue.h>
85
86 #include <sys/bus.h>
87 #include <sys/intr.h>
88
89 #include <uvm/uvm_extern.h>
90
91 #include <dev/scsipi/scsi_spc.h>
92 #include <dev/scsipi/scsi_all.h>
93 #include <dev/scsipi/scsi_message.h>
94 #include <dev/scsipi/scsipi_all.h>
95 #include <dev/scsipi/scsiconf.h>
96
97 #include <dev/pci/pcidevs.h>
98 #include <dev/pci/pcireg.h>
99 #include <dev/pci/pcivar.h>
100 #include <dev/pci/trmreg.h>
101
102 /*
103 * feature of chip set MAX value
104 */
105 #define TRM_MAX_TARGETS 16
106 #define TRM_MAX_LUNS 8
107 #define TRM_MAX_SG_ENTRIES (MAXPHYS / PAGE_SIZE + 1)
108 #define TRM_MAX_SRB 32 /* XXX */
109 #define TRM_MAX_TAG TRM_MAX_SRB /* XXX */
110 #define TRM_MAX_OFFSET 15
111 #define TRM_MAX_PERIOD 125
112
113 /*
114 * Segment Entry
115 */
116 struct trm_sg_entry {
117 uint32_t address;
118 uint32_t length;
119 };
120
121 #define TRM_SG_SIZE (sizeof(struct trm_sg_entry) * TRM_MAX_SG_ENTRIES)
122
123 /*
124 **********************************************************************
125 * The SEEPROM structure for TRM_S1040
126 **********************************************************************
127 */
128 struct nvram_target {
129 uint8_t config0; /* Target configuration byte 0 */
130 #define NTC_DO_WIDE_NEGO 0x20 /* Wide negotiate */
131 #define NTC_DO_TAG_QUEUING 0x10 /* Enable SCSI tagged queuing */
132 #define NTC_DO_SEND_START 0x08 /* Send start command SPINUP */
133 #define NTC_DO_DISCONNECT 0x04 /* Enable SCSI disconnect */
134 #define NTC_DO_SYNC_NEGO 0x02 /* Sync negotiation */
135 #define NTC_DO_PARITY_CHK 0x01 /* Parity check enable */
136 uint8_t period; /* Target period */
137 uint8_t config2; /* Target configuration byte 2 */
138 uint8_t config3; /* Target configuration byte 3 */
139 };
140
141 struct trm_nvram {
142 uint8_t subvendor_id[2]; /* 0,1 Sub Vendor ID */
143 uint8_t subsys_id[2]; /* 2,3 Sub System ID */
144 uint8_t subclass; /* 4 Sub Class */
145 uint8_t vendor_id[2]; /* 5,6 Vendor ID */
146 uint8_t device_id[2]; /* 7,8 Device ID */
147 uint8_t reserved0; /* 9 Reserved */
148 struct nvram_target target[TRM_MAX_TARGETS];
149 /* 10,11,12,13
150 * 14,15,16,17
151 * ....
152 * 70,71,72,73 */
153 uint8_t scsi_id; /* 74 Host Adapter SCSI ID */
154 uint8_t channel_cfg; /* 75 Channel configuration */
155 #define NAC_SCANLUN 0x20 /* Include LUN as BIOS device */
156 #define NAC_DO_PARITY_CHK 0x08 /* Parity check enable */
157 #define NAC_POWERON_SCSI_RESET 0x04 /* Power on reset enable */
158 #define NAC_GREATER_1G 0x02 /* > 1G support enable */
159 #define NAC_GT2DRIVES 0x01 /* Support more than 2 drives */
160 uint8_t delay_time; /* 76 Power on delay time */
161 uint8_t max_tag; /* 77 Maximum tags */
162 uint8_t reserved1; /* 78 */
163 uint8_t boot_target; /* 79 */
164 uint8_t boot_lun; /* 80 */
165 uint8_t reserved2; /* 81 */
166 uint8_t reserved3[44]; /* 82,..125 */
167 uint8_t checksum0; /* 126 */
168 uint8_t checksum1; /* 127 */
169 #define TRM_NVRAM_CKSUM 0x1234
170 };
171
172 /* Nvram Initiater bits definition */
173 #define MORE2_DRV 0x00000001
174 #define GREATER_1G 0x00000002
175 #define RST_SCSI_BUS 0x00000004
176 #define ACTIVE_NEGATION 0x00000008
177 #define NO_SEEK 0x00000010
178 #define LUN_CHECK 0x00000020
179
180 #define trm_eeprom_wait() DELAY(30)
181
182 /*
183 *-----------------------------------------------------------------------
184 * SCSI Request Block
185 *-----------------------------------------------------------------------
186 */
187 struct trm_srb {
188 TAILQ_ENTRY(trm_srb) next;
189
190 struct trm_sg_entry *sgentry;
191 struct scsipi_xfer *xs; /* scsipi_xfer for this cmd */
192 bus_dmamap_t dmap;
193 bus_size_t sgoffset; /* Xfer buf offset */
194
195 uint32_t buflen; /* Total xfer length */
196 uint32_t sgaddr; /* SGList physical starting address */
197
198 int sgcnt;
199 int sgindex;
200
201 int hastat; /* Host Adapter Status */
202 #define H_STATUS_GOOD 0x00
203 #define H_SEL_TIMEOUT 0x11
204 #define H_OVER_UNDER_RUN 0x12
205 #define H_UNEXP_BUS_FREE 0x13
206 #define H_TARGET_PHASE_F 0x14
207 #define H_INVALID_CCB_OP 0x16
208 #define H_LINK_CCB_BAD 0x17
209 #define H_BAD_TARGET_DIR 0x18
210 #define H_DUPLICATE_CCB 0x19
211 #define H_BAD_CCB_OR_SG 0x1A
212 #define H_ABORT 0xFF
213 int tastat; /* Target SCSI Status Byte */
214 int flag; /* SRBFlag */
215 #define AUTO_REQSENSE 0x0001
216 #define PARITY_ERROR 0x0002
217 #define SRB_TIMEOUT 0x0004
218
219 int cmdlen; /* SCSI command length */
220 uint8_t cmd[12]; /* SCSI command */
221
222 uint8_t tag[2];
223 };
224
225 /*
226 * some info about each target and lun on the SCSI bus
227 */
228 struct trm_linfo {
229 int used; /* number of slots in use */
230 int avail; /* where to start scanning */
231 int busy; /* lun in use */
232 struct trm_srb *untagged;
233 struct trm_srb *queued[TRM_MAX_TAG];
234 };
235
236 struct trm_tinfo {
237 u_int flag; /* Sync mode ? (1 sync):(0 async) */
238 #define SYNC_NEGO_ENABLE 0x0001
239 #define SYNC_NEGO_DOING 0x0002
240 #define SYNC_NEGO_DONE 0x0004
241 #define WIDE_NEGO_ENABLE 0x0008
242 #define WIDE_NEGO_DOING 0x0010
243 #define WIDE_NEGO_DONE 0x0020
244 #define USE_TAG_QUEUING 0x0040
245 #define NO_RESELECT 0x0080
246 struct trm_linfo *linfo[TRM_MAX_LUNS];
247
248 uint8_t config0; /* Target Config */
249 uint8_t period; /* Max Period for nego. */
250 uint8_t synctl; /* Sync control for reg. */
251 uint8_t offset; /* Sync offset for reg. and nego.(low nibble) */
252 };
253
254 /*
255 *-----------------------------------------------------------------------
256 * Adapter Control Block
257 *-----------------------------------------------------------------------
258 */
259 struct trm_softc {
260 device_t sc_dev;
261
262 bus_space_tag_t sc_iot;
263 bus_space_handle_t sc_ioh;
264 bus_dma_tag_t sc_dmat;
265 bus_dmamap_t sc_dmamap; /* Map the control structures */
266
267 struct trm_srb *sc_actsrb;
268 struct trm_tinfo sc_tinfo[TRM_MAX_TARGETS];
269
270 TAILQ_HEAD(, trm_srb) sc_freesrb,
271 sc_readysrb;
272 struct trm_srb *sc_srb; /* SRB array */
273
274 struct trm_sg_entry *sc_sglist;
275
276 int sc_maxid;
277 /*
278 * Link to the generic SCSI driver
279 */
280 struct scsipi_channel sc_channel;
281 struct scsipi_adapter sc_adapter;
282
283 int sc_id; /* Adapter SCSI Target ID */
284
285 int sc_state; /* SRB State */
286 #define TRM_IDLE 0
287 #define TRM_WAIT 1
288 #define TRM_READY 2
289 #define TRM_MSGOUT 3 /* arbitration+msg_out 1st byte */
290 #define TRM_MSGIN 4
291 #define TRM_EXTEND_MSGIN 5
292 #define TRM_COMMAND 6
293 #define TRM_START 7 /* arbitration+msg_out+command_out */
294 #define TRM_DISCONNECTED 8
295 #define TRM_DATA_XFER 9
296 #define TRM_XFERPAD 10
297 #define TRM_STATUS 11
298 #define TRM_COMPLETED 12
299 #define TRM_ABORT_SENT 13
300 #define TRM_UNEXPECT_RESEL 14
301
302 int sc_phase; /* SCSI phase */
303 int sc_config;
304 #define HCC_WIDE_CARD 0x01
305 #define HCC_SCSI_RESET 0x02
306 #define HCC_PARITY 0x04
307 #define HCC_AUTOTERM 0x08
308 #define HCC_LOW8TERM 0x10
309 #define HCC_UP8TERM 0x20
310
311 int sc_flag;
312 #define RESET_DEV 0x01
313 #define RESET_DETECT 0x02
314 #define RESET_DONE 0x04
315 #define WAIT_TAGMSG 0x08 /* XXX */
316
317 int sc_msgcnt;
318
319 int resel_target; /* XXX */
320 int resel_lun; /* XXX */
321
322 uint8_t *sc_msg;
323 uint8_t sc_msgbuf[6];
324 };
325
326 /*
327 * SCSI Status codes not defined in scsi_all.h
328 */
329 #define SCSI_COND_MET 0x04 /* Condition Met */
330 #define SCSI_INTERM_COND_MET 0x14 /* Intermediate condition met */
331 #define SCSI_UNEXP_BUS_FREE 0xFD /* Unexpected Bus Free */
332 #define SCSI_BUS_RST_DETECT 0xFE /* SCSI Bus Reset detected */
333 #define SCSI_SEL_TIMEOUT 0xFF /* Selection Timeout */
334
335 static int trm_match(device_t, cfdata_t, void *);
336 static void trm_attach(device_t, device_t, void *);
337
338 static int trm_init(struct trm_softc *);
339
340 static void trm_scsipi_request(struct scsipi_channel *, scsipi_adapter_req_t,
341 void *);
342 static void trm_update_xfer_mode(struct trm_softc *, int);
343 static void trm_sched(struct trm_softc *);
344 static int trm_select(struct trm_softc *, struct trm_srb *);
345 static void trm_reset(struct trm_softc *);
346 static void trm_timeout(void *);
347 static int trm_intr(void *);
348
349 static void trm_dataout_phase0(struct trm_softc *, int);
350 static void trm_datain_phase0(struct trm_softc *, int);
351 static void trm_status_phase0(struct trm_softc *);
352 static void trm_msgin_phase0(struct trm_softc *);
353 static void trm_command_phase1(struct trm_softc *);
354 static void trm_status_phase1(struct trm_softc *);
355 static void trm_msgout_phase1(struct trm_softc *);
356 static void trm_msgin_phase1(struct trm_softc *);
357
358 static void trm_dataio_xfer(struct trm_softc *, int);
359 static void trm_disconnect(struct trm_softc *);
360 static void trm_reselect(struct trm_softc *);
361 static void trm_done(struct trm_softc *, struct trm_srb *);
362 static int trm_request_sense(struct trm_softc *, struct trm_srb *);
363 static void trm_dequeue(struct trm_softc *, struct trm_srb *);
364
365 static void trm_scsi_reset_detect(struct trm_softc *);
366 static void trm_reset_scsi_bus(struct trm_softc *);
367
368 static void trm_check_eeprom(struct trm_softc *, struct trm_nvram *);
369 static void trm_eeprom_read_all(struct trm_softc *, struct trm_nvram *);
370 static void trm_eeprom_write_all(struct trm_softc *, struct trm_nvram *);
371 static void trm_eeprom_set_data(struct trm_softc *, uint8_t, uint8_t);
372 static void trm_eeprom_write_cmd(struct trm_softc *, uint8_t, uint8_t);
373 static uint8_t trm_eeprom_get_data(struct trm_softc *, uint8_t);
374
375 CFATTACH_DECL_NEW(trm, sizeof(struct trm_softc),
376 trm_match, trm_attach, NULL, NULL);
377
378 /* real period: */
379 static const uint8_t trm_clock_period[] = {
380 12, /* 48 ns 20.0 MB/sec */
381 18, /* 72 ns 13.3 MB/sec */
382 25, /* 100 ns 10.0 MB/sec */
383 31, /* 124 ns 8.0 MB/sec */
384 37, /* 148 ns 6.6 MB/sec */
385 43, /* 172 ns 5.7 MB/sec */
386 50, /* 200 ns 5.0 MB/sec */
387 62 /* 248 ns 4.0 MB/sec */
388 };
389 #define NPERIOD __arraycount(trm_clock_period)
390
391 static int
392 trm_match(device_t parent, cfdata_t cf, void *aux)
393 {
394 struct pci_attach_args *pa = aux;
395
396 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TEKRAM2)
397 switch (PCI_PRODUCT(pa->pa_id)) {
398 case PCI_PRODUCT_TEKRAM2_DC315:
399 return 1;
400 }
401 return 0;
402 }
403
404 /*
405 * attach and init a host adapter
406 */
407 static void
408 trm_attach(device_t parent, device_t self, void *aux)
409 {
410 struct trm_softc *sc = device_private(self);
411 struct pci_attach_args *const pa = aux;
412 bus_space_tag_t iot;
413 bus_space_handle_t ioh;
414 pci_intr_handle_t ih;
415 pcireg_t command;
416 const char *intrstr;
417
418 sc->sc_dev = self;
419
420 /*
421 * These cards do not allow memory mapped accesses
422 * pa_pc: chipset tag
423 * pa_tag: pci tag
424 */
425 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
426 if ((command & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) !=
427 (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) {
428 command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE;
429 pci_conf_write(pa->pa_pc, pa->pa_tag,
430 PCI_COMMAND_STATUS_REG, command);
431 }
432 /*
433 * mask for get correct base address of pci IO port
434 */
435 if (pci_mapreg_map(pa, PCI_MAPREG_START, PCI_MAPREG_TYPE_IO, 0,
436 &iot, &ioh, NULL, NULL)) {
437 aprint_error(": unable to map registers\n");
438 return;
439 }
440 /*
441 * test checksum of eeprom.. & initialize softc...
442 */
443 sc->sc_iot = iot;
444 sc->sc_ioh = ioh;
445 sc->sc_dmat = pa->pa_dmat;
446
447 if (trm_init(sc) != 0) {
448 /*
449 * Error during initialization!
450 */
451 return;
452 }
453 /*
454 * Now try to attach all the sub-devices
455 */
456 if ((sc->sc_config & HCC_WIDE_CARD) != 0)
457 aprint_normal(": Tekram DC395UW/F (TRM-S1040) Fast40 "
458 "Ultra Wide SCSI Adapter\n");
459 else
460 aprint_normal(": Tekram DC395U, DC315/U (TRM-S1040) Fast20 "
461 "Ultra SCSI Adapter\n");
462
463 /*
464 * Now tell the generic SCSI layer about our bus.
465 * map and establish interrupt
466 */
467 if (pci_intr_map(pa, &ih)) {
468 aprint_error_dev(self, "couldn't map interrupt\n");
469 return;
470 }
471 intrstr = pci_intr_string(pa->pa_pc, ih);
472
473 if (pci_intr_establish(pa->pa_pc, ih, IPL_BIO, trm_intr, sc) == NULL) {
474 aprint_error_dev(self, "couldn't establish interrupt");
475 if (intrstr != NULL)
476 aprint_error(" at %s", intrstr);
477 aprint_error("\n");
478 return;
479 }
480 if (intrstr != NULL)
481 aprint_normal_dev(self, "interrupting at %s\n", intrstr);
482
483 sc->sc_adapter.adapt_dev = self;
484 sc->sc_adapter.adapt_nchannels = 1;
485 sc->sc_adapter.adapt_openings = TRM_MAX_SRB;
486 sc->sc_adapter.adapt_max_periph = TRM_MAX_SRB;
487 sc->sc_adapter.adapt_request = trm_scsipi_request;
488 sc->sc_adapter.adapt_minphys = minphys;
489
490 sc->sc_channel.chan_adapter = &sc->sc_adapter;
491 sc->sc_channel.chan_bustype = &scsi_bustype;
492 sc->sc_channel.chan_channel = 0;
493 sc->sc_channel.chan_ntargets = sc->sc_maxid + 1;
494 sc->sc_channel.chan_nluns = 8;
495 sc->sc_channel.chan_id = sc->sc_id;
496
497 config_found(self, &sc->sc_channel, scsiprint);
498 }
499
500 /*
501 * initialize the internal structures for a given SCSI host
502 */
503 static int
504 trm_init(struct trm_softc *sc)
505 {
506 bus_space_tag_t iot = sc->sc_iot;
507 bus_space_handle_t ioh = sc->sc_ioh;
508 bus_dma_segment_t seg;
509 struct trm_nvram eeprom;
510 struct trm_srb *srb;
511 struct trm_tinfo *ti;
512 struct nvram_target *tconf;
513 int error, rseg, all_sgsize;
514 int i, target;
515 uint8_t bval;
516
517 DPRINTF(("\n"));
518
519 /*
520 * allocate the space for all SCSI control blocks (SRB) for DMA memory
521 */
522 all_sgsize = TRM_MAX_SRB * TRM_SG_SIZE;
523 if ((error = bus_dmamem_alloc(sc->sc_dmat, all_sgsize, PAGE_SIZE,
524 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
525 aprint_error(": unable to allocate SCSI REQUEST BLOCKS, "
526 "error = %d\n", error);
527 return 1;
528 }
529 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
530 all_sgsize, (void **) &sc->sc_sglist,
531 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
532 aprint_error(": unable to map SCSI REQUEST BLOCKS, "
533 "error = %d\n", error);
534 return 1;
535 }
536 if ((error = bus_dmamap_create(sc->sc_dmat, all_sgsize, 1,
537 all_sgsize, 0, BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) {
538 aprint_error(": unable to create SRB DMA maps, "
539 "error = %d\n", error);
540 return 1;
541 }
542 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap,
543 sc->sc_sglist, all_sgsize, NULL, BUS_DMA_NOWAIT)) != 0) {
544 aprint_error(": unable to load SRB DMA maps, "
545 "error = %d\n", error);
546 return 1;
547 }
548 DPRINTF(("all_sgsize=%x\n", all_sgsize));
549 memset(sc->sc_sglist, 0, all_sgsize);
550
551 /*
552 * EEPROM CHECKSUM
553 */
554 trm_check_eeprom(sc, &eeprom);
555
556 sc->sc_maxid = 7;
557 sc->sc_config = HCC_AUTOTERM | HCC_PARITY;
558 if (bus_space_read_1(iot, ioh, TRM_GEN_STATUS) & WIDESCSI) {
559 sc->sc_config |= HCC_WIDE_CARD;
560 sc->sc_maxid = 15;
561 }
562 if (eeprom.channel_cfg & NAC_POWERON_SCSI_RESET)
563 sc->sc_config |= HCC_SCSI_RESET;
564
565 sc->sc_actsrb = NULL;
566 sc->sc_id = eeprom.scsi_id;
567 sc->sc_flag = 0;
568
569 /*
570 * initialize and link all device's SRB queues of this adapter
571 */
572 TAILQ_INIT(&sc->sc_freesrb);
573 TAILQ_INIT(&sc->sc_readysrb);
574
575 sc->sc_srb = malloc(sizeof(struct trm_srb) * TRM_MAX_SRB,
576 M_DEVBUF, M_NOWAIT|M_ZERO);
577 DPRINTF(("all SRB size=%x\n", sizeof(struct trm_srb) * TRM_MAX_SRB));
578 if (sc->sc_srb == NULL) {
579 aprint_error(": can not allocate SRB\n");
580 return 1;
581 }
582
583 for (i = 0, srb = sc->sc_srb; i < TRM_MAX_SRB; i++) {
584 srb->sgentry = sc->sc_sglist + TRM_MAX_SG_ENTRIES * i;
585 srb->sgoffset = TRM_SG_SIZE * i;
586 srb->sgaddr = sc->sc_dmamap->dm_segs[0].ds_addr + srb->sgoffset;
587 /*
588 * map all SRB space to SRB_array
589 */
590 if (bus_dmamap_create(sc->sc_dmat,
591 MAXPHYS, TRM_MAX_SG_ENTRIES, MAXPHYS, 0,
592 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &srb->dmap)) {
593 aprint_error(": unable to create DMA transfer map.\n");
594 free(sc->sc_srb, M_DEVBUF);
595 return 1;
596 }
597 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next);
598 srb++;
599 }
600
601 /*
602 * initialize all target info structures
603 */
604 for (target = 0; target < TRM_MAX_TARGETS; target++) {
605 ti = &sc->sc_tinfo[target];
606 ti->synctl = 0;
607 ti->offset = 0;
608 tconf = &eeprom.target[target];
609 ti->config0 = tconf->config0;
610 ti->period = trm_clock_period[tconf->period & 0x07];
611 ti->flag = 0;
612 if ((ti->config0 & NTC_DO_DISCONNECT) != 0) {
613 #ifdef notyet
614 if ((ti->config0 & NTC_DO_TAG_QUEUING) != 0)
615 ti->flag |= USE_TAG_QUEUING;
616 #endif
617 } else
618 ti->flag |= NO_RESELECT;
619
620 DPRINTF(("target %d: config0 = 0x%02x, period = 0x%02x",
621 target, ti->config0, ti->period));
622 DPRINTF((", flag = 0x%02x\n", ti->flag));
623 }
624
625 /* program configuration 0 */
626 bval = PHASELATCH | INITIATOR | BLOCKRST;
627 if ((sc->sc_config & HCC_PARITY) != 0)
628 bval |= PARITYCHECK;
629 bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG0, bval);
630
631 /* program configuration 1 */
632 bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG1,
633 ACTIVE_NEG | ACTIVE_NEGPLUS);
634
635 /* 250ms selection timeout */
636 bus_space_write_1(iot, ioh, TRM_SCSI_TIMEOUT, SEL_TIMEOUT);
637
638 /* Mask all interrupts */
639 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0);
640 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0);
641
642 /* Reset SCSI module */
643 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTMODULE);
644
645 /* program Host ID */
646 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id);
647
648 /* set asynchronous transfer */
649 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, 0);
650
651 /* Turn LED control off */
652 bus_space_write_2(iot, ioh, TRM_GEN_CONTROL,
653 bus_space_read_2(iot, ioh, TRM_GEN_CONTROL) & ~EN_LED);
654
655 /* DMA config */
656 bus_space_write_2(iot, ioh, TRM_DMA_CONFIG,
657 bus_space_read_2(iot, ioh, TRM_DMA_CONFIG) | DMA_ENHANCE);
658
659 /* Clear pending interrupt status */
660 (void)bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS);
661
662 /* Enable SCSI interrupt */
663 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN,
664 EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED |
665 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE);
666 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR);
667
668 trm_reset(sc);
669
670 return 0;
671 }
672
673 /*
674 * enqueues a SCSI command
675 * called by the higher level SCSI driver
676 */
677 static void
678 trm_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req,
679 void *arg)
680 {
681 bus_space_tag_t iot;
682 bus_space_handle_t ioh;
683 struct trm_softc *sc;
684 struct trm_srb *srb;
685 struct scsipi_xfer *xs;
686 int error, i, target, lun, s;
687
688 sc = device_private(chan->chan_adapter->adapt_dev);
689 iot = sc->sc_iot;
690 ioh = sc->sc_ioh;
691
692 switch (req) {
693 case ADAPTER_REQ_RUN_XFER:
694 xs = arg;
695 target = xs->xs_periph->periph_target;
696 lun = xs->xs_periph->periph_lun;
697 DPRINTF(("trm_scsipi_request.....\n"));
698 DPRINTF(("target= %d lun= %d\n", target, lun));
699 if (xs->xs_control & XS_CTL_RESET) {
700 trm_reset(sc);
701 xs->error = XS_NOERROR | XS_RESET;
702 return;
703 }
704 if (xs->xs_status & XS_STS_DONE) {
705 printf("%s: Is it done?\n", device_xname(sc->sc_dev));
706 xs->xs_status &= ~XS_STS_DONE;
707 }
708
709 s = splbio();
710
711 /* Get SRB */
712 srb = TAILQ_FIRST(&sc->sc_freesrb);
713 if (srb != NULL) {
714 TAILQ_REMOVE(&sc->sc_freesrb, srb, next);
715 } else {
716 xs->error = XS_RESOURCE_SHORTAGE;
717 scsipi_done(xs);
718 splx(s);
719 return;
720 }
721
722 srb->xs = xs;
723 srb->cmdlen = xs->cmdlen;
724 memcpy(srb->cmd, xs->cmd, xs->cmdlen);
725
726 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) {
727 if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap,
728 xs->data, xs->datalen, NULL,
729 ((xs->xs_control & XS_CTL_NOSLEEP) ?
730 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) |
731 BUS_DMA_STREAMING |
732 ((xs->xs_control & XS_CTL_DATA_IN) ?
733 BUS_DMA_READ : BUS_DMA_WRITE))) != 0) {
734 printf("%s: DMA transfer map unable to load, "
735 "error = %d\n", device_xname(sc->sc_dev),
736 error);
737 xs->error = XS_DRIVER_STUFFUP;
738 /*
739 * free SRB
740 */
741 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next);
742 splx(s);
743 return;
744 }
745 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0,
746 srb->dmap->dm_mapsize,
747 (xs->xs_control & XS_CTL_DATA_IN) ?
748 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
749
750 /* Set up the scatter gather list */
751 for (i = 0; i < srb->dmap->dm_nsegs; i++) {
752 srb->sgentry[i].address =
753 htole32(srb->dmap->dm_segs[i].ds_addr);
754 srb->sgentry[i].length =
755 htole32(srb->dmap->dm_segs[i].ds_len);
756 }
757 srb->buflen = xs->datalen;
758 srb->sgcnt = srb->dmap->dm_nsegs;
759 } else {
760 srb->sgentry[0].address = 0;
761 srb->sgentry[0].length = 0;
762 srb->buflen = 0;
763 srb->sgcnt = 0;
764 }
765 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
766 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE);
767
768 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */
769
770 srb->sgindex = 0;
771 srb->hastat = 0;
772 srb->tastat = 0;
773 srb->flag = 0;
774
775 TAILQ_INSERT_TAIL(&sc->sc_readysrb, srb, next);
776 if (sc->sc_actsrb == NULL)
777 trm_sched(sc);
778 splx(s);
779
780 if ((xs->xs_control & XS_CTL_POLL) != 0) {
781 int timeout = xs->timeout;
782
783 s = splbio();
784 do {
785 while (--timeout) {
786 DELAY(1000);
787 if (bus_space_read_2(iot, ioh,
788 TRM_SCSI_STATUS) & SCSIINTERRUPT)
789 break;
790 }
791 if (timeout == 0) {
792 trm_timeout(srb);
793 break;
794 } else
795 trm_intr(sc);
796 } while ((xs->xs_status & XS_STS_DONE) == 0);
797 splx(s);
798 }
799 return;
800
801 case ADAPTER_REQ_GROW_RESOURCES:
802 /* XXX Not supported. */
803 return;
804
805 case ADAPTER_REQ_SET_XFER_MODE:
806 {
807 struct trm_tinfo *ti;
808 struct scsipi_xfer_mode *xm;
809
810 xm = arg;
811 ti = &sc->sc_tinfo[xm->xm_target];
812 ti->flag &= ~(SYNC_NEGO_ENABLE|WIDE_NEGO_ENABLE);
813
814 #ifdef notyet
815 if ((xm->xm_mode & PERIPH_CAP_TQING) != 0)
816 ti->flag |= USE_TAG_QUEUING;
817 else
818 #endif
819 ti->flag &= ~USE_TAG_QUEUING;
820
821 if ((xm->xm_mode & PERIPH_CAP_WIDE16) != 0 &&
822 (sc->sc_config & HCC_WIDE_CARD) != 0 &&
823 (ti->config0 & NTC_DO_WIDE_NEGO) != 0) {
824 ti->flag |= WIDE_NEGO_ENABLE;
825 ti->flag &= ~WIDE_NEGO_DONE;
826 }
827
828 if ((xm->xm_mode & PERIPH_CAP_SYNC) != 0 &&
829 (ti->config0 & NTC_DO_SYNC_NEGO) != 0) {
830 ti->flag |= SYNC_NEGO_ENABLE;
831 ti->flag &= ~SYNC_NEGO_DONE;
832 ti->period = trm_clock_period[0];
833 }
834
835 /*
836 * If we're not going to negotiate, send the
837 * notification now, since it won't happen later.
838 */
839 if ((ti->flag & (WIDE_NEGO_DONE|SYNC_NEGO_DONE)) ==
840 (WIDE_NEGO_DONE|SYNC_NEGO_DONE))
841 trm_update_xfer_mode(sc, xm->xm_target);
842
843 return;
844 }
845 }
846 }
847
848 static void
849 trm_update_xfer_mode(struct trm_softc *sc, int target)
850 {
851 struct scsipi_xfer_mode xm;
852 struct trm_tinfo *ti;
853
854 ti = &sc->sc_tinfo[target];
855 xm.xm_target = target;
856 xm.xm_mode = 0;
857 xm.xm_period = 0;
858 xm.xm_offset = 0;
859
860 if ((ti->synctl & WIDE_SYNC) != 0)
861 xm.xm_mode |= PERIPH_CAP_WIDE16;
862
863 if (ti->period > 0) {
864 xm.xm_mode |= PERIPH_CAP_SYNC;
865 xm.xm_period = ti->period;
866 xm.xm_offset = ti->offset;
867 }
868
869 #ifdef notyet
870 if ((ti->flag & USE_TAG_QUEUING) != 0)
871 xm.xm_mode |= PERIPH_CAP_TQING;
872 #endif
873
874 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm);
875 }
876
877 static void
878 trm_sched(struct trm_softc *sc)
879 {
880 struct trm_srb *srb;
881 struct scsipi_periph *periph;
882 struct trm_tinfo *ti;
883 struct trm_linfo *li;
884 int s, lun, tag;
885
886 DPRINTF(("trm_sched...\n"));
887
888 TAILQ_FOREACH(srb, &sc->sc_readysrb, next) {
889 periph = srb->xs->xs_periph;
890 ti = &sc->sc_tinfo[periph->periph_target];
891 lun = periph->periph_lun;
892
893 /* select type of tag for this command */
894 if ((ti->flag & NO_RESELECT) != 0 ||
895 (ti->flag & USE_TAG_QUEUING) == 0 ||
896 (srb->flag & AUTO_REQSENSE) != 0 ||
897 (srb->xs->xs_control & XS_CTL_REQSENSE) != 0)
898 tag = 0;
899 else
900 tag = srb->xs->xs_tag_type;
901 #if 0
902 /* XXX use tags for polled commands? */
903 if (srb->xs->xs_control & XS_CTL_POLL)
904 tag = 0;
905 #endif
906
907 s = splbio();
908 li = ti->linfo[lun];
909 if (li == NULL) {
910 /* initialize lun info */
911 if ((li = malloc(sizeof(*li), M_DEVBUF,
912 M_NOWAIT|M_ZERO)) == NULL) {
913 splx(s);
914 continue;
915 }
916 ti->linfo[lun] = li;
917 }
918
919 if (tag == 0) {
920 /* try to issue this srb as an un-tagged command */
921 if (li->untagged == NULL)
922 li->untagged = srb;
923 }
924 if (li->untagged != NULL) {
925 tag = 0;
926 if (li->busy != 1 && li->used == 0) {
927 /* we need to issue the untagged command now */
928 srb = li->untagged;
929 periph = srb->xs->xs_periph;
930 } else {
931 /* not ready yet */
932 splx(s);
933 continue;
934 }
935 }
936 srb->tag[0] = tag;
937 if (tag != 0) {
938 li->queued[srb->xs->xs_tag_id] = srb;
939 srb->tag[1] = srb->xs->xs_tag_id;
940 li->used++;
941 }
942
943 if (li->untagged != NULL && li->busy != 1) {
944 li->busy = 1;
945 TAILQ_REMOVE(&sc->sc_readysrb, srb, next);
946 sc->sc_actsrb = srb;
947 trm_select(sc, srb);
948 splx(s);
949 break;
950 }
951 if (li->untagged == NULL && tag != 0) {
952 TAILQ_REMOVE(&sc->sc_readysrb, srb, next);
953 sc->sc_actsrb = srb;
954 trm_select(sc, srb);
955 splx(s);
956 break;
957 } else
958 splx(s);
959 }
960 }
961
962 static int
963 trm_select(struct trm_softc *sc, struct trm_srb *srb)
964 {
965 bus_space_tag_t iot = sc->sc_iot;
966 bus_space_handle_t ioh = sc->sc_ioh;
967 struct scsipi_periph *periph = srb->xs->xs_periph;
968 int target = periph->periph_target;
969 int lun = periph->periph_lun;
970 struct trm_tinfo *ti = &sc->sc_tinfo[target];
971 uint8_t scsicmd;
972
973 DPRINTF(("trm_select.....\n"));
974
975 if ((srb->xs->xs_control & XS_CTL_POLL) == 0) {
976 callout_reset(&srb->xs->xs_callout, mstohz(srb->xs->timeout),
977 trm_timeout, srb);
978 }
979
980 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id);
981 bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, target);
982 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, ti->synctl);
983 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, ti->offset);
984 /* Flush FIFO */
985 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO);
986 DELAY(10);
987
988 sc->sc_phase = PH_BUS_FREE; /* initial phase */
989
990 DPRINTF(("cmd = 0x%02x\n", srb->cmd[0]));
991
992 if (((ti->flag & WIDE_NEGO_ENABLE) &&
993 (ti->flag & WIDE_NEGO_DONE) == 0) ||
994 ((ti->flag & SYNC_NEGO_ENABLE) &&
995 (ti->flag & SYNC_NEGO_DONE) == 0)) {
996 sc->sc_state = TRM_MSGOUT;
997 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO,
998 MSG_IDENTIFY(lun, 0));
999 bus_space_write_multi_1(iot, ioh,
1000 TRM_SCSI_FIFO, srb->cmd, srb->cmdlen);
1001 /* it's important for atn stop */
1002 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL,
1003 DO_DATALATCH | DO_HWRESELECT);
1004 /* SCSI command */
1005 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_SEL_ATNSTOP);
1006 DPRINTF(("select with SEL_ATNSTOP\n"));
1007 return 0;
1008 }
1009
1010 if (srb->tag[0] != 0) {
1011 /* Send identify message */
1012 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO,
1013 MSG_IDENTIFY(lun, 1));
1014 /* Send Tag id */
1015 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, srb->tag[0]);
1016 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, srb->tag[1]);
1017 scsicmd = SCMD_SEL_ATN3;
1018 DPRINTF(("select with SEL_ATN3\n"));
1019 } else {
1020 /* Send identify message */
1021 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO,
1022 MSG_IDENTIFY(lun,
1023 (ti->flag & NO_RESELECT) == 0 &&
1024 (srb->flag & AUTO_REQSENSE) == 0 &&
1025 (srb->xs->xs_control & XS_CTL_REQSENSE) == 0));
1026 scsicmd = SCMD_SEL_ATN;
1027 DPRINTF(("select with SEL_ATN\n"));
1028 }
1029 sc->sc_state = TRM_START;
1030
1031 /*
1032 * Send CDB ..command block...
1033 */
1034 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, srb->cmd, srb->cmdlen);
1035
1036 /*
1037 * If trm_select returns 0: current interrupt status
1038 * is interrupt enable. It's said that SCSI processor is
1039 * unoccupied.
1040 */
1041 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */
1042 /* SCSI command */
1043 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, scsicmd);
1044 return 0;
1045 }
1046
1047 /*
1048 * perform a hard reset on the SCSI bus (and TRM_S1040 chip).
1049 */
1050 static void
1051 trm_reset(struct trm_softc *sc)
1052 {
1053 bus_space_tag_t iot = sc->sc_iot;
1054 bus_space_handle_t ioh = sc->sc_ioh;
1055 int s;
1056
1057 DPRINTF(("trm_reset.........\n"));
1058
1059 s = splbio();
1060
1061 /* disable SCSI and DMA interrupt */
1062 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0);
1063 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0);
1064
1065 trm_reset_scsi_bus(sc);
1066 DELAY(100000);
1067
1068 /* Enable SCSI interrupt */
1069 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN,
1070 EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED |
1071 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE);
1072
1073 /* Enable DMA interrupt */
1074 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR);
1075
1076 /* Clear DMA FIFO */
1077 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO);
1078
1079 /* Clear SCSI FIFO */
1080 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO);
1081
1082 sc->sc_actsrb = NULL;
1083 sc->sc_flag = 0; /* RESET_DETECT, RESET_DONE, RESET_DEV */
1084
1085 splx(s);
1086 }
1087
1088 static void
1089 trm_timeout(void *arg)
1090 {
1091 struct trm_srb *srb = (struct trm_srb *)arg;
1092 struct scsipi_xfer *xs;
1093 struct scsipi_periph *periph;
1094 struct trm_softc *sc;
1095 int s;
1096
1097 if (srb == NULL) {
1098 printf("trm_timeout called with srb == NULL\n");
1099 return;
1100 }
1101
1102 xs = srb->xs;
1103 if (xs == NULL) {
1104 printf("trm_timeout called with xs == NULL\n");
1105 return;
1106 }
1107
1108 periph = xs->xs_periph;
1109 scsipi_printaddr(xs->xs_periph);
1110 printf("SCSI OpCode 0x%02x timed out\n", xs->cmd->opcode);
1111
1112 sc = device_private(periph->periph_channel->chan_adapter->adapt_dev);
1113
1114 trm_reset_scsi_bus(sc);
1115 s = splbio();
1116 srb->flag |= SRB_TIMEOUT;
1117 trm_done(sc, srb);
1118 /* XXX needs more.. */
1119 splx(s);
1120 }
1121
1122 /*
1123 * Catch an interrupt from the adapter
1124 * Process pending device interrupts.
1125 */
1126 static int
1127 trm_intr(void *arg)
1128 {
1129 bus_space_tag_t iot;
1130 bus_space_handle_t ioh;
1131 struct trm_softc *sc;
1132 int intstat, stat;
1133
1134 DPRINTF(("trm_intr......\n"));
1135 sc = arg;
1136 if (sc == NULL)
1137 return 0;
1138
1139 iot = sc->sc_iot;
1140 ioh = sc->sc_ioh;
1141
1142 stat = bus_space_read_2(iot, ioh, TRM_SCSI_STATUS);
1143 if ((stat & SCSIINTERRUPT) == 0)
1144 return 0;
1145
1146 DPRINTF(("stat = %04x, ", stat));
1147 intstat = bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS);
1148
1149 DPRINTF(("intstat=%02x, ", intstat));
1150 if (intstat & (INT_SELTIMEOUT | INT_DISCONNECT)) {
1151 DPRINTF(("\n"));
1152 trm_disconnect(sc);
1153 return 1;
1154 }
1155 if (intstat & INT_RESELECTED) {
1156 DPRINTF(("\n"));
1157 trm_reselect(sc);
1158 return 1;
1159 }
1160 if (intstat & INT_SCSIRESET) {
1161 DPRINTF(("\n"));
1162 trm_scsi_reset_detect(sc);
1163 return 1;
1164 }
1165 if (intstat & (INT_BUSSERVICE | INT_CMDDONE)) {
1166 DPRINTF(("sc->sc_phase = %2d, sc->sc_state = %2d\n",
1167 sc->sc_phase, sc->sc_state));
1168 /*
1169 * software sequential machine
1170 */
1171
1172 /*
1173 * call phase0 functions... "phase entry" handle
1174 * every phase before start transfer
1175 */
1176 switch (sc->sc_phase) {
1177 case PH_DATA_OUT:
1178 trm_dataout_phase0(sc, stat);
1179 break;
1180 case PH_DATA_IN:
1181 trm_datain_phase0(sc, stat);
1182 break;
1183 case PH_COMMAND:
1184 break;
1185 case PH_STATUS:
1186 trm_status_phase0(sc);
1187 stat = PH_BUS_FREE;
1188 break;
1189 case PH_MSG_OUT:
1190 if (sc->sc_state == TRM_UNEXPECT_RESEL ||
1191 sc->sc_state == TRM_ABORT_SENT)
1192 stat = PH_BUS_FREE;
1193 break;
1194 case PH_MSG_IN:
1195 trm_msgin_phase0(sc);
1196 stat = PH_BUS_FREE;
1197 break;
1198 case PH_BUS_FREE:
1199 break;
1200 default:
1201 printf("%s: unexpected phase in trm_intr() phase0\n",
1202 device_xname(sc->sc_dev));
1203 break;
1204 }
1205
1206 sc->sc_phase = stat & PHASEMASK;
1207
1208 switch (sc->sc_phase) {
1209 case PH_DATA_OUT:
1210 trm_dataio_xfer(sc, XFERDATAOUT);
1211 break;
1212 case PH_DATA_IN:
1213 trm_dataio_xfer(sc, XFERDATAIN);
1214 break;
1215 case PH_COMMAND:
1216 trm_command_phase1(sc);
1217 break;
1218 case PH_STATUS:
1219 trm_status_phase1(sc);
1220 break;
1221 case PH_MSG_OUT:
1222 trm_msgout_phase1(sc);
1223 break;
1224 case PH_MSG_IN:
1225 trm_msgin_phase1(sc);
1226 break;
1227 case PH_BUS_FREE:
1228 break;
1229 default:
1230 printf("%s: unexpected phase in trm_intr() phase1\n",
1231 device_xname(sc->sc_dev));
1232 break;
1233 }
1234
1235 return 1;
1236 }
1237 return 0;
1238 }
1239
1240 static void
1241 trm_msgout_phase1(struct trm_softc *sc)
1242 {
1243 bus_space_tag_t iot = sc->sc_iot;
1244 bus_space_handle_t ioh = sc->sc_ioh;
1245 struct trm_srb *srb;
1246 struct scsipi_periph *periph;
1247 struct trm_tinfo *ti;
1248
1249 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO);
1250
1251 srb = sc->sc_actsrb;
1252
1253 /* message out phase */
1254 if (srb != NULL) {
1255 periph = srb->xs->xs_periph;
1256 ti = &sc->sc_tinfo[periph->periph_target];
1257
1258 if ((ti->flag & WIDE_NEGO_DOING) == 0 &&
1259 (ti->flag & WIDE_NEGO_ENABLE)) {
1260 /* send WDTR */
1261 ti->flag &= ~SYNC_NEGO_DONE;
1262
1263 sc->sc_msgbuf[0] = MSG_IDENTIFY(periph->periph_lun, 0);
1264 sc->sc_msgbuf[1] = MSG_EXTENDED;
1265 sc->sc_msgbuf[2] = MSG_EXT_WDTR_LEN;
1266 sc->sc_msgbuf[3] = MSG_EXT_WDTR;
1267 sc->sc_msgbuf[4] = MSG_EXT_WDTR_BUS_16_BIT;
1268 sc->sc_msgcnt = 5;
1269
1270 ti->flag |= WIDE_NEGO_DOING;
1271 } else if ((ti->flag & SYNC_NEGO_DOING) == 0 &&
1272 (ti->flag & SYNC_NEGO_ENABLE)) {
1273 /* send SDTR */
1274 int cnt = 0;
1275
1276 if ((ti->flag & WIDE_NEGO_DONE) == 0)
1277 sc->sc_msgbuf[cnt++] =
1278 MSG_IDENTIFY(periph->periph_lun, 0);
1279
1280 sc->sc_msgbuf[cnt++] = MSG_EXTENDED;
1281 sc->sc_msgbuf[cnt++] = MSG_EXT_SDTR_LEN;
1282 sc->sc_msgbuf[cnt++] = MSG_EXT_SDTR;
1283 sc->sc_msgbuf[cnt++] = ti->period;
1284 sc->sc_msgbuf[cnt++] = TRM_MAX_OFFSET;
1285 sc->sc_msgcnt = cnt;
1286 ti->flag |= SYNC_NEGO_DOING;
1287 }
1288 }
1289 if (sc->sc_msgcnt == 0) {
1290 sc->sc_msgbuf[0] = MSG_ABORT;
1291 sc->sc_msgcnt = 1;
1292 sc->sc_state = TRM_ABORT_SENT;
1293 }
1294
1295 DPRINTF(("msgout: cnt = %d, ", sc->sc_msgcnt));
1296 DPRINTF(("msgbuf = %02x %02x %02x %02x %02x %02x\n",
1297 sc->sc_msgbuf[0], sc->sc_msgbuf[1], sc->sc_msgbuf[2],
1298 sc->sc_msgbuf[3], sc->sc_msgbuf[4], sc->sc_msgbuf[5]));
1299
1300 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO,
1301 sc->sc_msgbuf, sc->sc_msgcnt);
1302 sc->sc_msgcnt = 0;
1303 memset(sc->sc_msgbuf, 0, sizeof(sc->sc_msgbuf));
1304
1305 /* it's important for atn stop */
1306 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH);
1307
1308 /*
1309 * SCSI command
1310 */
1311 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT);
1312 }
1313
1314 static void
1315 trm_command_phase1(struct trm_softc *sc)
1316 {
1317 bus_space_tag_t iot = sc->sc_iot;
1318 bus_space_handle_t ioh = sc->sc_ioh;
1319 struct trm_srb *srb;
1320
1321 srb = sc->sc_actsrb;
1322 if (srb == NULL) {
1323 DPRINTF(("trm_command_phase1: no active srb\n"));
1324 return;
1325 }
1326
1327 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRATN | DO_CLRFIFO);
1328 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, srb->cmd, srb->cmdlen);
1329
1330 sc->sc_state = TRM_COMMAND;
1331 /* it's important for atn stop */
1332 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH);
1333
1334 /*
1335 * SCSI command
1336 */
1337 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT);
1338 }
1339
1340 static void
1341 trm_dataout_phase0(struct trm_softc *sc, int stat)
1342 {
1343 bus_space_tag_t iot = sc->sc_iot;
1344 bus_space_handle_t ioh = sc->sc_ioh;
1345 struct trm_srb *srb;
1346 struct scsipi_periph *periph;
1347 struct trm_tinfo *ti;
1348 struct trm_sg_entry *sg;
1349 int sgindex;
1350 uint32_t xferlen, leftcnt = 0;
1351
1352 if (sc->sc_state == TRM_XFERPAD)
1353 return;
1354
1355 srb = sc->sc_actsrb;
1356 if (srb == NULL) {
1357 DPRINTF(("trm_dataout_phase0: no active srb\n"));
1358 return;
1359 }
1360 periph = srb->xs->xs_periph;
1361 ti = &sc->sc_tinfo[periph->periph_target];
1362
1363 if ((stat & PARITYERROR) != 0)
1364 srb->flag |= PARITY_ERROR;
1365
1366 if ((stat & SCSIXFERDONE) == 0) {
1367 /*
1368 * when data transfer from DMA FIFO to SCSI FIFO
1369 * if there was some data left in SCSI FIFO
1370 */
1371 leftcnt = bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) &
1372 SCSI_FIFOCNT_MASK;
1373 if (ti->synctl & WIDE_SYNC)
1374 /*
1375 * if WIDE scsi SCSI FIFOCNT unit is word
1376 * so need to * 2
1377 */
1378 leftcnt <<= 1;
1379 }
1380 /*
1381 * calculate all the residue data that was not yet transferred
1382 * SCSI transfer counter + left in SCSI FIFO data
1383 *
1384 * .....TRM_SCSI_XCNT (24bits)
1385 * The counter always decrements by one for every SCSI
1386 * byte transfer.
1387 * .....TRM_SCSI_FIFOCNT ( 5bits)
1388 * The counter is SCSI FIFO offset counter
1389 */
1390 leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT);
1391 if (leftcnt == 1) {
1392 leftcnt = 0;
1393 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO);
1394 }
1395 if ((leftcnt == 0) || (stat & SCSIXFERCNT_2_ZERO)) {
1396 while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) &
1397 DMAXFERCOMP) == 0)
1398 ; /* XXX needs timeout */
1399
1400 srb->buflen = 0;
1401 } else {
1402 /* Update SG list */
1403
1404 /*
1405 * if transfer not yet complete
1406 * there were some data residue in SCSI FIFO or
1407 * SCSI transfer counter not empty
1408 */
1409 if (srb->buflen != leftcnt) {
1410 /* data that had transferred length */
1411 xferlen = srb->buflen - leftcnt;
1412
1413 /* next time to be transferred length */
1414 srb->buflen = leftcnt;
1415
1416 /*
1417 * parsing from last time disconnect sgindex
1418 */
1419 sg = srb->sgentry + srb->sgindex;
1420 for (sgindex = srb->sgindex;
1421 sgindex < srb->sgcnt;
1422 sgindex++, sg++) {
1423 /*
1424 * find last time which SG transfer
1425 * be disconnect
1426 */
1427 if (xferlen >= le32toh(sg->length))
1428 xferlen -= le32toh(sg->length);
1429 else {
1430 /*
1431 * update last time
1432 * disconnected SG list
1433 */
1434 /* residue data length */
1435 sg->length =
1436 htole32(le32toh(sg->length)
1437 - xferlen);
1438 /* residue data pointer */
1439 sg->address =
1440 htole32(le32toh(sg->address)
1441 + xferlen);
1442 srb->sgindex = sgindex;
1443 break;
1444 }
1445 }
1446 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1447 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE);
1448 }
1449 }
1450 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER);
1451 }
1452
1453 static void
1454 trm_datain_phase0(struct trm_softc *sc, int stat)
1455 {
1456 bus_space_tag_t iot = sc->sc_iot;
1457 bus_space_handle_t ioh = sc->sc_ioh;
1458 struct trm_srb *srb;
1459 struct trm_sg_entry *sg;
1460 int sgindex;
1461 uint32_t xferlen, leftcnt = 0;
1462
1463 if (sc->sc_state == TRM_XFERPAD)
1464 return;
1465
1466 srb = sc->sc_actsrb;
1467 if (srb == NULL) {
1468 DPRINTF(("trm_datain_phase0: no active srb\n"));
1469 return;
1470 }
1471
1472 if (stat & PARITYERROR)
1473 srb->flag |= PARITY_ERROR;
1474
1475 leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT);
1476 if ((leftcnt == 0) || (stat & SCSIXFERCNT_2_ZERO)) {
1477 while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) &
1478 DMAXFERCOMP) == 0)
1479 ; /* XXX needs timeout */
1480
1481 srb->buflen = 0;
1482 } else { /* phase changed */
1483 /*
1484 * parsing the case:
1485 * when a transfer not yet complete
1486 * but be disconnected by upper layer
1487 * if transfer not yet complete
1488 * there were some data residue in SCSI FIFO or
1489 * SCSI transfer counter not empty
1490 */
1491 if (srb->buflen != leftcnt) {
1492 /*
1493 * data that had transferred length
1494 */
1495 xferlen = srb->buflen - leftcnt;
1496
1497 /*
1498 * next time to be transferred length
1499 */
1500 srb->buflen = leftcnt;
1501
1502 /*
1503 * parsing from last time disconnect sgindex
1504 */
1505 sg = srb->sgentry + srb->sgindex;
1506 for (sgindex = srb->sgindex;
1507 sgindex < srb->sgcnt;
1508 sgindex++, sg++) {
1509 /*
1510 * find last time which SG transfer
1511 * be disconnect
1512 */
1513 if (xferlen >= le32toh(sg->length))
1514 xferlen -= le32toh(sg->length);
1515 else {
1516 /*
1517 * update last time
1518 * disconnected SG list
1519 */
1520 /* residue data length */
1521 sg->length =
1522 htole32(le32toh(sg->length)
1523 - xferlen);
1524 /* residue data pointer */
1525 sg->address =
1526 htole32(le32toh(sg->address)
1527 + xferlen);
1528 srb->sgindex = sgindex;
1529 break;
1530 }
1531 }
1532 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1533 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE);
1534 }
1535 }
1536 }
1537
1538 static void
1539 trm_dataio_xfer(struct trm_softc *sc, int iodir)
1540 {
1541 bus_space_tag_t iot = sc->sc_iot;
1542 bus_space_handle_t ioh = sc->sc_ioh;
1543 struct trm_srb *srb;
1544 struct scsipi_periph *periph;
1545 struct trm_tinfo *ti;
1546
1547 srb = sc->sc_actsrb;
1548 if (srb == NULL) {
1549 DPRINTF(("trm_dataio_xfer: no active srb\n"));
1550 return;
1551 }
1552 periph = srb->xs->xs_periph;
1553 ti = &sc->sc_tinfo[periph->periph_target];
1554
1555 if (srb->sgindex < srb->sgcnt) {
1556 if (srb->buflen > 0) {
1557 /*
1558 * load what physical address of Scatter/Gather
1559 * list table want to be transfer
1560 */
1561 sc->sc_state = TRM_DATA_XFER;
1562 bus_space_write_4(iot, ioh, TRM_DMA_XHIGHADDR, 0);
1563 bus_space_write_4(iot, ioh, TRM_DMA_XLOWADDR,
1564 srb->sgaddr +
1565 srb->sgindex * sizeof(struct trm_sg_entry));
1566 /*
1567 * load how many bytes in the Scatter/Gather list table
1568 */
1569 bus_space_write_4(iot, ioh, TRM_DMA_XCNT,
1570 (srb->sgcnt - srb->sgindex)
1571 * sizeof(struct trm_sg_entry));
1572 /*
1573 * load total xfer length (24bits) max value 16Mbyte
1574 */
1575 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, srb->buflen);
1576 /* Start DMA transfer */
1577 bus_space_write_1(iot, ioh, TRM_DMA_COMMAND,
1578 iodir | SGXFER);
1579 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL,
1580 STARTDMAXFER);
1581
1582 /* Start SCSI transfer */
1583 /* it's important for atn stop */
1584 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL,
1585 DO_DATALATCH);
1586
1587 /*
1588 * SCSI command
1589 */
1590 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND,
1591 (iodir == XFERDATAOUT) ?
1592 SCMD_DMA_OUT : SCMD_DMA_IN);
1593 } else { /* xfer pad */
1594 if (srb->sgcnt) {
1595 srb->hastat = H_OVER_UNDER_RUN;
1596 }
1597 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT,
1598 (ti->synctl & WIDE_SYNC) ? 2 : 1);
1599
1600 if (iodir == XFERDATAOUT)
1601 bus_space_write_2(iot, ioh, TRM_SCSI_FIFO, 0);
1602 else
1603 (void)bus_space_read_2(iot, ioh, TRM_SCSI_FIFO);
1604
1605 sc->sc_state = TRM_XFERPAD;
1606 /* it's important for atn stop */
1607 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL,
1608 DO_DATALATCH);
1609
1610 /*
1611 * SCSI command
1612 */
1613 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND,
1614 (iodir == XFERDATAOUT) ?
1615 SCMD_FIFO_OUT : SCMD_FIFO_IN);
1616 }
1617 }
1618 }
1619
1620 static void
1621 trm_status_phase0(struct trm_softc *sc)
1622 {
1623 bus_space_tag_t iot = sc->sc_iot;
1624 bus_space_handle_t ioh = sc->sc_ioh;
1625 struct trm_srb *srb;
1626
1627 srb = sc->sc_actsrb;
1628 if (srb == NULL) {
1629 DPRINTF(("trm_status_phase0: no active srb\n"));
1630 return;
1631 }
1632 srb->tastat = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO);
1633 sc->sc_state = TRM_COMPLETED;
1634 /* it's important for atn stop */
1635 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH);
1636
1637 /*
1638 * SCSI command
1639 */
1640 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT);
1641 }
1642
1643 static void
1644 trm_status_phase1(struct trm_softc *sc)
1645 {
1646 bus_space_tag_t iot = sc->sc_iot;
1647 bus_space_handle_t ioh = sc->sc_ioh;
1648
1649 if (bus_space_read_1(iot, ioh, TRM_DMA_COMMAND) & XFERDATAIN) {
1650 if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT)
1651 & SCSI_FIFO_EMPTY) == 0)
1652 bus_space_write_2(iot, ioh,
1653 TRM_SCSI_CONTROL, DO_CLRFIFO);
1654 if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS)
1655 & DMA_FIFO_EMPTY) == 0)
1656 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO);
1657 } else {
1658 if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS)
1659 & DMA_FIFO_EMPTY) == 0)
1660 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO);
1661 if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT)
1662 & SCSI_FIFO_EMPTY) == 0)
1663 bus_space_write_2(iot, ioh,
1664 TRM_SCSI_CONTROL, DO_CLRFIFO);
1665 }
1666 sc->sc_state = TRM_STATUS;
1667 /* it's important for atn stop */
1668 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH);
1669
1670 /*
1671 * SCSI command
1672 */
1673 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_COMP);
1674 }
1675
1676 static void
1677 trm_msgin_phase0(struct trm_softc *sc)
1678 {
1679 bus_space_tag_t iot = sc->sc_iot;
1680 bus_space_handle_t ioh = sc->sc_ioh;
1681 struct trm_srb *srb;
1682 struct scsipi_periph *periph;
1683 struct trm_tinfo *ti;
1684 int index;
1685 uint8_t msgin_code;
1686
1687 msgin_code = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO);
1688 if (sc->sc_state != TRM_EXTEND_MSGIN) {
1689 DPRINTF(("msgin: code = %02x\n", msgin_code));
1690 switch (msgin_code) {
1691 case MSG_DISCONNECT:
1692 sc->sc_state = TRM_DISCONNECTED;
1693 break;
1694
1695 case MSG_SAVEDATAPOINTER:
1696 break;
1697
1698 case MSG_EXTENDED:
1699 case MSG_SIMPLE_Q_TAG:
1700 case MSG_HEAD_OF_Q_TAG:
1701 case MSG_ORDERED_Q_TAG:
1702 sc->sc_state = TRM_EXTEND_MSGIN;
1703 /* extended message (01h) */
1704 sc->sc_msgbuf[0] = msgin_code;
1705
1706 sc->sc_msgcnt = 1;
1707 /* extended message length (n) */
1708 sc->sc_msg = &sc->sc_msgbuf[1];
1709
1710 break;
1711 case MSG_MESSAGE_REJECT:
1712 /* Reject message */
1713 srb = sc->sc_actsrb;
1714 if (srb == NULL) {
1715 DPRINTF(("trm_msgin_phase0: "
1716 " message reject without actsrb\n"));
1717 break;
1718 }
1719 periph = srb->xs->xs_periph;
1720 ti = &sc->sc_tinfo[periph->periph_target];
1721
1722 if (ti->flag & WIDE_NEGO_ENABLE) {
1723 /* do wide nego reject */
1724 ti->flag |= WIDE_NEGO_DONE;
1725 ti->flag &=
1726 ~(SYNC_NEGO_DONE | WIDE_NEGO_ENABLE);
1727 if ((ti->flag & SYNC_NEGO_ENABLE) &&
1728 (ti->flag & SYNC_NEGO_DONE) == 0) {
1729 /* Set ATN, in case ATN was clear */
1730 sc->sc_state = TRM_MSGOUT;
1731 bus_space_write_2(iot, ioh,
1732 TRM_SCSI_CONTROL, DO_SETATN);
1733 } else
1734 /* Clear ATN */
1735 bus_space_write_2(iot, ioh,
1736 TRM_SCSI_CONTROL, DO_CLRATN);
1737 } else if (ti->flag & SYNC_NEGO_ENABLE) {
1738 /* do sync nego reject */
1739 bus_space_write_2(iot, ioh,
1740 TRM_SCSI_CONTROL, DO_CLRATN);
1741 if (ti->flag & SYNC_NEGO_DOING) {
1742 ti->flag &=~(SYNC_NEGO_ENABLE |
1743 SYNC_NEGO_DONE);
1744 ti->synctl = 0;
1745 ti->offset = 0;
1746 bus_space_write_1(iot, ioh,
1747 TRM_SCSI_SYNC, ti->synctl);
1748 bus_space_write_1(iot, ioh,
1749 TRM_SCSI_OFFSET, ti->offset);
1750 }
1751 }
1752 break;
1753
1754 case MSG_IGN_WIDE_RESIDUE:
1755 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1);
1756 (void)bus_space_read_1(iot, ioh, TRM_SCSI_FIFO);
1757 break;
1758
1759 default:
1760 /*
1761 * Restore data pointer message
1762 * Save data pointer message
1763 * Completion message
1764 * NOP message
1765 */
1766 break;
1767 }
1768 } else {
1769 /*
1770 * when extend message in: sc->sc_state = TRM_EXTEND_MSGIN
1771 * Parsing incoming extented messages
1772 */
1773 *sc->sc_msg++ = msgin_code;
1774 sc->sc_msgcnt++;
1775
1776 DPRINTF(("extended_msgin: cnt = %d, ", sc->sc_msgcnt));
1777 DPRINTF(("msgbuf = %02x %02x %02x %02x %02x %02x\n",
1778 sc->sc_msgbuf[0], sc->sc_msgbuf[1], sc->sc_msgbuf[2],
1779 sc->sc_msgbuf[3], sc->sc_msgbuf[4], sc->sc_msgbuf[5]));
1780
1781 switch (sc->sc_msgbuf[0]) {
1782 case MSG_SIMPLE_Q_TAG:
1783 case MSG_HEAD_OF_Q_TAG:
1784 case MSG_ORDERED_Q_TAG:
1785 /*
1786 * is QUEUE tag message :
1787 *
1788 * byte 0:
1789 * HEAD QUEUE TAG (20h)
1790 * ORDERED QUEUE TAG (21h)
1791 * SIMPLE QUEUE TAG (22h)
1792 * byte 1:
1793 * Queue tag (00h - FFh)
1794 */
1795 if (sc->sc_msgcnt == 2 && sc->sc_actsrb == NULL) {
1796 /* XXX XXX XXX */
1797 struct trm_linfo *li;
1798 int tagid;
1799
1800 sc->sc_flag &= ~WAIT_TAGMSG;
1801 tagid = sc->sc_msgbuf[1];
1802 ti = &sc->sc_tinfo[sc->resel_target];
1803 li = ti->linfo[sc->resel_lun];
1804 srb = li->queued[tagid];
1805 if (srb != NULL) {
1806 sc->sc_actsrb = srb;
1807 sc->sc_state = TRM_DATA_XFER;
1808 break;
1809 } else {
1810 printf("%s: invalid tag id\n",
1811 device_xname(sc->sc_dev));
1812 }
1813
1814 sc->sc_state = TRM_UNEXPECT_RESEL;
1815 sc->sc_msgbuf[0] = MSG_ABORT_TAG;
1816 sc->sc_msgcnt = 1;
1817 bus_space_write_2(iot, ioh,
1818 TRM_SCSI_CONTROL, DO_SETATN);
1819 } else
1820 sc->sc_state = TRM_IDLE;
1821 break;
1822
1823 case MSG_EXTENDED:
1824 srb = sc->sc_actsrb;
1825 if (srb == NULL) {
1826 DPRINTF(("trm_msgin_phase0: "
1827 "extended message without actsrb\n"));
1828 break;
1829 }
1830 periph = srb->xs->xs_periph;
1831 ti = &sc->sc_tinfo[periph->periph_target];
1832
1833 if (sc->sc_msgbuf[2] == MSG_EXT_WDTR &&
1834 sc->sc_msgcnt == 4) {
1835 /*
1836 * is Wide data xfer Extended message :
1837 * ======================================
1838 * WIDE DATA TRANSFER REQUEST
1839 * ======================================
1840 * byte 0 : Extended message (01h)
1841 * byte 1 : Extended message length (02h)
1842 * byte 2 : WIDE DATA TRANSFER code (03h)
1843 * byte 3 : Transfer width exponent
1844 */
1845 if (sc->sc_msgbuf[1] != MSG_EXT_WDTR_LEN) {
1846 /* Length is wrong, reject it */
1847 ti->flag &= ~(WIDE_NEGO_ENABLE |
1848 WIDE_NEGO_DONE);
1849 sc->sc_state = TRM_MSGOUT;
1850 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT;
1851 sc->sc_msgcnt = 1;
1852 bus_space_write_2(iot, ioh,
1853 TRM_SCSI_CONTROL, DO_SETATN);
1854 break;
1855 }
1856
1857 if ((ti->flag & WIDE_NEGO_ENABLE) == 0)
1858 sc->sc_msgbuf[3] =
1859 MSG_EXT_WDTR_BUS_8_BIT;
1860
1861 if (sc->sc_msgbuf[3] >
1862 MSG_EXT_WDTR_BUS_32_BIT) {
1863 /* reject_msg: */
1864 ti->flag &= ~(WIDE_NEGO_ENABLE |
1865 WIDE_NEGO_DONE);
1866 sc->sc_state = TRM_MSGOUT;
1867 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT;
1868 sc->sc_msgcnt = 1;
1869 bus_space_write_2(iot, ioh,
1870 TRM_SCSI_CONTROL, DO_SETATN);
1871 break;
1872 }
1873 if (sc->sc_msgbuf[3] == MSG_EXT_WDTR_BUS_32_BIT)
1874 /* do 16 bits */
1875 sc->sc_msgbuf[3] =
1876 MSG_EXT_WDTR_BUS_16_BIT;
1877 if ((ti->flag & WIDE_NEGO_DONE) == 0) {
1878 ti->flag |= WIDE_NEGO_DONE;
1879 ti->flag &= ~(SYNC_NEGO_DONE |
1880 WIDE_NEGO_ENABLE);
1881 if (sc->sc_msgbuf[3] !=
1882 MSG_EXT_WDTR_BUS_8_BIT)
1883 /* is Wide data xfer */
1884 ti->synctl |= WIDE_SYNC;
1885 trm_update_xfer_mode(sc,
1886 periph->periph_target);
1887 }
1888
1889 sc->sc_state = TRM_MSGOUT;
1890 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL,
1891 DO_SETATN);
1892 break;
1893
1894 } else if (sc->sc_msgbuf[2] == MSG_EXT_SDTR &&
1895 sc->sc_msgcnt == 5) {
1896 /*
1897 * is 8bit transfer Extended message :
1898 * =================================
1899 * SYNCHRONOUS DATA TRANSFER REQUEST
1900 * =================================
1901 * byte 0 : Extended message (01h)
1902 * byte 1 : Extended message length (03)
1903 * byte 2 : SYNC DATA TRANSFER code (01h)
1904 * byte 3 : Transfer period factor
1905 * byte 4 : REQ/ACK offset
1906 */
1907 if (sc->sc_msgbuf[1] != MSG_EXT_SDTR_LEN) {
1908 /* reject_msg */
1909 sc->sc_state = TRM_MSGOUT;
1910 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT;
1911 sc->sc_msgcnt = 1;
1912 bus_space_write_2(iot, ioh,
1913 TRM_SCSI_CONTROL, DO_SETATN);
1914 break;
1915 }
1916
1917 if ((ti->flag & SYNC_NEGO_DONE) == 0) {
1918 ti->flag &=
1919 ~(SYNC_NEGO_ENABLE|SYNC_NEGO_DOING);
1920 ti->flag |= SYNC_NEGO_DONE;
1921 if (sc->sc_msgbuf[3] >= TRM_MAX_PERIOD)
1922 sc->sc_msgbuf[3] = 0;
1923 if (sc->sc_msgbuf[4] > TRM_MAX_OFFSET)
1924 sc->sc_msgbuf[4] =
1925 TRM_MAX_OFFSET;
1926
1927 if (sc->sc_msgbuf[3] == 0 ||
1928 sc->sc_msgbuf[4] == 0) {
1929 /* set async */
1930 ti->synctl = 0;
1931 ti->offset = 0;
1932 } else {
1933 /* set sync */
1934 /* Transfer period factor */
1935 ti->period = sc->sc_msgbuf[3];
1936 /* REQ/ACK offset */
1937 ti->offset = sc->sc_msgbuf[4];
1938 for (index = 0;
1939 index < NPERIOD;
1940 index++)
1941 if (ti->period <=
1942 trm_clock_period[
1943 index])
1944 break;
1945
1946 ti->synctl |= ALT_SYNC | index;
1947 }
1948 /*
1949 * program SCSI control register
1950 */
1951 bus_space_write_1(iot, ioh,
1952 TRM_SCSI_SYNC, ti->synctl);
1953 bus_space_write_1(iot, ioh,
1954 TRM_SCSI_OFFSET, ti->offset);
1955 trm_update_xfer_mode(sc,
1956 periph->periph_target);
1957 }
1958 sc->sc_state = TRM_IDLE;
1959 }
1960 break;
1961 default:
1962 break;
1963 }
1964 }
1965
1966 /* it's important for atn stop */
1967 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH);
1968
1969 /*
1970 * SCSI command
1971 */
1972 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT);
1973 }
1974
1975 static void
1976 trm_msgin_phase1(struct trm_softc *sc)
1977 {
1978 bus_space_tag_t iot = sc->sc_iot;
1979 bus_space_handle_t ioh = sc->sc_ioh;
1980
1981 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO);
1982 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1);
1983 if (sc->sc_state != TRM_MSGIN && sc->sc_state != TRM_EXTEND_MSGIN) {
1984 sc->sc_state = TRM_MSGIN;
1985 }
1986
1987 /* it's important for atn stop */
1988 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH);
1989
1990 /*
1991 * SCSI command
1992 */
1993 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_IN);
1994 }
1995
1996 static void
1997 trm_disconnect(struct trm_softc *sc)
1998 {
1999 bus_space_tag_t iot = sc->sc_iot;
2000 bus_space_handle_t ioh = sc->sc_ioh;
2001 struct trm_srb *srb;
2002 int s;
2003
2004 s = splbio();
2005
2006 srb = sc->sc_actsrb;
2007 DPRINTF(("trm_disconnect...............\n"));
2008
2009 if (srb == NULL) {
2010 DPRINTF(("trm_disconnect: no active srb\n"));
2011 DELAY(1000); /* 1 msec */
2012
2013 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL,
2014 DO_CLRFIFO | DO_HWRESELECT);
2015 return;
2016 }
2017 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */
2018 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL,
2019 DO_CLRFIFO | DO_HWRESELECT);
2020 DELAY(100);
2021
2022 switch (sc->sc_state) {
2023 case TRM_UNEXPECT_RESEL:
2024 sc->sc_state = TRM_IDLE;
2025 break;
2026
2027 case TRM_ABORT_SENT:
2028 goto finish;
2029
2030 case TRM_START:
2031 case TRM_MSGOUT:
2032 {
2033 /* Selection time out - discard all LUNs if empty */
2034 struct scsipi_periph *periph;
2035 struct trm_tinfo *ti;
2036 struct trm_linfo *li;
2037 int lun;
2038
2039 DPRINTF(("selection timeout\n"));
2040
2041 srb->tastat = SCSI_SEL_TIMEOUT; /* XXX Ok? */
2042
2043 periph = srb->xs->xs_periph;
2044 ti = &sc->sc_tinfo[periph->periph_target];
2045 for (lun = 0; lun < TRM_MAX_LUNS; lun++) {
2046 li = ti->linfo[lun];
2047 if (li != NULL &&
2048 li->untagged == NULL && li->used == 0) {
2049 ti->linfo[lun] = NULL;
2050 free(li, M_DEVBUF);
2051 }
2052 }
2053 }
2054 goto finish;
2055
2056 case TRM_DISCONNECTED:
2057 sc->sc_actsrb = NULL;
2058 sc->sc_state = TRM_IDLE;
2059 goto sched;
2060
2061 case TRM_COMPLETED:
2062 goto finish;
2063 }
2064
2065 out:
2066 splx(s);
2067 return;
2068
2069 finish:
2070 sc->sc_state = TRM_IDLE;
2071 trm_done(sc, srb);
2072 goto out;
2073
2074 sched:
2075 trm_sched(sc);
2076 goto out;
2077 }
2078
2079 static void
2080 trm_reselect(struct trm_softc *sc)
2081 {
2082 bus_space_tag_t iot = sc->sc_iot;
2083 bus_space_handle_t ioh = sc->sc_ioh;
2084 struct trm_tinfo *ti;
2085 struct trm_linfo *li;
2086 int target, lun;
2087
2088 DPRINTF(("trm_reselect.................\n"));
2089
2090 if (sc->sc_actsrb != NULL) {
2091 /* arbitration lost but reselection win */
2092 sc->sc_state = TRM_READY;
2093 target = sc->sc_actsrb->xs->xs_periph->periph_target;
2094 ti = &sc->sc_tinfo[target];
2095 } else {
2096 /* Read Reselected Target Id and LUN */
2097 target = bus_space_read_1(iot, ioh, TRM_SCSI_TARGETID);
2098 lun = bus_space_read_1(iot, ioh, TRM_SCSI_IDMSG) & 0x07;
2099 ti = &sc->sc_tinfo[target];
2100 li = ti->linfo[lun];
2101 DPRINTF(("target = %d, lun = %d\n", target, lun));
2102
2103 /*
2104 * Check to see if we are running an un-tagged command.
2105 * Otherwise ack the IDENTIFY and wait for a tag message.
2106 */
2107 if (li != NULL) {
2108 if (li->untagged != NULL && li->busy) {
2109 sc->sc_actsrb = li->untagged;
2110 sc->sc_state = TRM_DATA_XFER;
2111 } else {
2112 sc->resel_target = target;
2113 sc->resel_lun = lun;
2114 /* XXX XXX XXX */
2115 sc->sc_flag |= WAIT_TAGMSG;
2116 }
2117 }
2118
2119 if ((ti->flag & USE_TAG_QUEUING) == 0 &&
2120 sc->sc_actsrb == NULL) {
2121 printf("%s: reselect from target %d lun %d "
2122 "without nexus; sending abort\n",
2123 device_xname(sc->sc_dev), target, lun);
2124 sc->sc_state = TRM_UNEXPECT_RESEL;
2125 sc->sc_msgbuf[0] = MSG_ABORT_TAG;
2126 sc->sc_msgcnt = 1;
2127 bus_space_write_2(iot, ioh,
2128 TRM_SCSI_CONTROL, DO_SETATN);
2129 }
2130 }
2131 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */
2132 /*
2133 * Program HA ID, target ID, period and offset
2134 */
2135 /* target ID */
2136 bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, target);
2137
2138 /* host ID */
2139 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id);
2140
2141 /* period */
2142 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, ti->synctl);
2143
2144 /* offset */
2145 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, ti->offset);
2146
2147 /* it's important for atn stop */
2148 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH);
2149 /*
2150 * SCSI command
2151 */
2152 /* to rls the /ACK signal */
2153 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT);
2154 }
2155
2156 /*
2157 * Complete execution of a SCSI command
2158 * Signal completion to the generic SCSI driver
2159 */
2160 static void
2161 trm_done(struct trm_softc *sc, struct trm_srb *srb)
2162 {
2163 struct scsipi_xfer *xs = srb->xs;
2164
2165 DPRINTF(("trm_done..................\n"));
2166
2167 if (xs == NULL)
2168 return;
2169
2170 if ((xs->xs_control & XS_CTL_POLL) == 0)
2171 callout_stop(&xs->xs_callout);
2172
2173 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT) ||
2174 srb->flag & AUTO_REQSENSE) {
2175 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0,
2176 srb->dmap->dm_mapsize,
2177 ((xs->xs_control & XS_CTL_DATA_IN) ||
2178 (srb->flag & AUTO_REQSENSE)) ?
2179 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
2180 bus_dmamap_unload(sc->sc_dmat, srb->dmap);
2181 }
2182
2183 /*
2184 * target status
2185 */
2186 xs->status = srb->tastat;
2187
2188 DPRINTF(("xs->status = 0x%02x\n", xs->status));
2189
2190 switch (xs->status) {
2191 case SCSI_OK:
2192 /*
2193 * process initiator status......
2194 * Adapter (initiator) status
2195 */
2196 if ((srb->hastat & H_OVER_UNDER_RUN) != 0) {
2197 printf("%s: over/under run error\n",
2198 device_xname(sc->sc_dev));
2199 srb->tastat = 0;
2200 /* Illegal length (over/under run) */
2201 xs->error = XS_DRIVER_STUFFUP;
2202 } else if ((srb->flag & PARITY_ERROR) != 0) {
2203 printf("%s: parity error\n", device_xname(sc->sc_dev));
2204 /* Driver failed to perform operation */
2205 xs->error = XS_DRIVER_STUFFUP; /* XXX */
2206 } else if ((srb->flag & SRB_TIMEOUT) != 0) {
2207 xs->resid = srb->buflen;
2208 xs->error = XS_TIMEOUT;
2209 } else {
2210 /* No error */
2211 xs->resid = srb->buflen;
2212 srb->hastat = 0;
2213 if (srb->flag & AUTO_REQSENSE) {
2214 /* there is no error, (sense is invalid) */
2215 xs->error = XS_SENSE;
2216 } else {
2217 srb->tastat = 0;
2218 xs->error = XS_NOERROR;
2219 }
2220 }
2221 break;
2222
2223 case SCSI_CHECK:
2224 if ((srb->flag & AUTO_REQSENSE) != 0 ||
2225 trm_request_sense(sc, srb) != 0) {
2226 printf("%s: request sense failed\n",
2227 device_xname(sc->sc_dev));
2228 xs->error = XS_DRIVER_STUFFUP;
2229 break;
2230 }
2231 xs->error = XS_SENSE;
2232 return;
2233
2234 case SCSI_SEL_TIMEOUT:
2235 srb->hastat = H_SEL_TIMEOUT;
2236 srb->tastat = 0;
2237 xs->error = XS_SELTIMEOUT;
2238 break;
2239
2240 case SCSI_QUEUE_FULL:
2241 case SCSI_BUSY:
2242 xs->error = XS_BUSY;
2243 break;
2244
2245 case SCSI_RESV_CONFLICT:
2246 DPRINTF(("%s: target reserved at ", device_xname(sc->sc_dev)));
2247 DPRINTF(("%s %d\n", __FILE__, __LINE__));
2248 xs->error = XS_BUSY;
2249 break;
2250
2251 default:
2252 srb->hastat = 0;
2253 printf("%s: trm_done(): unknown status = %02x\n",
2254 device_xname(sc->sc_dev), xs->status);
2255 xs->error = XS_DRIVER_STUFFUP;
2256 break;
2257 }
2258
2259 trm_dequeue(sc, srb);
2260 if (srb == sc->sc_actsrb) {
2261 sc->sc_actsrb = NULL;
2262 trm_sched(sc);
2263 }
2264
2265 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next);
2266
2267 /* Notify cmd done */
2268 scsipi_done(xs);
2269 }
2270
2271 static int
2272 trm_request_sense(struct trm_softc *sc, struct trm_srb *srb)
2273 {
2274 struct scsipi_xfer *xs;
2275 struct scsipi_periph *periph;
2276 struct trm_tinfo *ti;
2277 struct trm_linfo *li;
2278 struct scsi_request_sense *ss = (struct scsi_request_sense *)srb->cmd;
2279 int error;
2280
2281 DPRINTF(("trm_request_sense...\n"));
2282
2283 xs = srb->xs;
2284 periph = xs->xs_periph;
2285
2286 srb->flag |= AUTO_REQSENSE;
2287
2288 /* Status of initiator/target */
2289 srb->hastat = 0;
2290 srb->tastat = 0;
2291
2292 memset(ss, 0, sizeof(*ss));
2293 ss->opcode = SCSI_REQUEST_SENSE;
2294 ss->byte2 = periph->periph_lun << SCSI_CMD_LUN_SHIFT;
2295 ss->length = sizeof(struct scsi_sense_data);
2296
2297 srb->buflen = sizeof(struct scsi_sense_data);
2298 srb->sgcnt = 1;
2299 srb->sgindex = 0;
2300 srb->cmdlen = sizeof(struct scsi_request_sense);
2301
2302 if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap,
2303 &xs->sense.scsi_sense, srb->buflen, NULL,
2304 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) {
2305 return error;
2306 }
2307 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0,
2308 srb->buflen, BUS_DMASYNC_PREREAD);
2309
2310 srb->sgentry[0].address = htole32(srb->dmap->dm_segs[0].ds_addr);
2311 srb->sgentry[0].length = htole32(sizeof(struct scsi_sense_data));
2312 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, srb->sgoffset,
2313 TRM_SG_SIZE, BUS_DMASYNC_PREWRITE);
2314
2315 ti = &sc->sc_tinfo[periph->periph_target];
2316 li = ti->linfo[periph->periph_lun];
2317 if (li->busy > 0)
2318 li->busy = 0;
2319 trm_dequeue(sc, srb);
2320 li->untagged = srb; /* must be executed first to fix C/A */
2321 li->busy = 2;
2322
2323 if (srb == sc->sc_actsrb)
2324 trm_select(sc, srb);
2325 else {
2326 TAILQ_INSERT_HEAD(&sc->sc_readysrb, srb, next);
2327 if (sc->sc_actsrb == NULL)
2328 trm_sched(sc);
2329 }
2330 return 0;
2331 }
2332
2333 static void
2334 trm_dequeue(struct trm_softc *sc, struct trm_srb *srb)
2335 {
2336 struct scsipi_periph *periph;
2337 struct trm_tinfo *ti;
2338 struct trm_linfo *li;
2339
2340 periph = srb->xs->xs_periph;
2341 ti = &sc->sc_tinfo[periph->periph_target];
2342 li = ti->linfo[periph->periph_lun];
2343
2344 if (li->untagged == srb) {
2345 li->busy = 0;
2346 li->untagged = NULL;
2347 }
2348 if (srb->tag[0] != 0 && li->queued[srb->tag[1]] != NULL) {
2349 li->queued[srb->tag[1]] = NULL;
2350 li->used--;
2351 }
2352 }
2353
2354 static void
2355 trm_reset_scsi_bus(struct trm_softc *sc)
2356 {
2357 bus_space_tag_t iot = sc->sc_iot;
2358 bus_space_handle_t ioh = sc->sc_ioh;
2359 int timeout, s;
2360
2361 DPRINTF(("trm_reset_scsi_bus.........\n"));
2362
2363 s = splbio();
2364
2365 sc->sc_flag |= RESET_DEV;
2366 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTSCSI);
2367 for (timeout = 20000; timeout >= 0; timeout--) {
2368 DELAY(1);
2369 if ((bus_space_read_2(iot, ioh, TRM_SCSI_INTSTATUS) &
2370 INT_SCSIRESET) == 0)
2371 break;
2372 }
2373 if (timeout == 0)
2374 printf(": scsibus reset timeout\n");
2375
2376 splx(s);
2377 }
2378
2379 static void
2380 trm_scsi_reset_detect(struct trm_softc *sc)
2381 {
2382 bus_space_tag_t iot = sc->sc_iot;
2383 bus_space_handle_t ioh = sc->sc_ioh;
2384 int s;
2385
2386 DPRINTF(("trm_scsi_reset_detect...............\n"));
2387 DELAY(1000000); /* delay 1 sec */
2388
2389 s = splbio();
2390
2391 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER);
2392 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO);
2393
2394 if (sc->sc_flag & RESET_DEV) {
2395 sc->sc_flag |= RESET_DONE;
2396 } else {
2397 sc->sc_flag |= RESET_DETECT;
2398 sc->sc_actsrb = NULL;
2399 sc->sc_flag = 0;
2400 trm_sched(sc);
2401 }
2402 splx(s);
2403 }
2404
2405 /*
2406 * read seeprom 128 bytes to struct eeprom and check checksum.
2407 * If it is wrong, update with default value.
2408 */
2409 static void
2410 trm_check_eeprom(struct trm_softc *sc, struct trm_nvram *eeprom)
2411 {
2412 struct nvram_target *target;
2413 uint16_t *ep;
2414 uint16_t chksum;
2415 int i;
2416
2417 DPRINTF(("trm_check_eeprom......\n"));
2418 trm_eeprom_read_all(sc, eeprom);
2419 ep = (uint16_t *)eeprom;
2420 chksum = 0;
2421 for (i = 0; i < 64; i++)
2422 chksum += le16toh(*ep++);
2423
2424 if (chksum != TRM_NVRAM_CKSUM) {
2425 DPRINTF(("TRM_S1040 EEPROM Check Sum ERROR (load default).\n"));
2426 /*
2427 * Checksum error, load default
2428 */
2429 eeprom->subvendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF;
2430 eeprom->subvendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8;
2431 eeprom->subsys_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF;
2432 eeprom->subsys_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8;
2433 eeprom->subclass = 0x00;
2434 eeprom->vendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF;
2435 eeprom->vendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8;
2436 eeprom->device_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF;
2437 eeprom->device_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8;
2438 eeprom->reserved0 = 0x00;
2439
2440 for (i = 0, target = eeprom->target;
2441 i < TRM_MAX_TARGETS;
2442 i++, target++) {
2443 target->config0 = 0x77;
2444 target->period = 0x00;
2445 target->config2 = 0x00;
2446 target->config3 = 0x00;
2447 }
2448
2449 eeprom->scsi_id = 7;
2450 eeprom->channel_cfg = 0x0F;
2451 eeprom->delay_time = 0;
2452 eeprom->max_tag = 4;
2453 eeprom->reserved1 = 0x15;
2454 eeprom->boot_target = 0;
2455 eeprom->boot_lun = 0;
2456 eeprom->reserved2 = 0;
2457 memset(eeprom->reserved3, 0, sizeof(eeprom->reserved3));
2458
2459 chksum = 0;
2460 ep = (uint16_t *)eeprom;
2461 for (i = 0; i < 63; i++)
2462 chksum += le16toh(*ep++);
2463
2464 chksum = TRM_NVRAM_CKSUM - chksum;
2465 eeprom->checksum0 = chksum & 0xFF;
2466 eeprom->checksum1 = chksum >> 8;
2467
2468 trm_eeprom_write_all(sc, eeprom);
2469 }
2470 }
2471
2472 /*
2473 * write struct eeprom 128 bytes to seeprom
2474 */
2475 static void
2476 trm_eeprom_write_all(struct trm_softc *sc, struct trm_nvram *eeprom)
2477 {
2478 bus_space_tag_t iot = sc->sc_iot;
2479 bus_space_handle_t ioh = sc->sc_ioh;
2480 uint8_t *sbuf = (uint8_t *)eeprom;
2481 uint8_t addr;
2482
2483 /* Enable SEEPROM */
2484 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL,
2485 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM);
2486
2487 /*
2488 * Write enable
2489 */
2490 trm_eeprom_write_cmd(sc, 0x04, 0xFF);
2491 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0);
2492 trm_eeprom_wait();
2493
2494 for (addr = 0; addr < 128; addr++, sbuf++)
2495 trm_eeprom_set_data(sc, addr, *sbuf);
2496
2497 /*
2498 * Write disable
2499 */
2500 trm_eeprom_write_cmd(sc, 0x04, 0x00);
2501 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0);
2502 trm_eeprom_wait();
2503
2504 /* Disable SEEPROM */
2505 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL,
2506 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM);
2507 }
2508
2509 /*
2510 * write one byte to seeprom
2511 */
2512 static void
2513 trm_eeprom_set_data(struct trm_softc *sc, uint8_t addr, uint8_t data)
2514 {
2515 bus_space_tag_t iot = sc->sc_iot;
2516 bus_space_handle_t ioh = sc->sc_ioh;
2517 int i;
2518 uint8_t send;
2519
2520 /*
2521 * Send write command & address
2522 */
2523 trm_eeprom_write_cmd(sc, 0x05, addr);
2524 /*
2525 * Write data
2526 */
2527 for (i = 0; i < 8; i++, data <<= 1) {
2528 send = NVR_SELECT;
2529 if (data & 0x80) /* Start from bit 7 */
2530 send |= NVR_BITOUT;
2531
2532 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send);
2533 trm_eeprom_wait();
2534 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK);
2535 trm_eeprom_wait();
2536 }
2537 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT);
2538 trm_eeprom_wait();
2539 /*
2540 * Disable chip select
2541 */
2542 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0);
2543 trm_eeprom_wait();
2544 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT);
2545 trm_eeprom_wait();
2546 /*
2547 * Wait for write ready
2548 */
2549 for (;;) {
2550 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM,
2551 NVR_SELECT | NVR_CLOCK);
2552 trm_eeprom_wait();
2553 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT);
2554 trm_eeprom_wait();
2555 if (bus_space_read_1(iot, ioh, TRM_GEN_NVRAM) & NVR_BITIN)
2556 break;
2557 }
2558 /*
2559 * Disable chip select
2560 */
2561 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0);
2562 }
2563
2564 /*
2565 * read seeprom 128 bytes to struct eeprom
2566 */
2567 static void
2568 trm_eeprom_read_all(struct trm_softc *sc, struct trm_nvram *eeprom)
2569 {
2570 bus_space_tag_t iot = sc->sc_iot;
2571 bus_space_handle_t ioh = sc->sc_ioh;
2572 uint8_t *sbuf = (uint8_t *)eeprom;
2573 uint8_t addr;
2574
2575 /*
2576 * Enable SEEPROM
2577 */
2578 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL,
2579 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM);
2580
2581 for (addr = 0; addr < 128; addr++)
2582 *sbuf++ = trm_eeprom_get_data(sc, addr);
2583
2584 /*
2585 * Disable SEEPROM
2586 */
2587 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL,
2588 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM);
2589 }
2590
2591 /*
2592 * read one byte from seeprom
2593 */
2594 static uint8_t
2595 trm_eeprom_get_data(struct trm_softc *sc, uint8_t addr)
2596 {
2597 bus_space_tag_t iot = sc->sc_iot;
2598 bus_space_handle_t ioh = sc->sc_ioh;
2599 int i;
2600 uint8_t read, data = 0;
2601
2602 /*
2603 * Send read command & address
2604 */
2605 trm_eeprom_write_cmd(sc, 0x06, addr);
2606
2607 for (i = 0; i < 8; i++) { /* Read data */
2608 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM,
2609 NVR_SELECT | NVR_CLOCK);
2610 trm_eeprom_wait();
2611 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT);
2612 /*
2613 * Get data bit while falling edge
2614 */
2615 read = bus_space_read_1(iot, ioh, TRM_GEN_NVRAM);
2616 data <<= 1;
2617 if (read & NVR_BITIN)
2618 data |= 1;
2619
2620 trm_eeprom_wait();
2621 }
2622 /*
2623 * Disable chip select
2624 */
2625 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0);
2626 return data;
2627 }
2628
2629 /*
2630 * write SB and Op Code into seeprom
2631 */
2632 static void
2633 trm_eeprom_write_cmd(struct trm_softc *sc, uint8_t cmd, uint8_t addr)
2634 {
2635 bus_space_tag_t iot = sc->sc_iot;
2636 bus_space_handle_t ioh = sc->sc_ioh;
2637 int i;
2638 uint8_t send;
2639
2640 /* Program SB+OP code */
2641 for (i = 0; i < 3; i++, cmd <<= 1) {
2642 send = NVR_SELECT;
2643 if (cmd & 0x04) /* Start from bit 2 */
2644 send |= NVR_BITOUT;
2645
2646 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send);
2647 trm_eeprom_wait();
2648 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK);
2649 trm_eeprom_wait();
2650 }
2651
2652 /* Program address */
2653 for (i = 0; i < 7; i++, addr <<= 1) {
2654 send = NVR_SELECT;
2655 if (addr & 0x40) /* Start from bit 6 */
2656 send |= NVR_BITOUT;
2657
2658 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send);
2659 trm_eeprom_wait();
2660 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK);
2661 trm_eeprom_wait();
2662 }
2663 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT);
2664 trm_eeprom_wait();
2665 }
NetBSD on the FriendlyARM MINI2440