sys/dev/pci/unichromeconfig.h

   1 /* $NetBSD: unichromeconfig.h,v 1.1 2006/08/02 01:44:09 jmcneill Exp $ */
   2
   3 /*
   4  * Copyright 1998-2006 VIA Technologies, Inc. All Rights Reserved.
   5  * Copyright 2001-2006 S3 Graphics, Inc. All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sub license,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHOR(S) OR COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  22  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  23  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  24  * DEALINGS IN THE SOFTWARE.
  25  */
  26
  27 #ifndef _DEV_PCI_UNICHROMECONFIG_H
  28 #define _DEV_PCI_UNICHROMECONFIG_H
  29
  30 static struct pll_map pll_value[] = {
  31     {CLK_25_175M,  CLE266_PLL_25_175M,  K800_PLL_25_175M,  CX700_25_175M},
  32     {CLK_29_581M,  CLE266_PLL_29_581M,  K800_PLL_29_581M,  CX700_29_581M},
  33     {CLK_26_880M,  CLE266_PLL_26_880M,  K800_PLL_26_880M,  CX700_26_880M},
  34     {CLK_31_490M,  CLE266_PLL_31_490M,  K800_PLL_31_490M,  CX700_31_490M},
  35     {CLK_31_500M,  CLE266_PLL_31_500M,  K800_PLL_31_500M,  CX700_31_500M},
  36     {CLK_31_728M,  CLE266_PLL_31_728M,  K800_PLL_31_728M,  CX700_31_728M},
  37     {CLK_32_668M,  CLE266_PLL_32_668M,  K800_PLL_32_668M,  CX700_32_668M},
  38     {CLK_36_000M,  CLE266_PLL_36_000M,  K800_PLL_36_000M,  CX700_36_000M},
  39     {CLK_40_000M,  CLE266_PLL_40_000M,  K800_PLL_40_000M,  CX700_40_000M},
  40     {CLK_41_291M,  CLE266_PLL_41_291M,  K800_PLL_41_291M,  CX700_41_291M},
  41     {CLK_43_163M,  CLE266_PLL_43_163M,  K800_PLL_43_163M,  CX700_43_163M},
  42     {CLK_49_500M,  CLE266_PLL_49_500M,  K800_PLL_49_500M,  CX700_49_500M},
  43     {CLK_52_406M,  CLE266_PLL_52_406M,  K800_PLL_52_406M,  CX700_52_406M},
  44     {CLK_56_250M,  CLE266_PLL_56_250M,  K800_PLL_56_250M,  CX700_56_250M},
  45     {CLK_65_000M,  CLE266_PLL_65_000M,  K800_PLL_65_000M,  CX700_65_000M},
  46     {CLK_68_179M,  CLE266_PLL_68_179M,  K800_PLL_68_179M,  CX700_68_179M},
  47     {CLK_78_750M,  CLE266_PLL_78_750M,  K800_PLL_78_750M,  CX700_78_750M},
  48     {CLK_80_136M,  CLE266_PLL_80_136M,  K800_PLL_80_136M,  CX700_80_136M},
  49     {CLK_83_950M,  CLE266_PLL_83_950M,  K800_PLL_83_950M,  CX700_83_950M},
  50     {CLK_85_860M,  CLE266_PLL_85_860M,  K800_PLL_85_860M,  CX700_85_860M},
  51     {CLK_94_500M,  CLE266_PLL_94_500M,  K800_PLL_94_500M,  CX700_94_500M},
  52     {CLK_108_000M, CLE266_PLL_108_000M, K800_PLL_108_000M, CX700_108_000M},
  53     {CLK_125_104M, CLE266_PLL_125_104M, K800_PLL_125_104M, CX700_125_104M},
  54     {CLK_133_308M, CLE266_PLL_133_308M, K800_PLL_133_308M, CX700_133_308M},
  55     {CLK_135_000M, CLE266_PLL_135_000M, K800_PLL_135_000M, CX700_135_000M},
  56     {CLK_157_500M, CLE266_PLL_157_500M, K800_PLL_157_500M, CX700_157_500M},
  57     {CLK_162_000M, CLE266_PLL_162_000M, K800_PLL_162_000M, CX700_162_000M},
  58     {CLK_202_500M, CLE266_PLL_202_500M, K800_PLL_202_500M, CX700_202_500M},
  59     {CLK_234_000M, CLE266_PLL_234_000M, K800_PLL_234_000M, CX700_234_000M},
  60     {CLK_297_500M, CLE266_PLL_297_500M, K800_PLL_297_500M, CX700_297_500M},
  61     {CLK_74_481M,  CLE266_PLL_74_481M,  K800_PLL_74_481M,  CX700_74_481M},
  62     {CLK_172_798M, CLE266_PLL_172_798M, K800_PLL_172_798M, CX700_172_798M}
  63 };
  64
  65 #define NUM_TOTAL_PLL_TABLE ARRAY_SIZE(pll_value)
  66
  67 static struct fifo_depth_select display_fifo_depth_reg= {
  68     // IGA1 FIFO Depth_Select
  69     {IGA1_FIFO_DEPTH_SELECT_REG_NUM, {{SR17,0,7}}},
  70     // IGA2 FIFO Depth_Select
  71     {IGA2_FIFO_DEPTH_SELECT_REG_NUM, {{CR68,4,7}, {CR94,7,7}, {CR95,7,7}}}
  72 };
  73
  74 static struct fifo_threshold_select fifo_threshold_select_reg= {
  75     // IGA1 FIFO Threshold Select
  76     {IGA1_FIFO_THRESHOLD_REG_NUM, {{SR16,0,5},{SR16,7,7}}},
  77     // IGA2 FIFO Threshold Select
  78     {IGA2_FIFO_THRESHOLD_REG_NUM, {{CR68,0,3}, {CR95,4,6}}}
  79 };
  80
  81 static struct fifo_high_threshold_select fifo_high_threshold_select_reg= {
  82     // IGA1 FIFO High Threshold Select
  83     {IGA1_FIFO_HIGH_THRESHOLD_REG_NUM, {{SR18,0,5},{SR18,7,7}}},
  84     // IGA2 FIFO High Threshold Select
  85     {IGA2_FIFO_HIGH_THRESHOLD_REG_NUM, {{CR92,0,3}, {CR95,0,2}}}
  86 };
  87
  88 static struct display_queue_expire_num display_queue_expire_num_reg= {
  89     // IGA1 Display Queue Expire Num
  90     {IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{SR22,0,4}}},
  91     // IGA2 Display Queue Expire Num
  92     {IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{CR94,0,6}}}
  93 };
  94
  95 // Definition Offset Registers
  96 static struct offset offset_reg = {
  97     // IGA1 Offset Register
  98     {IGA1_OFFSET_REG_NUM, {{CR13,0,7},{CR35,5,7}}},
  99     // IGA2 Offset Register
 100     {IGA2_OFFSET_REG_NUM, {{CR66,0,7},{CR67,0,1}}}
 101 };
 102
 103 // Definition Fetch Count Registers
 104 static struct fetch_count fetch_count_reg = {
 105     // IGA1 Fetch Count Register
 106     {IGA1_FETCH_COUNT_REG_NUM, {{SR1C,0,7},{SR1D,0,1}}},
 107     // IGA2 Fetch Count Register
 108     {IGA2_FETCH_COUNT_REG_NUM, {{CR65,0,7},{CR67,2,3}}}
 109 };
 110
 111 // Definition Starting Address Registers
 112 /*static static struct starting_addr starting_addr_reg = {
 113     // IGA1 Starting Address Register
 114     {IGA1_STARTING_ADDR_REG_NUM, {{CR0C,0,7},{CR0D,0,7},{CR34,0,7},{CR48,0,1}}},
 115     // IGA2 Starting Address Register
 116     {IGA2_STARTING_ADDR_REG_NUM, {{CR62,1,7},{CR63,0,7},{CR64,0,7}}}
 117 };*/
 118
 119 #define IGA1_STARTING_ADDR_REG_NUM      4           // location: {CR0C,0,7},{CR0D,0,7},{CR34,0,7},{CR48,0,1}
 120 #define IGA2_STARTING_ADDR_REG_NUM      3           // location: {CR62,1,7},{CR63,0,7},{CR64,0,7}
 121
 122 static struct iga1_crtc_timing iga1_crtc_reg = {
 123     // IGA1 Horizontal Total
 124     {IGA1_HOR_TOTAL_REG_NUM, {{CR00,0,7}, {CR36,3,3}}},
 125     // IGA1 Horizontal Addressable Video
 126     {IGA1_HOR_ADDR_REG_NUM, {{CR01,0,7}}},
 127     // IGA1 Horizontal Blank Start
 128     {IGA1_HOR_BLANK_START_REG_NUM, {{CR02,0,7}}},
 129     // IGA1 Horizontal Blank End
 130     {IGA1_HOR_BLANK_END_REG_NUM, {{CR03,0,4}, {CR05,7,7}, {CR33,5,5}}},
 131     // IGA1 Horizontal Sync Start
 132     {IGA1_HOR_SYNC_START_REG_NUM, {{CR04,0,7}, {CR33,4,4}}},
 133     // IGA1 Horizontal Sync End
 134     {IGA1_HOR_SYNC_END_REG_NUM, {{CR05,0,4}}},
 135     // IGA1 Vertical Total
 136     {IGA1_VER_TOTAL_REG_NUM, {{CR06,0,7}, {CR07,0,0}, {CR07,5,5}, {CR35,0,0}}},
 137     // IGA1 Vertical Addressable Video
 138     {IGA1_VER_ADDR_REG_NUM, {{CR12,0,7}, {CR07,1,1}, {CR07,6,6}, {CR35,2,2}}},
 139     // IGA1 Vertical Blank Start
 140     {IGA1_VER_BLANK_START_REG_NUM, {{CR15,0,7}, {CR07,3,3}, {CR09,5,5}, {CR35,3,3}}},
 141     // IGA1 Vertical Blank End
 142     {IGA1_VER_BLANK_END_REG_NUM, {{CR16,0,7}}},
 143     // IGA1 Vertical Sync Start
 144     {IGA1_VER_SYNC_START_REG_NUM, {{CR10,0,7}, {CR07,2,2}, {CR07,7,7}, {CR35,1,1}}},
 145     // IGA1 Vertical Sync End
 146     {IGA1_VER_SYNC_END_REG_NUM, {{CR11,0,3}}}
 147 };
 148
 149 #if notyet
 150 static struct iga2_shadow_crtc_timing iga2_shadow_crtc_reg = {
 151     // IGA2 Shadow Horizontal Total
 152     {IGA2_SHADOW_HOR_TOTAL_REG_NUM, {{CR6D,0,7}, {CR71,3,3}}},
 153     // IGA2 Shadow Horizontal Blank End
 154     {IGA2_SHADOW_HOR_BLANK_END_REG_NUM, {{CR6E,0,7}}},
 155     // IGA2 Shadow Vertical Total
 156     {IGA2_SHADOW_VER_TOTAL_REG_NUM, {{CR6F,0,7}, {CR71,0,2}}},
 157     // IGA2 Shadow Vertical Addressable Video
 158     {IGA2_SHADOW_VER_ADDR_REG_NUM, {{CR70,0,7}, {CR71,4,6}}},
 159     // IGA2 Shadow Vertical Blank Start
 160     {IGA2_SHADOW_VER_BLANK_START_REG_NUM, {{CR72,0,7}, {CR74,4,6}}},
 161     // IGA2 Shadow Vertical Blank End
 162     {IGA2_SHADOW_VER_BLANK_END_REG_NUM, {{CR73,0,7}, {CR74,0,2}}},
 163     // IGA2 Shadow Vertical Sync Start
 164     {IGA2_SHADOW_VER_SYNC_START_REG_NUM, {{CR75,0,7}, {CR76,4,6}}},
 165     // IGA2 Shadow Vertical Sync End
 166     {IGA2_SHADOW_VER_SYNC_END_REG_NUM, {{CR76,0,3}}}
 167 };
 168
 169 static struct iga2_crtc_timing iga2_crtc_reg = {
 170     // IGA2 Horizontal Total
 171     {IGA2_HOR_TOTAL_REG_NUM, {{CR50,0,7}, {CR55,0,3}}},
 172     // IGA2 Horizontal Addressable Video
 173     {IGA2_HOR_ADDR_REG_NUM, {{CR51,0,7}, {CR55,4,6}}},
 174     // IGA2 Horizontal Blank Start
 175     {IGA2_HOR_BLANK_START_REG_NUM, {{CR52,0,7}, {CR54,0,2}}},
 176     // IGA2 Horizontal Blank End
 177     {IGA2_HOR_BLANK_END_REG_NUM, {{CR53,0,7}, {CR54,3,5}, {CR5D,6,6}}},
 178     // IGA2 Horizontal Sync Start
 179     {IGA2_HOR_SYNC_START_REG_NUM, {{CR56,0,7}, {CR54,6,7}, {CR5C,7,7}}},
 180     // IGA2 Horizontal Sync End
 181     {IGA2_HOR_SYNC_END_REG_NUM, {{CR57,0,7}, {CR5C,6,6}}},
 182     // IGA2 Vertical Total
 183     {IGA2_VER_TOTAL_REG_NUM, {{CR58,0,7}, {CR5D,0,2}}},
 184     // IGA2 Vertical Addressable Video
 185     {IGA2_VER_ADDR_REG_NUM, {{CR59,0,7}, {CR5D,3,5}}},
 186     // IGA2 Vertical Blank Start
 187     {IGA2_VER_BLANK_START_REG_NUM, {{CR5A,0,7}, {CR5C,0,2}}},
 188     // IGA2 Vertical Blank End
 189     {IGA2_VER_BLANK_END_REG_NUM, {{CR5B,0,7}, {CR5C,3,5}}},
 190     // IGA2 Vertical Sync Start
 191     {IGA2_VER_SYNC_START_REG_NUM, {{CR5E,0,7}, {CR5F,5,7}}},
 192     // IGA2 Vertical Sync End
 193     {IGA2_VER_SYNC_END_REG_NUM, {{CR5F,0,4}}}
 194 };
 195
 196 /*static static struct _lcd_pwd_seq_timer lcd_pwd_seq_timer = {
 197     // LCD Power Sequence TD0
 198     {LCD_POWER_SEQ_TD0_REG_NUM, {{CR8B,0,7}, {CR8F,0,3}}},
 199     // LCD Power Sequence TD1
 200     {LCD_POWER_SEQ_TD1_REG_NUM, {{CR8C,0,7}, {CR8F,4,7}}},
 201     // LCD Power Sequence TD2
 202     {LCD_POWER_SEQ_TD2_REG_NUM, {{CR8D,0,7}, {CR90,0,3}}},
 203     // LCD Power Sequence TD3
 204     {LCD_POWER_SEQ_TD3_REG_NUM, {{CR8E,0,7}, {CR90,4,7}}}
 205
 206 };*/
 207
 208 static struct _lcd_scaling_factor lcd_scaling_factor = {
 209     // LCD Horizontal Scaling Factor Register
 210     {LCD_HOR_SCALING_FACTOR_REG_NUM, {{CR9F,0,1}, {CR77,0,7}, {CR79,4,5}}},
 211     // LCD Vertical Scaling Factor Register
 212     {LCD_VER_SCALING_FACTOR_REG_NUM, {{CR79,3,3}, {CR78,0,7}, {CR79,6,7}}}
 213 };
 214 static struct _lcd_scaling_factor lcd_scaling_factor_CLE = {
 215     /* LCD Horizontal Scaling Factor Register */
 216     {LCD_HOR_SCALING_FACTOR_REG_NUM_CLE, {{CR77,0,7}, {CR79,4,5}}},
 217     /* LCD Vertical Scaling Factor Register */
 218     {LCD_VER_SCALING_FACTOR_REG_NUM_CLE, {{CR78,0,7}, {CR79,6,7}}}
 219 };
 220 #endif
 221
 222 static struct rgbLUT palLUT_table[]= {
 223     // {R,G,B}
 224     // Index 0x00~0x03
 225     {0x00, 0x00, 0x00}, {0x00, 0x00, 0x2A}, {0x00, 0x2A, 0x00}, {0x00, 0x2A, 0x2A},
 226     // Index 0x04~0x07
 227     {0x2A, 0x00, 0x00}, {0x2A, 0x00, 0x2A}, {0x2A, 0x15, 0x00}, {0x2A, 0x2A, 0x2A},
 228     // Index 0x08~0x0B
 229     {0x15, 0x15, 0x15}, {0x15, 0x15, 0x3F}, {0x15, 0x3F, 0x15}, {0x15, 0x3F, 0x3F},
 230     // Index 0x0C~0x0F
 231     {0x3F, 0x15, 0x15}, {0x3F, 0x15, 0x3F}, {0x3F, 0x3F, 0x15}, {0x3F, 0x3F, 0x3F},
 232     // Index 0x10~0x13
 233     {0x00, 0x00, 0x00}, {0x05, 0x05, 0x05}, {0x08, 0x08, 0x08}, {0x0B, 0x0B, 0x0B},
 234     // Index 0x14~0x17
 235     {0x0E, 0x0E, 0x0E}, {0x11, 0x11, 0x11}, {0x14, 0x14, 0x14}, {0x18, 0x18, 0x18},
 236     // Index 0x18~0x1B
 237     {0x1C, 0x1C, 0x1C}, {0x20, 0x20, 0x20}, {0x24, 0x24, 0x24}, {0x28, 0x28, 0x28},
 238     // Index 0x1C~0x1F
 239     {0x2D, 0x2D, 0x2D}, {0x32, 0x32, 0x32}, {0x38, 0x38, 0x38}, {0x3F, 0x3F, 0x3F},
 240     // Index 0x20~0x23
 241     {0x00, 0x00, 0x3F}, {0x10, 0x00, 0x3F}, {0x1F, 0x00, 0x3F}, {0x2F, 0x00, 0x3F},
 242     // Index 0x24~0x27
 243     {0x3F, 0x00, 0x3F}, {0x3F, 0x00, 0x2F}, {0x3F, 0x00, 0x1F}, {0x3F, 0x00, 0x10},
 244     // Index 0x28~0x2B
 245     {0x3F, 0x00, 0x00}, {0x3F, 0x10, 0x00}, {0x3F, 0x1F, 0x00}, {0x3F, 0x2F, 0x00},
 246     // Index 0x2C~0x2F
 247     {0x3F, 0x3F, 0x00}, {0x2F, 0x3F, 0x00}, {0x1F, 0x3F, 0x00}, {0x10, 0x3F, 0x00},
 248     // Index 0x30~0x33
 249     {0x00, 0x3F, 0x00}, {0x00, 0x3F, 0x10}, {0x00, 0x3F, 0x1F}, {0x00, 0x3F, 0x2F},
 250     // Index 0x34~0x37
 251     {0x00, 0x3F, 0x3F}, {0x00, 0x2F, 0x3F}, {0x00, 0x1F, 0x3F}, {0x00, 0x10, 0x3F},
 252     // Index 0x38~0x3B
 253     {0x1F, 0x1F, 0x3F}, {0x27, 0x1F, 0x3F}, {0x2F, 0x1F, 0x3F}, {0x37, 0x1F, 0x3F},
 254     // Index 0x3C~0x3F
 255     {0x3F, 0x1F, 0x3F}, {0x3F, 0x1F, 0x37}, {0x3F, 0x1F, 0x2F}, {0x3F, 0x1F, 0x27},
 256     // Index 0x40~0x43
 257     {0x3F, 0x1F, 0x1F}, {0x3F, 0x27, 0x1F}, {0x3F, 0x2F, 0x1F}, {0x3F, 0x3F, 0x1F},
 258     // Index 0x44~0x47
 259     {0x3F, 0x3F, 0x1F}, {0x37, 0x3F, 0x1F}, {0x2F, 0x3F, 0x1F}, {0x27, 0x3F, 0x1F},
 260     // Index 0x48~0x4B
 261     {0x1F, 0x3F, 0x1F}, {0x1F, 0x3F, 0x27}, {0x1F, 0x3F, 0x2F}, {0x1F, 0x3F, 0x37},
 262     // Index 0x4C~0x4F
 263     {0x1F, 0x3F, 0x3F}, {0x1F, 0x37, 0x3F}, {0x1F, 0x2F, 0x3F}, {0x1F, 0x27, 0x3F},
 264     // Index 0x50~0x53
 265     {0x2D, 0x2D, 0x3F}, {0x31, 0x2D, 0x3F}, {0x36, 0x2D, 0x3F}, {0x3A, 0x2D, 0x3F},
 266     // Index 0x54~0x57
 267     {0x3F, 0x2D, 0x3F}, {0x3F, 0x2D, 0x3A}, {0x3F, 0x2D, 0x36}, {0x3F, 0x2D, 0x31},
 268     // Index 0x58~0x5B
 269     {0x3F, 0x2D, 0x2D}, {0x3F, 0x31, 0x2D}, {0x3F, 0x36, 0x2D}, {0x3F, 0x3A, 0x2D},
 270     // Index 0x5C~0x5F
 271     {0x3F, 0x3F, 0x2D}, {0x3A, 0x3F, 0x2D}, {0x36, 0x3F, 0x2D}, {0x31, 0x3F, 0x2D},
 272     // Index 0x60~0x63
 273     {0x2D, 0x3F, 0x2D}, {0x2D, 0x3F, 0x31}, {0x2D, 0x3F, 0x36}, {0x2D, 0x3F, 0x3A},
 274     // Index 0x64~0x67
 275     {0x2D, 0x3F, 0x3F}, {0x2D, 0x3A, 0x3F}, {0x2D, 0x36, 0x3F}, {0x2D, 0x31, 0x3F},
 276     // Index 0x68~0x6B
 277     {0x00, 0x00, 0x1C}, {0x07, 0x00, 0x1C}, {0x0E, 0x00, 0x1C}, {0x15, 0x00, 0x1C},
 278     // Index 0x6C~0x6F
 279     {0x1C, 0x00, 0x1C}, {0x1C, 0x00, 0x15}, {0x1C, 0x00, 0x0E}, {0x1C, 0x00, 0x07},
 280     // Index 0x70~0x73
 281     {0x1C, 0x00, 0x00}, {0x1C, 0x07, 0x00}, {0x1C, 0x0E, 0x00}, {0x1C, 0x15, 0x00},
 282     // Index 0x74~0x77
 283     {0x1C, 0x1C, 0x00}, {0x15, 0x1C, 0x00}, {0x0E, 0x1C, 0x00}, {0x07, 0x1C, 0x00},
 284     // Index 0x78~0x7B
 285     {0x00, 0x1C, 0x00}, {0x00, 0x1C, 0x07}, {0x00, 0x1C, 0x0E}, {0x00, 0x1C, 0x15},
 286     // Index 0x7C~0x7F
 287     {0x00, 0x1C, 0x1C}, {0x00, 0x15, 0x1C}, {0x00, 0x0E, 0x1C}, {0x00, 0x07, 0x1C},
 288     // Index 0x80~0x83
 289     {0x0E, 0x0E, 0x1C}, {0x11, 0x0E, 0x1C}, {0x15, 0x0E, 0x1C}, {0x18, 0x0E, 0x1C},
 290     // Index 0x84~0x87
 291     {0x1C, 0x0E, 0x1C}, {0x1C, 0x0E, 0x18}, {0x1C, 0x0E, 0x15}, {0x1C, 0x0E, 0x11},
 292     // Index 0x88~0x8B
 293     {0x1C, 0x0E, 0x0E}, {0x1C, 0x11, 0x0E}, {0x1C, 0x15, 0x0E}, {0x1C, 0x18, 0x0E},
 294     // Index 0x8C~0x8F
 295     {0x1C, 0x1C, 0x0E}, {0x18, 0x1C, 0x0E}, {0x15, 0x1C, 0x0E}, {0x11, 0x1C, 0x0E},
 296     // Index 0x90~0x93
 297     {0x0E, 0x1C, 0x0E}, {0x0E, 0x1C, 0x11}, {0x0E, 0x1C, 0x15}, {0x0E, 0x1C, 0x18},
 298     // Index 0x94~0x97
 299     {0x0E, 0x1C, 0x1C}, {0x0E, 0x18, 0x1C}, {0x0E, 0x15, 0x1C}, {0x0E, 0x11, 0x1C},
 300     // Index 0x98~0x9B
 301     {0x14, 0x14, 0x1C}, {0x16, 0x14, 0x1C}, {0x18, 0x14, 0x1C}, {0x1A, 0x14, 0x1C},
 302     // Index 0x9C~0x9F
 303     {0x1C, 0x14, 0x1C}, {0x1C, 0x14, 0x1A}, {0x1C, 0x14, 0x18}, {0x1C, 0x14, 0x16},
 304     // Index 0xA0~0xA3
 305     {0x1C, 0x14, 0x14}, {0x1C, 0x16, 0x14}, {0x1C, 0x18, 0x14}, {0x1C, 0x1A, 0x14},
 306     // Index 0xA4~0xA7
 307     {0x1C, 0x1C, 0x14}, {0x1A, 0x1C, 0x14}, {0x18, 0x1C, 0x14}, {0x16, 0x1C, 0x14},
 308     // Index 0xA8~0xAB
 309     {0x14, 0x1C, 0x14}, {0x14, 0x1C, 0x16}, {0x14, 0x1C, 0x18}, {0x14, 0x1C, 0x1A},
 310     // Index 0xAC~0xAF
 311     {0x14, 0x1C, 0x1C}, {0x14, 0x1A, 0x1C}, {0x14, 0x18, 0x1C}, {0x14, 0x16, 0x1C},
 312     // Index 0xB0~0xB3
 313     {0x00, 0x00, 0x10}, {0x04, 0x00, 0x10}, {0x08, 0x00, 0x10}, {0x0C, 0x00, 0x10},
 314     // Index 0xB4~0xB7
 315     {0x10, 0x00, 0x10}, {0x10, 0x00, 0x0C}, {0x10, 0x00, 0x08}, {0x10, 0x00, 0x04},
 316     // Index 0xB8~0xBB
 317     {0x10, 0x00, 0x00}, {0x10, 0x04, 0x00}, {0x10, 0x08, 0x00}, {0x10, 0x0C, 0x00},
 318     // Index 0xBC~0xBF
 319     {0x10, 0x10, 0x00}, {0x0C, 0x10, 0x00}, {0x08, 0x10, 0x00}, {0x04, 0x10, 0x00},
 320     // Index 0xC0~0xC3
 321     {0x00, 0x10, 0x00}, {0x00, 0x10, 0x04}, {0x00, 0x10, 0x08}, {0x00, 0x10, 0x0C},
 322     // Index 0xC4~0xC7
 323     {0x00, 0x10, 0x10}, {0x00, 0x0C, 0x10}, {0x00, 0x08, 0x10}, {0x00, 0x04, 0x10},
 324     // Index 0xC8~0xCB
 325     {0x08, 0x08, 0x10}, {0x0A, 0x08, 0x10}, {0x0C, 0x08, 0x10}, {0x0E, 0x08, 0x10},
 326     // Index 0xCC~0xCF
 327     {0x10, 0x08, 0x10}, {0x10, 0x08, 0x0E}, {0x10, 0x08, 0x0C}, {0x10, 0x08, 0x0A},
 328     // Index 0xD0~0xD3
 329     {0x10, 0x08, 0x08}, {0x10, 0x0A, 0x08}, {0x10, 0x0C, 0x08}, {0x10, 0x0E, 0x08},
 330     // Index 0xD4~0xD7
 331     {0x10, 0x10, 0x08}, {0x0E, 0x10, 0x08}, {0x0C, 0x10, 0x08}, {0x0A, 0x10, 0x08},
 332     // Index 0xD8~0xDB
 333     {0x08, 0x10, 0x08}, {0x08, 0x10, 0x0A}, {0x08, 0x10, 0x0C}, {0x08, 0x10, 0x0E},
 334     // Index 0xDC~0xDF
 335     {0x08, 0x10, 0x10}, {0x08, 0x0E, 0x10}, {0x08, 0x0C, 0x10}, {0x08, 0x0A, 0x10},
 336     // Index 0xE0~0xE3
 337     {0x0B, 0x0B, 0x10}, {0x0C, 0x0B, 0x10}, {0x0D, 0x0B, 0x10}, {0x0F, 0x0B, 0x10},
 338     // Index 0xE4~0xE7
 339     {0x10, 0x0B, 0x10}, {0x10, 0x0B, 0x0F}, {0x10, 0x0B, 0x0D}, {0x10, 0x0B, 0x0C},
 340     // Index 0xE8~0xEB
 341     {0x10, 0x0B, 0x0B}, {0x10, 0x0C, 0x0B}, {0x10, 0x0D, 0x0B}, {0x10, 0x0F, 0x0B},
 342     // Index 0xEC~0xEF
 343     {0x10, 0x10, 0x0B}, {0x0F, 0x10, 0x0B}, {0x0D, 0x10, 0x0B}, {0x0C, 0x10, 0x0B},
 344     // Index 0xF0~0xF3
 345     {0x0B, 0x10, 0x0B}, {0x0B, 0x10, 0x0C}, {0x0B, 0x10, 0x0D}, {0x0B, 0x10, 0x0F},
 346     // Index 0xF4~0xF7
 347     {0x0B, 0x10, 0x10}, {0x0B, 0x0F, 0x10}, {0x0B, 0x0D, 0x10}, {0x0B, 0x0C, 0x10},
 348     // Index 0xF8~0xFB
 349     {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00},
 350     // Index 0xFC~0xFF
 351     {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}
 352 };
 353
 354 #if notyet
 355 static uint16_t red256[] = {
 356 0x0   ,0x0   ,0x0   ,0x0   ,0xa800,0xa800,0xa800,0xa800,0x5400,0x5400,0x5400,0x5400,0xfc00,0xfc00,0xfc00,0xfc00,
 357 0x0   ,0x1400,0x2000,0x2c00,0x3800,0x4400,0x5000,0x6000,0x7000,0x8000,0x9000,0xa000,0xb400,0xc800,0xe000,0xfc00,
 358 0x0   ,0x4000,0x7c00,0xbc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xbc00,0x7c00,0x4000,
 359 0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x7c00,0x9c00,0xbc00,0xdc00,0xfc00,0xfc00,0xfc00,0xfc00,
 360 0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xdc00,0xbc00,0x9c00,0x7c00,0x7c00,0x7c00,0x7c00,0x7c00,0x7c00,0x7c00,0x7c00,
 361 0xb400,0xc400,0xd800,0xe800,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xe800,0xd800,0xc400,
 362 0xb400,0xb400,0xb400,0xb400,0xb400,0xb400,0xb400,0xb400,0x0   ,0x1c00,0x3800,0x5400,0x7000,0x7000,0x7000,0x7000,
 363 0x7000,0x7000,0x7000,0x7000,0x7000,0x5400,0x3800,0x1c00,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,
 364 0x3800,0x4400,0x5400,0x6000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x6000,0x5400,0x4400,
 365 0x3800,0x3800,0x3800,0x3800,0x3800,0x3800,0x3800,0x3800,0x5000,0x5800,0x6000,0x6800,0x7000,0x7000,0x7000,0x7000,
 366 0x7000,0x7000,0x7000,0x7000,0x7000,0x6800,0x6000,0x5800,0x5000,0x5000,0x5000,0x5000,0x5000,0x5000,0x5000,0x5000,
 367 0x0   ,0x1000,0x2000,0x3000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x3000,0x2000,0x1000,
 368 0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x2000,0x2800,0x3000,0x3800,0x4000,0x4000,0x4000,0x4000,
 369 0x4000,0x4000,0x4000,0x4000,0x4000,0x3800,0x3000,0x2800,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,
 370 0x2c00,0x3000,0x3400,0x3c00,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x3c00,0x3400,0x3000,
 371 0x2c00,0x2c00,0x2c00,0x2c00,0x2c00,0x2c00,0x2c00,0x2c00,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x0
 372 };
 373 static uint16_t green256[] = {
 374 0x0   ,0x0   ,0xa800,0xa800,0x0   ,0x0   ,0x5400,0xa800,0x5400,0x5400,0xfc00,0xfc00,0x5400,0x5400,0xfc00,0xfc00,
 375 0x0   ,0x1400,0x2000,0x2c00,0x3800,0x4400,0x5000,0x6000,0x7000,0x8000,0x9000,0xa000,0xb400,0xc800,0xe000,0xfc00,
 376 0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x7c00,0xbc00,0xfc00,0xfc00,0xfc00,0xfc00,
 377 0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xbc00,0x7c00,0x4000,0x7c00,0x7c00,0x7c00,0x7c00,0x7c00,0x7c00,0x7c00,0x7c00,
 378 0x7c00,0x9c00,0xbc00,0xdc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xdc00,0xbc00,0x9c00,
 379 0xb400,0xb400,0xb400,0xb400,0xb400,0xb400,0xb400,0xb400,0xb400,0xc400,0xd800,0xe800,0xfc00,0xfc00,0xfc00,0xfc00,
 380 0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xe800,0xd800,0xc400,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,
 381 0x0   ,0x1c00,0x3800,0x5400,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x5400,0x3800,0x1c00,
 382 0x3800,0x3800,0x3800,0x3800,0x3800,0x3800,0x3800,0x3800,0x3800,0x4400,0x5400,0x6000,0x7000,0x7000,0x7000,0x7000,
 383 0x7000,0x7000,0x7000,0x7000,0x7000,0x6000,0x5400,0x4400,0x5000,0x5000,0x5000,0x5000,0x5000,0x5000,0x5000,0x5000,
 384 0x5000,0x5800,0x6000,0x6800,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x6800,0x6000,0x5800,
 385 0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x1000,0x2000,0x3000,0x4000,0x4000,0x4000,0x4000,
 386 0x4000,0x4000,0x4000,0x4000,0x4000,0x3000,0x2000,0x1000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,
 387 0x2000,0x2800,0x3000,0x3800,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x3800,0x3000,0x2800,
 388 0x2c00,0x2c00,0x2c00,0x2c00,0x2c00,0x2c00,0x2c00,0x2c00,0x2c00,0x3000,0x3400,0x3c00,0x4000,0x4000,0x4000,0x4000,
 389 0x4000,0x4000,0x4000,0x4000,0x4000,0x3c00,0x3400,0x3000,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x0
 390 };
 391 static uint16_t blue256[] = {
 392 0x0   ,0xa800,0x0   ,0xa800,0x0   ,0xa800,0x0   ,0xa800,0x5400,0xfc00,0x5400,0xfc00,0x5400,0xfc00,0x5400,0xfc00,
 393 0x0   ,0x1400,0x2000,0x2c00,0x3800,0x4400,0x5000,0x6000,0x7000,0x8000,0x9000,0xa000,0xb400,0xc800,0xe000,0xfc00,
 394 0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xbc00,0x7c00,0x4000,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,
 395 0x0   ,0x4000,0x7c00,0xbc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xdc00,0xbc00,0x9c00,
 396 0x7c00,0x7c00,0x7c00,0x7c00,0x7c00,0x7c00,0x7c00,0x7c00,0x7c00,0x9c00,0xbc00,0xdc00,0xfc00,0xfc00,0xfc00,0xfc00,
 397 0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xe800,0xd800,0xc400,0xb400,0xb400,0xb400,0xb400,0xb400,0xb400,0xb400,0xb400,
 398 0xb400,0xc400,0xd800,0xe800,0xfc00,0xfc00,0xfc00,0xfc00,0x7000,0x7000,0x7000,0x7000,0x7000,0x5400,0x3800,0x1c00,
 399 0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x1c00,0x3800,0x5400,0x7000,0x7000,0x7000,0x7000,
 400 0x7000,0x7000,0x7000,0x7000,0x7000,0x6000,0x5400,0x4400,0x3800,0x3800,0x3800,0x3800,0x3800,0x3800,0x3800,0x3800,
 401 0x3800,0x4400,0x5400,0x6000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x6800,0x6000,0x5800,
 402 0x5000,0x5000,0x5000,0x5000,0x5000,0x5000,0x5000,0x5000,0x5000,0x5800,0x6000,0x6800,0x7000,0x7000,0x7000,0x7000,
 403 0x4000,0x4000,0x4000,0x4000,0x4000,0x3000,0x2000,0x1000,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,
 404 0x0   ,0x1000,0x2000,0x3000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x3800,0x3000,0x2800,
 405 0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2800,0x3000,0x3800,0x4000,0x4000,0x4000,0x4000,
 406 0x4000,0x4000,0x4000,0x4000,0x4000,0x3c00,0x3400,0x3000,0x2c00,0x2c00,0x2c00,0x2c00,0x2c00,0x2c00,0x2c00,0x2c00,
 407 0x2c00,0x3000,0x3400,0x3c00,0x4000,0x4000,0x4000,0x4000,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x0   ,0x0
 408 };
 409 #endif
 410
 411 #endif /* _DEV_PCI_UNICHROMECONFIG_H */