sys/dev/pci/unichromehw.h

   1 /* $NetBSD$ */
   2
   3 /*
   4  * Copyright 1998-2006 VIA Technologies, Inc. All Rights Reserved.
   5  * Copyright 2001-2006 S3 Graphics, Inc. All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sub license,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHOR(S) OR COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  22  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  23  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  24  * DEALINGS IN THE SOFTWARE.
  25  */
  26
  27 #ifndef _DEV_PCI_UNICHROMEHW_H
  28 #define _DEV_PCI_UNICHROMEHW_H
  29
  30 //***************************************************//
  31 //* Definition IGA1 Design Method of CRTC Registers *//
  32 //***************************************************//
  33 #define IGA1_HOR_TOTAL_FORMULA(x)           ((x)/8)-5
  34 #define IGA1_HOR_ADDR_FORMULA(x)            ((x)/8)-1
  35 #define IGA1_HOR_BLANK_START_FORMULA(x)     ((x)/8)-1
  36 #define IGA1_HOR_BLANK_END_FORMULA(x,y)     ((x+y)/8)-1
  37 #define IGA1_HOR_SYNC_START_FORMULA(x)      ((x)/8)-1
  38 #define IGA1_HOR_SYNC_END_FORMULA(x,y)      ((x+y)/8)-1
  39
  40 #define IGA1_VER_TOTAL_FORMULA(x)           (x)-2
  41 #define IGA1_VER_ADDR_FORMULA(x)            (x)-1
  42 #define IGA1_VER_BLANK_START_FORMULA(x)     (x)-1
  43 #define IGA1_VER_BLANK_END_FORMULA(x,y)     (x+y)-1
  44 #define IGA1_VER_SYNC_START_FORMULA(x)      (x)-1
  45 #define IGA1_VER_SYNC_END_FORMULA(x,y)      (x+y)-1
  46
  47 //***************************************************//
  48 //* Definition IGA2 Design Method of CRTC Registers *//
  49 //***************************************************//
  50 #define IGA2_HOR_TOTAL_FORMULA(x)           (x)-1
  51 #define IGA2_HOR_ADDR_FORMULA(x)            (x)-1
  52 #define IGA2_HOR_BLANK_START_FORMULA(x)     (x)-1
  53 #define IGA2_HOR_BLANK_END_FORMULA(x,y)     (x+y)-1
  54 #define IGA2_HOR_SYNC_START_FORMULA(x)      (x)-1
  55 #define IGA2_HOR_SYNC_END_FORMULA(x,y)      (x+y)-1
  56
  57 #define IGA2_VER_TOTAL_FORMULA(x)           (x)-1
  58 #define IGA2_VER_ADDR_FORMULA(x)            (x)-1
  59 #define IGA2_VER_BLANK_START_FORMULA(x)     (x)-1
  60 #define IGA2_VER_BLANK_END_FORMULA(x,y)     (x+y)-1
  61 #define IGA2_VER_SYNC_START_FORMULA(x)      (x)-1
  62 #define IGA2_VER_SYNC_END_FORMULA(x,y)      (x+y)-1
  63
  64 /**********************************************************/
  65 /* Definition IGA2 Design Method of CRTC Shadow Registers */
  66 /**********************************************************/
  67 #define IGA2_HOR_TOTAL_SHADOW_FORMULA(x)           (x/8)-5
  68 #define IGA2_HOR_BLANK_END_SHADOW_FORMULA(x,y)     ((x+y)/8)-1
  69 #define IGA2_VER_TOTAL_SHADOW_FORMULA(x)           (x)-2
  70 #define IGA2_VER_ADDR_SHADOW_FORMULA(x)            (x)-1
  71 #define IGA2_VER_BLANK_START_SHADOW_FORMULA(x)     (x)-1
  72 #define IGA2_VER_BLANK_END_SHADOW_FORMULA(x,y)     (x+y)-1
  73 #define IGA2_VER_SYNC_START_SHADOW_FORMULA(x)      (x)
  74 #define IGA2_VER_SYNC_END_SHADOW_FORMULA(x,y)      (x+y)
  75
  76 /* Define Register Number for IGA1 CRTC Timing */
  77 #define IGA1_HOR_TOTAL_REG_NUM          2           // location: {CR00,0,7},{CR36,3,3}
  78 #define IGA1_HOR_ADDR_REG_NUM           1           // location: {CR01,0,7}
  79 #define IGA1_HOR_BLANK_START_REG_NUM    1           // location: {CR02,0,7}
  80 #define IGA1_HOR_BLANK_END_REG_NUM      3           // location: {CR03,0,4},{CR05,7,7},{CR33,5,5}
  81 #define IGA1_HOR_SYNC_START_REG_NUM     2           // location: {CR04,0,7},{CR33,4,4}
  82 #define IGA1_HOR_SYNC_END_REG_NUM       1           // location: {CR05,0,4}
  83 #define IGA1_VER_TOTAL_REG_NUM          4           // location: {CR06,0,7},{CR07,0,0},{CR07,5,5},{CR35,0,0}
  84 #define IGA1_VER_ADDR_REG_NUM           4           // location: {CR12,0,7},{CR07,1,1},{CR07,6,6},{CR35,2,2}
  85 #define IGA1_VER_BLANK_START_REG_NUM    4           // location: {CR15,0,7},{CR07,3,3},{CR09,5,5},{CR35,3,3}
  86 #define IGA1_VER_BLANK_END_REG_NUM      1           // location: {CR16,0,7}
  87 #define IGA1_VER_SYNC_START_REG_NUM     4           // location: {CR10,0,7},{CR07,2,2},{CR07,7,7},{CR35,1,1}
  88 #define IGA1_VER_SYNC_END_REG_NUM       1           // location: {CR11,0,3}
  89
  90 /* Define Register Number for IGA2 Shadow CRTC Timing */
  91 #define IGA2_SHADOW_HOR_TOTAL_REG_NUM       2       // location: {CR6D,0,7},{CR71,3,3}
  92 #define IGA2_SHADOW_HOR_BLANK_END_REG_NUM   1       // location: {CR6E,0,7}
  93 #define IGA2_SHADOW_VER_TOTAL_REG_NUM       2       // location: {CR6F,0,7},{CR71,0,2}
  94 #define IGA2_SHADOW_VER_ADDR_REG_NUM        2       // location: {CR70,0,7},{CR71,4,6}
  95 #define IGA2_SHADOW_VER_BLANK_START_REG_NUM 2       // location: {CR72,0,7},{CR74,4,6}
  96 #define IGA2_SHADOW_VER_BLANK_END_REG_NUM   2       // location: {CR73,0,7},{CR74,0,2}
  97 #define IGA2_SHADOW_VER_SYNC_START_REG_NUM  2       // location: {CR75,0,7},{CR76,4,6}
  98 #define IGA2_SHADOW_VER_SYNC_END_REG_NUM    1       // location: {CR76,0,3}
  99
 100 /* Define Register Number for IGA2 CRTC Timing */
 101 #define IGA2_HOR_TOTAL_REG_NUM          2           // location: {CR50,0,7},{CR55,0,3}
 102 #define IGA2_HOR_ADDR_REG_NUM           2           // location: {CR51,0,7},{CR55,4,6}
 103 #define IGA2_HOR_BLANK_START_REG_NUM    2           // location: {CR52,0,7},{CR54,0,2}
 104 #define IGA2_HOR_BLANK_END_REG_NUM      3           // location: {CR53,0,7},{CR54,3,5},{CR5D,6,6}
 105 #define IGA2_HOR_SYNC_START_REG_NUM     3           // location: {CR56,0,7},{CR54,6,7},{CR5C,7,7}
 106 #define IGA2_HOR_SYNC_END_REG_NUM       2           // location: {CR57,0,7},{CR5C,6,6}
 107 #define IGA2_VER_TOTAL_REG_NUM          2           // location: {CR58,0,7},{CR5D,0,2}
 108 #define IGA2_VER_ADDR_REG_NUM           2           // location: {CR59,0,7},{CR5D,3,5}
 109 #define IGA2_VER_BLANK_START_REG_NUM    2           // location: {CR5A,0,7},{CR5C,0,2}
 110 #define IGA2_VER_BLANK_END_REG_NUM      2           // location: {CR5E,0,7},{CR5C,3,5}
 111 #define IGA2_VER_SYNC_START_REG_NUM     2           // location: {CR5E,0,7},{CR5F,5,7}
 112 #define IGA2_VER_SYNC_END_REG_NUM       1           // location: {CR5F,0,4}
 113
 114 /* Define Offset and Fetch Count Register*/
 115 #define IGA1_OFFSET_REG_NUM             2                                 // location: {CR13,0,7},{CR35,5,7}
 116 #define IGA1_OFFSER_ALIGN_BYTE          8                                 // 8 bytes alignment.
 117 #define IGA1_OFFSET_FORMULA(x,y)        (x*y)/IGA1_OFFSER_ALIGN_BYTE      // x: H resolution, y: color depth
 118
 119 #define IGA1_FETCH_COUNT_REG_NUM        2                                 // location: {SR1C,0,7},{SR1D,0,1}
 120 #define IGA1_FETCH_COUNT_ALIGN_BYTE     16                                // 16 bytes alignment.
 121 #define IGA1_FETCH_COUNT_PATCH_VALUE    4                                 // x: H resolution, y: color depth
 122 #define IGA1_FETCH_COUNT_FORMULA(x,y)   ((x*y)/IGA1_FETCH_COUNT_ALIGN_BYTE)+ IGA1_FETCH_COUNT_PATCH_VALUE
 123
 124 #define IGA2_OFFSET_REG_NUM             2           // location: {CR66,0,7},{CR67,0,1}
 125 #define IGA2_OFFSET_ALIGN_BYTE          8
 126 #define IGA2_OFFSET_FORMULA(x,y)        (x*y)/IGA2_OFFSET_ALIGN_BYTE     // x: H resolution, y: color depth
 127
 128 #define IGA2_FETCH_COUNT_REG_NUM        2           // location: {CR65,0,7},{CR67,2,3}
 129 #define IGA2_FETCH_COUNT_ALIGN_BYTE     16
 130 #define IGA2_FETCH_COUNT_PATCH_VALUE    0
 131 #define IGA2_FETCH_COUNT_FORMULA(x,y)   ((x*y)/IGA2_FETCH_COUNT_ALIGN_BYTE)+ IGA2_FETCH_COUNT_PATCH_VALUE
 132
 133 // Staring Address
 134 #define IGA1_STARTING_ADDR_REG_NUM      4           // location: {CR0C,0,7},{CR0D,0,7},{CR34,0,7},{CR48,0,1}
 135 #define IGA2_STARTING_ADDR_REG_NUM      3           // location: {CR62,1,7},{CR63,0,7},{CR64,0,7}
 136
 137 // Define Display OFFSET
 138 // These value are by HW suggested value
 139 #define K800_IGA1_FIFO_MAX_DEPTH                384     // location: {SR17,0,7}
 140 #define K800_IGA1_FIFO_THRESHOLD                328     // location: {SR16,0,5},{SR16,7,7}
 141 #define K800_IGA1_FIFO_HIGH_THRESHOLD           296     // location: {SR18,0,5},{SR18,7,7}
 142 #define K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM      0       // location: {SR22,0,4}. (128/4) =64, K800 must be set zero,
 143                                                         // because HW only 5 bits
 144
 145 #define K800_IGA2_FIFO_MAX_DEPTH                384     // location: {CR68,4,7},{CR94,7,7},{CR95,7,7}
 146 #define K800_IGA2_FIFO_THRESHOLD                328     // location: {CR68,0,3},{CR95,4,6}
 147 #define K800_IGA2_FIFO_HIGH_THRESHOLD           296     // location: {CR92,0,3},{CR95,0,2}
 148 #define K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM      128     // location: {CR94,0,6}
 149
 150 #define P880_IGA1_FIFO_MAX_DEPTH                192     // location: {SR17,0,7}
 151 #define P880_IGA1_FIFO_THRESHOLD                128     // location: {SR16,0,5},{SR16,7,7}
 152 #define P880_IGA1_FIFO_HIGH_THRESHOLD           64      // location: {SR18,0,5},{SR18,7,7}
 153 #define P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM      0       // location: {SR22,0,4}. (128/4) =64, K800 must be set zero,
 154                                                         // because HW only 5 bits
 155
 156 #define P880_IGA2_FIFO_MAX_DEPTH                96      // location: {CR68,4,7},{CR94,7,7},{CR95,7,7}
 157 #define P880_IGA2_FIFO_THRESHOLD                64      // location: {CR68,0,3},{CR95,4,6}
 158 #define P880_IGA2_FIFO_HIGH_THRESHOLD           32      // location: {CR92,0,3},{CR95,0,2}
 159 #define P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM      128     // location: {CR94,0,6}
 160
 161 /* VT3314 chipset*/
 162 #define CN900_IGA1_FIFO_MAX_DEPTH               96 /* location: {SR17,0,7}*/
 163 #define CN900_IGA1_FIFO_THRESHOLD               80 /* location: {SR16,0,5},{SR16,7,7}*/
 164 #define CN900_IGA1_FIFO_HIGH_THRESHOLD          64  /* location: {SR18,0,5},{SR18,7,7}*/
 165 #define CN900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     0   /* location: {SR22,0,4}. (128/4) =64, P800 must be set zero, because HW only 5 bits*/
 166
 167 #define CN900_IGA2_FIFO_MAX_DEPTH               96  /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7}*/
 168 #define CN900_IGA2_FIFO_THRESHOLD               80  /* location: {CR68,0,3},{CR95,4,6}*/
 169 #define CN900_IGA2_FIFO_HIGH_THRESHOLD          32  /* location: {CR92,0,3},{CR95,0,2}*/
 170 #define CN900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     128 /* location: {CR94,0,6}*/
 171
 172 /* For VT3324, these values are suggested by HW */
 173 #define CX700_IGA1_FIFO_MAX_DEPTH               192     /* location: {SR17,0,7}*/
 174 #define CX700_IGA1_FIFO_THRESHOLD               128     /* location: {SR16,0,5},{SR16,7,7}*/
 175 #define CX700_IGA1_FIFO_HIGH_THRESHOLD          128     /* location: {SR18,0,5},{SR18,7,7} */
 176 #define CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     124     /* location: {SR22,0,4} */
 177
 178 #define CX700_IGA2_FIFO_MAX_DEPTH               96      /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7}*/
 179 #define CX700_IGA2_FIFO_THRESHOLD               64      /* location: {CR68,0,3},{CR95,4,6}*/
 180 #define CX700_IGA2_FIFO_HIGH_THRESHOLD          32      /* location: {CR92,0,3},{CR95,0,2} */
 181 #define CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     128     /* location: {CR94,0,6}*/
 182
 183 #define IGA1_FIFO_DEPTH_SELECT_REG_NUM          1
 184 #define IGA1_FIFO_THRESHOLD_REG_NUM             2
 185 #define IGA1_FIFO_HIGH_THRESHOLD_REG_NUM        2
 186 #define IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM   1
 187
 188 #define IGA2_FIFO_DEPTH_SELECT_REG_NUM          3
 189 #define IGA2_FIFO_THRESHOLD_REG_NUM             2
 190 #define IGA2_FIFO_HIGH_THRESHOLD_REG_NUM        2
 191 #define IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM   1
 192
 193
 194 #define IGA1_FIFO_DEPTH_SELECT_FORMULA(x)                   (x/2)-1
 195 #define IGA1_FIFO_THRESHOLD_FORMULA(x)                      (x/4)
 196 #define IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(x)            (x/4)
 197 #define IGA1_FIFO_HIGH_THRESHOLD_FORMULA(x)                 (x/4)
 198 #define IGA2_FIFO_DEPTH_SELECT_FORMULA(x)                   ((x/2)/4)-1
 199 #define IGA2_FIFO_THRESHOLD_FORMULA(x)                      (x/4)
 200 #define IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(x)            (x/4)
 201 #define IGA2_FIFO_HIGH_THRESHOLD_FORMULA(x)                 (x/4)
 202
 203 /************************************************************************/
 204 /*  LCD Timing                                                          */
 205 /************************************************************************/
 206 #define LCD_POWER_SEQ_TD0               500000         // 500 ms = 500000 us
 207 #define LCD_POWER_SEQ_TD1               50000          // 50 ms = 50000 us
 208 #define LCD_POWER_SEQ_TD2               0              // 0 us
 209 #define LCD_POWER_SEQ_TD3               210000         // 210 ms = 210000 us
 210
 211 #define CLE266_POWER_SEQ_UNIT           71             // 2^10 * (1/14.31818M) = 71.475 us (K400.revA)
 212 #define K800_POWER_SEQ_UNIT             142            // 2^11 * (1/14.31818M) = 142.95 us (K400.revB)
 213 #define P880_POWER_SEQ_UNIT             572            // 2^13 * (1/14.31818M) = 572.1 us
 214
 215 #define CLE266_POWER_SEQ_FORMULA(x)     (x)/CLE266_POWER_SEQ_UNIT
 216 #define K800_POWER_SEQ_FORMULA(x)       (x)/K800_POWER_SEQ_UNIT
 217 #define P880_POWER_SEQ_FORMULA(x)       (x)/P880_POWER_SEQ_UNIT
 218
 219
 220 #define LCD_POWER_SEQ_TD0_REG_NUM       2   // location: {CR8B,0,7},{CR8F,0,3}
 221 #define LCD_POWER_SEQ_TD1_REG_NUM       2   // location: {CR8C,0,7},{CR8F,4,7}
 222 #define LCD_POWER_SEQ_TD2_REG_NUM       2   // location: {CR8D,0,7},{CR90,0,3}
 223 #define LCD_POWER_SEQ_TD3_REG_NUM       2   // location: {CR8E,0,7},{CR90,4,7}
 224
 225
 226 // LCD Scaling factor
 227 // x: indicate setting horizontal size
 228 // y: indicate panel horizontal size
 229
 230 #define CLE266_LCD_HOR_SCF_FORMULA(x,y)   (((x-1)*1024)/(y-1))    // Horizontal scaling factor 10 bits (2^10)
 231 #define CLE266_LCD_VER_SCF_FORMULA(x,y)   (((x-1)*1024)/(y-1))    // Vertical scaling factor 10 bits (2^10)
 232 #define K800_LCD_HOR_SCF_FORMULA(x,y)     (((x-1)*4096)/(y-1))    // Horizontal scaling factor 10 bits (2^12)
 233 #define K800_LCD_VER_SCF_FORMULA(x,y)     (((x-1)*2048)/(y-1))    // Vertical scaling factor 10 bits (2^11)
 234
 235 #define LCD_HOR_SCALING_FACTOR_REG_NUM  3   // location: {CR9F,0,1},{CR77,0,7},{CR79,4,5}
 236 #define LCD_VER_SCALING_FACTOR_REG_NUM  3   // location: {CR79,3,3},{CR78,0,7},{CR79,6,7}
 237 #define LCD_HOR_SCALING_FACTOR_REG_NUM_CLE  2               /* location: {CR77,0,7},{CR79,4,5} */
 238 #define LCD_VER_SCALING_FACTOR_REG_NUM_CLE  2               /* location: {CR78,0,7},{CR79,6,7} */
 239
 240
 241
 242 //************************************************//
 243 //*      Define IGA1 Display Timing              *//
 244 //************************************************//
 245 struct io_register {
 246     uint8_t      io_addr;
 247     uint8_t      start_bit;
 248     uint8_t      end_bit;
 249 };
 250
 251
 252 /* IGA1 Horizontal Total */
 253 struct iga1_hor_total
 254 {
 255     int     reg_num;
 256     struct  io_register reg[IGA1_HOR_TOTAL_REG_NUM];
 257 };
 258
 259 /* IGA1 Horizontal Addressable Video */
 260 struct iga1_hor_addr {
 261     int     reg_num;
 262     struct  io_register reg[IGA1_HOR_ADDR_REG_NUM];
 263 };
 264
 265 /* IGA1 Horizontal Blank Start */
 266 struct iga1_hor_blank_start {
 267     int     reg_num;
 268     struct  io_register reg[IGA1_HOR_BLANK_START_REG_NUM];
 269 };
 270
 271 /* IGA1 Horizontal Blank End */
 272 struct iga1_hor_blank_end {
 273     int     reg_num;
 274     struct  io_register reg[IGA1_HOR_BLANK_END_REG_NUM];
 275 };
 276
 277 /* IGA1 Horizontal Sync Start */
 278 struct iga1_hor_sync_start {
 279     int     reg_num;
 280     struct  io_register reg[IGA1_HOR_SYNC_START_REG_NUM];
 281 };
 282
 283 /* IGA1 Horizontal Sync End */
 284 struct iga1_hor_sync_end {
 285     int     reg_num;
 286     struct  io_register reg[IGA1_HOR_SYNC_END_REG_NUM];
 287 };
 288
 289 /* IGA1 Vertical Total */
 290 struct iga1_ver_total {
 291     int     reg_num;
 292     struct  io_register reg[IGA1_VER_TOTAL_REG_NUM];
 293 };
 294
 295 /* IGA1 Vertical Addressable Video */
 296 struct iga1_ver_addr {
 297     int     reg_num;
 298     struct  io_register reg[IGA1_VER_ADDR_REG_NUM];
 299 };
 300
 301 /* IGA1 Vertical Blank Start */
 302 struct iga1_ver_blank_start {
 303     int     reg_num;
 304     struct  io_register reg[IGA1_VER_BLANK_START_REG_NUM];
 305 };
 306
 307 /* IGA1 Vertical Blank End */
 308 struct iga1_ver_blank_end {
 309     int     reg_num;
 310     struct  io_register reg[IGA1_VER_BLANK_END_REG_NUM];
 311 };
 312
 313 /* IGA1 Vertical Sync Start */
 314 struct iga1_ver_sync_start {
 315     int     reg_num;
 316     struct  io_register reg[IGA1_VER_SYNC_START_REG_NUM];
 317 };
 318
 319 /* IGA1 Vertical Sync End */
 320 struct iga1_ver_sync_end {
 321     int     reg_num;
 322     struct  io_register reg[IGA1_VER_SYNC_END_REG_NUM];
 323 };
 324
 325 //************************************************//
 326 //      Define IGA2 Shadow Display Timing         //
 327 //************************************************//
 328
 329 /* IGA2 Shadow Horizontal Total */
 330 struct iga2_shadow_hor_total
 331 {
 332     int     reg_num;
 333     struct  io_register reg[IGA2_SHADOW_HOR_TOTAL_REG_NUM];
 334 };
 335
 336 /* IGA2 Shadow Horizontal Blank End */
 337 struct iga2_shadow_hor_blank_end {
 338     int     reg_num;
 339     struct  io_register reg[IGA2_SHADOW_HOR_BLANK_END_REG_NUM];
 340 };
 341
 342
 343 /* IGA2 Shadow Vertical Total */
 344 struct iga2_shadow_ver_total {
 345     int     reg_num;
 346     struct  io_register reg[IGA2_SHADOW_VER_TOTAL_REG_NUM];
 347 };
 348
 349 /* IGA2 Shadow Vertical Addressable Video */
 350 struct iga2_shadow_ver_addr {
 351     int     reg_num;
 352     struct  io_register reg[IGA2_SHADOW_VER_ADDR_REG_NUM];
 353 };
 354
 355 /* IGA2 Shadow Vertical Blank Start */
 356 struct iga2_shadow_ver_blank_start {
 357     int     reg_num;
 358     struct  io_register reg[IGA2_SHADOW_VER_BLANK_START_REG_NUM];
 359 };
 360
 361 /* IGA2 Shadow Vertical Blank End */
 362 struct iga2_shadow_ver_blank_end {
 363     int     reg_num;
 364     struct  io_register reg[IGA2_SHADOW_VER_BLANK_END_REG_NUM];
 365 };
 366
 367 /* IGA2 Shadow Vertical Sync Start */
 368 struct iga2_shadow_ver_sync_start {
 369     int     reg_num;
 370     struct  io_register reg[IGA2_SHADOW_VER_SYNC_START_REG_NUM];
 371 };
 372
 373 /* IGA2 Shadow Vertical Sync End */
 374 struct iga2_shadow_ver_sync_end {
 375     int     reg_num;
 376     struct  io_register reg[IGA2_SHADOW_VER_SYNC_END_REG_NUM];
 377 };
 378
 379 //************************************************//
 380 //      Define IGA2 Display Timing                //
 381 //************************************************//
 382
 383 /* IGA2 Horizontal Total */
 384 struct iga2_hor_total {
 385     int     reg_num;
 386     struct  io_register reg[IGA2_HOR_TOTAL_REG_NUM];
 387 };
 388
 389 /* IGA2 Horizontal Addressable Video */
 390 struct iga2_hor_addr {
 391     int     reg_num;
 392     struct  io_register reg[IGA2_HOR_ADDR_REG_NUM];
 393 };
 394
 395 /* IGA2 Horizontal Blank Start */
 396 struct iga2_hor_blank_start {
 397     int     reg_num;
 398     struct  io_register reg[IGA2_HOR_BLANK_START_REG_NUM];
 399 };
 400
 401 /* IGA2 Horizontal Blank End */
 402 struct iga2_hor_blank_end {
 403     int     reg_num;
 404     struct  io_register reg[IGA2_HOR_BLANK_END_REG_NUM];
 405 };
 406
 407 /* IGA2 Horizontal Sync Start */
 408 struct iga2_hor_sync_start {
 409     int     reg_num;
 410     struct  io_register reg[IGA2_HOR_SYNC_START_REG_NUM];
 411 };
 412
 413 /* IGA2 Horizontal Sync End */
 414 struct iga2_hor_sync_end {
 415     int     reg_num;
 416     struct  io_register reg[IGA2_HOR_SYNC_END_REG_NUM];
 417 };
 418
 419 /* IGA2 Vertical Total */
 420 struct iga2_ver_total {
 421     int     reg_num;
 422     struct  io_register reg[IGA2_VER_TOTAL_REG_NUM];
 423 };
 424
 425 /* IGA2 Vertical Addressable Video */
 426 struct iga2_ver_addr {
 427     int     reg_num;
 428     struct  io_register reg[IGA2_VER_ADDR_REG_NUM];
 429 };
 430
 431 /* IGA2 Vertical Blank Start */
 432 struct iga2_ver_blank_start {
 433     int     reg_num;
 434     struct  io_register reg[IGA2_VER_BLANK_START_REG_NUM];
 435 };
 436
 437 /* IGA2 Vertical Blank End */
 438 struct iga2_ver_blank_end {
 439     int     reg_num;
 440     struct  io_register reg[IGA2_VER_BLANK_END_REG_NUM];
 441 };
 442
 443 /* IGA2 Vertical Sync Start */
 444 struct iga2_ver_sync_start {
 445     int     reg_num;
 446     struct  io_register reg[IGA2_VER_SYNC_START_REG_NUM];
 447 };
 448
 449 /* IGA2 Vertical Sync End */
 450 struct iga2_ver_sync_end {
 451     int     reg_num;
 452     struct  io_register reg[IGA2_VER_SYNC_END_REG_NUM];
 453 };
 454
 455 /* IGA1 Offset Register */
 456 struct iga1_offset {
 457     int     reg_num;
 458     struct  io_register reg[IGA1_OFFSET_REG_NUM];
 459 };
 460
 461 /* IGA2 Offset Register */
 462 struct iga2_offset {
 463     int     reg_num;
 464     struct  io_register reg[IGA2_OFFSET_REG_NUM];
 465 };
 466
 467 struct offset{
 468     struct iga1_offset            iga1_offset_reg;
 469     struct iga2_offset            iga2_offset_reg;
 470 };
 471
 472 /* IGA1 Fetch Count Register */
 473 struct iga1_fetch_count {
 474     int     reg_num;
 475     struct  io_register reg[IGA1_FETCH_COUNT_REG_NUM];
 476 };
 477
 478 /* IGA2 Fetch Count Register */
 479 struct iga2_fetch_count {
 480     int     reg_num;
 481     struct  io_register reg[IGA2_FETCH_COUNT_REG_NUM];
 482 };
 483
 484 struct fetch_count{
 485     struct iga1_fetch_count       iga1_fetch_count_reg;
 486     struct iga2_fetch_count       iga2_fetch_count_reg;
 487 };
 488
 489 /* Starting Address Register */
 490 struct iga1_starting_addr {
 491     int     reg_num;
 492     struct  io_register reg[IGA1_STARTING_ADDR_REG_NUM];
 493 };
 494
 495 struct iga2_starting_addr {
 496     int     reg_num;
 497     struct  io_register reg[IGA2_STARTING_ADDR_REG_NUM];
 498 };
 499
 500 struct starting_addr {
 501     struct iga1_starting_addr       iga1_starting_addr_reg;
 502     struct iga2_starting_addr       iga2_starting_addr_reg;
 503 };
 504
 505 /* LCD Power Sequence Timer */
 506 struct lcd_pwd_seq_td0{
 507     int     reg_num;
 508     struct  io_register reg[LCD_POWER_SEQ_TD0_REG_NUM];
 509 };
 510
 511 struct lcd_pwd_seq_td1{
 512     int     reg_num;
 513     struct  io_register reg[LCD_POWER_SEQ_TD1_REG_NUM];
 514 };
 515
 516 struct lcd_pwd_seq_td2{
 517     int     reg_num;
 518     struct  io_register reg[LCD_POWER_SEQ_TD2_REG_NUM];
 519 };
 520
 521 struct lcd_pwd_seq_td3{
 522     int     reg_num;
 523     struct  io_register reg[LCD_POWER_SEQ_TD3_REG_NUM];
 524 };
 525
 526 struct _lcd_pwd_seq_timer{
 527     struct lcd_pwd_seq_td0       td0;
 528     struct lcd_pwd_seq_td1       td1;
 529     struct lcd_pwd_seq_td2       td2;
 530     struct lcd_pwd_seq_td3       td3;
 531 };
 532
 533 /* LCD Scaling Factor */
 534 struct _lcd_hor_scaling_factor{
 535     int     reg_num;
 536     struct  io_register reg[LCD_HOR_SCALING_FACTOR_REG_NUM];
 537 };
 538
 539 struct _lcd_ver_scaling_factor{
 540     int     reg_num;
 541     struct  io_register reg[LCD_VER_SCALING_FACTOR_REG_NUM];
 542 };
 543
 544
 545 struct _lcd_scaling_factor{
 546     struct _lcd_hor_scaling_factor  lcd_hor_scaling_factor;
 547     struct _lcd_ver_scaling_factor  lcd_ver_scaling_factor;
 548 };
 549
 550 struct pll_map {
 551     uint32_t     clk;
 552     uint32_t     cle266_pll;
 553     uint32_t     k800_pll;
 554     uint32_t     cx700_pll;
 555 };
 556
 557 struct rgbLUT {
 558     uint8_t     red;
 559     uint8_t     green;
 560     uint8_t     blue;
 561 };
 562
 563 struct lcd_pwd_seq_timer {
 564     uint16_t     td0;
 565     uint16_t     td1;
 566     uint16_t     td2;
 567     uint16_t     td3;
 568 };
 569
 570
 571 // Display FIFO Relation Registers
 572 struct iga1_fifo_depth_select {
 573     int     reg_num;
 574     struct  io_register reg[IGA1_FIFO_DEPTH_SELECT_REG_NUM];
 575 };
 576
 577 struct iga1_fifo_threshold_select {
 578     int     reg_num;
 579     struct  io_register reg[IGA1_FIFO_THRESHOLD_REG_NUM];
 580 };
 581
 582 struct iga1_fifo_high_threshold_select {
 583     int     reg_num;
 584     struct  io_register reg[IGA1_FIFO_HIGH_THRESHOLD_REG_NUM];
 585 };
 586
 587 struct iga1_display_queue_expire_num {
 588     int     reg_num;
 589     struct  io_register reg[IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM];
 590 };
 591
 592 struct iga2_fifo_depth_select {
 593     int     reg_num;
 594     struct  io_register reg[IGA2_FIFO_DEPTH_SELECT_REG_NUM];
 595 };
 596
 597 struct iga2_fifo_threshold_select {
 598     int     reg_num;
 599     struct  io_register reg[IGA2_FIFO_THRESHOLD_REG_NUM];
 600 };
 601
 602 struct iga2_fifo_high_threshold_select {
 603     int     reg_num;
 604     struct  io_register reg[IGA2_FIFO_HIGH_THRESHOLD_REG_NUM];
 605 };
 606
 607 struct iga2_display_queue_expire_num {
 608     int     reg_num;
 609     struct  io_register reg[IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM];
 610 };
 611
 612 struct fifo_depth_select {
 613     struct  iga1_fifo_depth_select iga1_fifo_depth_select_reg;
 614     struct  iga2_fifo_depth_select iga2_fifo_depth_select_reg;
 615 };
 616
 617 struct fifo_threshold_select {
 618     struct  iga1_fifo_threshold_select iga1_fifo_threshold_select_reg;
 619     struct  iga2_fifo_threshold_select iga2_fifo_threshold_select_reg;
 620 };
 621
 622 struct fifo_high_threshold_select {
 623     struct  iga1_fifo_high_threshold_select iga1_fifo_high_threshold_select_reg;
 624     struct  iga2_fifo_high_threshold_select iga2_fifo_high_threshold_select_reg;
 625 };
 626
 627 struct display_queue_expire_num {
 628     struct  iga1_display_queue_expire_num iga1_display_queue_expire_num_reg;
 629     struct  iga2_display_queue_expire_num iga2_display_queue_expire_num_reg;
 630 };
 631
 632
 633
 634 struct iga1_crtc_timing {
 635     struct iga1_hor_total         hor_total;
 636     struct iga1_hor_addr          hor_addr;
 637     struct iga1_hor_blank_start   hor_blank_start;
 638     struct iga1_hor_blank_end     hor_blank_end;
 639     struct iga1_hor_sync_start    hor_sync_start;
 640     struct iga1_hor_sync_end      hor_sync_end;
 641     struct iga1_ver_total         ver_total;
 642     struct iga1_ver_addr          ver_addr;
 643     struct iga1_ver_blank_start   ver_blank_start;
 644     struct iga1_ver_blank_end     ver_blank_end;
 645     struct iga1_ver_sync_start    ver_sync_start;
 646     struct iga1_ver_sync_end      ver_sync_end;
 647 };
 648
 649 struct iga2_shadow_crtc_timing {
 650     struct iga2_shadow_hor_total        hor_total_shadow;
 651     struct iga2_shadow_hor_blank_end    hor_blank_end_shadow;
 652     struct iga2_shadow_ver_total        ver_total_shadow;
 653     struct iga2_shadow_ver_addr         ver_addr_shadow;
 654     struct iga2_shadow_ver_blank_start  ver_blank_start_shadow;
 655     struct iga2_shadow_ver_blank_end    ver_blank_end_shadow;
 656     struct iga2_shadow_ver_sync_start   ver_sync_start_shadow;
 657     struct iga2_shadow_ver_sync_end     ver_sync_end_shadow;
 658 };
 659
 660 struct iga2_crtc_timing {
 661     struct iga2_hor_total         hor_total;
 662     struct iga2_hor_addr          hor_addr;
 663     struct iga2_hor_blank_start   hor_blank_start;
 664     struct iga2_hor_blank_end     hor_blank_end;
 665     struct iga2_hor_sync_start    hor_sync_start;
 666     struct iga2_hor_sync_end      hor_sync_end;
 667     struct iga2_ver_total         ver_total;
 668     struct iga2_ver_addr          ver_addr;
 669     struct iga2_ver_blank_start   ver_blank_start;
 670     struct iga2_ver_blank_end     ver_blank_end;
 671     struct iga2_ver_sync_start    ver_sync_start;
 672     struct iga2_ver_sync_end      ver_sync_end;
 673 };
 674
 675 #endif /* _DEV_PCI_UNICHROMEHW_H */