Expand PMF_FN_* macros.
[netbsd-mini2440.git] / sys / dev / qbus / if_qereg.h
blob3438abda1e8702dd8ab234dbca9540f04482eba5
1 /* $NetBSD: if_qereg.h,v 1.6.22.4 2005/03/04 16:49:54 skrll Exp $ */
2 /*
3 * Copyright (c) 1988 Regents of the University of California.
4 * All rights reserved.
6 * This code is derived from software contributed to Berkeley by
7 * Digital Equipment Corp.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
33 * @(#)if_qereg.h 7.3 (Berkeley) 6/28/90
36 /* @(#)if_qereg.h 1.2 (ULTRIX) 1/3/85 */
38 /****************************************************************
39 * *
40 * Licensed from Digital Equipment Corporation *
41 * Copyright (c) *
42 * Digital Equipment Corporation *
43 * Maynard, Massachusetts *
44 * 1985, 1986 *
45 * All rights reserved. *
46 * *
47 * The Information in this software is subject to change *
48 * without notice and should not be construed as a commitment *
49 * by Digital Equipment Corporation. Digital makes no *
50 * representations about the suitability of this software for *
51 * any purpose. It is supplied "As Is" without expressed or *
52 * implied warranty. *
53 * *
54 * If the Regents of the University of California or its *
55 * licensees modify the software in a manner creating *
56 * derivative copyright rights, appropriate copyright *
57 * legends may be placed on the derivative work in addition *
58 * to that set forth above. *
59 * *
60 ****************************************************************/
61 /* ---------------------------------------------------------------------
62 * Modification History
64 * 13 Feb. 84 -- rjl
66 * Initial version of driver. derived from IL driver.
68 * ---------------------------------------------------------------------
72 * Digital Q-BUS to NI Adapter
74 #ifdef notdef
75 struct qedevice {
76 u_short qe_sta_addr[2]; /* Station address (actually 6 */
77 u_short qe_rcvlist_lo; /* Receive list lo address */
78 u_short qe_rcvlist_hi; /* Receive list hi address */
79 u_short qe_xmtlist_lo; /* Transmit list lo address */
80 u_short qe_xmtlist_hi; /* Transmit list hi address */
81 u_short qe_vector; /* Interrupt vector */
82 u_short qe_csr; /* Command and Status Register */
84 #endif
87 * Register offsets in register space.
89 #define QE_CSR_ADDR1 0
90 #define QE_CSR_ADDR2 2
91 #define QE_CSR_RCLL 4
92 #define QE_CSR_RCLH 6
93 #define QE_CSR_XMTL 8
94 #define QE_CSR_XMTH 10
95 #define QE_CSR_VECTOR 12
96 #define QE_CSR_CSR 14
99 * Command and status bits (csr)
101 #define QE_RCV_ENABLE 0x0001 /* Receiver enable */
102 #define QE_RESET 0x0002 /* Software reset */
103 #define QE_NEX_MEM_INT 0x0004 /* Non existent mem interrupt */
104 #define QE_LOAD_ROM 0x0008 /* Load boot/diag from rom */
105 #define QE_XL_INVALID 0x0010 /* Transmit list invalid */
106 #define QE_RL_INVALID 0x0020 /* Receive list invalid */
107 #define QE_INT_ENABLE 0x0040 /* Interrupt enable */
108 #define QE_XMIT_INT 0x0080 /* Transmit interrupt */
109 #define QE_ILOOP 0x0100 /* Internal loopback */
110 #define QE_ELOOP 0x0200 /* External loopback */
111 #define QE_STIM_ENABLE 0x0400 /* Sanity timer enable */
112 #define QE_POWERUP 0x1000 /* Tranceiver power on */
113 #define QE_CARRIER 0x2000 /* Carrier detect */
114 #define QE_RCV_INT 0x8000 /* Receiver interrupt */
117 * Transmit and receive ring discriptor ---------------------------
119 * The QNA uses the flag, status1 and the valid bit as a handshake/semiphore
120 * mechinism.
122 * The flag word is written on ( bits 15,15 set to 1 ) when it reads the
123 * descriptor. If the valid bit is set it considers the address to be valid.
124 * When it uses the buffer pointed to by the valid address it sets status word
125 * one.
127 struct qe_ring {
128 u_short qe_flag; /* Buffer utilization flags */
129 u_short qe_addr_hi;
130 u_short qe_addr_lo; /* Low order bits of address */
131 short qe_buf_len; /* Negative buffer length */
132 u_short qe_status1; /* Status word one */
133 u_short qe_status2; /* Status word two */
137 * High word address control bits.
139 #define QE_VALID 0x8000
140 #define QE_CHAIN 0x4000
141 #define QE_EOMSG 0x2000
142 #define QE_SETUP 0x1000
143 #define QE_ODDEND 0x0080
144 #define QE_ODDBEGIN 0x0040
147 * Status word definations (receive)
148 * word1
150 #define QE_OVF 0x0001 /* Receiver overflow */
151 #define QE_CRCERR 0x0002 /* CRC error */
152 #define QE_FRAME 0x0004 /* Framing alignment error */
153 #define QE_SHORT 0x0008 /* Packet size < 10 bytes */
154 #define QE_RBL_HI 0x0700 /* Hi bits of receive len */
155 #define QE_RUNT 0x0800 /* Runt packet */
156 #define QE_DISCARD 0x1000 /* Discard the packet */
157 #define QE_ESETUP 0x2000 /* Looped back setup or eloop */
158 #define QE_ERROR 0x4000 /* Receiver error */
159 #define QE_LASTNOT 0x8000 /* Not the last in the packet */
160 /* word2 */
161 #define QE_RBL_LO 0x00ff /* Low bits of receive len */
164 * Status word definations (transmit)
165 * word1
167 #define QE_CCNT 0x00f0 /* Collision count this packet */
168 #define QE_FAIL 0x0100 /* Heart beat check failure */
169 #define QE_ABORT 0x0200 /* Transmission abort */
170 #define QE_STE16 0x0400 /* Sanity timer default on */
171 #define QE_NOCAR 0x0800 /* No carrier */
172 #define QE_LOSS 0x1000 /* Loss of carrier while xmit */
173 /* word2 */
174 #define QE_TDR 0x3fff /* Time domain reflectometry */
177 * General constant definations
179 #define QEALLOC 0 /* Allocate an mbuf */
180 #define QENOALLOC 1 /* No mbuf allocation */
181 #define QEDEALLOC 2 /* Release an mbuf chain */
183 #define QE_NOTYET 0x8000 /* Descriptor not in use yet */
184 #define QE_INUSE 0x4000 /* Descriptor being used by QNA */
185 #define QE_MASK 0xc000 /* Lastnot/error/used mask */
188 * Values for the length of the setup packet that control reception filter.
190 #define QE_SETUPLEN 128 /* Size of setup packet */
191 #define QE_ALLMULTI 1 /* Receive all multicasts */
192 #define QE_PROMISC 2 /* Receive all packets */