1 /* $NetBSD: sfbreg.h,v 1.2 1999/10/20 02:44:48 nisimura Exp $ */
4 * Copyright (c) 1996 Carnegie-Mellon University.
7 * Author: Chris G. Demetriou
9 * Permission to use, copy, modify and distribute this software and
10 * its documentation is hereby granted, provided that both the copyright
11 * notice and this permission notice appear in all copies of the
12 * software, derivative works or modified versions, and any portions
13 * thereof, and that both notices appear in supporting documentation.
15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
19 * Carnegie Mellon requests users of this software to return to
21 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
22 * School of Computer Science
23 * Carnegie Mellon University
24 * Pittsburgh PA 15213-3890
26 * any improvements or extensions that they make and grant Carnegie the
27 * rights to redistribute these changes.
31 * Smart ("CXTurbo") Frame Buffer definitions, from:
32 * ``DEC 3000 300/400/500/600/700/800/900 AXP Models System Prgrammer's Manual''
33 * (DEC order number EK-D3SYS-PM), section 6.
35 * All definitions are in "dense" TURBOchannel space.
38 #ifndef _DEV_TC_SFBREG_H_
39 #define _DEV_TC_SFBREG_H_
42 * Size of the SFB address space.
44 #define SFB_SIZE 0x1000000
47 * Offsets into slot space of each functional unit.
49 #define SFB_ASIC_OFFSET 0x0100000 /* SFB ASIC Control Registers */
50 #define SFB_ASIC_SIZE 0x0020000
51 #define SFB_RAMDAC_OFFSET 0x01c0000 /* BrookTree RAMDAC */
52 #define SFB_RAMDAC_SIZE 0x0040000
53 #define SFB_FB_OFFSET 0x0200000 /* Frame buffer */
54 #define SFB_FB_SIZE 0x0200000
55 #define SFB_OSBM_OFFSET 0x0600000 /* Off-screen buffer memory */
56 #define SFB_OSBM_SIZE 0x0200000
59 * SFB ASIC registers (offsets from SFB_ASIC_OFFSET).
61 #define SFB_ASIC_COPYBUF_0 0x0000 /* Copy buffer register 0 (R/W) */
62 #define SFB_ASIC_COPYBUF_1 0x0004 /* Copy buffer register 1 (R/W) */
63 #define SFB_ASIC_COPYBUF_2 0x0008 /* Copy buffer register 2 (R/W) */
64 #define SFB_ASIC_COPYBUF_3 0x000c /* Copy buffer register 3 (R/W) */
65 #define SFB_ASIC_COPYBUF_4 0x0010 /* Copy buffer register 4 (R/W) */
66 #define SFB_ASIC_COPYBUF_5 0x0014 /* Copy buffer register 5 (R/W) */
67 #define SFB_ASIC_COPYBUF_6 0x0018 /* Copy buffer register 6 (R/W) */
68 #define SFB_ASIC_COPYBUF_7 0x001c /* Copy buffer register 7 (R/W) */
69 #define SFB_ASIC_FG 0x0020 /* Foreground (R/W) */
70 #define SFB_ASIC_BG 0x0024 /* Background (R/W) */
71 #define SFB_ASIC_PLANEMASK 0x0028 /* PlaneMask (R/W) */
72 #define SFB_ASIC_PIXELMASK 0x002c /* PixelMask (R/W) */
73 #define SFB_ASIC_MODE 0x0030 /* Mode (R/W) */
74 #define SFB_ASIC_ROP 0x0034 /* RasterOp (R/W) */
75 #define SFB_ASIC_PIXELSHIFT 0x0038 /* PixelShift (R/W) */
76 #define SFB_ASIC_ADDRESS 0x003c /* Address (R/W) */
77 #define SFB_ASIC_BRES1 0x0040 /* Bresenham register 1 (R/W) */
78 #define SFB_ASIC_BRES2 0x0044 /* Bresenham register 2 (R/W) */
79 #define SFB_ASIC_BRES3 0x0048 /* Bresenham register 3 (R/W) */
80 #define SFB_ASIC_BCONT 0x004c /* Bcont (W) */
81 #define SFB_ASIC_DEEP 0x0050 /* Deep (R/W) */
82 #define SFB_ASIC_START 0x0054 /* Start (W) */
83 #define SFB_ASIC_CLEAR_INTR 0x0058 /* Clear Interrupt (W) */
84 #define SFB_ASIC_VIDEO_REFRESH 0x0060 /* Video refresh counter (R/W) */
85 #define SFB_ASIC_VIDEO_HSETUP 0x0064 /* Video horizontal setup (R/W) */
86 #define SFB_ASIC_VIDEO_VSETUP 0x0068 /* Video vertical setup (R/W) */
87 #define SFB_ASIC_VIDEO_BASE 0x006c /* Video base address (R/W) */
88 #define SFB_ASIC_VIDEO_VALID 0x0070 /* Video valid (W) */
89 #define SFB_ASIC_ENABLE_INTR 0x0074 /* Enable/Disable Interrupts (W) */
90 #define SFB_ASIC_TCCLK 0x0078 /* TCCLK count (R/W) */
91 #define SFB_ASIC_VIDCLK 0x007c /* VIDCLK count (R/W) */
94 * Same as above but in 32-bit units, and named like the corrseponding
95 * TGA registers, for easy comparison.
97 typedef u_int32_t sfb_reg_t
;
99 #define SFB_REG_GCBR0 0x000 /* Copy buffer 0 */
100 #define SFB_REG_GCBR1 0x001 /* Copy buffer 1 */
101 #define SFB_REG_GCBR2 0x002 /* Copy buffer 2 */
102 #define SFB_REG_GCBR3 0x003 /* Copy buffer 3 */
103 #define SFB_REG_GCBR4 0x004 /* Copy buffer 4 */
104 #define SFB_REG_GCBR5 0x005 /* Copy buffer 5 */
105 #define SFB_REG_GCBR6 0x006 /* Copy buffer 6 */
106 #define SFB_REG_GCBR7 0x007 /* Copy buffer 7 */
108 #define SFB_REG_GFGR 0x008 /* Foreground */
109 #define SFB_REG_GBGR 0x009 /* Background */
110 #define SFB_REG_GPMR 0x00a /* Plane Mask */
111 #define SFB_REG_GPXR_S 0x00b /* Pixel Mask (one-shot) */
112 #define SFB_REG_GMOR 0x00c /* Mode */
113 #define SFB_REG_GOPR 0x00d /* Raster Operation */
114 #define SFB_REG_GPSR 0x00e /* Pixel Shift */
115 #define SFB_REG_GADR 0x00f /* Address */
117 #define SFB_REG_GB1R 0x010 /* Bresenham 1 */
118 #define SFB_REG_GB2R 0x011 /* Bresenham 2 */
119 #define SFB_REG_GB3R 0x012 /* Bresenham 3 */
121 #define SFB_REG_GCTR 0x013 /* Continue */
122 #define SFB_REG_GDER 0x014 /* Deep */
123 #define SFB_REG_GREV 0x015 /* Start/Version on SFB,
125 * Revision on SFB2 */
126 #define SFB_REG_CINT 0x016 /* Clear Interrupt */
128 #define SFB_REG_VRFR 0x018 /* Video Refresh */
129 #define SFB_REG_VHCR 0x019 /* Horizontal Control */
130 #define SFB_REG_VVCR 0x01a /* Vertical Control */
131 #define SFB_REG_VVBR 0x01b /* Video Base Address */
132 #define SFB_REG_VVVR 0x01c /* Video Valid */
133 #define SFB_REG_SISR 0x01d /* Enable/Disable Interrupts */
134 #define SFB_REG_TCCLK 0x01e /* TCCLK count (R/W) */
135 #define SFB_REG_VIDCLK 0x01f /* VIDCLK count (R/W) */
137 #endif /* _DEV_TC_SFBREG_H_ */
