gnu/dist/gcc4/gcc/combine.c

   1 /* Optimize by combining instructions for GNU compiler.
   2    Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
   3    1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
   4
   5 This file is part of GCC.
   6
   7 GCC is free software; you can redistribute it and/or modify it under
   8 the terms of the GNU General Public License as published by the Free
   9 Software Foundation; either version 2, or (at your option) any later
  10 version.
  11
  12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  15 for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with GCC; see the file COPYING.  If not, write to the Free
  19 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
  20 02110-1301, USA.  */
  21
  22 /* This module is essentially the "combiner" phase of the U. of Arizona
  23    Portable Optimizer, but redone to work on our list-structured
  24    representation for RTL instead of their string representation.
  25
  26    The LOG_LINKS of each insn identify the most recent assignment
  27    to each REG used in the insn.  It is a list of previous insns,
  28    each of which contains a SET for a REG that is used in this insn
  29    and not used or set in between.  LOG_LINKs never cross basic blocks.
  30    They were set up by the preceding pass (lifetime analysis).
  31
  32    We try to combine each pair of insns joined by a logical link.
  33    We also try to combine triples of insns A, B and C when
  34    C has a link back to B and B has a link back to A.
  35
  36    LOG_LINKS does not have links for use of the CC0.  They don't
  37    need to, because the insn that sets the CC0 is always immediately
  38    before the insn that tests it.  So we always regard a branch
  39    insn as having a logical link to the preceding insn.  The same is true
  40    for an insn explicitly using CC0.
  41
  42    We check (with use_crosses_set_p) to avoid combining in such a way
  43    as to move a computation to a place where its value would be different.
  44
  45    Combination is done by mathematically substituting the previous
  46    insn(s) values for the regs they set into the expressions in
  47    the later insns that refer to these regs.  If the result is a valid insn
  48    for our target machine, according to the machine description,
  49    we install it, delete the earlier insns, and update the data flow
  50    information (LOG_LINKS and REG_NOTES) for what we did.
  51
  52    There are a few exceptions where the dataflow information created by
  53    flow.c aren't completely updated:
  54
  55    - reg_live_length is not updated
  56    - reg_n_refs is not adjusted in the rare case when a register is
  57      no longer required in a computation
  58    - there are extremely rare cases (see distribute_regnotes) when a
  59      REG_DEAD note is lost
  60    - a LOG_LINKS entry that refers to an insn with multiple SETs may be
  61      removed because there is no way to know which register it was
  62      linking
  63
  64    To simplify substitution, we combine only when the earlier insn(s)
  65    consist of only a single assignment.  To simplify updating afterward,
  66    we never combine when a subroutine call appears in the middle.
  67
  68    Since we do not represent assignments to CC0 explicitly except when that
  69    is all an insn does, there is no LOG_LINKS entry in an insn that uses
  70    the condition code for the insn that set the condition code.
  71    Fortunately, these two insns must be consecutive.
  72    Therefore, every JUMP_INSN is taken to have an implicit logical link
  73    to the preceding insn.  This is not quite right, since non-jumps can
  74    also use the condition code; but in practice such insns would not
  75    combine anyway.  */
  76
  77 #include "config.h"
  78 #include "system.h"
  79 #include "coretypes.h"
  80 #include "tm.h"
  81 #include "rtl.h"
  82 #include "tree.h"
  83 #include "tm_p.h"
  84 #include "flags.h"
  85 #include "regs.h"
  86 #include "hard-reg-set.h"
  87 #include "basic-block.h"
  88 #include "insn-config.h"
  89 #include "function.h"
  90 /* Include expr.h after insn-config.h so we get HAVE_conditional_move.  */
  91 #include "expr.h"
  92 #include "insn-attr.h"
  93 #include "recog.h"
  94 #include "real.h"
  95 #include "toplev.h"
  96 #include "target.h"
  97 #include "optabs.h"
  98 #include "insn-codes.h"
  99 #include "rtlhooks-def.h"
 100 /* Include output.h for dump_file.  */
 101 #include "output.h"
 102 #include "params.h"
 103 #include "timevar.h"
 104 #include "tree-pass.h"
 105
 106 /* Number of attempts to combine instructions in this function.  */
 107
 108 static int combine_attempts;
 109
 110 /* Number of attempts that got as far as substitution in this function.  */
 111
 112 static int combine_merges;
 113
 114 /* Number of instructions combined with added SETs in this function.  */
 115
 116 static int combine_extras;
 117
 118 /* Number of instructions combined in this function.  */
 119
 120 static int combine_successes;
 121
 122 /* Totals over entire compilation.  */
 123
 124 static int total_attempts, total_merges, total_extras, total_successes;
 125
 126 /* combine_instructions may try to replace the right hand side of the
 127    second instruction with the value of an associated REG_EQUAL note
 128    before throwing it at try_combine.  That is problematic when there
 129    is a REG_DEAD note for a register used in the old right hand side
 130    and can cause distribute_notes to do wrong things.  This is the
 131    second instruction if it has been so modified, null otherwise.  */
 132
 133 static rtx i2mod;
 134
 135 /* When I2MOD is nonnull, this is a copy of the old right hand side.  */
 136
 137 static rtx i2mod_old_rhs;
 138
 139 /* When I2MOD is nonnull, this is a copy of the new right hand side.  */
 140
 141 static rtx i2mod_new_rhs;
 142 \f
 143 /* Vector mapping INSN_UIDs to cuids.
 144    The cuids are like uids but increase monotonically always.
 145    Combine always uses cuids so that it can compare them.
 146    But actually renumbering the uids, which we used to do,
 147    proves to be a bad idea because it makes it hard to compare
 148    the dumps produced by earlier passes with those from later passes.  */
 149
 150 static int *uid_cuid;
 151 static int max_uid_cuid;
 152
 153 /* Get the cuid of an insn.  */
 154
 155 #define INSN_CUID(INSN) \
 156 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
 157
 158 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
 159    BITS_PER_WORD would invoke undefined behavior.  Work around it.  */
 160
 161 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
 162   (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
 163
 164 /* Maximum register number, which is the size of the tables below.  */
 165
 166 static unsigned int combine_max_regno;
 167
 168 struct reg_stat {
 169   /* Record last point of death of (hard or pseudo) register n.  */
 170   rtx                           last_death;
 171
 172   /* Record last point of modification of (hard or pseudo) register n.  */
 173   rtx                           last_set;
 174
 175   /* The next group of fields allows the recording of the last value assigned
 176      to (hard or pseudo) register n.  We use this information to see if an
 177      operation being processed is redundant given a prior operation performed
 178      on the register.  For example, an `and' with a constant is redundant if
 179      all the zero bits are already known to be turned off.
 180
 181      We use an approach similar to that used by cse, but change it in the
 182      following ways:
 183
 184      (1) We do not want to reinitialize at each label.
 185      (2) It is useful, but not critical, to know the actual value assigned
 186          to a register.  Often just its form is helpful.
 187
 188      Therefore, we maintain the following fields:
 189
 190      last_set_value             the last value assigned
 191      last_set_label             records the value of label_tick when the
 192                                 register was assigned
 193      last_set_table_tick        records the value of label_tick when a
 194                                 value using the register is assigned
 195      last_set_invalid           set to nonzero when it is not valid
 196                                 to use the value of this register in some
 197                                 register's value
 198
 199      To understand the usage of these tables, it is important to understand
 200      the distinction between the value in last_set_value being valid and
 201      the register being validly contained in some other expression in the
 202      table.
 203
 204      (The next two parameters are out of date).
 205
 206      reg_stat[i].last_set_value is valid if it is nonzero, and either
 207      reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
 208
 209      Register I may validly appear in any expression returned for the value
 210      of another register if reg_n_sets[i] is 1.  It may also appear in the
 211      value for register J if reg_stat[j].last_set_invalid is zero, or
 212      reg_stat[i].last_set_label < reg_stat[j].last_set_label.
 213
 214      If an expression is found in the table containing a register which may
 215      not validly appear in an expression, the register is replaced by
 216      something that won't match, (clobber (const_int 0)).  */
 217
 218   /* Record last value assigned to (hard or pseudo) register n.  */
 219
 220   rtx                           last_set_value;
 221
 222   /* Record the value of label_tick when an expression involving register n
 223      is placed in last_set_value.  */
 224
 225   int                           last_set_table_tick;
 226
 227   /* Record the value of label_tick when the value for register n is placed in
 228      last_set_value.  */
 229
 230   int                           last_set_label;
 231
 232   /* These fields are maintained in parallel with last_set_value and are
 233      used to store the mode in which the register was last set, the bits
 234      that were known to be zero when it was last set, and the number of
 235      sign bits copies it was known to have when it was last set.  */
 236
 237   unsigned HOST_WIDE_INT        last_set_nonzero_bits;
 238   char                          last_set_sign_bit_copies;
 239   ENUM_BITFIELD(machine_mode)   last_set_mode : 8;
 240
 241   /* Set nonzero if references to register n in expressions should not be
 242      used.  last_set_invalid is set nonzero when this register is being
 243      assigned to and last_set_table_tick == label_tick.  */
 244
 245   char                          last_set_invalid;
 246
 247   /* Some registers that are set more than once and used in more than one
 248      basic block are nevertheless always set in similar ways.  For example,
 249      a QImode register may be loaded from memory in two places on a machine
 250      where byte loads zero extend.
 251
 252      We record in the following fields if a register has some leading bits
 253      that are always equal to the sign bit, and what we know about the
 254      nonzero bits of a register, specifically which bits are known to be
 255      zero.
 256
 257      If an entry is zero, it means that we don't know anything special.  */
 258
 259   unsigned char                 sign_bit_copies;
 260
 261   unsigned HOST_WIDE_INT        nonzero_bits;
 262 };
 263
 264 static struct reg_stat *reg_stat;
 265
 266 /* Record the cuid of the last insn that invalidated memory
 267    (anything that writes memory, and subroutine calls, but not pushes).  */
 268
 269 static int mem_last_set;
 270
 271 /* Record the cuid of the last CALL_INSN
 272    so we can tell whether a potential combination crosses any calls.  */
 273
 274 static int last_call_cuid;
 275
 276 /* When `subst' is called, this is the insn that is being modified
 277    (by combining in a previous insn).  The PATTERN of this insn
 278    is still the old pattern partially modified and it should not be
 279    looked at, but this may be used to examine the successors of the insn
 280    to judge whether a simplification is valid.  */
 281
 282 static rtx subst_insn;
 283
 284 /* This is the lowest CUID that `subst' is currently dealing with.
 285    get_last_value will not return a value if the register was set at or
 286    after this CUID.  If not for this mechanism, we could get confused if
 287    I2 or I1 in try_combine were an insn that used the old value of a register
 288    to obtain a new value.  In that case, we might erroneously get the
 289    new value of the register when we wanted the old one.  */
 290
 291 static int subst_low_cuid;
 292
 293 /* This contains any hard registers that are used in newpat; reg_dead_at_p
 294    must consider all these registers to be always live.  */
 295
 296 static HARD_REG_SET newpat_used_regs;
 297
 298 /* This is an insn to which a LOG_LINKS entry has been added.  If this
 299    insn is the earlier than I2 or I3, combine should rescan starting at
 300    that location.  */
 301
 302 static rtx added_links_insn;
 303
 304 /* Basic block in which we are performing combines.  */
 305 static basic_block this_basic_block;
 306
 307 /* A bitmap indicating which blocks had registers go dead at entry.
 308    After combine, we'll need to re-do global life analysis with
 309    those blocks as starting points.  */
 310 static sbitmap refresh_blocks;
 311 \f
 312 /* The following array records the insn_rtx_cost for every insn
 313    in the instruction stream.  */
 314
 315 static int *uid_insn_cost;
 316
 317 /* Length of the currently allocated uid_insn_cost array.  */
 318
 319 static int last_insn_cost;
 320
 321 /* Incremented for each label.  */
 322
 323 static int label_tick;
 324
 325 /* Mode used to compute significance in reg_stat[].nonzero_bits.  It is the
 326    largest integer mode that can fit in HOST_BITS_PER_WIDE_INT.  */
 327
 328 static enum machine_mode nonzero_bits_mode;
 329
 330 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
 331    be safely used.  It is zero while computing them and after combine has
 332    completed.  This former test prevents propagating values based on
 333    previously set values, which can be incorrect if a variable is modified
 334    in a loop.  */
 335
 336 static int nonzero_sign_valid;
 337
 338 \f
 339 /* Record one modification to rtl structure
 340    to be undone by storing old_contents into *where.
 341    is_int is 1 if the contents are an int.  */
 342
 343 struct undo
 344 {
 345   struct undo *next;
 346   int is_int;
 347   union {rtx r; int i;} old_contents;
 348   union {rtx *r; int *i;} where;
 349 };
 350
 351 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
 352    num_undo says how many are currently recorded.
 353
 354    other_insn is nonzero if we have modified some other insn in the process
 355    of working on subst_insn.  It must be verified too.  */
 356
 357 struct undobuf
 358 {
 359   struct undo *undos;
 360   struct undo *frees;
 361   rtx other_insn;
 362 };
 363
 364 static struct undobuf undobuf;
 365
 366 /* Number of times the pseudo being substituted for
 367    was found and replaced.  */
 368
 369 static int n_occurrences;
 370
 371 static rtx reg_nonzero_bits_for_combine (rtx, enum machine_mode, rtx,
 372                                          enum machine_mode,
 373                                          unsigned HOST_WIDE_INT,
 374                                          unsigned HOST_WIDE_INT *);
 375 static rtx reg_num_sign_bit_copies_for_combine (rtx, enum machine_mode, rtx,
 376                                                 enum machine_mode,
 377                                                 unsigned int, unsigned int *);
 378 static void do_SUBST (rtx *, rtx);
 379 static void do_SUBST_INT (int *, int);
 380 static void init_reg_last (void);
 381 static void setup_incoming_promotions (void);
 382 static void set_nonzero_bits_and_sign_copies (rtx, rtx, void *);
 383 static int cant_combine_insn_p (rtx);
 384 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
 385 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
 386 static int contains_muldiv (rtx);
 387 static rtx try_combine (rtx, rtx, rtx, int *);
 388 static void undo_all (void);
 389 static void undo_commit (void);
 390 static rtx *find_split_point (rtx *, rtx);
 391 static rtx subst (rtx, rtx, rtx, int, int);
 392 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
 393 static rtx simplify_if_then_else (rtx);
 394 static rtx simplify_set (rtx);
 395 static rtx simplify_logical (rtx);
 396 static rtx expand_compound_operation (rtx);
 397 static rtx expand_field_assignment (rtx);
 398 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
 399                             rtx, unsigned HOST_WIDE_INT, int, int, int);
 400 static rtx extract_left_shift (rtx, int);
 401 static rtx make_compound_operation (rtx, enum rtx_code);
 402 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
 403                               unsigned HOST_WIDE_INT *);
 404 static rtx force_to_mode (rtx, enum machine_mode,
 405                           unsigned HOST_WIDE_INT, rtx, int);
 406 static rtx if_then_else_cond (rtx, rtx *, rtx *);
 407 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
 408 static int rtx_equal_for_field_assignment_p (rtx, rtx);
 409 static rtx make_field_assignment (rtx);
 410 static rtx apply_distributive_law (rtx);
 411 static rtx distribute_and_simplify_rtx (rtx, int);
 412 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
 413                                    unsigned HOST_WIDE_INT);
 414 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
 415                             HOST_WIDE_INT, enum machine_mode, int *);
 416 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
 417                                  int);
 418 static int recog_for_combine (rtx *, rtx, rtx *);
 419 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
 420 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
 421 static void update_table_tick (rtx);
 422 static void record_value_for_reg (rtx, rtx, rtx);
 423 static void check_promoted_subreg (rtx, rtx);
 424 static void record_dead_and_set_regs_1 (rtx, rtx, void *);
 425 static void record_dead_and_set_regs (rtx);
 426 static int get_last_value_validate (rtx *, rtx, int, int);
 427 static rtx get_last_value (rtx);
 428 static int use_crosses_set_p (rtx, int);
 429 static void reg_dead_at_p_1 (rtx, rtx, void *);
 430 static int reg_dead_at_p (rtx, rtx);
 431 static void move_deaths (rtx, rtx, int, rtx, rtx *);
 432 static int reg_bitfield_target_p (rtx, rtx);
 433 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
 434 static void distribute_links (rtx);
 435 static void mark_used_regs_combine (rtx);
 436 static int insn_cuid (rtx);
 437 static void record_promoted_value (rtx, rtx);
 438 static int unmentioned_reg_p_1 (rtx *, void *);
 439 static bool unmentioned_reg_p (rtx, rtx);
 440 \f
 441
 442 /* It is not safe to use ordinary gen_lowpart in combine.
 443    See comments in gen_lowpart_for_combine.  */
 444 #undef RTL_HOOKS_GEN_LOWPART
 445 #define RTL_HOOKS_GEN_LOWPART              gen_lowpart_for_combine
 446
 447 /* Our implementation of gen_lowpart never emits a new pseudo.  */
 448 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
 449 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT      gen_lowpart_for_combine
 450
 451 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
 452 #define RTL_HOOKS_REG_NONZERO_REG_BITS     reg_nonzero_bits_for_combine
 453
 454 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
 455 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES  reg_num_sign_bit_copies_for_combine
 456
 457 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
 458
 459 \f
 460 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
 461    insn.  The substitution can be undone by undo_all.  If INTO is already
 462    set to NEWVAL, do not record this change.  Because computing NEWVAL might
 463    also call SUBST, we have to compute it before we put anything into
 464    the undo table.  */
 465
 466 static void
 467 do_SUBST (rtx *into, rtx newval)
 468 {
 469   struct undo *buf;
 470   rtx oldval = *into;
 471
 472   if (oldval == newval)
 473     return;
 474
 475   /* We'd like to catch as many invalid transformations here as
 476      possible.  Unfortunately, there are way too many mode changes
 477      that are perfectly valid, so we'd waste too much effort for
 478      little gain doing the checks here.  Focus on catching invalid
 479      transformations involving integer constants.  */
 480   if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
 481       && GET_CODE (newval) == CONST_INT)
 482     {
 483       /* Sanity check that we're replacing oldval with a CONST_INT
 484          that is a valid sign-extension for the original mode.  */
 485       gcc_assert (INTVAL (newval)
 486                   == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
 487
 488       /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
 489          CONST_INT is not valid, because after the replacement, the
 490          original mode would be gone.  Unfortunately, we can't tell
 491          when do_SUBST is called to replace the operand thereof, so we
 492          perform this test on oldval instead, checking whether an
 493          invalid replacement took place before we got here.  */
 494       gcc_assert (!(GET_CODE (oldval) == SUBREG
 495                     && GET_CODE (SUBREG_REG (oldval)) == CONST_INT));
 496       gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
 497                     && GET_CODE (XEXP (oldval, 0)) == CONST_INT));
 498     }
 499
 500   if (undobuf.frees)
 501     buf = undobuf.frees, undobuf.frees = buf->next;
 502   else
 503     buf = xmalloc (sizeof (struct undo));
 504
 505   buf->is_int = 0;
 506   buf->where.r = into;
 507   buf->old_contents.r = oldval;
 508   *into = newval;
 509
 510   buf->next = undobuf.undos, undobuf.undos = buf;
 511 }
 512
 513 #define SUBST(INTO, NEWVAL)     do_SUBST(&(INTO), (NEWVAL))
 514
 515 /* Similar to SUBST, but NEWVAL is an int expression.  Note that substitution
 516    for the value of a HOST_WIDE_INT value (including CONST_INT) is
 517    not safe.  */
 518
 519 static void
 520 do_SUBST_INT (int *into, int newval)
 521 {
 522   struct undo *buf;
 523   int oldval = *into;
 524
 525   if (oldval == newval)
 526     return;
 527
 528   if (undobuf.frees)
 529     buf = undobuf.frees, undobuf.frees = buf->next;
 530   else
 531     buf = xmalloc (sizeof (struct undo));
 532
 533   buf->is_int = 1;
 534   buf->where.i = into;
 535   buf->old_contents.i = oldval;
 536   *into = newval;
 537
 538   buf->next = undobuf.undos, undobuf.undos = buf;
 539 }
 540
 541 #define SUBST_INT(INTO, NEWVAL)  do_SUBST_INT(&(INTO), (NEWVAL))
 542 \f
 543 /* Subroutine of try_combine.  Determine whether the combine replacement
 544    patterns NEWPAT and NEWI2PAT are cheaper according to insn_rtx_cost
 545    that the original instruction sequence I1, I2 and I3.  Note that I1
 546    and/or NEWI2PAT may be NULL_RTX.  This function returns false, if the
 547    costs of all instructions can be estimated, and the replacements are
 548    more expensive than the original sequence.  */
 549
 550 static bool
 551 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat)
 552 {
 553   int i1_cost, i2_cost, i3_cost;
 554   int new_i2_cost, new_i3_cost;
 555   int old_cost, new_cost;
 556
 557   /* Lookup the original insn_rtx_costs.  */
 558   i2_cost = INSN_UID (i2) <= last_insn_cost
 559             ? uid_insn_cost[INSN_UID (i2)] : 0;
 560   i3_cost = INSN_UID (i3) <= last_insn_cost
 561             ? uid_insn_cost[INSN_UID (i3)] : 0;
 562
 563   if (i1)
 564     {
 565       i1_cost = INSN_UID (i1) <= last_insn_cost
 566                 ? uid_insn_cost[INSN_UID (i1)] : 0;
 567       old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
 568                  ? i1_cost + i2_cost + i3_cost : 0;
 569     }
 570   else
 571     {
 572       old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
 573       i1_cost = 0;
 574     }
 575
 576   /* Calculate the replacement insn_rtx_costs.  */
 577   new_i3_cost = insn_rtx_cost (newpat);
 578   if (newi2pat)
 579     {
 580       new_i2_cost = insn_rtx_cost (newi2pat);
 581       new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
 582                  ? new_i2_cost + new_i3_cost : 0;
 583     }
 584   else
 585     {
 586       new_cost = new_i3_cost;
 587       new_i2_cost = 0;
 588     }
 589
 590   if (undobuf.other_insn)
 591     {
 592       int old_other_cost, new_other_cost;
 593
 594       old_other_cost = (INSN_UID (undobuf.other_insn) <= last_insn_cost
 595                         ? uid_insn_cost[INSN_UID (undobuf.other_insn)] : 0);
 596       new_other_cost = insn_rtx_cost (PATTERN (undobuf.other_insn));
 597       if (old_other_cost > 0 && new_other_cost > 0)
 598         {
 599           old_cost += old_other_cost;
 600           new_cost += new_other_cost;
 601         }
 602       else
 603         old_cost = 0;
 604     }
 605
 606   /* Disallow this recombination if both new_cost and old_cost are
 607      greater than zero, and new_cost is greater than old cost.  */
 608   if (old_cost > 0
 609       && new_cost > old_cost)
 610     {
 611       if (dump_file)
 612         {
 613           if (i1)
 614             {
 615               fprintf (dump_file,
 616                        "rejecting combination of insns %d, %d and %d\n",
 617                        INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
 618               fprintf (dump_file, "original costs %d + %d + %d = %d\n",
 619                        i1_cost, i2_cost, i3_cost, old_cost);
 620             }
 621           else
 622             {
 623               fprintf (dump_file,
 624                        "rejecting combination of insns %d and %d\n",
 625                        INSN_UID (i2), INSN_UID (i3));
 626               fprintf (dump_file, "original costs %d + %d = %d\n",
 627                        i2_cost, i3_cost, old_cost);
 628             }
 629
 630           if (newi2pat)
 631             {
 632               fprintf (dump_file, "replacement costs %d + %d = %d\n",
 633                        new_i2_cost, new_i3_cost, new_cost);
 634             }
 635           else
 636             fprintf (dump_file, "replacement cost %d\n", new_cost);
 637         }
 638
 639       return false;
 640     }
 641
 642   /* Update the uid_insn_cost array with the replacement costs.  */
 643   uid_insn_cost[INSN_UID (i2)] = new_i2_cost;
 644   uid_insn_cost[INSN_UID (i3)] = new_i3_cost;
 645   if (i1)
 646     uid_insn_cost[INSN_UID (i1)] = 0;
 647
 648   return true;
 649 }
 650 \f
 651 /* Main entry point for combiner.  F is the first insn of the function.
 652    NREGS is the first unused pseudo-reg number.
 653
 654    Return nonzero if the combiner has turned an indirect jump
 655    instruction into a direct jump.  */
 656 int
 657 combine_instructions (rtx f, unsigned int nregs)
 658 {
 659   rtx insn, next;
 660 #ifdef HAVE_cc0
 661   rtx prev;
 662 #endif
 663   int i;
 664   unsigned int j = 0;
 665   rtx links, nextlinks;
 666   sbitmap_iterator sbi;
 667
 668   int new_direct_jump_p = 0;
 669
 670   combine_attempts = 0;
 671   combine_merges = 0;
 672   combine_extras = 0;
 673   combine_successes = 0;
 674
 675   combine_max_regno = nregs;
 676
 677   rtl_hooks = combine_rtl_hooks;
 678
 679   reg_stat = xcalloc (nregs, sizeof (struct reg_stat));
 680
 681   init_recog_no_volatile ();
 682
 683   /* Compute maximum uid value so uid_cuid can be allocated.  */
 684
 685   for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
 686     if (INSN_UID (insn) > i)
 687       i = INSN_UID (insn);
 688
 689   uid_cuid = xmalloc ((i + 1) * sizeof (int));
 690   max_uid_cuid = i;
 691
 692   nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
 693
 694   /* Don't use reg_stat[].nonzero_bits when computing it.  This can cause
 695      problems when, for example, we have j <<= 1 in a loop.  */
 696
 697   nonzero_sign_valid = 0;
 698
 699   /* Compute the mapping from uids to cuids.
 700      Cuids are numbers assigned to insns, like uids,
 701      except that cuids increase monotonically through the code.
 702
 703      Scan all SETs and see if we can deduce anything about what
 704      bits are known to be zero for some registers and how many copies
 705      of the sign bit are known to exist for those registers.
 706
 707      Also set any known values so that we can use it while searching
 708      for what bits are known to be set.  */
 709
 710   label_tick = 1;
 711
 712   setup_incoming_promotions ();
 713
 714   refresh_blocks = sbitmap_alloc (last_basic_block);
 715   sbitmap_zero (refresh_blocks);
 716
 717   /* Allocate array of current insn_rtx_costs.  */
 718   uid_insn_cost = xcalloc (max_uid_cuid + 1, sizeof (int));
 719   last_insn_cost = max_uid_cuid;
 720
 721   for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
 722     {
 723       uid_cuid[INSN_UID (insn)] = ++i;
 724       subst_low_cuid = i;
 725       subst_insn = insn;
 726
 727       if (INSN_P (insn))
 728         {
 729           note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
 730                        NULL);
 731           record_dead_and_set_regs (insn);
 732
 733 #ifdef AUTO_INC_DEC
 734           for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
 735             if (REG_NOTE_KIND (links) == REG_INC)
 736               set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
 737                                                 NULL);
 738 #endif
 739
 740           /* Record the current insn_rtx_cost of this instruction.  */
 741           if (NONJUMP_INSN_P (insn))
 742             uid_insn_cost[INSN_UID (insn)] = insn_rtx_cost (PATTERN (insn));
 743           if (dump_file)
 744             fprintf(dump_file, "insn_cost %d: %d\n",
 745                     INSN_UID (insn), uid_insn_cost[INSN_UID (insn)]);
 746         }
 747
 748       if (LABEL_P (insn))
 749         label_tick++;
 750     }
 751
 752   nonzero_sign_valid = 1;
 753
 754   /* Now scan all the insns in forward order.  */
 755
 756   label_tick = 1;
 757   last_call_cuid = 0;
 758   mem_last_set = 0;
 759   init_reg_last ();
 760   setup_incoming_promotions ();
 761
 762   FOR_EACH_BB (this_basic_block)
 763     {
 764       for (insn = BB_HEAD (this_basic_block);
 765            insn != NEXT_INSN (BB_END (this_basic_block));
 766            insn = next ? next : NEXT_INSN (insn))
 767         {
 768           next = 0;
 769
 770           if (LABEL_P (insn))
 771             label_tick++;
 772
 773           else if (INSN_P (insn))
 774             {
 775               /* See if we know about function return values before this
 776                  insn based upon SUBREG flags.  */
 777               check_promoted_subreg (insn, PATTERN (insn));
 778
 779               /* Try this insn with each insn it links back to.  */
 780
 781               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 782                 if ((next = try_combine (insn, XEXP (links, 0),
 783                                          NULL_RTX, &new_direct_jump_p)) != 0)
 784                   goto retry;
 785
 786               /* Try each sequence of three linked insns ending with this one.  */
 787
 788               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 789                 {
 790                   rtx link = XEXP (links, 0);
 791
 792                   /* If the linked insn has been replaced by a note, then there
 793                      is no point in pursuing this chain any further.  */
 794                   if (NOTE_P (link))
 795                     continue;
 796
 797                   for (nextlinks = LOG_LINKS (link);
 798                        nextlinks;
 799                        nextlinks = XEXP (nextlinks, 1))
 800                     if ((next = try_combine (insn, link,
 801                                              XEXP (nextlinks, 0),
 802                                              &new_direct_jump_p)) != 0)
 803                       goto retry;
 804                 }
 805
 806 #ifdef HAVE_cc0
 807               /* Try to combine a jump insn that uses CC0
 808                  with a preceding insn that sets CC0, and maybe with its
 809                  logical predecessor as well.
 810                  This is how we make decrement-and-branch insns.
 811                  We need this special code because data flow connections
 812                  via CC0 do not get entered in LOG_LINKS.  */
 813
 814               if (JUMP_P (insn)
 815                   && (prev = prev_nonnote_insn (insn)) != 0
 816                   && NONJUMP_INSN_P (prev)
 817                   && sets_cc0_p (PATTERN (prev)))
 818                 {
 819                   if ((next = try_combine (insn, prev,
 820                                            NULL_RTX, &new_direct_jump_p)) != 0)
 821                     goto retry;
 822
 823                   for (nextlinks = LOG_LINKS (prev); nextlinks;
 824                        nextlinks = XEXP (nextlinks, 1))
 825                     if ((next = try_combine (insn, prev,
 826                                              XEXP (nextlinks, 0),
 827                                              &new_direct_jump_p)) != 0)
 828                       goto retry;
 829                 }
 830
 831               /* Do the same for an insn that explicitly references CC0.  */
 832               if (NONJUMP_INSN_P (insn)
 833                   && (prev = prev_nonnote_insn (insn)) != 0
 834                   && NONJUMP_INSN_P (prev)
 835                   && sets_cc0_p (PATTERN (prev))
 836                   && GET_CODE (PATTERN (insn)) == SET
 837                   && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
 838                 {
 839                   if ((next = try_combine (insn, prev,
 840                                            NULL_RTX, &new_direct_jump_p)) != 0)
 841                     goto retry;
 842
 843                   for (nextlinks = LOG_LINKS (prev); nextlinks;
 844                        nextlinks = XEXP (nextlinks, 1))
 845                     if ((next = try_combine (insn, prev,
 846                                              XEXP (nextlinks, 0),
 847                                              &new_direct_jump_p)) != 0)
 848                       goto retry;
 849                 }
 850
 851               /* Finally, see if any of the insns that this insn links to
 852                  explicitly references CC0.  If so, try this insn, that insn,
 853                  and its predecessor if it sets CC0.  */
 854               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 855                 if (NONJUMP_INSN_P (XEXP (links, 0))
 856                     && GET_CODE (PATTERN (XEXP (links, 0))) == SET
 857                     && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
 858                     && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
 859                     && NONJUMP_INSN_P (prev)
 860                     && sets_cc0_p (PATTERN (prev))
 861                     && (next = try_combine (insn, XEXP (links, 0),
 862                                             prev, &new_direct_jump_p)) != 0)
 863                   goto retry;
 864 #endif
 865
 866               /* Try combining an insn with two different insns whose results it
 867                  uses.  */
 868               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 869                 for (nextlinks = XEXP (links, 1); nextlinks;
 870                      nextlinks = XEXP (nextlinks, 1))
 871                   if ((next = try_combine (insn, XEXP (links, 0),
 872                                            XEXP (nextlinks, 0),
 873                                            &new_direct_jump_p)) != 0)
 874                     goto retry;
 875
 876               /* Try this insn with each REG_EQUAL note it links back to.  */
 877               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 878                 {
 879                   rtx set, note;
 880                   rtx temp = XEXP (links, 0);
 881                   if ((set = single_set (temp)) != 0
 882                       && (note = find_reg_equal_equiv_note (temp)) != 0
 883                       && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
 884                       /* Avoid using a register that may already been marked
 885                          dead by an earlier instruction.  */
 886                       && ! unmentioned_reg_p (note, SET_SRC (set))
 887                       && (GET_MODE (note) == VOIDmode
 888                           ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
 889                           : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
 890                     {
 891                       /* Temporarily replace the set's source with the
 892                          contents of the REG_EQUAL note.  The insn will
 893                          be deleted or recognized by try_combine.  */
 894                       rtx orig = SET_SRC (set);
 895                       SET_SRC (set) = note;
 896                       i2mod = temp;
 897                       i2mod_old_rhs = copy_rtx (orig);
 898                       i2mod_new_rhs = copy_rtx (note);
 899                       next = try_combine (insn, i2mod, NULL_RTX,
 900                                           &new_direct_jump_p);
 901                       i2mod = NULL_RTX;
 902                       if (next)
 903                         goto retry;
 904                       SET_SRC (set) = orig;
 905                     }
 906                 }
 907
 908               if (!NOTE_P (insn))
 909                 record_dead_and_set_regs (insn);
 910
 911             retry:
 912               ;
 913             }
 914         }
 915     }
 916   clear_bb_flags ();
 917
 918   EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, j, sbi)
 919     BASIC_BLOCK (j)->flags |= BB_DIRTY;
 920   new_direct_jump_p |= purge_all_dead_edges ();
 921   delete_noop_moves ();
 922
 923   update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
 924                                     PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
 925                                     | PROP_KILL_DEAD_CODE);
 926
 927   /* Clean up.  */
 928   sbitmap_free (refresh_blocks);
 929   free (uid_insn_cost);
 930   free (reg_stat);
 931   free (uid_cuid);
 932
 933   {
 934     struct undo *undo, *next;
 935     for (undo = undobuf.frees; undo; undo = next)
 936       {
 937         next = undo->next;
 938         free (undo);
 939       }
 940     undobuf.frees = 0;
 941   }
 942
 943   total_attempts += combine_attempts;
 944   total_merges += combine_merges;
 945   total_extras += combine_extras;
 946   total_successes += combine_successes;
 947
 948   nonzero_sign_valid = 0;
 949   rtl_hooks = general_rtl_hooks;
 950
 951   /* Make recognizer allow volatile MEMs again.  */
 952   init_recog ();
 953
 954   return new_direct_jump_p;
 955 }
 956
 957 /* Wipe the last_xxx fields of reg_stat in preparation for another pass.  */
 958
 959 static void
 960 init_reg_last (void)
 961 {
 962   unsigned int i;
 963   for (i = 0; i < combine_max_regno; i++)
 964     memset (reg_stat + i, 0, offsetof (struct reg_stat, sign_bit_copies));
 965 }
 966 \f
 967 /* Set up any promoted values for incoming argument registers.  */
 968
 969 static void
 970 setup_incoming_promotions (void)
 971 {
 972   unsigned int regno;
 973   rtx reg;
 974   enum machine_mode mode;
 975   int unsignedp;
 976   rtx first = get_insns ();
 977
 978   if (targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
 979     {
 980       for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
 981         /* Check whether this register can hold an incoming pointer
 982            argument.  FUNCTION_ARG_REGNO_P tests outgoing register
 983            numbers, so translate if necessary due to register windows.  */
 984         if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
 985             && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
 986           {
 987             record_value_for_reg
 988               (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
 989                                            : SIGN_EXTEND),
 990                                           GET_MODE (reg),
 991                                           gen_rtx_CLOBBER (mode, const0_rtx)));
 992           }
 993     }
 994 }
 995 \f
 996 /* Called via note_stores.  If X is a pseudo that is narrower than
 997    HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
 998
 999    If we are setting only a portion of X and we can't figure out what
1000    portion, assume all bits will be used since we don't know what will
1001    be happening.
1002
1003    Similarly, set how many bits of X are known to be copies of the sign bit
1004    at all locations in the function.  This is the smallest number implied
1005    by any set of X.  */
1006
1007 static void
1008 set_nonzero_bits_and_sign_copies (rtx x, rtx set,
1009                                   void *data ATTRIBUTE_UNUSED)
1010 {
1011   unsigned int num;
1012
1013   if (REG_P (x)
1014       && REGNO (x) >= FIRST_PSEUDO_REGISTER
1015       /* If this register is undefined at the start of the file, we can't
1016          say what its contents were.  */
1017       && ! REGNO_REG_SET_P
1018          (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start, REGNO (x))
1019       && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1020     {
1021       if (set == 0 || GET_CODE (set) == CLOBBER)
1022         {
1023           reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1024           reg_stat[REGNO (x)].sign_bit_copies = 1;
1025           return;
1026         }
1027
1028       /* If this is a complex assignment, see if we can convert it into a
1029          simple assignment.  */
1030       set = expand_field_assignment (set);
1031
1032       /* If this is a simple assignment, or we have a paradoxical SUBREG,
1033          set what we know about X.  */
1034
1035       if (SET_DEST (set) == x
1036           || (GET_CODE (SET_DEST (set)) == SUBREG
1037               && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1038                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1039               && SUBREG_REG (SET_DEST (set)) == x))
1040         {
1041           rtx src = SET_SRC (set);
1042
1043 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1044           /* If X is narrower than a word and SRC is a non-negative
1045              constant that would appear negative in the mode of X,
1046              sign-extend it for use in reg_stat[].nonzero_bits because some
1047              machines (maybe most) will actually do the sign-extension
1048              and this is the conservative approach.
1049
1050              ??? For 2.5, try to tighten up the MD files in this regard
1051              instead of this kludge.  */
1052
1053           if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1054               && GET_CODE (src) == CONST_INT
1055               && INTVAL (src) > 0
1056               && 0 != (INTVAL (src)
1057                        & ((HOST_WIDE_INT) 1
1058                           << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1059             src = GEN_INT (INTVAL (src)
1060                            | ((HOST_WIDE_INT) (-1)
1061                               << GET_MODE_BITSIZE (GET_MODE (x))));
1062 #endif
1063
1064           /* Don't call nonzero_bits if it cannot change anything.  */
1065           if (reg_stat[REGNO (x)].nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1066             reg_stat[REGNO (x)].nonzero_bits
1067               |= nonzero_bits (src, nonzero_bits_mode);
1068           num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1069           if (reg_stat[REGNO (x)].sign_bit_copies == 0
1070               || reg_stat[REGNO (x)].sign_bit_copies > num)
1071             reg_stat[REGNO (x)].sign_bit_copies = num;
1072         }
1073       else
1074         {
1075           reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1076           reg_stat[REGNO (x)].sign_bit_copies = 1;
1077         }
1078     }
1079 }
1080 \f
1081 /* See if INSN can be combined into I3.  PRED and SUCC are optionally
1082    insns that were previously combined into I3 or that will be combined
1083    into the merger of INSN and I3.
1084
1085    Return 0 if the combination is not allowed for any reason.
1086
1087    If the combination is allowed, *PDEST will be set to the single
1088    destination of INSN and *PSRC to the single source, and this function
1089    will return 1.  */
1090
1091 static int
1092 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1093                rtx *pdest, rtx *psrc)
1094 {
1095   int i;
1096   rtx set = 0, src, dest;
1097   rtx p;
1098 #ifdef AUTO_INC_DEC
1099   rtx link;
1100 #endif
1101   int all_adjacent = (succ ? (next_active_insn (insn) == succ
1102                               && next_active_insn (succ) == i3)
1103                       : next_active_insn (insn) == i3);
1104
1105   /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1106      or a PARALLEL consisting of such a SET and CLOBBERs.
1107
1108      If INSN has CLOBBER parallel parts, ignore them for our processing.
1109      By definition, these happen during the execution of the insn.  When it
1110      is merged with another insn, all bets are off.  If they are, in fact,
1111      needed and aren't also supplied in I3, they may be added by
1112      recog_for_combine.  Otherwise, it won't match.
1113
1114      We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1115      note.
1116
1117      Get the source and destination of INSN.  If more than one, can't
1118      combine.  */
1119
1120   if (GET_CODE (PATTERN (insn)) == SET)
1121     set = PATTERN (insn);
1122   else if (GET_CODE (PATTERN (insn)) == PARALLEL
1123            && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1124     {
1125       for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1126         {
1127           rtx elt = XVECEXP (PATTERN (insn), 0, i);
1128           rtx note;
1129
1130           switch (GET_CODE (elt))
1131             {
1132             /* This is important to combine floating point insns
1133                for the SH4 port.  */
1134             case USE:
1135               /* Combining an isolated USE doesn't make sense.
1136                  We depend here on combinable_i3pat to reject them.  */
1137               /* The code below this loop only verifies that the inputs of
1138                  the SET in INSN do not change.  We call reg_set_between_p
1139                  to verify that the REG in the USE does not change between
1140                  I3 and INSN.
1141                  If the USE in INSN was for a pseudo register, the matching
1142                  insn pattern will likely match any register; combining this
1143                  with any other USE would only be safe if we knew that the
1144                  used registers have identical values, or if there was
1145                  something to tell them apart, e.g. different modes.  For
1146                  now, we forgo such complicated tests and simply disallow
1147                  combining of USES of pseudo registers with any other USE.  */
1148               if (REG_P (XEXP (elt, 0))
1149                   && GET_CODE (PATTERN (i3)) == PARALLEL)
1150                 {
1151                   rtx i3pat = PATTERN (i3);
1152                   int i = XVECLEN (i3pat, 0) - 1;
1153                   unsigned int regno = REGNO (XEXP (elt, 0));
1154
1155                   do
1156                     {
1157                       rtx i3elt = XVECEXP (i3pat, 0, i);
1158
1159                       if (GET_CODE (i3elt) == USE
1160                           && REG_P (XEXP (i3elt, 0))
1161                           && (REGNO (XEXP (i3elt, 0)) == regno
1162                               ? reg_set_between_p (XEXP (elt, 0),
1163                                                    PREV_INSN (insn), i3)
1164                               : regno >= FIRST_PSEUDO_REGISTER))
1165                         return 0;
1166                     }
1167                   while (--i >= 0);
1168                 }
1169               break;
1170
1171               /* We can ignore CLOBBERs.  */
1172             case CLOBBER:
1173               break;
1174
1175             case SET:
1176               /* Ignore SETs whose result isn't used but not those that
1177                  have side-effects.  */
1178               if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1179                   && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1180                       || INTVAL (XEXP (note, 0)) <= 0)
1181                   && ! side_effects_p (elt))
1182                 break;
1183
1184               /* If we have already found a SET, this is a second one and
1185                  so we cannot combine with this insn.  */
1186               if (set)
1187                 return 0;
1188
1189               set = elt;
1190               break;
1191
1192             default:
1193               /* Anything else means we can't combine.  */
1194               return 0;
1195             }
1196         }
1197
1198       if (set == 0
1199           /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1200              so don't do anything with it.  */
1201           || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1202         return 0;
1203     }
1204   else
1205     return 0;
1206
1207   if (set == 0)
1208     return 0;
1209
1210   set = expand_field_assignment (set);
1211   src = SET_SRC (set), dest = SET_DEST (set);
1212
1213   /* Don't eliminate a store in the stack pointer.  */
1214   if (dest == stack_pointer_rtx
1215       /* Don't combine with an insn that sets a register to itself if it has
1216          a REG_EQUAL note.  This may be part of a REG_NO_CONFLICT sequence.  */
1217       || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1218       /* Can't merge an ASM_OPERANDS.  */
1219       || GET_CODE (src) == ASM_OPERANDS
1220       /* Can't merge a function call.  */
1221       || GET_CODE (src) == CALL
1222       /* Don't eliminate a function call argument.  */
1223       || (CALL_P (i3)
1224           && (find_reg_fusage (i3, USE, dest)
1225               || (REG_P (dest)
1226                   && REGNO (dest) < FIRST_PSEUDO_REGISTER
1227                   && global_regs[REGNO (dest)])))
1228       /* Don't substitute into an incremented register.  */
1229       || FIND_REG_INC_NOTE (i3, dest)
1230       || (succ && FIND_REG_INC_NOTE (succ, dest))
1231       /* Don't substitute into a non-local goto, this confuses CFG.  */
1232       || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1233 #if 0
1234       /* Don't combine the end of a libcall into anything.  */
1235       /* ??? This gives worse code, and appears to be unnecessary, since no
1236          pass after flow uses REG_LIBCALL/REG_RETVAL notes.  Local-alloc does
1237          use REG_RETVAL notes for noconflict blocks, but other code here
1238          makes sure that those insns don't disappear.  */
1239       || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1240 #endif
1241       /* Make sure that DEST is not used after SUCC but before I3.  */
1242       || (succ && ! all_adjacent
1243           && reg_used_between_p (dest, succ, i3))
1244       /* Make sure that the value that is to be substituted for the register
1245          does not use any registers whose values alter in between.  However,
1246          If the insns are adjacent, a use can't cross a set even though we
1247          think it might (this can happen for a sequence of insns each setting
1248          the same destination; last_set of that register might point to
1249          a NOTE).  If INSN has a REG_EQUIV note, the register is always
1250          equivalent to the memory so the substitution is valid even if there
1251          are intervening stores.  Also, don't move a volatile asm or
1252          UNSPEC_VOLATILE across any other insns.  */
1253       || (! all_adjacent
1254           && (((!MEM_P (src)
1255                 || ! find_reg_note (insn, REG_EQUIV, src))
1256                && use_crosses_set_p (src, INSN_CUID (insn)))
1257               || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1258               || GET_CODE (src) == UNSPEC_VOLATILE))
1259       /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1260          better register allocation by not doing the combine.  */
1261       || find_reg_note (i3, REG_NO_CONFLICT, dest)
1262       || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1263       /* Don't combine across a CALL_INSN, because that would possibly
1264          change whether the life span of some REGs crosses calls or not,
1265          and it is a pain to update that information.
1266          Exception: if source is a constant, moving it later can't hurt.
1267          Accept that special case, because it helps -fforce-addr a lot.  */
1268       || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1269     return 0;
1270
1271   /* DEST must either be a REG or CC0.  */
1272   if (REG_P (dest))
1273     {
1274       /* If register alignment is being enforced for multi-word items in all
1275          cases except for parameters, it is possible to have a register copy
1276          insn referencing a hard register that is not allowed to contain the
1277          mode being copied and which would not be valid as an operand of most
1278          insns.  Eliminate this problem by not combining with such an insn.
1279
1280          Also, on some machines we don't want to extend the life of a hard
1281          register.  */
1282
1283       if (REG_P (src)
1284           && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1285                && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1286               /* Don't extend the life of a hard register unless it is
1287                  user variable (if we have few registers) or it can't
1288                  fit into the desired register (meaning something special
1289                  is going on).
1290                  Also avoid substituting a return register into I3, because
1291                  reload can't handle a conflict with constraints of other
1292                  inputs.  */
1293               || (REGNO (src) < FIRST_PSEUDO_REGISTER
1294                   && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1295         return 0;
1296     }
1297   else if (GET_CODE (dest) != CC0)
1298     return 0;
1299
1300
1301   if (GET_CODE (PATTERN (i3)) == PARALLEL)
1302     for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1303       if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1304         {
1305           /* Don't substitute for a register intended as a clobberable
1306              operand.  */
1307           rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1308           if (rtx_equal_p (reg, dest))
1309             return 0;
1310
1311           /* If the clobber represents an earlyclobber operand, we must not
1312              substitute an expression containing the clobbered register.
1313              As we do not analyze the constraint strings here, we have to
1314              make the conservative assumption.  However, if the register is
1315              a fixed hard reg, the clobber cannot represent any operand;
1316              we leave it up to the machine description to either accept or
1317              reject use-and-clobber patterns.  */
1318           if (!REG_P (reg)
1319               || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1320               || !fixed_regs[REGNO (reg)])
1321             if (reg_overlap_mentioned_p (reg, src))
1322               return 0;
1323         }
1324
1325   /* If INSN contains anything volatile, or is an `asm' (whether volatile
1326      or not), reject, unless nothing volatile comes between it and I3 */
1327
1328   if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1329     {
1330       /* Make sure succ doesn't contain a volatile reference.  */
1331       if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1332         return 0;
1333
1334       for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1335         if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1336           return 0;
1337     }
1338
1339   /* If INSN is an asm, and DEST is a hard register, reject, since it has
1340      to be an explicit register variable, and was chosen for a reason.  */
1341
1342   if (GET_CODE (src) == ASM_OPERANDS
1343       && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1344     return 0;
1345
1346   /* If there are any volatile insns between INSN and I3, reject, because
1347      they might affect machine state.  */
1348
1349   for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1350     if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1351       return 0;
1352
1353   /* If INSN contains an autoincrement or autodecrement, make sure that
1354      register is not used between there and I3, and not already used in
1355      I3 either.  Neither must it be used in PRED or SUCC, if they exist.
1356      Also insist that I3 not be a jump; if it were one
1357      and the incremented register were spilled, we would lose.  */
1358
1359 #ifdef AUTO_INC_DEC
1360   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1361     if (REG_NOTE_KIND (link) == REG_INC
1362         && (JUMP_P (i3)
1363             || reg_used_between_p (XEXP (link, 0), insn, i3)
1364             || (pred != NULL_RTX
1365                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1366             || (succ != NULL_RTX
1367                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1368             || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1369       return 0;
1370 #endif
1371
1372 #ifdef HAVE_cc0
1373   /* Don't combine an insn that follows a CC0-setting insn.
1374      An insn that uses CC0 must not be separated from the one that sets it.
1375      We do, however, allow I2 to follow a CC0-setting insn if that insn
1376      is passed as I1; in that case it will be deleted also.
1377      We also allow combining in this case if all the insns are adjacent
1378      because that would leave the two CC0 insns adjacent as well.
1379      It would be more logical to test whether CC0 occurs inside I1 or I2,
1380      but that would be much slower, and this ought to be equivalent.  */
1381
1382   p = prev_nonnote_insn (insn);
1383   if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1384       && ! all_adjacent)
1385     return 0;
1386 #endif
1387
1388   /* If we get here, we have passed all the tests and the combination is
1389      to be allowed.  */
1390
1391   *pdest = dest;
1392   *psrc = src;
1393
1394   return 1;
1395 }
1396 \f
1397 /* LOC is the location within I3 that contains its pattern or the component
1398    of a PARALLEL of the pattern.  We validate that it is valid for combining.
1399
1400    One problem is if I3 modifies its output, as opposed to replacing it
1401    entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1402    so would produce an insn that is not equivalent to the original insns.
1403
1404    Consider:
1405
1406          (set (reg:DI 101) (reg:DI 100))
1407          (set (subreg:SI (reg:DI 101) 0) <foo>)
1408
1409    This is NOT equivalent to:
1410
1411          (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1412                     (set (reg:DI 101) (reg:DI 100))])
1413
1414    Not only does this modify 100 (in which case it might still be valid
1415    if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1416
1417    We can also run into a problem if I2 sets a register that I1
1418    uses and I1 gets directly substituted into I3 (not via I2).  In that
1419    case, we would be getting the wrong value of I2DEST into I3, so we
1420    must reject the combination.  This case occurs when I2 and I1 both
1421    feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1422    If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1423    of a SET must prevent combination from occurring.
1424
1425    Before doing the above check, we first try to expand a field assignment
1426    into a set of logical operations.
1427
1428    If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1429    we place a register that is both set and used within I3.  If more than one
1430    such register is detected, we fail.
1431
1432    Return 1 if the combination is valid, zero otherwise.  */
1433
1434 static int
1435 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1436                   int i1_not_in_src, rtx *pi3dest_killed)
1437 {
1438   rtx x = *loc;
1439
1440   if (GET_CODE (x) == SET)
1441     {
1442       rtx set = x ;
1443       rtx dest = SET_DEST (set);
1444       rtx src = SET_SRC (set);
1445       rtx inner_dest = dest;
1446       rtx subdest;
1447
1448       while (GET_CODE (inner_dest) == STRICT_LOW_PART
1449              || GET_CODE (inner_dest) == SUBREG
1450              || GET_CODE (inner_dest) == ZERO_EXTRACT)
1451         inner_dest = XEXP (inner_dest, 0);
1452
1453       /* Check for the case where I3 modifies its output, as discussed
1454          above.  We don't want to prevent pseudos from being combined
1455          into the address of a MEM, so only prevent the combination if
1456          i1 or i2 set the same MEM.  */
1457       if ((inner_dest != dest &&
1458            (!MEM_P (inner_dest)
1459             || rtx_equal_p (i2dest, inner_dest)
1460             || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1461            && (reg_overlap_mentioned_p (i2dest, inner_dest)
1462                || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1463
1464           /* This is the same test done in can_combine_p except we can't test
1465              all_adjacent; we don't have to, since this instruction will stay
1466              in place, thus we are not considering increasing the lifetime of
1467              INNER_DEST.
1468
1469              Also, if this insn sets a function argument, combining it with
1470              something that might need a spill could clobber a previous
1471              function argument; the all_adjacent test in can_combine_p also
1472              checks this; here, we do a more specific test for this case.  */
1473
1474           || (REG_P (inner_dest)
1475               && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1476               && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1477                                         GET_MODE (inner_dest))))
1478           || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1479         return 0;
1480
1481       /* If DEST is used in I3, it is being killed in this insn, so
1482          record that for later.  We have to consider paradoxical
1483          subregs here, since they kill the whole register, but we
1484          ignore partial subregs, STRICT_LOW_PART, etc.
1485          Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1486          STACK_POINTER_REGNUM, since these are always considered to be
1487          live.  Similarly for ARG_POINTER_REGNUM if it is fixed.  */
1488       subdest = dest;
1489       if (GET_CODE (subdest) == SUBREG
1490           && (GET_MODE_SIZE (GET_MODE (subdest))
1491               >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
1492         subdest = SUBREG_REG (subdest);
1493       if (pi3dest_killed
1494           && REG_P (subdest)
1495           && reg_referenced_p (subdest, PATTERN (i3))
1496           && REGNO (subdest) != FRAME_POINTER_REGNUM
1497 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1498           && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
1499 #endif
1500 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1501           && (REGNO (subdest) != ARG_POINTER_REGNUM
1502               || ! fixed_regs [REGNO (subdest)])
1503 #endif
1504           && REGNO (subdest) != STACK_POINTER_REGNUM)
1505         {
1506           if (*pi3dest_killed)
1507             return 0;
1508
1509           *pi3dest_killed = subdest;
1510         }
1511     }
1512
1513   else if (GET_CODE (x) == PARALLEL)
1514     {
1515       int i;
1516
1517       for (i = 0; i < XVECLEN (x, 0); i++)
1518         if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1519                                 i1_not_in_src, pi3dest_killed))
1520           return 0;
1521     }
1522
1523   return 1;
1524 }
1525 \f
1526 /* Return 1 if X is an arithmetic expression that contains a multiplication
1527    and division.  We don't count multiplications by powers of two here.  */
1528
1529 static int
1530 contains_muldiv (rtx x)
1531 {
1532   switch (GET_CODE (x))
1533     {
1534     case MOD:  case DIV:  case UMOD:  case UDIV:
1535       return 1;
1536
1537     case MULT:
1538       return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1539                 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1540     default:
1541       if (BINARY_P (x))
1542         return contains_muldiv (XEXP (x, 0))
1543             || contains_muldiv (XEXP (x, 1));
1544
1545       if (UNARY_P (x))
1546         return contains_muldiv (XEXP (x, 0));
1547
1548       return 0;
1549     }
1550 }
1551 \f
1552 /* Determine whether INSN can be used in a combination.  Return nonzero if
1553    not.  This is used in try_combine to detect early some cases where we
1554    can't perform combinations.  */
1555
1556 static int
1557 cant_combine_insn_p (rtx insn)
1558 {
1559   rtx set;
1560   rtx src, dest;
1561
1562   /* If this isn't really an insn, we can't do anything.
1563      This can occur when flow deletes an insn that it has merged into an
1564      auto-increment address.  */
1565   if (! INSN_P (insn))
1566     return 1;
1567
1568   /* Never combine loads and stores involving hard regs that are likely
1569      to be spilled.  The register allocator can usually handle such
1570      reg-reg moves by tying.  If we allow the combiner to make
1571      substitutions of likely-spilled regs, reload might die.
1572      As an exception, we allow combinations involving fixed regs; these are
1573      not available to the register allocator so there's no risk involved.  */
1574
1575   set = single_set (insn);
1576   if (! set)
1577     return 0;
1578   src = SET_SRC (set);
1579   dest = SET_DEST (set);
1580   if (GET_CODE (src) == SUBREG)
1581     src = SUBREG_REG (src);
1582   if (GET_CODE (dest) == SUBREG)
1583     dest = SUBREG_REG (dest);
1584   if (REG_P (src) && REG_P (dest)
1585       && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1586            && ! fixed_regs[REGNO (src)]
1587            && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
1588           || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1589               && ! fixed_regs[REGNO (dest)]
1590               && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
1591     return 1;
1592
1593   return 0;
1594 }
1595
1596 struct likely_spilled_retval_info
1597 {
1598   unsigned regno, nregs;
1599   unsigned mask;
1600 };
1601
1602 /* Called via note_stores by likely_spilled_retval_p.  Remove from info->mask
1603    hard registers that are known to be written to / clobbered in full.  */
1604 static void
1605 likely_spilled_retval_1 (rtx x, rtx set, void *data)
1606 {
1607   struct likely_spilled_retval_info *info = data;
1608   unsigned regno, nregs;
1609   unsigned new_mask;
1610
1611   if (!REG_P (XEXP (set, 0)))
1612     return;
1613   regno = REGNO (x);
1614   if (regno >= info->regno + info->nregs)
1615     return;
1616   nregs = hard_regno_nregs[regno][GET_MODE (x)];
1617   if (regno + nregs <= info->regno)
1618     return;
1619   new_mask = (2U << (nregs - 1)) - 1;
1620   if (regno < info->regno)
1621     new_mask >>= info->regno - regno;
1622   else
1623     new_mask <<= regno - info->regno;
1624   info->mask &= new_mask;
1625 }
1626
1627 /* Return nonzero iff part of the return value is live during INSN, and
1628    it is likely spilled.  This can happen when more than one insn is needed
1629    to copy the return value, e.g. when we consider to combine into the
1630    second copy insn for a complex value.  */
1631
1632 static int
1633 likely_spilled_retval_p (rtx insn)
1634 {
1635   rtx use = BB_END (this_basic_block);
1636   rtx reg, p;
1637   unsigned regno, nregs;
1638   /* We assume here that no machine mode needs more than
1639      32 hard registers when the value overlaps with a register
1640      for which FUNCTION_VALUE_REGNO_P is true.  */
1641   unsigned mask;
1642   struct likely_spilled_retval_info info;
1643
1644   if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
1645     return 0;
1646   reg = XEXP (PATTERN (use), 0);
1647   if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg)))
1648     return 0;
1649   regno = REGNO (reg);
1650   nregs = hard_regno_nregs[regno][GET_MODE (reg)];
1651   if (nregs == 1)
1652     return 0;
1653   mask = (2U << (nregs - 1)) - 1;
1654
1655   /* Disregard parts of the return value that are set later.  */
1656   info.regno = regno;
1657   info.nregs = nregs;
1658   info.mask = mask;
1659   for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
1660     note_stores (PATTERN (insn), likely_spilled_retval_1, &info);
1661   mask = info.mask;
1662
1663   /* Check if any of the (probably) live return value registers is
1664      likely spilled.  */
1665   nregs --;
1666   do
1667     {
1668       if ((mask & 1 << nregs)
1669           && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
1670         return 1;
1671     } while (nregs--);
1672   return 0;
1673 }
1674
1675 /* Adjust INSN after we made a change to its destination.
1676
1677    Changing the destination can invalidate notes that say something about
1678    the results of the insn and a LOG_LINK pointing to the insn.  */
1679
1680 static void
1681 adjust_for_new_dest (rtx insn)
1682 {
1683   rtx *loc;
1684
1685   /* For notes, be conservative and simply remove them.  */
1686   loc = &REG_NOTES (insn);
1687   while (*loc)
1688     {
1689       enum reg_note kind = REG_NOTE_KIND (*loc);
1690       if (kind == REG_EQUAL || kind == REG_EQUIV)
1691         *loc = XEXP (*loc, 1);
1692       else
1693         loc = &XEXP (*loc, 1);
1694     }
1695
1696   /* The new insn will have a destination that was previously the destination
1697      of an insn just above it.  Call distribute_links to make a LOG_LINK from
1698      the next use of that destination.  */
1699   distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
1700 }
1701
1702 /* Return TRUE if combine can reuse reg X in mode MODE.
1703    ADDED_SETS is nonzero if the original set is still required.  */
1704 static bool
1705 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
1706 {
1707   unsigned int regno;
1708
1709   if (!REG_P(x))
1710     return false;
1711
1712   regno = REGNO (x);
1713   /* Allow hard registers if the new mode is legal, and occupies no more
1714      registers than the old mode.  */
1715   if (regno < FIRST_PSEUDO_REGISTER)
1716     return (HARD_REGNO_MODE_OK (regno, mode)
1717             && (hard_regno_nregs[regno][GET_MODE (x)]
1718                 >= hard_regno_nregs[regno][mode]));
1719
1720   /* Or a pseudo that is only used once.  */
1721   return (REG_N_SETS (regno) == 1 && !added_sets
1722           && !REG_USERVAR_P (x));
1723 }
1724
1725 /* Try to combine the insns I1 and I2 into I3.
1726    Here I1 and I2 appear earlier than I3.
1727    I1 can be zero; then we combine just I2 into I3.
1728
1729    If we are combining three insns and the resulting insn is not recognized,
1730    try splitting it into two insns.  If that happens, I2 and I3 are retained
1731    and I1 is pseudo-deleted by turning it into a NOTE.  Otherwise, I1 and I2
1732    are pseudo-deleted.
1733
1734    Return 0 if the combination does not work.  Then nothing is changed.
1735    If we did the combination, return the insn at which combine should
1736    resume scanning.
1737
1738    Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1739    new direct jump instruction.  */
1740
1741 static rtx
1742 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
1743 {
1744   /* New patterns for I3 and I2, respectively.  */
1745   rtx newpat, newi2pat = 0;
1746   rtvec newpat_vec_with_clobbers = 0;
1747   int substed_i2 = 0, substed_i1 = 0;
1748   /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead.  */
1749   int added_sets_1, added_sets_2;
1750   /* Total number of SETs to put into I3.  */
1751   int total_sets;
1752   /* Nonzero if I2's body now appears in I3.  */
1753   int i2_is_used;
1754   /* INSN_CODEs for new I3, new I2, and user of condition code.  */
1755   int insn_code_number, i2_code_number = 0, other_code_number = 0;
1756   /* Contains I3 if the destination of I3 is used in its source, which means
1757      that the old life of I3 is being killed.  If that usage is placed into
1758      I2 and not in I3, a REG_DEAD note must be made.  */
1759   rtx i3dest_killed = 0;
1760   /* SET_DEST and SET_SRC of I2 and I1.  */
1761   rtx i2dest, i2src, i1dest = 0, i1src = 0;
1762   /* PATTERN (I1) and PATTERN (I2), or a copy of it in certain cases.  */
1763   rtx i1pat = 0, i2pat = 0;
1764   /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC.  */
1765   int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1766   int i2dest_killed = 0, i1dest_killed = 0;
1767   int i1_feeds_i3 = 0;
1768   /* Notes that must be added to REG_NOTES in I3 and I2.  */
1769   rtx new_i3_notes, new_i2_notes;
1770   /* Notes that we substituted I3 into I2 instead of the normal case.  */
1771   int i3_subst_into_i2 = 0;
1772   /* Notes that I1, I2 or I3 is a MULT operation.  */
1773   int have_mult = 0;
1774   int swap_i2i3 = 0;
1775
1776   int maxreg;
1777   rtx temp;
1778   rtx link;
1779   int i;
1780
1781   /* Exit early if one of the insns involved can't be used for
1782      combinations.  */
1783   if (cant_combine_insn_p (i3)
1784       || cant_combine_insn_p (i2)
1785       || (i1 && cant_combine_insn_p (i1))
1786       || likely_spilled_retval_p (i3)
1787       /* We also can't do anything if I3 has a
1788          REG_LIBCALL note since we don't want to disrupt the contiguity of a
1789          libcall.  */
1790 #if 0
1791       /* ??? This gives worse code, and appears to be unnecessary, since no
1792          pass after flow uses REG_LIBCALL/REG_RETVAL notes.  */
1793       || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1794 #endif
1795       )
1796     return 0;
1797
1798   combine_attempts++;
1799   undobuf.other_insn = 0;
1800
1801   /* Reset the hard register usage information.  */
1802   CLEAR_HARD_REG_SET (newpat_used_regs);
1803
1804   /* If I1 and I2 both feed I3, they can be in any order.  To simplify the
1805      code below, set I1 to be the earlier of the two insns.  */
1806   if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1807     temp = i1, i1 = i2, i2 = temp;
1808
1809   added_links_insn = 0;
1810
1811   /* First check for one important special-case that the code below will
1812      not handle.  Namely, the case where I1 is zero, I2 is a PARALLEL
1813      and I3 is a SET whose SET_SRC is a SET_DEST in I2.  In that case,
1814      we may be able to replace that destination with the destination of I3.
1815      This occurs in the common code where we compute both a quotient and
1816      remainder into a structure, in which case we want to do the computation
1817      directly into the structure to avoid register-register copies.
1818
1819      Note that this case handles both multiple sets in I2 and also
1820      cases where I2 has a number of CLOBBER or PARALLELs.
1821
1822      We make very conservative checks below and only try to handle the
1823      most common cases of this.  For example, we only handle the case
1824      where I2 and I3 are adjacent to avoid making difficult register
1825      usage tests.  */
1826
1827   if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
1828       && REG_P (SET_SRC (PATTERN (i3)))
1829       && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1830       && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1831       && GET_CODE (PATTERN (i2)) == PARALLEL
1832       && ! side_effects_p (SET_DEST (PATTERN (i3)))
1833       /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1834          below would need to check what is inside (and reg_overlap_mentioned_p
1835          doesn't support those codes anyway).  Don't allow those destinations;
1836          the resulting insn isn't likely to be recognized anyway.  */
1837       && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1838       && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1839       && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1840                                     SET_DEST (PATTERN (i3)))
1841       && next_real_insn (i2) == i3)
1842     {
1843       rtx p2 = PATTERN (i2);
1844
1845       /* Make sure that the destination of I3,
1846          which we are going to substitute into one output of I2,
1847          is not used within another output of I2.  We must avoid making this:
1848          (parallel [(set (mem (reg 69)) ...)
1849                     (set (reg 69) ...)])
1850          which is not well-defined as to order of actions.
1851          (Besides, reload can't handle output reloads for this.)
1852
1853          The problem can also happen if the dest of I3 is a memory ref,
1854          if another dest in I2 is an indirect memory ref.  */
1855       for (i = 0; i < XVECLEN (p2, 0); i++)
1856         if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1857              || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1858             && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1859                                         SET_DEST (XVECEXP (p2, 0, i))))
1860           break;
1861
1862       if (i == XVECLEN (p2, 0))
1863         for (i = 0; i < XVECLEN (p2, 0); i++)
1864           if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1865                || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1866               && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1867             {
1868               combine_merges++;
1869
1870               subst_insn = i3;
1871               subst_low_cuid = INSN_CUID (i2);
1872
1873               added_sets_2 = added_sets_1 = 0;
1874               i2dest = SET_SRC (PATTERN (i3));
1875               i2dest_killed = dead_or_set_p (i2, i2dest);
1876
1877               /* Replace the dest in I2 with our dest and make the resulting
1878                  insn the new pattern for I3.  Then skip to where we
1879                  validate the pattern.  Everything was set up above.  */
1880               SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1881                      SET_DEST (PATTERN (i3)));
1882
1883               newpat = p2;
1884               i3_subst_into_i2 = 1;
1885               goto validate_replacement;
1886             }
1887     }
1888
1889   /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1890      one of those words to another constant, merge them by making a new
1891      constant.  */
1892   if (i1 == 0
1893       && (temp = single_set (i2)) != 0
1894       && (GET_CODE (SET_SRC (temp)) == CONST_INT
1895           || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1896       && REG_P (SET_DEST (temp))
1897       && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1898       && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1899       && GET_CODE (PATTERN (i3)) == SET
1900       && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1901       && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1902       && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1903       && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1904       && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1905     {
1906       HOST_WIDE_INT lo, hi;
1907
1908       if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1909         lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1910       else
1911         {
1912           lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1913           hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1914         }
1915
1916       if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1917         {
1918           /* We don't handle the case of the target word being wider
1919              than a host wide int.  */
1920           gcc_assert (HOST_BITS_PER_WIDE_INT >= BITS_PER_WORD);
1921
1922           lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1923           lo |= (INTVAL (SET_SRC (PATTERN (i3)))
1924                  & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1925         }
1926       else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1927         hi = INTVAL (SET_SRC (PATTERN (i3)));
1928       else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD)
1929         {
1930           int sign = -(int) ((unsigned HOST_WIDE_INT) lo
1931                              >> (HOST_BITS_PER_WIDE_INT - 1));
1932
1933           lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1934                    (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1935           lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1936                  (INTVAL (SET_SRC (PATTERN (i3)))));
1937           if (hi == sign)
1938             hi = lo < 0 ? -1 : 0;
1939         }
1940       else
1941         /* We don't handle the case of the higher word not fitting
1942            entirely in either hi or lo.  */
1943         gcc_unreachable ();
1944
1945       combine_merges++;
1946       subst_insn = i3;
1947       subst_low_cuid = INSN_CUID (i2);
1948       added_sets_2 = added_sets_1 = 0;
1949       i2dest = SET_DEST (temp);
1950       i2dest_killed = dead_or_set_p (i2, i2dest);
1951
1952       SUBST (SET_SRC (temp),
1953              immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1954
1955       newpat = PATTERN (i2);
1956       goto validate_replacement;
1957     }
1958
1959 #ifndef HAVE_cc0
1960   /* If we have no I1 and I2 looks like:
1961         (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1962                    (set Y OP)])
1963      make up a dummy I1 that is
1964         (set Y OP)
1965      and change I2 to be
1966         (set (reg:CC X) (compare:CC Y (const_int 0)))
1967
1968      (We can ignore any trailing CLOBBERs.)
1969
1970      This undoes a previous combination and allows us to match a branch-and-
1971      decrement insn.  */
1972
1973   if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1974       && XVECLEN (PATTERN (i2), 0) >= 2
1975       && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1976       && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1977           == MODE_CC)
1978       && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1979       && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1980       && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1981       && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
1982       && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1983                       SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1984     {
1985       for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1986         if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1987           break;
1988
1989       if (i == 1)
1990         {
1991           /* We make I1 with the same INSN_UID as I2.  This gives it
1992              the same INSN_CUID for value tracking.  Our fake I1 will
1993              never appear in the insn stream so giving it the same INSN_UID
1994              as I2 will not cause a problem.  */
1995
1996           i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1997                              BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
1998                              XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1999                              NULL_RTX);
2000
2001           SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2002           SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2003                  SET_DEST (PATTERN (i1)));
2004         }
2005     }
2006 #endif
2007
2008   /* Verify that I2 and I1 are valid for combining.  */
2009   if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
2010       || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
2011     {
2012       undo_all ();
2013       return 0;
2014     }
2015
2016   /* Record whether I2DEST is used in I2SRC and similarly for the other
2017      cases.  Knowing this will help in register status updating below.  */
2018   i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2019   i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2020   i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2021   i2dest_killed = dead_or_set_p (i2, i2dest);
2022   i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2023
2024   /* See if I1 directly feeds into I3.  It does if I1DEST is not used
2025      in I2SRC.  */
2026   i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
2027
2028   /* Ensure that I3's pattern can be the destination of combines.  */
2029   if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
2030                           i1 && i2dest_in_i1src && i1_feeds_i3,
2031                           &i3dest_killed))
2032     {
2033       undo_all ();
2034       return 0;
2035     }
2036
2037   /* See if any of the insns is a MULT operation.  Unless one is, we will
2038      reject a combination that is, since it must be slower.  Be conservative
2039      here.  */
2040   if (GET_CODE (i2src) == MULT
2041       || (i1 != 0 && GET_CODE (i1src) == MULT)
2042       || (GET_CODE (PATTERN (i3)) == SET
2043           && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2044     have_mult = 1;
2045
2046   /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2047      We used to do this EXCEPT in one case: I3 has a post-inc in an
2048      output operand.  However, that exception can give rise to insns like
2049         mov r3,(r3)+
2050      which is a famous insn on the PDP-11 where the value of r3 used as the
2051      source was model-dependent.  Avoid this sort of thing.  */
2052
2053 #if 0
2054   if (!(GET_CODE (PATTERN (i3)) == SET
2055         && REG_P (SET_SRC (PATTERN (i3)))
2056         && MEM_P (SET_DEST (PATTERN (i3)))
2057         && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2058             || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2059     /* It's not the exception.  */
2060 #endif
2061 #ifdef AUTO_INC_DEC
2062     for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2063       if (REG_NOTE_KIND (link) == REG_INC
2064           && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2065               || (i1 != 0
2066                   && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2067         {
2068           undo_all ();
2069           return 0;
2070         }
2071 #endif
2072
2073   /* See if the SETs in I1 or I2 need to be kept around in the merged
2074      instruction: whenever the value set there is still needed past I3.
2075      For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2076
2077      For the SET in I1, we have two cases:  If I1 and I2 independently
2078      feed into I3, the set in I1 needs to be kept around if I1DEST dies
2079      or is set in I3.  Otherwise (if I1 feeds I2 which feeds I3), the set
2080      in I1 needs to be kept around unless I1DEST dies or is set in either
2081      I2 or I3.  We can distinguish these cases by seeing if I2SRC mentions
2082      I1DEST.  If so, we know I1 feeds into I2.  */
2083
2084   added_sets_2 = ! dead_or_set_p (i3, i2dest);
2085
2086   added_sets_1
2087     = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2088                : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2089
2090   /* If the set in I2 needs to be kept around, we must make a copy of
2091      PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2092      PATTERN (I2), we are only substituting for the original I1DEST, not into
2093      an already-substituted copy.  This also prevents making self-referential
2094      rtx.  If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2095      I2DEST.  */
2096
2097   if (added_sets_2)
2098     {
2099       if (GET_CODE (PATTERN (i2)) == PARALLEL)
2100         i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2101       else
2102         i2pat = copy_rtx (PATTERN (i2));
2103     }
2104
2105   if (added_sets_1)
2106     {
2107       if (GET_CODE (PATTERN (i1)) == PARALLEL)
2108         i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2109       else
2110         i1pat = copy_rtx (PATTERN (i1));
2111     }
2112
2113   combine_merges++;
2114
2115   /* Substitute in the latest insn for the regs set by the earlier ones.  */
2116
2117   maxreg = max_reg_num ();
2118
2119   subst_insn = i3;
2120
2121   /* It is possible that the source of I2 or I1 may be performing an
2122      unneeded operation, such as a ZERO_EXTEND of something that is known
2123      to have the high part zero.  Handle that case by letting subst look at
2124      the innermost one of them.
2125
2126      Another way to do this would be to have a function that tries to
2127      simplify a single insn instead of merging two or more insns.  We don't
2128      do this because of the potential of infinite loops and because
2129      of the potential extra memory required.  However, doing it the way
2130      we are is a bit of a kludge and doesn't catch all cases.
2131
2132      But only do this if -fexpensive-optimizations since it slows things down
2133      and doesn't usually win.  */
2134
2135   if (flag_expensive_optimizations)
2136     {
2137       /* Pass pc_rtx so no substitutions are done, just simplifications.  */
2138       if (i1)
2139         {
2140           subst_low_cuid = INSN_CUID (i1);
2141           i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2142         }
2143       else
2144         {
2145           subst_low_cuid = INSN_CUID (i2);
2146           i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2147         }
2148     }
2149
2150 #ifndef HAVE_cc0
2151   /* Many machines that don't use CC0 have insns that can both perform an
2152      arithmetic operation and set the condition code.  These operations will
2153      be represented as a PARALLEL with the first element of the vector
2154      being a COMPARE of an arithmetic operation with the constant zero.
2155      The second element of the vector will set some pseudo to the result
2156      of the same arithmetic operation.  If we simplify the COMPARE, we won't
2157      match such a pattern and so will generate an extra insn.   Here we test
2158      for this case, where both the comparison and the operation result are
2159      needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2160      I2SRC.  Later we will make the PARALLEL that contains I2.  */
2161
2162   if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2163       && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2164       && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2165       && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2166     {
2167 #ifdef SELECT_CC_MODE
2168       rtx *cc_use;
2169       enum machine_mode compare_mode;
2170 #endif
2171
2172       newpat = PATTERN (i3);
2173       SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2174
2175       i2_is_used = 1;
2176
2177 #ifdef SELECT_CC_MODE
2178       /* See if a COMPARE with the operand we substituted in should be done
2179          with the mode that is currently being used.  If not, do the same
2180          processing we do in `subst' for a SET; namely, if the destination
2181          is used only once, try to replace it with a register of the proper
2182          mode and also replace the COMPARE.  */
2183       if (undobuf.other_insn == 0
2184           && (cc_use = find_single_use (SET_DEST (newpat), i3,
2185                                         &undobuf.other_insn))
2186           && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2187                                               i2src, const0_rtx))
2188               != GET_MODE (SET_DEST (newpat))))
2189         {
2190           if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
2191                                    compare_mode))
2192             {
2193               unsigned int regno = REGNO (SET_DEST (newpat));
2194               rtx new_dest = gen_rtx_REG (compare_mode, regno);
2195
2196               if (regno >= FIRST_PSEUDO_REGISTER)
2197                 SUBST (regno_reg_rtx[regno], new_dest);
2198
2199               SUBST (SET_DEST (newpat), new_dest);
2200               SUBST (XEXP (*cc_use, 0), new_dest);
2201               SUBST (SET_SRC (newpat),
2202                      gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2203             }
2204           else
2205             undobuf.other_insn = 0;
2206         }
2207 #endif
2208     }
2209   else
2210 #endif
2211     {
2212       n_occurrences = 0;                /* `subst' counts here */
2213
2214       /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2215          need to make a unique copy of I2SRC each time we substitute it
2216          to avoid self-referential rtl.  */
2217
2218       subst_low_cuid = INSN_CUID (i2);
2219       newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2220                       ! i1_feeds_i3 && i1dest_in_i1src);
2221       substed_i2 = 1;
2222
2223       /* Record whether i2's body now appears within i3's body.  */
2224       i2_is_used = n_occurrences;
2225     }
2226
2227   /* If we already got a failure, don't try to do more.  Otherwise,
2228      try to substitute in I1 if we have it.  */
2229
2230   if (i1 && GET_CODE (newpat) != CLOBBER)
2231     {
2232       /* Before we can do this substitution, we must redo the test done
2233          above (see detailed comments there) that ensures  that I1DEST
2234          isn't mentioned in any SETs in NEWPAT that are field assignments.  */
2235
2236       if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
2237                               0, (rtx*) 0))
2238         {
2239           undo_all ();
2240           return 0;
2241         }
2242
2243       n_occurrences = 0;
2244       subst_low_cuid = INSN_CUID (i1);
2245       newpat = subst (newpat, i1dest, i1src, 0, 0);
2246       substed_i1 = 1;
2247     }
2248
2249   /* Fail if an autoincrement side-effect has been duplicated.  Be careful
2250      to count all the ways that I2SRC and I1SRC can be used.  */
2251   if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2252        && i2_is_used + added_sets_2 > 1)
2253       || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2254           && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2255               > 1))
2256       /* Fail if we tried to make a new register.  */
2257       || max_reg_num () != maxreg
2258       /* Fail if we couldn't do something and have a CLOBBER.  */
2259       || GET_CODE (newpat) == CLOBBER
2260       /* Fail if this new pattern is a MULT and we didn't have one before
2261          at the outer level.  */
2262       || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2263           && ! have_mult))
2264     {
2265       undo_all ();
2266       return 0;
2267     }
2268
2269   /* If the actions of the earlier insns must be kept
2270      in addition to substituting them into the latest one,
2271      we must make a new PARALLEL for the latest insn
2272      to hold additional the SETs.  */
2273
2274   if (added_sets_1 || added_sets_2)
2275     {
2276       combine_extras++;
2277
2278       if (GET_CODE (newpat) == PARALLEL)
2279         {
2280           rtvec old = XVEC (newpat, 0);
2281           total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2282           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2283           memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2284                   sizeof (old->elem[0]) * old->num_elem);
2285         }
2286       else
2287         {
2288           rtx old = newpat;
2289           total_sets = 1 + added_sets_1 + added_sets_2;
2290           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2291           XVECEXP (newpat, 0, 0) = old;
2292         }
2293
2294       if (added_sets_1)
2295         XVECEXP (newpat, 0, --total_sets) = i1pat;
2296
2297       if (added_sets_2)
2298         {
2299           /* If there is no I1, use I2's body as is.  We used to also not do
2300              the subst call below if I2 was substituted into I3,
2301              but that could lose a simplification.  */
2302           if (i1 == 0)
2303             XVECEXP (newpat, 0, --total_sets) = i2pat;
2304           else
2305             /* See comment where i2pat is assigned.  */
2306             XVECEXP (newpat, 0, --total_sets)
2307               = subst (i2pat, i1dest, i1src, 0, 0);
2308         }
2309     }
2310
2311   /* We come here when we are replacing a destination in I2 with the
2312      destination of I3.  */
2313  validate_replacement:
2314
2315   /* Note which hard regs this insn has as inputs.  */
2316   mark_used_regs_combine (newpat);
2317
2318   /* If recog_for_combine fails, it strips existing clobbers.  If we'll
2319      consider splitting this pattern, we might need these clobbers.  */
2320   if (i1 && GET_CODE (newpat) == PARALLEL
2321       && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
2322     {
2323       int len = XVECLEN (newpat, 0);
2324
2325       newpat_vec_with_clobbers = rtvec_alloc (len);
2326       for (i = 0; i < len; i++)
2327         RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
2328     }
2329
2330   /* Is the result of combination a valid instruction?  */
2331   insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2332
2333   /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2334      the second SET's destination is a register that is unused and isn't
2335      marked as an instruction that might trap in an EH region.  In that case,
2336      we just need the first SET.   This can occur when simplifying a divmod
2337      insn.  We *must* test for this case here because the code below that
2338      splits two independent SETs doesn't handle this case correctly when it
2339      updates the register status.
2340
2341      It's pointless doing this if we originally had two sets, one from
2342      i3, and one from i2.  Combining then splitting the parallel results
2343      in the original i2 again plus an invalid insn (which we delete).
2344      The net effect is only to move instructions around, which makes
2345      debug info less accurate.
2346
2347      Also check the case where the first SET's destination is unused.
2348      That would not cause incorrect code, but does cause an unneeded
2349      insn to remain.  */
2350
2351   if (insn_code_number < 0
2352       && !(added_sets_2 && i1 == 0)
2353       && GET_CODE (newpat) == PARALLEL
2354       && XVECLEN (newpat, 0) == 2
2355       && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2356       && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2357       && asm_noperands (newpat) < 0)
2358     {
2359       rtx set0 = XVECEXP (newpat, 0, 0);
2360       rtx set1 = XVECEXP (newpat, 0, 1);
2361       rtx note;
2362
2363       if (((REG_P (SET_DEST (set1))
2364             && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2365            || (GET_CODE (SET_DEST (set1)) == SUBREG
2366                && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2367           && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2368               || INTVAL (XEXP (note, 0)) <= 0)
2369           && ! side_effects_p (SET_SRC (set1)))
2370         {
2371           newpat = set0;
2372           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2373         }
2374
2375       else if (((REG_P (SET_DEST (set0))
2376                  && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2377                 || (GET_CODE (SET_DEST (set0)) == SUBREG
2378                     && find_reg_note (i3, REG_UNUSED,
2379                                       SUBREG_REG (SET_DEST (set0)))))
2380                && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2381                    || INTVAL (XEXP (note, 0)) <= 0)
2382                && ! side_effects_p (SET_SRC (set0)))
2383         {
2384           newpat = set1;
2385           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2386
2387           if (insn_code_number >= 0)
2388             {
2389               /* If we will be able to accept this, we have made a
2390                  change to the destination of I3.  This requires us to
2391                  do a few adjustments.  */
2392
2393               PATTERN (i3) = newpat;
2394               adjust_for_new_dest (i3);
2395             }
2396         }
2397     }
2398
2399   /* If we were combining three insns and the result is a simple SET
2400      with no ASM_OPERANDS that wasn't recognized, try to split it into two
2401      insns.  There are two ways to do this.  It can be split using a
2402      machine-specific method (like when you have an addition of a large
2403      constant) or by combine in the function find_split_point.  */
2404
2405   if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2406       && asm_noperands (newpat) < 0)
2407     {
2408       rtx m_split, *split;
2409       rtx ni2dest = i2dest;
2410
2411       /* See if the MD file can split NEWPAT.  If it can't, see if letting it
2412          use I2DEST as a scratch register will help.  In the latter case,
2413          convert I2DEST to the mode of the source of NEWPAT if we can.  */
2414
2415       m_split = split_insns (newpat, i3);
2416
2417       /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2418          inputs of NEWPAT.  */
2419
2420       /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2421          possible to try that as a scratch reg.  This would require adding
2422          more code to make it work though.  */
2423
2424       if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2425         {
2426           enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
2427           /* If I2DEST is a hard register or the only use of a pseudo,
2428              we can change its mode.  */
2429           if (new_mode != GET_MODE (i2dest)
2430               && new_mode != VOIDmode
2431               && can_change_dest_mode (i2dest, added_sets_2, new_mode))
2432             ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2433                                    REGNO (i2dest));
2434
2435           m_split = split_insns (gen_rtx_PARALLEL
2436                                  (VOIDmode,
2437                                   gen_rtvec (2, newpat,
2438                                              gen_rtx_CLOBBER (VOIDmode,
2439                                                               ni2dest))),
2440                                  i3);
2441           /* If the split with the mode-changed register didn't work, try
2442              the original register.  */
2443           if (! m_split && ni2dest != i2dest)
2444             {
2445               ni2dest = i2dest;
2446               m_split = split_insns (gen_rtx_PARALLEL
2447                                      (VOIDmode,
2448                                       gen_rtvec (2, newpat,
2449                                                  gen_rtx_CLOBBER (VOIDmode,
2450                                                                   i2dest))),
2451                                      i3);
2452             }
2453         }
2454
2455       /* If recog_for_combine has discarded clobbers, try to use them
2456          again for the split.  */
2457       if (m_split == 0 && newpat_vec_with_clobbers)
2458         m_split
2459           = split_insns (gen_rtx_PARALLEL (VOIDmode,
2460                                            newpat_vec_with_clobbers), i3);
2461
2462       if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2463         {
2464           m_split = PATTERN (m_split);
2465           insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2466           if (insn_code_number >= 0)
2467             newpat = m_split;
2468         }
2469       else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2470                && (next_real_insn (i2) == i3
2471                    || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2472         {
2473           rtx i2set, i3set;
2474           rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2475           newi2pat = PATTERN (m_split);
2476
2477           i3set = single_set (NEXT_INSN (m_split));
2478           i2set = single_set (m_split);
2479
2480           /* In case we changed the mode of I2DEST, replace it in the
2481              pseudo-register table here.  We can't do it above in case this
2482              code doesn't get executed and we do a split the other way.  */
2483
2484           if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2485             SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2486
2487           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2488
2489           /* If I2 or I3 has multiple SETs, we won't know how to track
2490              register status, so don't use these insns.  If I2's destination
2491              is used between I2 and I3, we also can't use these insns.  */
2492
2493           if (i2_code_number >= 0 && i2set && i3set
2494               && (next_real_insn (i2) == i3
2495                   || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2496             insn_code_number = recog_for_combine (&newi3pat, i3,
2497                                                   &new_i3_notes);
2498           if (insn_code_number >= 0)
2499             newpat = newi3pat;
2500
2501           /* It is possible that both insns now set the destination of I3.
2502              If so, we must show an extra use of it.  */
2503
2504           if (insn_code_number >= 0)
2505             {
2506               rtx new_i3_dest = SET_DEST (i3set);
2507               rtx new_i2_dest = SET_DEST (i2set);
2508
2509               while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2510                      || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2511                      || GET_CODE (new_i3_dest) == SUBREG)
2512                 new_i3_dest = XEXP (new_i3_dest, 0);
2513
2514               while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2515                      || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2516                      || GET_CODE (new_i2_dest) == SUBREG)
2517                 new_i2_dest = XEXP (new_i2_dest, 0);
2518
2519               if (REG_P (new_i3_dest)
2520                   && REG_P (new_i2_dest)
2521                   && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2522                 REG_N_SETS (REGNO (new_i2_dest))++;
2523             }
2524         }
2525
2526       /* If we can split it and use I2DEST, go ahead and see if that
2527          helps things be recognized.  Verify that none of the registers
2528          are set between I2 and I3.  */
2529       if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2530 #ifdef HAVE_cc0
2531           && REG_P (i2dest)
2532 #endif
2533           /* We need I2DEST in the proper mode.  If it is a hard register
2534              or the only use of a pseudo, we can change its mode.
2535              Make sure we don't change a hard register to have a mode that
2536              isn't valid for it, or change the number of registers.  */
2537           && (GET_MODE (*split) == GET_MODE (i2dest)
2538               || GET_MODE (*split) == VOIDmode
2539               || can_change_dest_mode (i2dest, added_sets_2,
2540                                        GET_MODE (*split)))
2541           && (next_real_insn (i2) == i3
2542               || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2543           /* We can't overwrite I2DEST if its value is still used by
2544              NEWPAT.  */
2545           && ! reg_referenced_p (i2dest, newpat))
2546         {
2547           rtx newdest = i2dest;
2548           enum rtx_code split_code = GET_CODE (*split);
2549           enum machine_mode split_mode = GET_MODE (*split);
2550
2551           /* Get NEWDEST as a register in the proper mode.  We have already
2552              validated that we can do this.  */
2553           if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2554             {
2555               newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2556
2557               if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2558                 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2559             }
2560
2561           /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2562              an ASHIFT.  This can occur if it was inside a PLUS and hence
2563              appeared to be a memory address.  This is a kludge.  */
2564           if (split_code == MULT
2565               && GET_CODE (XEXP (*split, 1)) == CONST_INT
2566               && INTVAL (XEXP (*split, 1)) > 0
2567               && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2568             {
2569               SUBST (*split, gen_rtx_ASHIFT (split_mode,
2570                                              XEXP (*split, 0), GEN_INT (i)));
2571               /* Update split_code because we may not have a multiply
2572                  anymore.  */
2573               split_code = GET_CODE (*split);
2574             }
2575
2576 #ifdef INSN_SCHEDULING
2577           /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2578              be written as a ZERO_EXTEND.  */
2579           if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
2580             {
2581 #ifdef LOAD_EXTEND_OP
2582               /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2583                  what it really is.  */
2584               if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
2585                   == SIGN_EXTEND)
2586                 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
2587                                                     SUBREG_REG (*split)));
2588               else
2589 #endif
2590                 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2591                                                     SUBREG_REG (*split)));
2592             }
2593 #endif
2594
2595           newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2596           SUBST (*split, newdest);
2597           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2598
2599           /* recog_for_combine might have added CLOBBERs to newi2pat.
2600              Make sure NEWPAT does not depend on the clobbered regs.  */
2601           if (GET_CODE (newi2pat) == PARALLEL)
2602             for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
2603               if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
2604                 {
2605                   rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
2606                   if (reg_overlap_mentioned_p (reg, newpat))
2607                     {
2608                       undo_all ();
2609                       return 0;
2610                     }
2611                 }
2612
2613           /* If the split point was a MULT and we didn't have one before,
2614              don't use one now.  */
2615           if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2616             insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2617         }
2618     }
2619
2620   /* Check for a case where we loaded from memory in a narrow mode and
2621      then sign extended it, but we need both registers.  In that case,
2622      we have a PARALLEL with both loads from the same memory location.
2623      We can split this into a load from memory followed by a register-register
2624      copy.  This saves at least one insn, more if register allocation can
2625      eliminate the copy.
2626
2627      We cannot do this if the destination of the first assignment is a
2628      condition code register or cc0.  We eliminate this case by making sure
2629      the SET_DEST and SET_SRC have the same mode.
2630
2631      We cannot do this if the destination of the second assignment is
2632      a register that we have already assumed is zero-extended.  Similarly
2633      for a SUBREG of such a register.  */
2634
2635   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2636            && GET_CODE (newpat) == PARALLEL
2637            && XVECLEN (newpat, 0) == 2
2638            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2639            && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2640            && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
2641                == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
2642            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2643            && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2644                            XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2645            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2646                                    INSN_CUID (i2))
2647            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2648            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2649            && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2650                  (REG_P (temp)
2651                   && reg_stat[REGNO (temp)].nonzero_bits != 0
2652                   && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2653                   && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2654                   && (reg_stat[REGNO (temp)].nonzero_bits
2655                       != GET_MODE_MASK (word_mode))))
2656            && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2657                  && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2658                      (REG_P (temp)
2659                       && reg_stat[REGNO (temp)].nonzero_bits != 0
2660                       && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2661                       && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2662                       && (reg_stat[REGNO (temp)].nonzero_bits
2663                           != GET_MODE_MASK (word_mode)))))
2664            && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2665                                          SET_SRC (XVECEXP (newpat, 0, 1)))
2666            && ! find_reg_note (i3, REG_UNUSED,
2667                                SET_DEST (XVECEXP (newpat, 0, 0))))
2668     {
2669       rtx ni2dest;
2670
2671       newi2pat = XVECEXP (newpat, 0, 0);
2672       ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2673       newpat = XVECEXP (newpat, 0, 1);
2674       SUBST (SET_SRC (newpat),
2675              gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
2676       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2677
2678       if (i2_code_number >= 0)
2679         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2680
2681       if (insn_code_number >= 0)
2682         swap_i2i3 = 1;
2683     }
2684
2685   /* Similarly, check for a case where we have a PARALLEL of two independent
2686      SETs but we started with three insns.  In this case, we can do the sets
2687      as two separate insns.  This case occurs when some SET allows two
2688      other insns to combine, but the destination of that SET is still live.  */
2689
2690   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2691            && GET_CODE (newpat) == PARALLEL
2692            && XVECLEN (newpat, 0) == 2
2693            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2694            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2695            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2696            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2697            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2698            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2699            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2700                                    INSN_CUID (i2))
2701            /* Don't pass sets with (USE (MEM ...)) dests to the following.  */
2702            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2703            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2704            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2705                                   XVECEXP (newpat, 0, 0))
2706            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2707                                   XVECEXP (newpat, 0, 1))
2708            && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2709                  && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2710     {
2711       /* Normally, it doesn't matter which of the two is done first,
2712          but it does if one references cc0.  In that case, it has to
2713          be first.  */
2714 #ifdef HAVE_cc0
2715       if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2716         {
2717           newi2pat = XVECEXP (newpat, 0, 0);
2718           newpat = XVECEXP (newpat, 0, 1);
2719         }
2720       else
2721 #endif
2722         {
2723           newi2pat = XVECEXP (newpat, 0, 1);
2724           newpat = XVECEXP (newpat, 0, 0);
2725         }
2726
2727       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2728
2729       if (i2_code_number >= 0)
2730         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2731     }
2732
2733   /* If it still isn't recognized, fail and change things back the way they
2734      were.  */
2735   if ((insn_code_number < 0
2736        /* Is the result a reasonable ASM_OPERANDS?  */
2737        && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2738     {
2739       undo_all ();
2740       return 0;
2741     }
2742
2743   /* If we had to change another insn, make sure it is valid also.  */
2744   if (undobuf.other_insn)
2745     {
2746       rtx other_pat = PATTERN (undobuf.other_insn);
2747       rtx new_other_notes;
2748       rtx note, next;
2749
2750       CLEAR_HARD_REG_SET (newpat_used_regs);
2751
2752       other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2753                                              &new_other_notes);
2754
2755       if (other_code_number < 0 && ! check_asm_operands (other_pat))
2756         {
2757           undo_all ();
2758           return 0;
2759         }
2760
2761       PATTERN (undobuf.other_insn) = other_pat;
2762
2763       /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2764          are still valid.  Then add any non-duplicate notes added by
2765          recog_for_combine.  */
2766       for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2767         {
2768           next = XEXP (note, 1);
2769
2770           if (REG_NOTE_KIND (note) == REG_UNUSED
2771               && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2772             {
2773               if (REG_P (XEXP (note, 0)))
2774                 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2775
2776               remove_note (undobuf.other_insn, note);
2777             }
2778         }
2779
2780       for (note = new_other_notes; note; note = XEXP (note, 1))
2781         if (REG_P (XEXP (note, 0)))
2782           REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2783
2784       distribute_notes (new_other_notes, undobuf.other_insn,
2785                         undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2786     }
2787 #ifdef HAVE_cc0
2788   /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
2789      they are adjacent to each other or not.  */
2790   {
2791     rtx p = prev_nonnote_insn (i3);
2792     if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
2793         && sets_cc0_p (newi2pat))
2794       {
2795         undo_all ();
2796         return 0;
2797       }
2798   }
2799 #endif
2800
2801   /* Only allow this combination if insn_rtx_costs reports that the
2802      replacement instructions are cheaper than the originals.  */
2803   if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat))
2804     {
2805       undo_all ();
2806       return 0;
2807     }
2808
2809   /* We now know that we can do this combination.  Merge the insns and
2810      update the status of registers and LOG_LINKS.  */
2811
2812   if (swap_i2i3)
2813     {
2814       rtx insn;
2815       rtx link;
2816       rtx ni2dest;
2817
2818       /* I3 now uses what used to be its destination and which is now
2819          I2's destination.  This requires us to do a few adjustments.  */
2820       PATTERN (i3) = newpat;
2821       adjust_for_new_dest (i3);
2822
2823       /* We need a LOG_LINK from I3 to I2.  But we used to have one,
2824          so we still will.
2825
2826          However, some later insn might be using I2's dest and have
2827          a LOG_LINK pointing at I3.  We must remove this link.
2828          The simplest way to remove the link is to point it at I1,
2829          which we know will be a NOTE.  */
2830
2831       /* newi2pat is usually a SET here; however, recog_for_combine might
2832          have added some clobbers.  */
2833       if (GET_CODE (newi2pat) == PARALLEL)
2834         ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
2835       else
2836         ni2dest = SET_DEST (newi2pat);
2837
2838       for (insn = NEXT_INSN (i3);
2839            insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2840                     || insn != BB_HEAD (this_basic_block->next_bb));
2841            insn = NEXT_INSN (insn))
2842         {
2843           if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2844             {
2845               for (link = LOG_LINKS (insn); link;
2846                    link = XEXP (link, 1))
2847                 if (XEXP (link, 0) == i3)
2848                   XEXP (link, 0) = i1;
2849
2850               break;
2851             }
2852         }
2853     }
2854
2855   {
2856     rtx i3notes, i2notes, i1notes = 0;
2857     rtx i3links, i2links, i1links = 0;
2858     rtx midnotes = 0;
2859     unsigned int regno;
2860     /* Compute which registers we expect to eliminate.  newi2pat may be setting
2861        either i3dest or i2dest, so we must check it.  Also, i1dest may be the
2862        same as i3dest, in which case newi2pat may be setting i1dest.  */
2863     rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2864                    || i2dest_in_i2src || i2dest_in_i1src
2865                    || !i2dest_killed
2866                    ? 0 : i2dest);
2867     rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2868                    || (newi2pat && reg_set_p (i1dest, newi2pat))
2869                    || !i1dest_killed
2870                    ? 0 : i1dest);
2871
2872     /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2873        clear them.  */
2874     i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2875     i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2876     if (i1)
2877       i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2878
2879     /* Ensure that we do not have something that should not be shared but
2880        occurs multiple times in the new insns.  Check this by first
2881        resetting all the `used' flags and then copying anything is shared.  */
2882
2883     reset_used_flags (i3notes);
2884     reset_used_flags (i2notes);
2885     reset_used_flags (i1notes);
2886     reset_used_flags (newpat);
2887     reset_used_flags (newi2pat);
2888     if (undobuf.other_insn)
2889       reset_used_flags (PATTERN (undobuf.other_insn));
2890
2891     i3notes = copy_rtx_if_shared (i3notes);
2892     i2notes = copy_rtx_if_shared (i2notes);
2893     i1notes = copy_rtx_if_shared (i1notes);
2894     newpat = copy_rtx_if_shared (newpat);
2895     newi2pat = copy_rtx_if_shared (newi2pat);
2896     if (undobuf.other_insn)
2897       reset_used_flags (PATTERN (undobuf.other_insn));
2898
2899     INSN_CODE (i3) = insn_code_number;
2900     PATTERN (i3) = newpat;
2901
2902     if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
2903       {
2904         rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
2905
2906         reset_used_flags (call_usage);
2907         call_usage = copy_rtx (call_usage);
2908
2909         if (substed_i2)
2910           replace_rtx (call_usage, i2dest, i2src);
2911
2912         if (substed_i1)
2913           replace_rtx (call_usage, i1dest, i1src);
2914
2915         CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
2916       }
2917
2918     if (undobuf.other_insn)
2919       INSN_CODE (undobuf.other_insn) = other_code_number;
2920
2921     /* We had one special case above where I2 had more than one set and
2922        we replaced a destination of one of those sets with the destination
2923        of I3.  In that case, we have to update LOG_LINKS of insns later
2924        in this basic block.  Note that this (expensive) case is rare.
2925
2926        Also, in this case, we must pretend that all REG_NOTEs for I2
2927        actually came from I3, so that REG_UNUSED notes from I2 will be
2928        properly handled.  */
2929
2930     if (i3_subst_into_i2)
2931       {
2932         for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2933           if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
2934               && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
2935               && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2936               && ! find_reg_note (i2, REG_UNUSED,
2937                                   SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2938             for (temp = NEXT_INSN (i2);
2939                  temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2940                           || BB_HEAD (this_basic_block) != temp);
2941                  temp = NEXT_INSN (temp))
2942               if (temp != i3 && INSN_P (temp))
2943                 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2944                   if (XEXP (link, 0) == i2)
2945                     XEXP (link, 0) = i3;
2946
2947         if (i3notes)
2948           {
2949             rtx link = i3notes;
2950             while (XEXP (link, 1))
2951               link = XEXP (link, 1);
2952             XEXP (link, 1) = i2notes;
2953           }
2954         else
2955           i3notes = i2notes;
2956         i2notes = 0;
2957       }
2958
2959     LOG_LINKS (i3) = 0;
2960     REG_NOTES (i3) = 0;
2961     LOG_LINKS (i2) = 0;
2962     REG_NOTES (i2) = 0;
2963
2964     if (newi2pat)
2965       {
2966         INSN_CODE (i2) = i2_code_number;
2967         PATTERN (i2) = newi2pat;
2968       }
2969     else
2970       SET_INSN_DELETED (i2);
2971
2972     if (i1)
2973       {
2974         LOG_LINKS (i1) = 0;
2975         REG_NOTES (i1) = 0;
2976         SET_INSN_DELETED (i1);
2977       }
2978
2979     /* Get death notes for everything that is now used in either I3 or
2980        I2 and used to die in a previous insn.  If we built two new
2981        patterns, move from I1 to I2 then I2 to I3 so that we get the
2982        proper movement on registers that I2 modifies.  */
2983
2984     if (newi2pat)
2985       {
2986         move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2987         move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2988       }
2989     else
2990       move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2991                    i3, &midnotes);
2992
2993     /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3.  */
2994     if (i3notes)
2995       distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2996                         elim_i2, elim_i1);
2997     if (i2notes)
2998       distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2999                         elim_i2, elim_i1);
3000     if (i1notes)
3001       distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
3002                         elim_i2, elim_i1);
3003     if (midnotes)
3004       distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3005                         elim_i2, elim_i1);
3006
3007     /* Distribute any notes added to I2 or I3 by recog_for_combine.  We
3008        know these are REG_UNUSED and want them to go to the desired insn,
3009        so we always pass it as i3.  We have not counted the notes in
3010        reg_n_deaths yet, so we need to do so now.  */
3011
3012     if (newi2pat && new_i2_notes)
3013       {
3014         for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
3015           if (REG_P (XEXP (temp, 0)))
3016             REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
3017
3018         distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3019       }
3020
3021     if (new_i3_notes)
3022       {
3023         for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
3024           if (REG_P (XEXP (temp, 0)))
3025             REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
3026
3027         distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
3028       }
3029
3030     /* If I3DEST was used in I3SRC, it really died in I3.  We may need to
3031        put a REG_DEAD note for it somewhere.  If NEWI2PAT exists and sets
3032        I3DEST, the death must be somewhere before I2, not I3.  If we passed I3
3033        in that case, it might delete I2.  Similarly for I2 and I1.
3034        Show an additional death due to the REG_DEAD note we make here.  If
3035        we discard it in distribute_notes, we will decrement it again.  */
3036
3037     if (i3dest_killed)
3038       {
3039         if (REG_P (i3dest_killed))
3040           REG_N_DEATHS (REGNO (i3dest_killed))++;
3041
3042         if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
3043           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3044                                                NULL_RTX),
3045                             NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
3046         else
3047           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3048                                                NULL_RTX),
3049                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3050                             elim_i2, elim_i1);
3051       }
3052
3053     if (i2dest_in_i2src)
3054       {
3055         if (REG_P (i2dest))
3056           REG_N_DEATHS (REGNO (i2dest))++;
3057
3058         if (newi2pat && reg_set_p (i2dest, newi2pat))
3059           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3060                             NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3061         else
3062           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3063                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3064                             NULL_RTX, NULL_RTX);
3065       }
3066
3067     if (i1dest_in_i1src)
3068       {
3069         if (REG_P (i1dest))
3070           REG_N_DEATHS (REGNO (i1dest))++;
3071
3072         if (newi2pat && reg_set_p (i1dest, newi2pat))
3073           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3074                             NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3075         else
3076           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3077                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3078                             NULL_RTX, NULL_RTX);
3079       }
3080
3081     distribute_links (i3links);
3082     distribute_links (i2links);
3083     distribute_links (i1links);
3084
3085     if (REG_P (i2dest))
3086       {
3087         rtx link;
3088         rtx i2_insn = 0, i2_val = 0, set;
3089
3090         /* The insn that used to set this register doesn't exist, and
3091            this life of the register may not exist either.  See if one of
3092            I3's links points to an insn that sets I2DEST.  If it does,
3093            that is now the last known value for I2DEST. If we don't update
3094            this and I2 set the register to a value that depended on its old
3095            contents, we will get confused.  If this insn is used, thing
3096            will be set correctly in combine_instructions.  */
3097
3098         for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3099           if ((set = single_set (XEXP (link, 0))) != 0
3100               && rtx_equal_p (i2dest, SET_DEST (set)))
3101             i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3102
3103         record_value_for_reg (i2dest, i2_insn, i2_val);
3104
3105         /* If the reg formerly set in I2 died only once and that was in I3,
3106            zero its use count so it won't make `reload' do any work.  */
3107         if (! added_sets_2
3108             && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3109             && ! i2dest_in_i2src)
3110           {
3111             regno = REGNO (i2dest);
3112             REG_N_SETS (regno)--;
3113           }
3114       }
3115
3116     if (i1 && REG_P (i1dest))
3117       {
3118         rtx link;
3119         rtx i1_insn = 0, i1_val = 0, set;
3120
3121         for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3122           if ((set = single_set (XEXP (link, 0))) != 0
3123               && rtx_equal_p (i1dest, SET_DEST (set)))
3124             i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
3125
3126         record_value_for_reg (i1dest, i1_insn, i1_val);
3127
3128         regno = REGNO (i1dest);
3129         if (! added_sets_1 && ! i1dest_in_i1src)
3130           REG_N_SETS (regno)--;
3131       }
3132
3133     /* Update reg_stat[].nonzero_bits et al for any changes that may have
3134        been made to this insn.  The order of
3135        set_nonzero_bits_and_sign_copies() is important.  Because newi2pat
3136        can affect nonzero_bits of newpat */
3137     if (newi2pat)
3138       note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
3139     note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
3140
3141     /* Set new_direct_jump_p if a new return or simple jump instruction
3142        has been created.
3143
3144        If I3 is now an unconditional jump, ensure that it has a
3145        BARRIER following it since it may have initially been a
3146        conditional jump.  It may also be the last nonnote insn.  */
3147
3148     if (returnjump_p (i3) || any_uncondjump_p (i3))
3149       {
3150         *new_direct_jump_p = 1;
3151         mark_jump_label (PATTERN (i3), i3, 0);
3152
3153         if ((temp = next_nonnote_insn (i3)) == NULL_RTX
3154             || !BARRIER_P (temp))
3155           emit_barrier_after (i3);
3156       }
3157
3158     if (undobuf.other_insn != NULL_RTX
3159         && (returnjump_p (undobuf.other_insn)
3160             || any_uncondjump_p (undobuf.other_insn)))
3161       {
3162         *new_direct_jump_p = 1;
3163
3164         if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
3165             || !BARRIER_P (temp))
3166           emit_barrier_after (undobuf.other_insn);
3167       }
3168
3169     /* An NOOP jump does not need barrier, but it does need cleaning up
3170        of CFG.  */
3171     if (GET_CODE (newpat) == SET
3172         && SET_SRC (newpat) == pc_rtx
3173         && SET_DEST (newpat) == pc_rtx)
3174       *new_direct_jump_p = 1;
3175   }
3176
3177   combine_successes++;
3178   undo_commit ();
3179
3180   if (added_links_insn
3181       && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
3182       && INSN_CUID (added_links_insn) < INSN_CUID (i3))
3183     return added_links_insn;
3184   else
3185     return newi2pat ? i2 : i3;
3186 }
3187 \f
3188 /* Undo all the modifications recorded in undobuf.  */
3189
3190 static void
3191 undo_all (void)
3192 {
3193   struct undo *undo, *next;
3194
3195   for (undo = undobuf.undos; undo; undo = next)
3196     {
3197       next = undo->next;
3198       if (undo->is_int)
3199         *undo->where.i = undo->old_contents.i;
3200       else
3201         *undo->where.r = undo->old_contents.r;
3202
3203       undo->next = undobuf.frees;
3204       undobuf.frees = undo;
3205     }
3206
3207   undobuf.undos = 0;
3208 }
3209
3210 /* We've committed to accepting the changes we made.  Move all
3211    of the undos to the free list.  */
3212
3213 static void
3214 undo_commit (void)
3215 {
3216   struct undo *undo, *next;
3217
3218   for (undo = undobuf.undos; undo; undo = next)
3219     {
3220       next = undo->next;
3221       undo->next = undobuf.frees;
3222       undobuf.frees = undo;
3223     }
3224   undobuf.undos = 0;
3225 }
3226
3227 \f
3228 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3229    where we have an arithmetic expression and return that point.  LOC will
3230    be inside INSN.
3231
3232    try_combine will call this function to see if an insn can be split into
3233    two insns.  */
3234
3235 static rtx *
3236 find_split_point (rtx *loc, rtx insn)
3237 {
3238   rtx x = *loc;
3239   enum rtx_code code = GET_CODE (x);
3240   rtx *split;
3241   unsigned HOST_WIDE_INT len = 0;
3242   HOST_WIDE_INT pos = 0;
3243   int unsignedp = 0;
3244   rtx inner = NULL_RTX;
3245
3246   /* First special-case some codes.  */
3247   switch (code)
3248     {
3249     case SUBREG:
3250 #ifdef INSN_SCHEDULING
3251       /* If we are making a paradoxical SUBREG invalid, it becomes a split
3252          point.  */
3253       if (MEM_P (SUBREG_REG (x)))
3254         return loc;
3255 #endif
3256       return find_split_point (&SUBREG_REG (x), insn);
3257
3258     case MEM:
3259 #ifdef HAVE_lo_sum
3260       /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3261          using LO_SUM and HIGH.  */
3262       if (GET_CODE (XEXP (x, 0)) == CONST
3263           || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
3264         {
3265           SUBST (XEXP (x, 0),
3266                  gen_rtx_LO_SUM (Pmode,
3267                                  gen_rtx_HIGH (Pmode, XEXP (x, 0)),
3268                                  XEXP (x, 0)));
3269           return &XEXP (XEXP (x, 0), 0);
3270         }
3271 #endif
3272
3273       /* If we have a PLUS whose second operand is a constant and the
3274          address is not valid, perhaps will can split it up using
3275          the machine-specific way to split large constants.  We use
3276          the first pseudo-reg (one of the virtual regs) as a placeholder;
3277          it will not remain in the result.  */
3278       if (GET_CODE (XEXP (x, 0)) == PLUS
3279           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3280           && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
3281         {
3282           rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
3283           rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
3284                                  subst_insn);
3285
3286           /* This should have produced two insns, each of which sets our
3287              placeholder.  If the source of the second is a valid address,
3288              we can make put both sources together and make a split point
3289              in the middle.  */
3290
3291           if (seq
3292               && NEXT_INSN (seq) != NULL_RTX
3293               && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
3294               && NONJUMP_INSN_P (seq)
3295               && GET_CODE (PATTERN (seq)) == SET
3296               && SET_DEST (PATTERN (seq)) == reg
3297               && ! reg_mentioned_p (reg,
3298                                     SET_SRC (PATTERN (seq)))
3299               && NONJUMP_INSN_P (NEXT_INSN (seq))
3300               && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
3301               && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
3302               && memory_address_p (GET_MODE (x),
3303                                    SET_SRC (PATTERN (NEXT_INSN (seq)))))
3304             {
3305               rtx src1 = SET_SRC (PATTERN (seq));
3306               rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3307
3308               /* Replace the placeholder in SRC2 with SRC1.  If we can
3309                  find where in SRC2 it was placed, that can become our
3310                  split point and we can replace this address with SRC2.
3311                  Just try two obvious places.  */
3312
3313               src2 = replace_rtx (src2, reg, src1);
3314               split = 0;
3315               if (XEXP (src2, 0) == src1)
3316                 split = &XEXP (src2, 0);
3317               else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3318                        && XEXP (XEXP (src2, 0), 0) == src1)
3319                 split = &XEXP (XEXP (src2, 0), 0);
3320
3321               if (split)
3322                 {
3323                   SUBST (XEXP (x, 0), src2);
3324                   return split;
3325                 }
3326             }
3327
3328           /* If that didn't work, perhaps the first operand is complex and
3329              needs to be computed separately, so make a split point there.
3330              This will occur on machines that just support REG + CONST
3331              and have a constant moved through some previous computation.  */
3332
3333           else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
3334                    && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3335                          && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3336             return &XEXP (XEXP (x, 0), 0);
3337         }
3338       break;
3339
3340     case SET:
3341 #ifdef HAVE_cc0
3342       /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3343          ZERO_EXTRACT, the most likely reason why this doesn't match is that
3344          we need to put the operand into a register.  So split at that
3345          point.  */
3346
3347       if (SET_DEST (x) == cc0_rtx
3348           && GET_CODE (SET_SRC (x)) != COMPARE
3349           && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3350           && !OBJECT_P (SET_SRC (x))
3351           && ! (GET_CODE (SET_SRC (x)) == SUBREG
3352                 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
3353         return &SET_SRC (x);
3354 #endif
3355
3356       /* See if we can split SET_SRC as it stands.  */
3357       split = find_split_point (&SET_SRC (x), insn);
3358       if (split && split != &SET_SRC (x))
3359         return split;
3360
3361       /* See if we can split SET_DEST as it stands.  */
3362       split = find_split_point (&SET_DEST (x), insn);
3363       if (split && split != &SET_DEST (x))
3364         return split;
3365
3366       /* See if this is a bitfield assignment with everything constant.  If
3367          so, this is an IOR of an AND, so split it into that.  */
3368       if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3369           && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3370               <= HOST_BITS_PER_WIDE_INT)
3371           && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3372           && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3373           && GET_CODE (SET_SRC (x)) == CONST_INT
3374           && ((INTVAL (XEXP (SET_DEST (x), 1))
3375                + INTVAL (XEXP (SET_DEST (x), 2)))
3376               <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3377           && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3378         {
3379           HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3380           unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3381           unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3382           rtx dest = XEXP (SET_DEST (x), 0);
3383           enum machine_mode mode = GET_MODE (dest);
3384           unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3385           rtx or_mask;
3386
3387           if (BITS_BIG_ENDIAN)
3388             pos = GET_MODE_BITSIZE (mode) - len - pos;
3389
3390           or_mask = gen_int_mode (src << pos, mode);
3391           if (src == mask)
3392             SUBST (SET_SRC (x),
3393                    simplify_gen_binary (IOR, mode, dest, or_mask));
3394           else
3395             {
3396               rtx negmask = gen_int_mode (~(mask << pos), mode);
3397               SUBST (SET_SRC (x),
3398                      simplify_gen_binary (IOR, mode,
3399                                           simplify_gen_binary (AND, mode,
3400                                                                dest, negmask),
3401                                           or_mask));
3402             }
3403
3404           SUBST (SET_DEST (x), dest);
3405
3406           split = find_split_point (&SET_SRC (x), insn);
3407           if (split && split != &SET_SRC (x))
3408             return split;
3409         }
3410
3411       /* Otherwise, see if this is an operation that we can split into two.
3412          If so, try to split that.  */
3413       code = GET_CODE (SET_SRC (x));
3414
3415       switch (code)
3416         {
3417         case AND:
3418           /* If we are AND'ing with a large constant that is only a single
3419              bit and the result is only being used in a context where we
3420              need to know if it is zero or nonzero, replace it with a bit
3421              extraction.  This will avoid the large constant, which might
3422              have taken more than one insn to make.  If the constant were
3423              not a valid argument to the AND but took only one insn to make,
3424              this is no worse, but if it took more than one insn, it will
3425              be better.  */
3426
3427           if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3428               && REG_P (XEXP (SET_SRC (x), 0))
3429               && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3430               && REG_P (SET_DEST (x))
3431               && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3432               && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3433               && XEXP (*split, 0) == SET_DEST (x)
3434               && XEXP (*split, 1) == const0_rtx)
3435             {
3436               rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3437                                                 XEXP (SET_SRC (x), 0),
3438                                                 pos, NULL_RTX, 1, 1, 0, 0);
3439               if (extraction != 0)
3440                 {
3441                   SUBST (SET_SRC (x), extraction);
3442                   return find_split_point (loc, insn);
3443                 }
3444             }
3445           break;
3446
3447         case NE:
3448           /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3449              is known to be on, this can be converted into a NEG of a shift.  */
3450           if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3451               && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3452               && 1 <= (pos = exact_log2
3453                        (nonzero_bits (XEXP (SET_SRC (x), 0),
3454                                       GET_MODE (XEXP (SET_SRC (x), 0))))))
3455             {
3456               enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3457
3458               SUBST (SET_SRC (x),
3459                      gen_rtx_NEG (mode,
3460                                   gen_rtx_LSHIFTRT (mode,
3461                                                     XEXP (SET_SRC (x), 0),
3462                                                     GEN_INT (pos))));
3463
3464               split = find_split_point (&SET_SRC (x), insn);
3465               if (split && split != &SET_SRC (x))
3466                 return split;
3467             }
3468           break;
3469
3470         case SIGN_EXTEND:
3471           inner = XEXP (SET_SRC (x), 0);
3472
3473           /* We can't optimize if either mode is a partial integer
3474              mode as we don't know how many bits are significant
3475              in those modes.  */
3476           if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3477               || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3478             break;
3479
3480           pos = 0;
3481           len = GET_MODE_BITSIZE (GET_MODE (inner));
3482           unsignedp = 0;
3483           break;
3484
3485         case SIGN_EXTRACT:
3486         case ZERO_EXTRACT:
3487           if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3488               && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3489             {
3490               inner = XEXP (SET_SRC (x), 0);
3491               len = INTVAL (XEXP (SET_SRC (x), 1));
3492               pos = INTVAL (XEXP (SET_SRC (x), 2));
3493
3494               if (BITS_BIG_ENDIAN)
3495                 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3496               unsignedp = (code == ZERO_EXTRACT);
3497             }
3498           break;
3499
3500         default:
3501           break;
3502         }
3503
3504       if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3505         {
3506           enum machine_mode mode = GET_MODE (SET_SRC (x));
3507
3508           /* For unsigned, we have a choice of a shift followed by an
3509              AND or two shifts.  Use two shifts for field sizes where the
3510              constant might be too large.  We assume here that we can
3511              always at least get 8-bit constants in an AND insn, which is
3512              true for every current RISC.  */
3513
3514           if (unsignedp && len <= 8)
3515             {
3516               SUBST (SET_SRC (x),
3517                      gen_rtx_AND (mode,
3518                                   gen_rtx_LSHIFTRT
3519                                   (mode, gen_lowpart (mode, inner),
3520                                    GEN_INT (pos)),
3521                                   GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3522
3523               split = find_split_point (&SET_SRC (x), insn);
3524               if (split && split != &SET_SRC (x))
3525                 return split;
3526             }
3527           else
3528             {
3529               SUBST (SET_SRC (x),
3530                      gen_rtx_fmt_ee
3531                      (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3532                       gen_rtx_ASHIFT (mode,
3533                                       gen_lowpart (mode, inner),
3534                                       GEN_INT (GET_MODE_BITSIZE (mode)
3535                                                - len - pos)),
3536                       GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3537
3538               split = find_split_point (&SET_SRC (x), insn);
3539               if (split && split != &SET_SRC (x))
3540                 return split;
3541             }
3542         }
3543
3544       /* See if this is a simple operation with a constant as the second
3545          operand.  It might be that this constant is out of range and hence
3546          could be used as a split point.  */
3547       if (BINARY_P (SET_SRC (x))
3548           && CONSTANT_P (XEXP (SET_SRC (x), 1))
3549           && (OBJECT_P (XEXP (SET_SRC (x), 0))
3550               || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3551                   && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
3552         return &XEXP (SET_SRC (x), 1);
3553
3554       /* Finally, see if this is a simple operation with its first operand
3555          not in a register.  The operation might require this operand in a
3556          register, so return it as a split point.  We can always do this
3557          because if the first operand were another operation, we would have
3558          already found it as a split point.  */
3559       if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
3560           && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3561         return &XEXP (SET_SRC (x), 0);
3562
3563       return 0;
3564
3565     case AND:
3566     case IOR:
3567       /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3568          it is better to write this as (not (ior A B)) so we can split it.
3569          Similarly for IOR.  */
3570       if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3571         {
3572           SUBST (*loc,
3573                  gen_rtx_NOT (GET_MODE (x),
3574                               gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3575                                               GET_MODE (x),
3576                                               XEXP (XEXP (x, 0), 0),
3577                                               XEXP (XEXP (x, 1), 0))));
3578           return find_split_point (loc, insn);
3579         }
3580
3581       /* Many RISC machines have a large set of logical insns.  If the
3582          second operand is a NOT, put it first so we will try to split the
3583          other operand first.  */
3584       if (GET_CODE (XEXP (x, 1)) == NOT)
3585         {
3586           rtx tem = XEXP (x, 0);
3587           SUBST (XEXP (x, 0), XEXP (x, 1));
3588           SUBST (XEXP (x, 1), tem);
3589         }
3590       break;
3591
3592     default:
3593       break;
3594     }
3595
3596   /* Otherwise, select our actions depending on our rtx class.  */
3597   switch (GET_RTX_CLASS (code))
3598     {
3599     case RTX_BITFIELD_OPS:              /* This is ZERO_EXTRACT and SIGN_EXTRACT.  */
3600     case RTX_TERNARY:
3601       split = find_split_point (&XEXP (x, 2), insn);
3602       if (split)
3603         return split;
3604       /* ... fall through ...  */
3605     case RTX_BIN_ARITH:
3606     case RTX_COMM_ARITH:
3607     case RTX_COMPARE:
3608     case RTX_COMM_COMPARE:
3609       split = find_split_point (&XEXP (x, 1), insn);
3610       if (split)
3611         return split;
3612       /* ... fall through ...  */
3613     case RTX_UNARY:
3614       /* Some machines have (and (shift ...) ...) insns.  If X is not
3615          an AND, but XEXP (X, 0) is, use it as our split point.  */
3616       if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3617         return &XEXP (x, 0);
3618
3619       split = find_split_point (&XEXP (x, 0), insn);
3620       if (split)
3621         return split;
3622       return loc;
3623
3624     default:
3625       /* Otherwise, we don't have a split point.  */
3626       return 0;
3627     }
3628 }
3629 \f
3630 /* Throughout X, replace FROM with TO, and return the result.
3631    The result is TO if X is FROM;
3632    otherwise the result is X, but its contents may have been modified.
3633    If they were modified, a record was made in undobuf so that
3634    undo_all will (among other things) return X to its original state.
3635
3636    If the number of changes necessary is too much to record to undo,
3637    the excess changes are not made, so the result is invalid.
3638    The changes already made can still be undone.
3639    undobuf.num_undo is incremented for such changes, so by testing that
3640    the caller can tell whether the result is valid.
3641
3642    `n_occurrences' is incremented each time FROM is replaced.
3643
3644    IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3645
3646    UNIQUE_COPY is nonzero if each substitution must be unique.  We do this
3647    by copying if `n_occurrences' is nonzero.  */
3648
3649 static rtx
3650 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
3651 {
3652   enum rtx_code code = GET_CODE (x);
3653   enum machine_mode op0_mode = VOIDmode;
3654   const char *fmt;
3655   int len, i;
3656   rtx new;
3657
3658 /* Two expressions are equal if they are identical copies of a shared
3659    RTX or if they are both registers with the same register number
3660    and mode.  */
3661
3662 #define COMBINE_RTX_EQUAL_P(X,Y)                        \
3663   ((X) == (Y)                                           \
3664    || (REG_P (X) && REG_P (Y)   \
3665        && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3666
3667   if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3668     {
3669       n_occurrences++;
3670       return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3671     }
3672
3673   /* If X and FROM are the same register but different modes, they will
3674      not have been seen as equal above.  However, flow.c will make a
3675      LOG_LINKS entry for that case.  If we do nothing, we will try to
3676      rerecognize our original insn and, when it succeeds, we will
3677      delete the feeding insn, which is incorrect.
3678
3679      So force this insn not to match in this (rare) case.  */
3680   if (! in_dest && code == REG && REG_P (from)
3681       && REGNO (x) == REGNO (from))
3682     return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3683
3684   /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3685      of which may contain things that can be combined.  */
3686   if (code != MEM && code != LO_SUM && OBJECT_P (x))
3687     return x;
3688
3689   /* It is possible to have a subexpression appear twice in the insn.
3690      Suppose that FROM is a register that appears within TO.
3691      Then, after that subexpression has been scanned once by `subst',
3692      the second time it is scanned, TO may be found.  If we were
3693      to scan TO here, we would find FROM within it and create a
3694      self-referent rtl structure which is completely wrong.  */
3695   if (COMBINE_RTX_EQUAL_P (x, to))
3696     return to;
3697
3698   /* Parallel asm_operands need special attention because all of the
3699      inputs are shared across the arms.  Furthermore, unsharing the
3700      rtl results in recognition failures.  Failure to handle this case
3701      specially can result in circular rtl.
3702
3703      Solve this by doing a normal pass across the first entry of the
3704      parallel, and only processing the SET_DESTs of the subsequent
3705      entries.  Ug.  */
3706
3707   if (code == PARALLEL
3708       && GET_CODE (XVECEXP (x, 0, 0)) == SET
3709       && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3710     {
3711       new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3712
3713       /* If this substitution failed, this whole thing fails.  */
3714       if (GET_CODE (new) == CLOBBER
3715           && XEXP (new, 0) == const0_rtx)
3716         return new;
3717
3718       SUBST (XVECEXP (x, 0, 0), new);
3719
3720       for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3721         {
3722           rtx dest = SET_DEST (XVECEXP (x, 0, i));
3723
3724           if (!REG_P (dest)
3725               && GET_CODE (dest) != CC0
3726               && GET_CODE (dest) != PC)
3727             {
3728               new = subst (dest, from, to, 0, unique_copy);
3729
3730               /* If this substitution failed, this whole thing fails.  */
3731               if (GET_CODE (new) == CLOBBER
3732                   && XEXP (new, 0) == const0_rtx)
3733                 return new;
3734
3735               SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3736             }
3737         }
3738     }
3739   else
3740     {
3741       len = GET_RTX_LENGTH (code);
3742       fmt = GET_RTX_FORMAT (code);
3743
3744       /* We don't need to process a SET_DEST that is a register, CC0,
3745          or PC, so set up to skip this common case.  All other cases
3746          where we want to suppress replacing something inside a
3747          SET_SRC are handled via the IN_DEST operand.  */
3748       if (code == SET
3749           && (REG_P (SET_DEST (x))
3750               || GET_CODE (SET_DEST (x)) == CC0
3751               || GET_CODE (SET_DEST (x)) == PC))
3752         fmt = "ie";
3753
3754       /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3755          constant.  */
3756       if (fmt[0] == 'e')
3757         op0_mode = GET_MODE (XEXP (x, 0));
3758
3759       for (i = 0; i < len; i++)
3760         {
3761           if (fmt[i] == 'E')
3762             {
3763               int j;
3764               for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3765                 {
3766                   if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3767                     {
3768                       new = (unique_copy && n_occurrences
3769                              ? copy_rtx (to) : to);
3770                       n_occurrences++;
3771                     }
3772                   else
3773                     {
3774                       new = subst (XVECEXP (x, i, j), from, to, 0,
3775                                    unique_copy);
3776
3777                       /* If this substitution failed, this whole thing
3778                          fails.  */
3779                       if (GET_CODE (new) == CLOBBER
3780                           && XEXP (new, 0) == const0_rtx)
3781                         return new;
3782                     }
3783
3784                   SUBST (XVECEXP (x, i, j), new);
3785                 }
3786             }
3787           else if (fmt[i] == 'e')
3788             {
3789               /* If this is a register being set, ignore it.  */
3790               new = XEXP (x, i);
3791               if (in_dest
3792                   && i == 0
3793                   && (((code == SUBREG || code == ZERO_EXTRACT)
3794                        && REG_P (new))
3795                       || code == STRICT_LOW_PART))
3796                 ;
3797
3798               else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3799                 {
3800                   /* In general, don't install a subreg involving two
3801                      modes not tieable.  It can worsen register
3802                      allocation, and can even make invalid reload
3803                      insns, since the reg inside may need to be copied
3804                      from in the outside mode, and that may be invalid
3805                      if it is an fp reg copied in integer mode.
3806
3807                      We allow two exceptions to this: It is valid if
3808                      it is inside another SUBREG and the mode of that
3809                      SUBREG and the mode of the inside of TO is
3810                      tieable and it is valid if X is a SET that copies
3811                      FROM to CC0.  */
3812
3813                   if (GET_CODE (to) == SUBREG
3814                       && ! MODES_TIEABLE_P (GET_MODE (to),
3815                                             GET_MODE (SUBREG_REG (to)))
3816                       && ! (code == SUBREG
3817                             && MODES_TIEABLE_P (GET_MODE (x),
3818                                                 GET_MODE (SUBREG_REG (to))))
3819 #ifdef HAVE_cc0
3820                       && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3821 #endif
3822                       )
3823                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3824
3825 #ifdef CANNOT_CHANGE_MODE_CLASS
3826                   if (code == SUBREG
3827                       && REG_P (to)
3828                       && REGNO (to) < FIRST_PSEUDO_REGISTER
3829                       && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
3830                                                    GET_MODE (to),
3831                                                    GET_MODE (x)))
3832                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3833 #endif
3834
3835                   new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3836                   n_occurrences++;
3837                 }
3838               else
3839                 /* If we are in a SET_DEST, suppress most cases unless we
3840                    have gone inside a MEM, in which case we want to
3841                    simplify the address.  We assume here that things that
3842                    are actually part of the destination have their inner
3843                    parts in the first expression.  This is true for SUBREG,
3844                    STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3845                    things aside from REG and MEM that should appear in a
3846                    SET_DEST.  */
3847                 new = subst (XEXP (x, i), from, to,
3848                              (((in_dest
3849                                 && (code == SUBREG || code == STRICT_LOW_PART
3850                                     || code == ZERO_EXTRACT))
3851                                || code == SET)
3852                               && i == 0), unique_copy);
3853
3854               /* If we found that we will have to reject this combination,
3855                  indicate that by returning the CLOBBER ourselves, rather than
3856                  an expression containing it.  This will speed things up as
3857                  well as prevent accidents where two CLOBBERs are considered
3858                  to be equal, thus producing an incorrect simplification.  */
3859
3860               if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3861                 return new;
3862
3863               if (GET_CODE (x) == SUBREG
3864                   && (GET_CODE (new) == CONST_INT
3865                       || GET_CODE (new) == CONST_DOUBLE))
3866                 {
3867                   enum machine_mode mode = GET_MODE (x);
3868
3869                   x = simplify_subreg (GET_MODE (x), new,
3870                                        GET_MODE (SUBREG_REG (x)),
3871                                        SUBREG_BYTE (x));
3872                   if (! x)
3873                     x = gen_rtx_CLOBBER (mode, const0_rtx);
3874                 }
3875               else if (GET_CODE (new) == CONST_INT
3876                        && GET_CODE (x) == ZERO_EXTEND)
3877                 {
3878                   x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
3879                                                 new, GET_MODE (XEXP (x, 0)));
3880                   gcc_assert (x);
3881                 }
3882               else
3883                 SUBST (XEXP (x, i), new);
3884             }
3885         }
3886     }
3887
3888   /* Try to simplify X.  If the simplification changed the code, it is likely
3889      that further simplification will help, so loop, but limit the number
3890      of repetitions that will be performed.  */
3891
3892   for (i = 0; i < 4; i++)
3893     {
3894       /* If X is sufficiently simple, don't bother trying to do anything
3895          with it.  */
3896       if (code != CONST_INT && code != REG && code != CLOBBER)
3897         x = combine_simplify_rtx (x, op0_mode, in_dest);
3898
3899       if (GET_CODE (x) == code)
3900         break;
3901
3902       code = GET_CODE (x);
3903
3904       /* We no longer know the original mode of operand 0 since we
3905          have changed the form of X)  */
3906       op0_mode = VOIDmode;
3907     }
3908
3909   return x;
3910 }
3911 \f
3912 /* Simplify X, a piece of RTL.  We just operate on the expression at the
3913    outer level; call `subst' to simplify recursively.  Return the new
3914    expression.
3915
3916    OP0_MODE is the original mode of XEXP (x, 0).  IN_DEST is nonzero
3917    if we are inside a SET_DEST.  */
3918
3919 static rtx
3920 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
3921 {
3922   enum rtx_code code = GET_CODE (x);
3923   enum machine_mode mode = GET_MODE (x);
3924   rtx temp;
3925   rtx reversed;
3926   int i;
3927
3928   /* If this is a commutative operation, put a constant last and a complex
3929      expression first.  We don't need to do this for comparisons here.  */
3930   if (COMMUTATIVE_ARITH_P (x)
3931       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
3932     {
3933       temp = XEXP (x, 0);
3934       SUBST (XEXP (x, 0), XEXP (x, 1));
3935       SUBST (XEXP (x, 1), temp);
3936     }
3937
3938   /* If this is a simple operation applied to an IF_THEN_ELSE, try
3939      applying it to the arms of the IF_THEN_ELSE.  This often simplifies
3940      things.  Check for cases where both arms are testing the same
3941      condition.
3942
3943      Don't do anything if all operands are very simple.  */
3944
3945   if ((BINARY_P (x)
3946        && ((!OBJECT_P (XEXP (x, 0))
3947             && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3948                   && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
3949            || (!OBJECT_P (XEXP (x, 1))
3950                && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3951                      && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
3952       || (UNARY_P (x)
3953           && (!OBJECT_P (XEXP (x, 0))
3954                && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3955                      && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
3956     {
3957       rtx cond, true_rtx, false_rtx;
3958
3959       cond = if_then_else_cond (x, &true_rtx, &false_rtx);
3960       if (cond != 0
3961           /* If everything is a comparison, what we have is highly unlikely
3962              to be simpler, so don't use it.  */
3963           && ! (COMPARISON_P (x)
3964                 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
3965         {
3966           rtx cop1 = const0_rtx;
3967           enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3968
3969           if (cond_code == NE && COMPARISON_P (cond))
3970             return x;
3971
3972           /* Simplify the alternative arms; this may collapse the true and
3973              false arms to store-flag values.  Be careful to use copy_rtx
3974              here since true_rtx or false_rtx might share RTL with x as a
3975              result of the if_then_else_cond call above.  */
3976           true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
3977           false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
3978
3979           /* If true_rtx and false_rtx are not general_operands, an if_then_else
3980              is unlikely to be simpler.  */
3981           if (general_operand (true_rtx, VOIDmode)
3982               && general_operand (false_rtx, VOIDmode))
3983             {
3984               enum rtx_code reversed;
3985
3986               /* Restarting if we generate a store-flag expression will cause
3987                  us to loop.  Just drop through in this case.  */
3988
3989               /* If the result values are STORE_FLAG_VALUE and zero, we can
3990                  just make the comparison operation.  */
3991               if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
3992                 x = simplify_gen_relational (cond_code, mode, VOIDmode,
3993                                              cond, cop1);
3994               else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
3995                        && ((reversed = reversed_comparison_code_parts
3996                                         (cond_code, cond, cop1, NULL))
3997                            != UNKNOWN))
3998                 x = simplify_gen_relational (reversed, mode, VOIDmode,
3999                                              cond, cop1);
4000
4001               /* Likewise, we can make the negate of a comparison operation
4002                  if the result values are - STORE_FLAG_VALUE and zero.  */
4003               else if (GET_CODE (true_rtx) == CONST_INT
4004                        && INTVAL (true_rtx) == - STORE_FLAG_VALUE
4005                        && false_rtx == const0_rtx)
4006                 x = simplify_gen_unary (NEG, mode,
4007                                         simplify_gen_relational (cond_code,
4008                                                                  mode, VOIDmode,
4009                                                                  cond, cop1),
4010                                         mode);
4011               else if (GET_CODE (false_rtx) == CONST_INT
4012                        && INTVAL (false_rtx) == - STORE_FLAG_VALUE
4013                        && true_rtx == const0_rtx
4014                        && ((reversed = reversed_comparison_code_parts
4015                                         (cond_code, cond, cop1, NULL))
4016                            != UNKNOWN))
4017                 x = simplify_gen_unary (NEG, mode,
4018                                         simplify_gen_relational (reversed,
4019                                                                  mode, VOIDmode,
4020                                                                  cond, cop1),
4021                                         mode);
4022               else
4023                 return gen_rtx_IF_THEN_ELSE (mode,
4024                                              simplify_gen_relational (cond_code,
4025                                                                       mode,
4026                                                                       VOIDmode,
4027                                                                       cond,
4028                                                                       cop1),
4029                                              true_rtx, false_rtx);
4030
4031               code = GET_CODE (x);
4032               op0_mode = VOIDmode;
4033             }
4034         }
4035     }
4036
4037   /* Try to fold this expression in case we have constants that weren't
4038      present before.  */
4039   temp = 0;
4040   switch (GET_RTX_CLASS (code))
4041     {
4042     case RTX_UNARY:
4043       if (op0_mode == VOIDmode)
4044         op0_mode = GET_MODE (XEXP (x, 0));
4045       temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
4046       break;
4047     case RTX_COMPARE:
4048     case RTX_COMM_COMPARE:
4049       {
4050         enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
4051         if (cmp_mode == VOIDmode)
4052           {
4053             cmp_mode = GET_MODE (XEXP (x, 1));
4054             if (cmp_mode == VOIDmode)
4055               cmp_mode = op0_mode;
4056           }
4057         temp = simplify_relational_operation (code, mode, cmp_mode,
4058                                               XEXP (x, 0), XEXP (x, 1));
4059       }
4060       break;
4061     case RTX_COMM_ARITH:
4062     case RTX_BIN_ARITH:
4063       temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
4064       break;
4065     case RTX_BITFIELD_OPS:
4066     case RTX_TERNARY:
4067       temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
4068                                          XEXP (x, 1), XEXP (x, 2));
4069       break;
4070     default:
4071       break;
4072     }
4073
4074   if (temp)
4075     {
4076       x = temp;
4077       code = GET_CODE (temp);
4078       op0_mode = VOIDmode;
4079       mode = GET_MODE (temp);
4080     }
4081
4082   /* First see if we can apply the inverse distributive law.  */
4083   if (code == PLUS || code == MINUS
4084       || code == AND || code == IOR || code == XOR)
4085     {
4086       x = apply_distributive_law (x);
4087       code = GET_CODE (x);
4088       op0_mode = VOIDmode;
4089     }
4090
4091   /* If CODE is an associative operation not otherwise handled, see if we
4092      can associate some operands.  This can win if they are constants or
4093      if they are logically related (i.e. (a & b) & a).  */
4094   if ((code == PLUS || code == MINUS || code == MULT || code == DIV
4095        || code == AND || code == IOR || code == XOR
4096        || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
4097       && ((INTEGRAL_MODE_P (mode) && code != DIV)
4098           || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
4099     {
4100       if (GET_CODE (XEXP (x, 0)) == code)
4101         {
4102           rtx other = XEXP (XEXP (x, 0), 0);
4103           rtx inner_op0 = XEXP (XEXP (x, 0), 1);
4104           rtx inner_op1 = XEXP (x, 1);
4105           rtx inner;
4106
4107           /* Make sure we pass the constant operand if any as the second
4108              one if this is a commutative operation.  */
4109           if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
4110             {
4111               rtx tem = inner_op0;
4112               inner_op0 = inner_op1;
4113               inner_op1 = tem;
4114             }
4115           inner = simplify_binary_operation (code == MINUS ? PLUS
4116                                              : code == DIV ? MULT
4117                                              : code,
4118                                              mode, inner_op0, inner_op1);
4119
4120           /* For commutative operations, try the other pair if that one
4121              didn't simplify.  */
4122           if (inner == 0 && COMMUTATIVE_ARITH_P (x))
4123             {
4124               other = XEXP (XEXP (x, 0), 1);
4125               inner = simplify_binary_operation (code, mode,
4126                                                  XEXP (XEXP (x, 0), 0),
4127                                                  XEXP (x, 1));
4128             }
4129
4130           if (inner)
4131             return simplify_gen_binary (code, mode, other, inner);
4132         }
4133     }
4134
4135   /* A little bit of algebraic simplification here.  */
4136   switch (code)
4137     {
4138     case MEM:
4139       /* Ensure that our address has any ASHIFTs converted to MULT in case
4140          address-recognizing predicates are called later.  */
4141       temp = make_compound_operation (XEXP (x, 0), MEM);
4142       SUBST (XEXP (x, 0), temp);
4143       break;
4144
4145     case SUBREG:
4146       if (op0_mode == VOIDmode)
4147         op0_mode = GET_MODE (SUBREG_REG (x));
4148
4149       /* See if this can be moved to simplify_subreg.  */
4150       if (CONSTANT_P (SUBREG_REG (x))
4151           && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
4152              /* Don't call gen_lowpart if the inner mode
4153                 is VOIDmode and we cannot simplify it, as SUBREG without
4154                 inner mode is invalid.  */
4155           && (GET_MODE (SUBREG_REG (x)) != VOIDmode
4156               || gen_lowpart_common (mode, SUBREG_REG (x))))
4157         return gen_lowpart (mode, SUBREG_REG (x));
4158
4159       if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
4160         break;
4161       {
4162         rtx temp;
4163         temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
4164                                 SUBREG_BYTE (x));
4165         if (temp)
4166           return temp;
4167       }
4168
4169       /* Don't change the mode of the MEM if that would change the meaning
4170          of the address.  */
4171       if (MEM_P (SUBREG_REG (x))
4172           && (MEM_VOLATILE_P (SUBREG_REG (x))
4173               || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
4174         return gen_rtx_CLOBBER (mode, const0_rtx);
4175
4176       /* Note that we cannot do any narrowing for non-constants since
4177          we might have been counting on using the fact that some bits were
4178          zero.  We now do this in the SET.  */
4179
4180       break;
4181
4182     case NOT:
4183       if (GET_CODE (XEXP (x, 0)) == SUBREG
4184           && subreg_lowpart_p (XEXP (x, 0))
4185           && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
4186               < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
4187           && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
4188           && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
4189         {
4190           enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
4191
4192           x = gen_rtx_ROTATE (inner_mode,
4193                               simplify_gen_unary (NOT, inner_mode, const1_rtx,
4194                                                   inner_mode),
4195                               XEXP (SUBREG_REG (XEXP (x, 0)), 1));
4196           return gen_lowpart (mode, x);
4197         }
4198
4199       /* Apply De Morgan's laws to reduce number of patterns for machines
4200          with negating logical insns (and-not, nand, etc.).  If result has
4201          only one NOT, put it first, since that is how the patterns are
4202          coded.  */
4203
4204       if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
4205         {
4206           rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
4207           enum machine_mode op_mode;
4208
4209           op_mode = GET_MODE (in1);
4210           in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode);
4211
4212           op_mode = GET_MODE (in2);
4213           if (op_mode == VOIDmode)
4214             op_mode = mode;
4215           in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode);
4216
4217           if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT)
4218             {
4219               rtx tem = in2;
4220               in2 = in1; in1 = tem;
4221             }
4222
4223           return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
4224                                  mode, in1, in2);
4225         }
4226       break;
4227
4228     case NEG:
4229       /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1.  */
4230       if (GET_CODE (XEXP (x, 0)) == XOR
4231           && XEXP (XEXP (x, 0), 1) == const1_rtx
4232           && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
4233         return simplify_gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4234                                     constm1_rtx);
4235
4236       temp = expand_compound_operation (XEXP (x, 0));
4237
4238       /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4239          replaced by (lshiftrt X C).  This will convert
4240          (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y).  */
4241
4242       if (GET_CODE (temp) == ASHIFTRT
4243           && GET_CODE (XEXP (temp, 1)) == CONST_INT
4244           && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4245         return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
4246                                      INTVAL (XEXP (temp, 1)));
4247
4248       /* If X has only a single bit that might be nonzero, say, bit I, convert
4249          (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4250          MODE minus 1.  This will convert (neg (zero_extract X 1 Y)) to
4251          (sign_extract X 1 Y).  But only do this if TEMP isn't a register
4252          or a SUBREG of one since we'd be making the expression more
4253          complex if it was just a register.  */
4254
4255       if (!REG_P (temp)
4256           && ! (GET_CODE (temp) == SUBREG
4257                 && REG_P (SUBREG_REG (temp)))
4258           && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4259         {
4260           rtx temp1 = simplify_shift_const
4261             (NULL_RTX, ASHIFTRT, mode,
4262              simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4263                                    GET_MODE_BITSIZE (mode) - 1 - i),
4264              GET_MODE_BITSIZE (mode) - 1 - i);
4265
4266           /* If all we did was surround TEMP with the two shifts, we
4267              haven't improved anything, so don't use it.  Otherwise,
4268              we are better off with TEMP1.  */
4269           if (GET_CODE (temp1) != ASHIFTRT
4270               || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4271               || XEXP (XEXP (temp1, 0), 0) != temp)
4272             return temp1;
4273         }
4274       break;
4275
4276     case TRUNCATE:
4277       /* We can't handle truncation to a partial integer mode here
4278          because we don't know the real bitsize of the partial
4279          integer mode.  */
4280       if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4281         break;
4282
4283       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4284           && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4285                                     GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4286         SUBST (XEXP (x, 0),
4287                force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4288                               GET_MODE_MASK (mode), NULL_RTX, 0));
4289
4290       /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI.  */
4291       if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4292            || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4293           && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4294         return XEXP (XEXP (x, 0), 0);
4295
4296       /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4297          (OP:SI foo:SI) if OP is NEG or ABS.  */
4298       if ((GET_CODE (XEXP (x, 0)) == ABS
4299            || GET_CODE (XEXP (x, 0)) == NEG)
4300           && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
4301               || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
4302           && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4303         return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4304                                    XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4305
4306       /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4307          (truncate:SI x).  */
4308       if (GET_CODE (XEXP (x, 0)) == SUBREG
4309           && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
4310           && subreg_lowpart_p (XEXP (x, 0)))
4311         return SUBREG_REG (XEXP (x, 0));
4312
4313       /* If we know that the value is already truncated, we can
4314          replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4315          is nonzero for the corresponding modes.  But don't do this
4316          for an (LSHIFTRT (MULT ...)) since this will cause problems
4317          with the umulXi3_highpart patterns.  */
4318       if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4319                                  GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4320           && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4321              >= (unsigned int) (GET_MODE_BITSIZE (mode) + 1)
4322           && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4323                 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4324         return gen_lowpart (mode, XEXP (x, 0));
4325
4326       /* A truncate of a comparison can be replaced with a subreg if
4327          STORE_FLAG_VALUE permits.  This is like the previous test,
4328          but it works even if the comparison is done in a mode larger
4329          than HOST_BITS_PER_WIDE_INT.  */
4330       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4331           && COMPARISON_P (XEXP (x, 0))
4332           && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
4333         return gen_lowpart (mode, XEXP (x, 0));
4334
4335       /* Similarly, a truncate of a register whose value is a
4336          comparison can be replaced with a subreg if STORE_FLAG_VALUE
4337          permits.  */
4338       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4339           && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4340           && (temp = get_last_value (XEXP (x, 0)))
4341           && COMPARISON_P (temp))
4342         return gen_lowpart (mode, XEXP (x, 0));
4343
4344       break;
4345
4346     case FLOAT_TRUNCATE:
4347       /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF.  */
4348       if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4349           && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4350         return XEXP (XEXP (x, 0), 0);
4351
4352       /* (float_truncate:SF (float_truncate:DF foo:XF))
4353          = (float_truncate:SF foo:XF).
4354          This may eliminate double rounding, so it is unsafe.
4355
4356          (float_truncate:SF (float_extend:XF foo:DF))
4357          = (float_truncate:SF foo:DF).
4358
4359          (float_truncate:DF (float_extend:XF foo:SF))
4360          = (float_extend:SF foo:DF).  */
4361       if ((GET_CODE (XEXP (x, 0)) == FLOAT_TRUNCATE
4362            && flag_unsafe_math_optimizations)
4363           || GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND)
4364         return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x, 0),
4365                                                             0)))
4366                                    > GET_MODE_SIZE (mode)
4367                                    ? FLOAT_TRUNCATE : FLOAT_EXTEND,
4368                                    mode,
4369                                    XEXP (XEXP (x, 0), 0), mode);
4370
4371       /*  (float_truncate (float x)) is (float x)  */
4372       if (GET_CODE (XEXP (x, 0)) == FLOAT
4373           && (flag_unsafe_math_optimizations
4374               || ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
4375                   >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
4376                       - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
4377                                              GET_MODE (XEXP (XEXP (x, 0), 0)))))))
4378         return simplify_gen_unary (FLOAT, mode,
4379                                    XEXP (XEXP (x, 0), 0),
4380                                    GET_MODE (XEXP (XEXP (x, 0), 0)));
4381
4382       /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4383          (OP:SF foo:SF) if OP is NEG or ABS.  */
4384       if ((GET_CODE (XEXP (x, 0)) == ABS
4385            || GET_CODE (XEXP (x, 0)) == NEG)
4386           && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4387           && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4388         return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4389                                    XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4390
4391       /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4392          is (float_truncate:SF x).  */
4393       if (GET_CODE (XEXP (x, 0)) == SUBREG
4394           && subreg_lowpart_p (XEXP (x, 0))
4395           && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4396         return SUBREG_REG (XEXP (x, 0));
4397       break;
4398     case FLOAT_EXTEND:
4399       /*  (float_extend (float_extend x)) is (float_extend x)
4400
4401           (float_extend (float x)) is (float x) assuming that double
4402           rounding can't happen.
4403           */
4404       if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4405           || (GET_CODE (XEXP (x, 0)) == FLOAT
4406               && ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
4407                   >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
4408                       - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
4409                                              GET_MODE (XEXP (XEXP (x, 0), 0)))))))
4410         return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4411                                    XEXP (XEXP (x, 0), 0),
4412                                    GET_MODE (XEXP (XEXP (x, 0), 0)));
4413
4414       break;
4415 #ifdef HAVE_cc0
4416     case COMPARE:
4417       /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4418          using cc0, in which case we want to leave it as a COMPARE
4419          so we can distinguish it from a register-register-copy.  */
4420       if (XEXP (x, 1) == const0_rtx)
4421         return XEXP (x, 0);
4422
4423       /* x - 0 is the same as x unless x's mode has signed zeros and
4424          allows rounding towards -infinity.  Under those conditions,
4425          0 - 0 is -0.  */
4426       if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4427             && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4428           && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4429         return XEXP (x, 0);
4430       break;
4431 #endif
4432
4433     case CONST:
4434       /* (const (const X)) can become (const X).  Do it this way rather than
4435          returning the inner CONST since CONST can be shared with a
4436          REG_EQUAL note.  */
4437       if (GET_CODE (XEXP (x, 0)) == CONST)
4438         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4439       break;
4440
4441 #ifdef HAVE_lo_sum
4442     case LO_SUM:
4443       /* Convert (lo_sum (high FOO) FOO) to FOO.  This is necessary so we
4444          can add in an offset.  find_split_point will split this address up
4445          again if it doesn't match.  */
4446       if (GET_CODE (XEXP (x, 0)) == HIGH
4447           && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4448         return XEXP (x, 1);
4449       break;
4450 #endif
4451
4452     case PLUS:
4453       /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4454        */
4455       if (GET_CODE (XEXP (x, 0)) == MULT
4456           && GET_CODE (XEXP (XEXP (x, 0), 0)) == NEG)
4457         {
4458           rtx in1, in2;
4459
4460           in1 = XEXP (XEXP (XEXP (x, 0), 0), 0);
4461           in2 = XEXP (XEXP (x, 0), 1);
4462           return simplify_gen_binary (MINUS, mode, XEXP (x, 1),
4463                                       simplify_gen_binary (MULT, mode,
4464                                                            in1, in2));
4465         }
4466
4467       /* If we have (plus (plus (A const) B)), associate it so that CONST is
4468          outermost.  That's because that's the way indexed addresses are
4469          supposed to appear.  This code used to check many more cases, but
4470          they are now checked elsewhere.  */
4471       if (GET_CODE (XEXP (x, 0)) == PLUS
4472           && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4473         return simplify_gen_binary (PLUS, mode,
4474                                     simplify_gen_binary (PLUS, mode,
4475                                                          XEXP (XEXP (x, 0), 0),
4476                                                          XEXP (x, 1)),
4477                                     XEXP (XEXP (x, 0), 1));
4478
4479       /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4480          when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4481          bit-field and can be replaced by either a sign_extend or a
4482          sign_extract.  The `and' may be a zero_extend and the two
4483          <c>, -<c> constants may be reversed.  */
4484       if (GET_CODE (XEXP (x, 0)) == XOR
4485           && GET_CODE (XEXP (x, 1)) == CONST_INT
4486           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4487           && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4488           && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4489               || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4490           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4491           && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4492                && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4493                && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4494                    == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4495               || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4496                   && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4497                       == (unsigned int) i + 1))))
4498         return simplify_shift_const
4499           (NULL_RTX, ASHIFTRT, mode,
4500            simplify_shift_const (NULL_RTX, ASHIFT, mode,
4501                                  XEXP (XEXP (XEXP (x, 0), 0), 0),
4502                                  GET_MODE_BITSIZE (mode) - (i + 1)),
4503            GET_MODE_BITSIZE (mode) - (i + 1));
4504
4505       /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4506          C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4507          is 1.  This produces better code than the alternative immediately
4508          below.  */
4509       if (COMPARISON_P (XEXP (x, 0))
4510           && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4511               || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))
4512           && (reversed = reversed_comparison (XEXP (x, 0), mode)))
4513         return
4514           simplify_gen_unary (NEG, mode, reversed, mode);
4515
4516       /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4517          can become (ashiftrt (ashift (xor x 1) C) C) where C is
4518          the bitsize of the mode - 1.  This allows simplification of
4519          "a = (b & 8) == 0;"  */
4520       if (XEXP (x, 1) == constm1_rtx
4521           && !REG_P (XEXP (x, 0))
4522           && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4523                 && REG_P (SUBREG_REG (XEXP (x, 0))))
4524           && nonzero_bits (XEXP (x, 0), mode) == 1)
4525         return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4526            simplify_shift_const (NULL_RTX, ASHIFT, mode,
4527                                  gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4528                                  GET_MODE_BITSIZE (mode) - 1),
4529            GET_MODE_BITSIZE (mode) - 1);
4530
4531       /* If we are adding two things that have no bits in common, convert
4532          the addition into an IOR.  This will often be further simplified,
4533          for example in cases like ((a & 1) + (a & 2)), which can
4534          become a & 3.  */
4535
4536       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4537           && (nonzero_bits (XEXP (x, 0), mode)
4538               & nonzero_bits (XEXP (x, 1), mode)) == 0)
4539         {
4540           /* Try to simplify the expression further.  */
4541           rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4542           temp = combine_simplify_rtx (tor, mode, in_dest);
4543
4544           /* If we could, great.  If not, do not go ahead with the IOR
4545              replacement, since PLUS appears in many special purpose
4546              address arithmetic instructions.  */
4547           if (GET_CODE (temp) != CLOBBER && temp != tor)
4548             return temp;
4549         }
4550       break;
4551
4552     case MINUS:
4553       /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4554          by reversing the comparison code if valid.  */
4555       if (STORE_FLAG_VALUE == 1
4556           && XEXP (x, 0) == const1_rtx
4557           && COMPARISON_P (XEXP (x, 1))
4558           && (reversed = reversed_comparison (XEXP (x, 1), mode)))
4559         return reversed;
4560
4561       /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4562          (and <foo> (const_int pow2-1))  */
4563       if (GET_CODE (XEXP (x, 1)) == AND
4564           && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4565           && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4566           && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4567         return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4568                                        -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4569
4570       /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4571        */
4572       if (GET_CODE (XEXP (x, 1)) == MULT
4573           && GET_CODE (XEXP (XEXP (x, 1), 0)) == NEG)
4574         {
4575           rtx in1, in2;
4576
4577           in1 = XEXP (XEXP (XEXP (x, 1), 0), 0);
4578           in2 = XEXP (XEXP (x, 1), 1);
4579           return simplify_gen_binary (PLUS, mode,
4580                                       simplify_gen_binary (MULT, mode,
4581                                                            in1, in2),
4582                                       XEXP (x, 0));
4583         }
4584
4585       /* Canonicalize (minus (neg A) (mult B C)) to
4586          (minus (mult (neg B) C) A).  */
4587       if (GET_CODE (XEXP (x, 1)) == MULT
4588           && GET_CODE (XEXP (x, 0)) == NEG)
4589         {
4590           rtx in1, in2;
4591
4592           in1 = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 1), 0), mode);
4593           in2 = XEXP (XEXP (x, 1), 1);
4594           return simplify_gen_binary (MINUS, mode,
4595                                       simplify_gen_binary (MULT, mode,
4596                                                            in1, in2),
4597                                       XEXP (XEXP (x, 0), 0));
4598         }
4599
4600       /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4601          integers.  */
4602       if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4603         return simplify_gen_binary (MINUS, mode,
4604                                     simplify_gen_binary (MINUS, mode,
4605                                                          XEXP (x, 0),
4606                                                          XEXP (XEXP (x, 1), 0)),
4607                                     XEXP (XEXP (x, 1), 1));
4608       break;
4609
4610     case MULT:
4611       /* If we have (mult (plus A B) C), apply the distributive law and then
4612          the inverse distributive law to see if things simplify.  This
4613          occurs mostly in addresses, often when unrolling loops.  */
4614
4615       if (GET_CODE (XEXP (x, 0)) == PLUS)
4616         {
4617           rtx result = distribute_and_simplify_rtx (x, 0);
4618           if (result)
4619             return result;
4620         }
4621
4622       /* Try simplify a*(b/c) as (a*b)/c.  */
4623       if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4624           && GET_CODE (XEXP (x, 0)) == DIV)
4625         {
4626           rtx tem = simplify_binary_operation (MULT, mode,
4627                                                XEXP (XEXP (x, 0), 0),
4628                                                XEXP (x, 1));
4629           if (tem)
4630             return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4631         }
4632       break;
4633
4634     case UDIV:
4635       /* If this is a divide by a power of two, treat it as a shift if
4636          its first operand is a shift.  */
4637       if (GET_CODE (XEXP (x, 1)) == CONST_INT
4638           && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4639           && (GET_CODE (XEXP (x, 0)) == ASHIFT
4640               || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4641               || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4642               || GET_CODE (XEXP (x, 0)) == ROTATE
4643               || GET_CODE (XEXP (x, 0)) == ROTATERT))
4644         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4645       break;
4646
4647     case EQ:  case NE:
4648     case GT:  case GTU:  case GE:  case GEU:
4649     case LT:  case LTU:  case LE:  case LEU:
4650     case UNEQ:  case LTGT:
4651     case UNGT:  case UNGE:
4652     case UNLT:  case UNLE:
4653     case UNORDERED: case ORDERED:
4654       /* If the first operand is a condition code, we can't do anything
4655          with it.  */
4656       if (GET_CODE (XEXP (x, 0)) == COMPARE
4657           || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4658               && ! CC0_P (XEXP (x, 0))))
4659         {
4660           rtx op0 = XEXP (x, 0);
4661           rtx op1 = XEXP (x, 1);
4662           enum rtx_code new_code;
4663
4664           if (GET_CODE (op0) == COMPARE)
4665             op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4666
4667           /* Simplify our comparison, if possible.  */
4668           new_code = simplify_comparison (code, &op0, &op1);
4669
4670           /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4671              if only the low-order bit is possibly nonzero in X (such as when
4672              X is a ZERO_EXTRACT of one bit).  Similarly, we can convert EQ to
4673              (xor X 1) or (minus 1 X); we use the former.  Finally, if X is
4674              known to be either 0 or -1, NE becomes a NEG and EQ becomes
4675              (plus X 1).
4676
4677              Remove any ZERO_EXTRACT we made when thinking this was a
4678              comparison.  It may now be simpler to use, e.g., an AND.  If a
4679              ZERO_EXTRACT is indeed appropriate, it will be placed back by
4680              the call to make_compound_operation in the SET case.  */
4681
4682           if (STORE_FLAG_VALUE == 1
4683               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4684               && op1 == const0_rtx
4685               && mode == GET_MODE (op0)
4686               && nonzero_bits (op0, mode) == 1)
4687             return gen_lowpart (mode,
4688                                 expand_compound_operation (op0));
4689
4690           else if (STORE_FLAG_VALUE == 1
4691                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4692                    && op1 == const0_rtx
4693                    && mode == GET_MODE (op0)
4694                    && (num_sign_bit_copies (op0, mode)
4695                        == GET_MODE_BITSIZE (mode)))
4696             {
4697               op0 = expand_compound_operation (op0);
4698               return simplify_gen_unary (NEG, mode,
4699                                          gen_lowpart (mode, op0),
4700                                          mode);
4701             }
4702
4703           else if (STORE_FLAG_VALUE == 1
4704                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4705                    && op1 == const0_rtx
4706                    && mode == GET_MODE (op0)
4707                    && nonzero_bits (op0, mode) == 1)
4708             {
4709               op0 = expand_compound_operation (op0);
4710               return simplify_gen_binary (XOR, mode,
4711                                           gen_lowpart (mode, op0),
4712                                           const1_rtx);
4713             }
4714
4715           else if (STORE_FLAG_VALUE == 1
4716                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4717                    && op1 == const0_rtx
4718                    && mode == GET_MODE (op0)
4719                    && (num_sign_bit_copies (op0, mode)
4720                        == GET_MODE_BITSIZE (mode)))
4721             {
4722               op0 = expand_compound_operation (op0);
4723               return plus_constant (gen_lowpart (mode, op0), 1);
4724             }
4725
4726           /* If STORE_FLAG_VALUE is -1, we have cases similar to
4727              those above.  */
4728           if (STORE_FLAG_VALUE == -1
4729               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4730               && op1 == const0_rtx
4731               && (num_sign_bit_copies (op0, mode)
4732                   == GET_MODE_BITSIZE (mode)))
4733             return gen_lowpart (mode,
4734                                 expand_compound_operation (op0));
4735
4736           else if (STORE_FLAG_VALUE == -1
4737                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4738                    && op1 == const0_rtx
4739                    && mode == GET_MODE (op0)
4740                    && nonzero_bits (op0, mode) == 1)
4741             {
4742               op0 = expand_compound_operation (op0);
4743               return simplify_gen_unary (NEG, mode,
4744                                          gen_lowpart (mode, op0),
4745                                          mode);
4746             }
4747
4748           else if (STORE_FLAG_VALUE == -1
4749                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4750                    && op1 == const0_rtx
4751                    && mode == GET_MODE (op0)
4752                    && (num_sign_bit_copies (op0, mode)
4753                        == GET_MODE_BITSIZE (mode)))
4754             {
4755               op0 = expand_compound_operation (op0);
4756               return simplify_gen_unary (NOT, mode,
4757                                          gen_lowpart (mode, op0),
4758                                          mode);
4759             }
4760
4761           /* If X is 0/1, (eq X 0) is X-1.  */
4762           else if (STORE_FLAG_VALUE == -1
4763                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4764                    && op1 == const0_rtx
4765                    && mode == GET_MODE (op0)
4766                    && nonzero_bits (op0, mode) == 1)
4767             {
4768               op0 = expand_compound_operation (op0);
4769               return plus_constant (gen_lowpart (mode, op0), -1);
4770             }
4771
4772           /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4773              one bit that might be nonzero, we can convert (ne x 0) to
4774              (ashift x c) where C puts the bit in the sign bit.  Remove any
4775              AND with STORE_FLAG_VALUE when we are done, since we are only
4776              going to test the sign bit.  */
4777           if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4778               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4779               && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4780                   == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4781               && op1 == const0_rtx
4782               && mode == GET_MODE (op0)
4783               && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4784             {
4785               x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4786                                         expand_compound_operation (op0),
4787                                         GET_MODE_BITSIZE (mode) - 1 - i);
4788               if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4789                 return XEXP (x, 0);
4790               else
4791                 return x;
4792             }
4793
4794           /* If the code changed, return a whole new comparison.  */
4795           if (new_code != code)
4796             return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4797
4798           /* Otherwise, keep this operation, but maybe change its operands.
4799              This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR).  */
4800           SUBST (XEXP (x, 0), op0);
4801           SUBST (XEXP (x, 1), op1);
4802         }
4803       break;
4804
4805     case IF_THEN_ELSE:
4806       return simplify_if_then_else (x);
4807
4808     case ZERO_EXTRACT:
4809     case SIGN_EXTRACT:
4810     case ZERO_EXTEND:
4811     case SIGN_EXTEND:
4812       /* If we are processing SET_DEST, we are done.  */
4813       if (in_dest)
4814         return x;
4815
4816       return expand_compound_operation (x);
4817
4818     case SET:
4819       return simplify_set (x);
4820
4821     case AND:
4822     case IOR:
4823     case XOR:
4824       return simplify_logical (x);
4825
4826     case ABS:
4827       /* (abs (neg <foo>)) -> (abs <foo>) */
4828       if (GET_CODE (XEXP (x, 0)) == NEG)
4829         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4830
4831       /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4832          do nothing.  */
4833       if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4834         break;
4835
4836       /* If operand is something known to be positive, ignore the ABS.  */
4837       if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4838           || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4839                <= HOST_BITS_PER_WIDE_INT)
4840               && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4841                    & ((HOST_WIDE_INT) 1
4842                       << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4843                   == 0)))
4844         return XEXP (x, 0);
4845
4846       /* If operand is known to be only -1 or 0, convert ABS to NEG.  */
4847       if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4848         return gen_rtx_NEG (mode, XEXP (x, 0));
4849
4850       break;
4851
4852     case FFS:
4853       /* (ffs (*_extend <X>)) = (ffs <X>) */
4854       if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4855           || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4856         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4857       break;
4858
4859     case POPCOUNT:
4860     case PARITY:
4861       /* (pop* (zero_extend <X>)) = (pop* <X>) */
4862       if (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4863         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4864       break;
4865
4866     case FLOAT:
4867       /* (float (sign_extend <X>)) = (float <X>).  */
4868       if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4869         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4870       break;
4871
4872     case ASHIFT:
4873     case LSHIFTRT:
4874     case ASHIFTRT:
4875     case ROTATE:
4876     case ROTATERT:
4877       /* If this is a shift by a constant amount, simplify it.  */
4878       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4879         return simplify_shift_const (x, code, mode, XEXP (x, 0),
4880                                      INTVAL (XEXP (x, 1)));
4881
4882       else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
4883         SUBST (XEXP (x, 1),
4884                force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4885                               ((HOST_WIDE_INT) 1
4886                                << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4887                               - 1,
4888                               NULL_RTX, 0));
4889       break;
4890
4891     case VEC_SELECT:
4892       {
4893         rtx op0 = XEXP (x, 0);
4894         rtx op1 = XEXP (x, 1);
4895         int len;
4896
4897         gcc_assert (GET_CODE (op1) == PARALLEL);
4898         len = XVECLEN (op1, 0);
4899         if (len == 1
4900             && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT
4901             && GET_CODE (op0) == VEC_CONCAT)
4902           {
4903             int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x));
4904
4905             /* Try to find the element in the VEC_CONCAT.  */
4906             for (;;)
4907               {
4908                 if (GET_MODE (op0) == GET_MODE (x))
4909                   return op0;
4910                 if (GET_CODE (op0) == VEC_CONCAT)
4911                   {
4912                     HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)));
4913                     if (offset < op0_size)
4914                       op0 = XEXP (op0, 0);
4915                     else
4916                       {
4917                         offset -= op0_size;
4918                         op0 = XEXP (op0, 1);
4919                       }
4920                   }
4921                 else
4922                   break;
4923               }
4924           }
4925       }
4926
4927       break;
4928
4929     default:
4930       break;
4931     }
4932
4933   return x;
4934 }
4935 \f
4936 /* Simplify X, an IF_THEN_ELSE expression.  Return the new expression.  */
4937
4938 static rtx
4939 simplify_if_then_else (rtx x)
4940 {
4941   enum machine_mode mode = GET_MODE (x);
4942   rtx cond = XEXP (x, 0);
4943   rtx true_rtx = XEXP (x, 1);
4944   rtx false_rtx = XEXP (x, 2);
4945   enum rtx_code true_code = GET_CODE (cond);
4946   int comparison_p = COMPARISON_P (cond);
4947   rtx temp;
4948   int i;
4949   enum rtx_code false_code;
4950   rtx reversed;
4951
4952   /* Simplify storing of the truth value.  */
4953   if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4954     return simplify_gen_relational (true_code, mode, VOIDmode,
4955                                     XEXP (cond, 0), XEXP (cond, 1));
4956
4957   /* Also when the truth value has to be reversed.  */
4958   if (comparison_p
4959       && true_rtx == const0_rtx && false_rtx == const_true_rtx
4960       && (reversed = reversed_comparison (cond, mode)))
4961     return reversed;
4962
4963   /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4964      in it is being compared against certain values.  Get the true and false
4965      comparisons and see if that says anything about the value of each arm.  */
4966
4967   if (comparison_p
4968       && ((false_code = reversed_comparison_code (cond, NULL))
4969           != UNKNOWN)
4970       && REG_P (XEXP (cond, 0)))
4971     {
4972       HOST_WIDE_INT nzb;
4973       rtx from = XEXP (cond, 0);
4974       rtx true_val = XEXP (cond, 1);
4975       rtx false_val = true_val;
4976       int swapped = 0;
4977
4978       /* If FALSE_CODE is EQ, swap the codes and arms.  */
4979
4980       if (false_code == EQ)
4981         {
4982           swapped = 1, true_code = EQ, false_code = NE;
4983           temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4984         }
4985
4986       /* If we are comparing against zero and the expression being tested has
4987          only a single bit that might be nonzero, that is its value when it is
4988          not equal to zero.  Similarly if it is known to be -1 or 0.  */
4989
4990       if (true_code == EQ && true_val == const0_rtx
4991           && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4992         false_code = EQ, false_val = GEN_INT (nzb);
4993       else if (true_code == EQ && true_val == const0_rtx
4994                && (num_sign_bit_copies (from, GET_MODE (from))
4995                    == GET_MODE_BITSIZE (GET_MODE (from))))
4996         false_code = EQ, false_val = constm1_rtx;
4997
4998       /* Now simplify an arm if we know the value of the register in the
4999          branch and it is used in the arm.  Be careful due to the potential
5000          of locally-shared RTL.  */
5001
5002       if (reg_mentioned_p (from, true_rtx))
5003         true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5004                                       from, true_val),
5005                       pc_rtx, pc_rtx, 0, 0);
5006       if (reg_mentioned_p (from, false_rtx))
5007         false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5008                                    from, false_val),
5009                        pc_rtx, pc_rtx, 0, 0);
5010
5011       SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
5012       SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
5013
5014       true_rtx = XEXP (x, 1);
5015       false_rtx = XEXP (x, 2);
5016       true_code = GET_CODE (cond);
5017     }
5018
5019   /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5020      reversed, do so to avoid needing two sets of patterns for
5021      subtract-and-branch insns.  Similarly if we have a constant in the true
5022      arm, the false arm is the same as the first operand of the comparison, or
5023      the false arm is more complicated than the true arm.  */
5024
5025   if (comparison_p
5026       && reversed_comparison_code (cond, NULL) != UNKNOWN
5027       && (true_rtx == pc_rtx
5028           || (CONSTANT_P (true_rtx)
5029               && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
5030           || true_rtx == const0_rtx
5031           || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
5032           || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
5033               && !OBJECT_P (false_rtx))
5034           || reg_mentioned_p (true_rtx, false_rtx)
5035           || rtx_equal_p (false_rtx, XEXP (cond, 0))))
5036     {
5037       true_code = reversed_comparison_code (cond, NULL);
5038       SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
5039       SUBST (XEXP (x, 1), false_rtx);
5040       SUBST (XEXP (x, 2), true_rtx);
5041
5042       temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5043       cond = XEXP (x, 0);
5044
5045       /* It is possible that the conditional has been simplified out.  */
5046       true_code = GET_CODE (cond);
5047       comparison_p = COMPARISON_P (cond);
5048     }
5049
5050   /* If the two arms are identical, we don't need the comparison.  */
5051
5052   if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
5053     return true_rtx;
5054
5055   /* Convert a == b ? b : a to "a".  */
5056   if (true_code == EQ && ! side_effects_p (cond)
5057       && !HONOR_NANS (mode)
5058       && rtx_equal_p (XEXP (cond, 0), false_rtx)
5059       && rtx_equal_p (XEXP (cond, 1), true_rtx))
5060     return false_rtx;
5061   else if (true_code == NE && ! side_effects_p (cond)
5062            && !HONOR_NANS (mode)
5063            && rtx_equal_p (XEXP (cond, 0), true_rtx)
5064            && rtx_equal_p (XEXP (cond, 1), false_rtx))
5065     return true_rtx;
5066
5067   /* Look for cases where we have (abs x) or (neg (abs X)).  */
5068
5069   if (GET_MODE_CLASS (mode) == MODE_INT
5070       && comparison_p
5071       && XEXP (cond, 1) == const0_rtx
5072       && GET_CODE (false_rtx) == NEG
5073       && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
5074       && rtx_equal_p (true_rtx, XEXP (cond, 0))
5075       && ! side_effects_p (true_rtx))
5076     switch (true_code)
5077       {
5078       case GT:
5079       case GE:
5080         return simplify_gen_unary (ABS, mode, true_rtx, mode);
5081       case LT:
5082       case LE:
5083         return
5084           simplify_gen_unary (NEG, mode,
5085                               simplify_gen_unary (ABS, mode, true_rtx, mode),
5086                               mode);
5087       default:
5088         break;
5089       }
5090
5091   /* Look for MIN or MAX.  */
5092
5093   if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
5094       && comparison_p
5095       && rtx_equal_p (XEXP (cond, 0), true_rtx)
5096       && rtx_equal_p (XEXP (cond, 1), false_rtx)
5097       && ! side_effects_p (cond))
5098     switch (true_code)
5099       {
5100       case GE:
5101       case GT:
5102         return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
5103       case LE:
5104       case LT:
5105         return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
5106       case GEU:
5107       case GTU:
5108         return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
5109       case LEU:
5110       case LTU:
5111         return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
5112       default:
5113         break;
5114       }
5115
5116   /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
5117      second operand is zero, this can be done as (OP Z (mult COND C2)) where
5118      C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
5119      SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
5120      We can do this kind of thing in some cases when STORE_FLAG_VALUE is
5121      neither 1 or -1, but it isn't worth checking for.  */
5122
5123   if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
5124       && comparison_p
5125       && GET_MODE_CLASS (mode) == MODE_INT
5126       && ! side_effects_p (x))
5127     {
5128       rtx t = make_compound_operation (true_rtx, SET);
5129       rtx f = make_compound_operation (false_rtx, SET);
5130       rtx cond_op0 = XEXP (cond, 0);
5131       rtx cond_op1 = XEXP (cond, 1);
5132       enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
5133       enum machine_mode m = mode;
5134       rtx z = 0, c1 = NULL_RTX;
5135
5136       if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
5137            || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5138            || GET_CODE (t) == ASHIFT
5139            || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
5140           && rtx_equal_p (XEXP (t, 0), f))
5141         c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
5142
5143       /* If an identity-zero op is commutative, check whether there
5144          would be a match if we swapped the operands.  */
5145       else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
5146                 || GET_CODE (t) == XOR)
5147                && rtx_equal_p (XEXP (t, 1), f))
5148         c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
5149       else if (GET_CODE (t) == SIGN_EXTEND
5150                && (GET_CODE (XEXP (t, 0)) == PLUS
5151                    || GET_CODE (XEXP (t, 0)) == MINUS
5152                    || GET_CODE (XEXP (t, 0)) == IOR
5153                    || GET_CODE (XEXP (t, 0)) == XOR
5154                    || GET_CODE (XEXP (t, 0)) == ASHIFT
5155                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5156                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5157                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5158                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5159                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5160                && (num_sign_bit_copies (f, GET_MODE (f))
5161                    > (unsigned int)
5162                      (GET_MODE_BITSIZE (mode)
5163                       - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5164         {
5165           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5166           extend_op = SIGN_EXTEND;
5167           m = GET_MODE (XEXP (t, 0));
5168         }
5169       else if (GET_CODE (t) == SIGN_EXTEND
5170                && (GET_CODE (XEXP (t, 0)) == PLUS
5171                    || GET_CODE (XEXP (t, 0)) == IOR
5172                    || GET_CODE (XEXP (t, 0)) == XOR)
5173                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5174                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5175                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5176                && (num_sign_bit_copies (f, GET_MODE (f))
5177                    > (unsigned int)
5178                      (GET_MODE_BITSIZE (mode)
5179                       - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5180         {
5181           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5182           extend_op = SIGN_EXTEND;
5183           m = GET_MODE (XEXP (t, 0));
5184         }
5185       else if (GET_CODE (t) == ZERO_EXTEND
5186                && (GET_CODE (XEXP (t, 0)) == PLUS
5187                    || GET_CODE (XEXP (t, 0)) == MINUS
5188                    || GET_CODE (XEXP (t, 0)) == IOR
5189                    || GET_CODE (XEXP (t, 0)) == XOR
5190                    || GET_CODE (XEXP (t, 0)) == ASHIFT
5191                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5192                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5193                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5194                && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5195                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5196                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5197                && ((nonzero_bits (f, GET_MODE (f))
5198                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5199                    == 0))
5200         {
5201           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5202           extend_op = ZERO_EXTEND;
5203           m = GET_MODE (XEXP (t, 0));
5204         }
5205       else if (GET_CODE (t) == ZERO_EXTEND
5206                && (GET_CODE (XEXP (t, 0)) == PLUS
5207                    || GET_CODE (XEXP (t, 0)) == IOR
5208                    || GET_CODE (XEXP (t, 0)) == XOR)
5209                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5210                && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5211                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5212                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5213                && ((nonzero_bits (f, GET_MODE (f))
5214                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5215                    == 0))
5216         {
5217           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5218           extend_op = ZERO_EXTEND;
5219           m = GET_MODE (XEXP (t, 0));
5220         }
5221
5222       if (z)
5223         {
5224           temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5225                                                  cond_op0, cond_op1),
5226                         pc_rtx, pc_rtx, 0, 0);
5227           temp = simplify_gen_binary (MULT, m, temp,
5228                                       simplify_gen_binary (MULT, m, c1,
5229                                                            const_true_rtx));
5230           temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5231           temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5232
5233           if (extend_op != UNKNOWN)
5234             temp = simplify_gen_unary (extend_op, mode, temp, m);
5235
5236           return temp;
5237         }
5238     }
5239
5240   /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5241      1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5242      negation of a single bit, we can convert this operation to a shift.  We
5243      can actually do this more generally, but it doesn't seem worth it.  */
5244
5245   if (true_code == NE && XEXP (cond, 1) == const0_rtx
5246       && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5247       && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5248            && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5249           || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5250                == GET_MODE_BITSIZE (mode))
5251               && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5252     return
5253       simplify_shift_const (NULL_RTX, ASHIFT, mode,
5254                             gen_lowpart (mode, XEXP (cond, 0)), i);
5255
5256   /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8.  */
5257   if (true_code == NE && XEXP (cond, 1) == const0_rtx
5258       && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5259       && GET_MODE (XEXP (cond, 0)) == mode
5260       && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5261           == nonzero_bits (XEXP (cond, 0), mode)
5262       && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5263     return XEXP (cond, 0);
5264
5265   return x;
5266 }
5267 \f
5268 /* Simplify X, a SET expression.  Return the new expression.  */
5269
5270 static rtx
5271 simplify_set (rtx x)
5272 {
5273   rtx src = SET_SRC (x);
5274   rtx dest = SET_DEST (x);
5275   enum machine_mode mode
5276     = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5277   rtx other_insn;
5278   rtx *cc_use;
5279
5280   /* (set (pc) (return)) gets written as (return).  */
5281   if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5282     return src;
5283
5284   /* Now that we know for sure which bits of SRC we are using, see if we can
5285      simplify the expression for the object knowing that we only need the
5286      low-order bits.  */
5287
5288   if (GET_MODE_CLASS (mode) == MODE_INT
5289       && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5290     {
5291       src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
5292       SUBST (SET_SRC (x), src);
5293     }
5294
5295   /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5296      the comparison result and try to simplify it unless we already have used
5297      undobuf.other_insn.  */
5298   if ((GET_MODE_CLASS (mode) == MODE_CC
5299        || GET_CODE (src) == COMPARE
5300        || CC0_P (dest))
5301       && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5302       && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5303       && COMPARISON_P (*cc_use)
5304       && rtx_equal_p (XEXP (*cc_use, 0), dest))
5305     {
5306       enum rtx_code old_code = GET_CODE (*cc_use);
5307       enum rtx_code new_code;
5308       rtx op0, op1, tmp;
5309       int other_changed = 0;
5310       enum machine_mode compare_mode = GET_MODE (dest);
5311
5312       if (GET_CODE (src) == COMPARE)
5313         op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5314       else
5315         op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5316
5317       tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5318                                            op0, op1);
5319       if (!tmp)
5320         new_code = old_code;
5321       else if (!CONSTANT_P (tmp))
5322         {
5323           new_code = GET_CODE (tmp);
5324           op0 = XEXP (tmp, 0);
5325           op1 = XEXP (tmp, 1);
5326         }
5327       else
5328         {
5329           rtx pat = PATTERN (other_insn);
5330           undobuf.other_insn = other_insn;
5331           SUBST (*cc_use, tmp);
5332
5333           /* Attempt to simplify CC user.  */
5334           if (GET_CODE (pat) == SET)
5335             {
5336               rtx new = simplify_rtx (SET_SRC (pat));
5337               if (new != NULL_RTX)
5338                 SUBST (SET_SRC (pat), new);
5339             }
5340
5341           /* Convert X into a no-op move.  */
5342           SUBST (SET_DEST (x), pc_rtx);
5343           SUBST (SET_SRC (x), pc_rtx);
5344           return x;
5345         }
5346
5347       /* Simplify our comparison, if possible.  */
5348       new_code = simplify_comparison (new_code, &op0, &op1);
5349
5350 #ifdef SELECT_CC_MODE
5351       /* If this machine has CC modes other than CCmode, check to see if we
5352          need to use a different CC mode here.  */
5353       if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5354         compare_mode = GET_MODE (op0);
5355       else
5356         compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5357
5358 #ifndef HAVE_cc0
5359       /* If the mode changed, we have to change SET_DEST, the mode in the
5360          compare, and the mode in the place SET_DEST is used.  If SET_DEST is
5361          a hard register, just build new versions with the proper mode.  If it
5362          is a pseudo, we lose unless it is only time we set the pseudo, in
5363          which case we can safely change its mode.  */
5364       if (compare_mode != GET_MODE (dest))
5365         {
5366           if (can_change_dest_mode (dest, 0, compare_mode))
5367             {
5368               unsigned int regno = REGNO (dest);
5369               rtx new_dest = gen_rtx_REG (compare_mode, regno);
5370
5371               if (regno >= FIRST_PSEUDO_REGISTER)
5372                 SUBST (regno_reg_rtx[regno], new_dest);
5373
5374               SUBST (SET_DEST (x), new_dest);
5375               SUBST (XEXP (*cc_use, 0), new_dest);
5376               other_changed = 1;
5377
5378               dest = new_dest;
5379             }
5380         }
5381 #endif  /* cc0 */
5382 #endif  /* SELECT_CC_MODE */
5383
5384       /* If the code changed, we have to build a new comparison in
5385          undobuf.other_insn.  */
5386       if (new_code != old_code)
5387         {
5388           int other_changed_previously = other_changed;
5389           unsigned HOST_WIDE_INT mask;
5390
5391           SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5392                                           dest, const0_rtx));
5393           other_changed = 1;
5394
5395           /* If the only change we made was to change an EQ into an NE or
5396              vice versa, OP0 has only one bit that might be nonzero, and OP1
5397              is zero, check if changing the user of the condition code will
5398              produce a valid insn.  If it won't, we can keep the original code
5399              in that insn by surrounding our operation with an XOR.  */
5400
5401           if (((old_code == NE && new_code == EQ)
5402                || (old_code == EQ && new_code == NE))
5403               && ! other_changed_previously && op1 == const0_rtx
5404               && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5405               && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5406             {
5407               rtx pat = PATTERN (other_insn), note = 0;
5408
5409               if ((recog_for_combine (&pat, other_insn, &note) < 0
5410                    && ! check_asm_operands (pat)))
5411                 {
5412                   PUT_CODE (*cc_use, old_code);
5413                   other_changed = 0;
5414
5415                   op0 = simplify_gen_binary (XOR, GET_MODE (op0),
5416                                              op0, GEN_INT (mask));
5417                 }
5418             }
5419         }
5420
5421       if (other_changed)
5422         undobuf.other_insn = other_insn;
5423
5424 #ifdef HAVE_cc0
5425       /* If we are now comparing against zero, change our source if
5426          needed.  If we do not use cc0, we always have a COMPARE.  */
5427       if (op1 == const0_rtx && dest == cc0_rtx)
5428         {
5429           SUBST (SET_SRC (x), op0);
5430           src = op0;
5431         }
5432       else
5433 #endif
5434
5435       /* Otherwise, if we didn't previously have a COMPARE in the
5436          correct mode, we need one.  */
5437       if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5438         {
5439           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5440           src = SET_SRC (x);
5441         }
5442       else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
5443         {
5444           SUBST (SET_SRC (x), op0);
5445           src = SET_SRC (x);
5446         }
5447       /* Otherwise, update the COMPARE if needed.  */
5448       else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
5449         {
5450           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5451           src = SET_SRC (x);
5452         }
5453     }
5454   else
5455     {
5456       /* Get SET_SRC in a form where we have placed back any
5457          compound expressions.  Then do the checks below.  */
5458       src = make_compound_operation (src, SET);
5459       SUBST (SET_SRC (x), src);
5460     }
5461
5462   /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5463      and X being a REG or (subreg (reg)), we may be able to convert this to
5464      (set (subreg:m2 x) (op)).
5465
5466      We can always do this if M1 is narrower than M2 because that means that
5467      we only care about the low bits of the result.
5468
5469      However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5470      perform a narrower operation than requested since the high-order bits will
5471      be undefined.  On machine where it is defined, this transformation is safe
5472      as long as M1 and M2 have the same number of words.  */
5473
5474   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5475       && !OBJECT_P (SUBREG_REG (src))
5476       && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5477            / UNITS_PER_WORD)
5478           == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5479                + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5480 #ifndef WORD_REGISTER_OPERATIONS
5481       && (GET_MODE_SIZE (GET_MODE (src))
5482         < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5483 #endif
5484 #ifdef CANNOT_CHANGE_MODE_CLASS
5485       && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
5486             && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5487                                          GET_MODE (SUBREG_REG (src)),
5488                                          GET_MODE (src)))
5489 #endif
5490       && (REG_P (dest)
5491           || (GET_CODE (dest) == SUBREG
5492               && REG_P (SUBREG_REG (dest)))))
5493     {
5494       SUBST (SET_DEST (x),
5495              gen_lowpart (GET_MODE (SUBREG_REG (src)),
5496                                       dest));
5497       SUBST (SET_SRC (x), SUBREG_REG (src));
5498
5499       src = SET_SRC (x), dest = SET_DEST (x);
5500     }
5501
5502 #ifdef HAVE_cc0
5503   /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5504      in SRC.  */
5505   if (dest == cc0_rtx
5506       && GET_CODE (src) == SUBREG
5507       && subreg_lowpart_p (src)
5508       && (GET_MODE_BITSIZE (GET_MODE (src))
5509           < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5510     {
5511       rtx inner = SUBREG_REG (src);
5512       enum machine_mode inner_mode = GET_MODE (inner);
5513
5514       /* Here we make sure that we don't have a sign bit on.  */
5515       if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5516           && (nonzero_bits (inner, inner_mode)
5517               < ((unsigned HOST_WIDE_INT) 1
5518                  << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5519         {
5520           SUBST (SET_SRC (x), inner);
5521           src = SET_SRC (x);
5522         }
5523     }
5524 #endif
5525
5526 #ifdef LOAD_EXTEND_OP
5527   /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5528      would require a paradoxical subreg.  Replace the subreg with a
5529      zero_extend to avoid the reload that would otherwise be required.  */
5530
5531   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5532       && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
5533       && SUBREG_BYTE (src) == 0
5534       && (GET_MODE_SIZE (GET_MODE (src))
5535           > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5536       && MEM_P (SUBREG_REG (src)))
5537     {
5538       SUBST (SET_SRC (x),
5539              gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5540                             GET_MODE (src), SUBREG_REG (src)));
5541
5542       src = SET_SRC (x);
5543     }
5544 #endif
5545
5546   /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5547      are comparing an item known to be 0 or -1 against 0, use a logical
5548      operation instead. Check for one of the arms being an IOR of the other
5549      arm with some value.  We compute three terms to be IOR'ed together.  In
5550      practice, at most two will be nonzero.  Then we do the IOR's.  */
5551
5552   if (GET_CODE (dest) != PC
5553       && GET_CODE (src) == IF_THEN_ELSE
5554       && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5555       && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5556       && XEXP (XEXP (src, 0), 1) == const0_rtx
5557       && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5558 #ifdef HAVE_conditional_move
5559       && ! can_conditionally_move_p (GET_MODE (src))
5560 #endif
5561       && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5562                                GET_MODE (XEXP (XEXP (src, 0), 0)))
5563           == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5564       && ! side_effects_p (src))
5565     {
5566       rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5567                       ? XEXP (src, 1) : XEXP (src, 2));
5568       rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5569                    ? XEXP (src, 2) : XEXP (src, 1));
5570       rtx term1 = const0_rtx, term2, term3;
5571
5572       if (GET_CODE (true_rtx) == IOR
5573           && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5574         term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5575       else if (GET_CODE (true_rtx) == IOR
5576                && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5577         term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5578       else if (GET_CODE (false_rtx) == IOR
5579                && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5580         term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5581       else if (GET_CODE (false_rtx) == IOR
5582                && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5583         term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5584
5585       term2 = simplify_gen_binary (AND, GET_MODE (src),
5586                                    XEXP (XEXP (src, 0), 0), true_rtx);
5587       term3 = simplify_gen_binary (AND, GET_MODE (src),
5588                                    simplify_gen_unary (NOT, GET_MODE (src),
5589                                                        XEXP (XEXP (src, 0), 0),
5590                                                        GET_MODE (src)),
5591                                    false_rtx);
5592
5593       SUBST (SET_SRC (x),
5594              simplify_gen_binary (IOR, GET_MODE (src),
5595                                   simplify_gen_binary (IOR, GET_MODE (src),
5596                                                        term1, term2),
5597                                   term3));
5598
5599       src = SET_SRC (x);
5600     }
5601
5602   /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5603      whole thing fail.  */
5604   if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5605     return src;
5606   else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5607     return dest;
5608   else
5609     /* Convert this into a field assignment operation, if possible.  */
5610     return make_field_assignment (x);
5611 }
5612 \f
5613 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5614    result.  */
5615
5616 static rtx
5617 simplify_logical (rtx x)
5618 {
5619   enum machine_mode mode = GET_MODE (x);
5620   rtx op0 = XEXP (x, 0);
5621   rtx op1 = XEXP (x, 1);
5622   rtx reversed;
5623
5624   switch (GET_CODE (x))
5625     {
5626     case AND:
5627       /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5628          insn (and may simplify more).  */
5629       if (GET_CODE (op0) == XOR
5630           && rtx_equal_p (XEXP (op0, 0), op1)
5631           && ! side_effects_p (op1))
5632         x = simplify_gen_binary (AND, mode,
5633                                  simplify_gen_unary (NOT, mode,
5634                                                      XEXP (op0, 1), mode),
5635                                  op1);
5636
5637       if (GET_CODE (op0) == XOR
5638           && rtx_equal_p (XEXP (op0, 1), op1)
5639           && ! side_effects_p (op1))
5640         x = simplify_gen_binary (AND, mode,
5641                                  simplify_gen_unary (NOT, mode,
5642                                                      XEXP (op0, 0), mode),
5643                                  op1);
5644
5645       /* Similarly for (~(A ^ B)) & A.  */
5646       if (GET_CODE (op0) == NOT
5647           && GET_CODE (XEXP (op0, 0)) == XOR
5648           && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5649           && ! side_effects_p (op1))
5650         x = simplify_gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5651
5652       if (GET_CODE (op0) == NOT
5653           && GET_CODE (XEXP (op0, 0)) == XOR
5654           && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5655           && ! side_effects_p (op1))
5656         x = simplify_gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5657
5658       /* We can call simplify_and_const_int only if we don't lose
5659          any (sign) bits when converting INTVAL (op1) to
5660          "unsigned HOST_WIDE_INT".  */
5661       if (GET_CODE (op1) == CONST_INT
5662           && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5663               || INTVAL (op1) > 0))
5664         {
5665           x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5666
5667           /* If we have (ior (and (X C1) C2)) and the next restart would be
5668              the last, simplify this by making C1 as small as possible
5669              and then exit.  Only do this if C1 actually changes: for now
5670              this only saves memory but, should this transformation be
5671              moved to simplify-rtx.c, we'd risk unbounded recursion there.  */
5672           if (GET_CODE (x) == IOR && GET_CODE (op0) == AND
5673               && GET_CODE (XEXP (op0, 1)) == CONST_INT
5674               && GET_CODE (op1) == CONST_INT
5675               && (INTVAL (XEXP (op0, 1)) & INTVAL (op1)) != 0)
5676             return simplify_gen_binary (IOR, mode,
5677                                         simplify_gen_binary
5678                                           (AND, mode, XEXP (op0, 0),
5679                                            GEN_INT (INTVAL (XEXP (op0, 1))
5680                                                     & ~INTVAL (op1))), op1);
5681
5682           if (GET_CODE (x) != AND)
5683             return x;
5684
5685           op0 = XEXP (x, 0);
5686           op1 = XEXP (x, 1);
5687         }
5688
5689       /* Convert (A | B) & A to A.  */
5690       if (GET_CODE (op0) == IOR
5691           && (rtx_equal_p (XEXP (op0, 0), op1)
5692               || rtx_equal_p (XEXP (op0, 1), op1))
5693           && ! side_effects_p (XEXP (op0, 0))
5694           && ! side_effects_p (XEXP (op0, 1)))
5695         return op1;
5696
5697       /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5698          apply the distributive law and then the inverse distributive
5699          law to see if things simplify.  */
5700       if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5701         {
5702           rtx result = distribute_and_simplify_rtx (x, 0);
5703           if (result)
5704             return result;
5705         }
5706       if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5707         {
5708           rtx result = distribute_and_simplify_rtx (x, 1);
5709           if (result)
5710             return result;
5711         }
5712       break;
5713
5714     case IOR:
5715       /* (ior A C) is C if all bits of A that might be nonzero are on in C.  */
5716       if (GET_CODE (op1) == CONST_INT
5717           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5718           && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
5719         return op1;
5720
5721       /* Convert (A & B) | A to A.  */
5722       if (GET_CODE (op0) == AND
5723           && (rtx_equal_p (XEXP (op0, 0), op1)
5724               || rtx_equal_p (XEXP (op0, 1), op1))
5725           && ! side_effects_p (XEXP (op0, 0))
5726           && ! side_effects_p (XEXP (op0, 1)))
5727         return op1;
5728
5729       /* If we have (ior (and A B) C), apply the distributive law and then
5730          the inverse distributive law to see if things simplify.  */
5731
5732       if (GET_CODE (op0) == AND)
5733         {
5734           rtx result = distribute_and_simplify_rtx (x, 0);
5735           if (result)
5736             return result;
5737         }
5738
5739       if (GET_CODE (op1) == AND)
5740         {
5741           rtx result = distribute_and_simplify_rtx (x, 1);
5742           if (result)
5743             return result;
5744         }
5745
5746       /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5747          mode size to (rotate A CX).  */
5748
5749       if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5750            || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5751           && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5752           && GET_CODE (XEXP (op0, 1)) == CONST_INT
5753           && GET_CODE (XEXP (op1, 1)) == CONST_INT
5754           && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5755               == GET_MODE_BITSIZE (mode)))
5756         return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5757                                (GET_CODE (op0) == ASHIFT
5758                                 ? XEXP (op0, 1) : XEXP (op1, 1)));
5759
5760       /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5761          a (sign_extend (plus ...)).  If so, OP1 is a CONST_INT, and the PLUS
5762          does not affect any of the bits in OP1, it can really be done
5763          as a PLUS and we can associate.  We do this by seeing if OP1
5764          can be safely shifted left C bits.  */
5765       if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5766           && GET_CODE (XEXP (op0, 0)) == PLUS
5767           && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5768           && GET_CODE (XEXP (op0, 1)) == CONST_INT
5769           && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5770         {
5771           int count = INTVAL (XEXP (op0, 1));
5772           HOST_WIDE_INT mask = INTVAL (op1) << count;
5773
5774           if (mask >> count == INTVAL (op1)
5775               && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5776             {
5777               SUBST (XEXP (XEXP (op0, 0), 1),
5778                      GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5779               return op0;
5780             }
5781         }
5782       break;
5783
5784     case XOR:
5785       /* If we are XORing two things that have no bits in common,
5786          convert them into an IOR.  This helps to detect rotation encoded
5787          using those methods and possibly other simplifications.  */
5788
5789       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5790           && (nonzero_bits (op0, mode)
5791               & nonzero_bits (op1, mode)) == 0)
5792         return (simplify_gen_binary (IOR, mode, op0, op1));
5793
5794       /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5795          Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5796          (NOT y).  */
5797       {
5798         int num_negated = 0;
5799
5800         if (GET_CODE (op0) == NOT)
5801           num_negated++, op0 = XEXP (op0, 0);
5802         if (GET_CODE (op1) == NOT)
5803           num_negated++, op1 = XEXP (op1, 0);
5804
5805         if (num_negated == 2)
5806           {
5807             SUBST (XEXP (x, 0), op0);
5808             SUBST (XEXP (x, 1), op1);
5809           }
5810         else if (num_negated == 1)
5811           return
5812             simplify_gen_unary (NOT, mode,
5813                                 simplify_gen_binary (XOR, mode, op0, op1),
5814                                 mode);
5815       }
5816
5817       /* Convert (xor (and A B) B) to (and (not A) B).  The latter may
5818          correspond to a machine insn or result in further simplifications
5819          if B is a constant.  */
5820
5821       if (GET_CODE (op0) == AND
5822           && rtx_equal_p (XEXP (op0, 1), op1)
5823           && ! side_effects_p (op1))
5824         return simplify_gen_binary (AND, mode,
5825                                     simplify_gen_unary (NOT, mode,
5826                                                         XEXP (op0, 0), mode),
5827                                     op1);
5828
5829       else if (GET_CODE (op0) == AND
5830                && rtx_equal_p (XEXP (op0, 0), op1)
5831                && ! side_effects_p (op1))
5832         return simplify_gen_binary (AND, mode,
5833                                     simplify_gen_unary (NOT, mode,
5834                                                         XEXP (op0, 1), mode),
5835                                     op1);
5836
5837       /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5838          comparison if STORE_FLAG_VALUE is 1.  */
5839       if (STORE_FLAG_VALUE == 1
5840           && op1 == const1_rtx
5841           && COMPARISON_P (op0)
5842           && (reversed = reversed_comparison (op0, mode)))
5843         return reversed;
5844
5845       /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5846          is (lt foo (const_int 0)), so we can perform the above
5847          simplification if STORE_FLAG_VALUE is 1.  */
5848
5849       if (STORE_FLAG_VALUE == 1
5850           && op1 == const1_rtx
5851           && GET_CODE (op0) == LSHIFTRT
5852           && GET_CODE (XEXP (op0, 1)) == CONST_INT
5853           && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5854         return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx);
5855
5856       /* (xor (comparison foo bar) (const_int sign-bit))
5857          when STORE_FLAG_VALUE is the sign bit.  */
5858       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5859           && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5860               == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5861           && op1 == const_true_rtx
5862           && COMPARISON_P (op0)
5863           && (reversed = reversed_comparison (op0, mode)))
5864         return reversed;
5865
5866       break;
5867
5868     default:
5869       gcc_unreachable ();
5870     }
5871
5872   return x;
5873 }
5874 \f
5875 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5876    operations" because they can be replaced with two more basic operations.
5877    ZERO_EXTEND is also considered "compound" because it can be replaced with
5878    an AND operation, which is simpler, though only one operation.
5879
5880    The function expand_compound_operation is called with an rtx expression
5881    and will convert it to the appropriate shifts and AND operations,
5882    simplifying at each stage.
5883
5884    The function make_compound_operation is called to convert an expression
5885    consisting of shifts and ANDs into the equivalent compound expression.
5886    It is the inverse of this function, loosely speaking.  */
5887
5888 static rtx
5889 expand_compound_operation (rtx x)
5890 {
5891   unsigned HOST_WIDE_INT pos = 0, len;
5892   int unsignedp = 0;
5893   unsigned int modewidth;
5894   rtx tem;
5895
5896   switch (GET_CODE (x))
5897     {
5898     case ZERO_EXTEND:
5899       unsignedp = 1;
5900     case SIGN_EXTEND:
5901       /* We can't necessarily use a const_int for a multiword mode;
5902          it depends on implicitly extending the value.
5903          Since we don't know the right way to extend it,
5904          we can't tell whether the implicit way is right.
5905
5906          Even for a mode that is no wider than a const_int,
5907          we can't win, because we need to sign extend one of its bits through
5908          the rest of it, and we don't know which bit.  */
5909       if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5910         return x;
5911
5912       /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5913          (zero_extend:MODE FROM) or (sign_extend:MODE FROM).  It is for any MEM
5914          because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5915          reloaded. If not for that, MEM's would very rarely be safe.
5916
5917          Reject MODEs bigger than a word, because we might not be able
5918          to reference a two-register group starting with an arbitrary register
5919          (and currently gen_lowpart might crash for a SUBREG).  */
5920
5921       if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5922         return x;
5923
5924       /* Reject MODEs that aren't scalar integers because turning vector
5925          or complex modes into shifts causes problems.  */
5926
5927       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5928         return x;
5929
5930       len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5931       /* If the inner object has VOIDmode (the only way this can happen
5932          is if it is an ASM_OPERANDS), we can't do anything since we don't
5933          know how much masking to do.  */
5934       if (len == 0)
5935         return x;
5936
5937       break;
5938
5939     case ZERO_EXTRACT:
5940       unsignedp = 1;
5941
5942       /* ... fall through ...  */
5943
5944     case SIGN_EXTRACT:
5945       /* If the operand is a CLOBBER, just return it.  */
5946       if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5947         return XEXP (x, 0);
5948
5949       if (GET_CODE (XEXP (x, 1)) != CONST_INT
5950           || GET_CODE (XEXP (x, 2)) != CONST_INT
5951           || GET_MODE (XEXP (x, 0)) == VOIDmode)
5952         return x;
5953
5954       /* Reject MODEs that aren't scalar integers because turning vector
5955          or complex modes into shifts causes problems.  */
5956
5957       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5958         return x;
5959
5960       len = INTVAL (XEXP (x, 1));
5961       pos = INTVAL (XEXP (x, 2));
5962
5963       /* If this goes outside the object being extracted, replace the object
5964          with a (use (mem ...)) construct that only combine understands
5965          and is used only for this purpose.  */
5966       if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5967         SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5968
5969       if (BITS_BIG_ENDIAN)
5970         pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5971
5972       break;
5973
5974     default:
5975       return x;
5976     }
5977   /* Convert sign extension to zero extension, if we know that the high
5978      bit is not set, as this is easier to optimize.  It will be converted
5979      back to cheaper alternative in make_extraction.  */
5980   if (GET_CODE (x) == SIGN_EXTEND
5981       && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5982           && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5983                 & ~(((unsigned HOST_WIDE_INT)
5984                       GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5985                      >> 1))
5986                == 0)))
5987     {
5988       rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5989       rtx temp2 = expand_compound_operation (temp);
5990
5991       /* Make sure this is a profitable operation.  */
5992       if (rtx_cost (x, SET) > rtx_cost (temp2, SET))
5993        return temp2;
5994       else if (rtx_cost (x, SET) > rtx_cost (temp, SET))
5995        return temp;
5996       else
5997        return x;
5998     }
5999
6000   /* We can optimize some special cases of ZERO_EXTEND.  */
6001   if (GET_CODE (x) == ZERO_EXTEND)
6002     {
6003       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6004          know that the last value didn't have any inappropriate bits
6005          set.  */
6006       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6007           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6008           && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6009           && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6010               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6011         return XEXP (XEXP (x, 0), 0);
6012
6013       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
6014       if (GET_CODE (XEXP (x, 0)) == SUBREG
6015           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6016           && subreg_lowpart_p (XEXP (x, 0))
6017           && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6018           && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6019               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6020         return SUBREG_REG (XEXP (x, 0));
6021
6022       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6023          is a comparison and STORE_FLAG_VALUE permits.  This is like
6024          the first case, but it works even when GET_MODE (x) is larger
6025          than HOST_WIDE_INT.  */
6026       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6027           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6028           && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6029           && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6030               <= HOST_BITS_PER_WIDE_INT)
6031           && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6032               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6033         return XEXP (XEXP (x, 0), 0);
6034
6035       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
6036       if (GET_CODE (XEXP (x, 0)) == SUBREG
6037           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6038           && subreg_lowpart_p (XEXP (x, 0))
6039           && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6040           && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6041               <= HOST_BITS_PER_WIDE_INT)
6042           && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6043               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6044         return SUBREG_REG (XEXP (x, 0));
6045
6046     }
6047
6048   /* If we reach here, we want to return a pair of shifts.  The inner
6049      shift is a left shift of BITSIZE - POS - LEN bits.  The outer
6050      shift is a right shift of BITSIZE - LEN bits.  It is arithmetic or
6051      logical depending on the value of UNSIGNEDP.
6052
6053      If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6054      converted into an AND of a shift.
6055
6056      We must check for the case where the left shift would have a negative
6057      count.  This can happen in a case like (x >> 31) & 255 on machines
6058      that can't shift by a constant.  On those machines, we would first
6059      combine the shift with the AND to produce a variable-position
6060      extraction.  Then the constant of 31 would be substituted in to produce
6061      a such a position.  */
6062
6063   modewidth = GET_MODE_BITSIZE (GET_MODE (x));
6064   if (modewidth + len >= pos)
6065     tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6066                                 GET_MODE (x),
6067                                 simplify_shift_const (NULL_RTX, ASHIFT,
6068                                                       GET_MODE (x),
6069                                                       XEXP (x, 0),
6070                                                       modewidth - pos - len),
6071                                 modewidth - len);
6072
6073   else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6074     tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6075                                   simplify_shift_const (NULL_RTX, LSHIFTRT,
6076                                                         GET_MODE (x),
6077                                                         XEXP (x, 0), pos),
6078                                   ((HOST_WIDE_INT) 1 << len) - 1);
6079   else
6080     /* Any other cases we can't handle.  */
6081     return x;
6082
6083   /* If we couldn't do this for some reason, return the original
6084      expression.  */
6085   if (GET_CODE (tem) == CLOBBER)
6086     return x;
6087
6088   return tem;
6089 }
6090 \f
6091 /* X is a SET which contains an assignment of one object into
6092    a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6093    or certain SUBREGS). If possible, convert it into a series of
6094    logical operations.
6095
6096    We half-heartedly support variable positions, but do not at all
6097    support variable lengths.  */
6098
6099 static rtx
6100 expand_field_assignment (rtx x)
6101 {
6102   rtx inner;
6103   rtx pos;                      /* Always counts from low bit.  */
6104   int len;
6105   rtx mask, cleared, masked;
6106   enum machine_mode compute_mode;
6107
6108   /* Loop until we find something we can't simplify.  */
6109   while (1)
6110     {
6111       if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6112           && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6113         {
6114           inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6115           len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
6116           pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6117         }
6118       else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6119                && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
6120         {
6121           inner = XEXP (SET_DEST (x), 0);
6122           len = INTVAL (XEXP (SET_DEST (x), 1));
6123           pos = XEXP (SET_DEST (x), 2);
6124
6125           /* If the position is constant and spans the width of INNER,
6126              surround INNER  with a USE to indicate this.  */
6127           if (GET_CODE (pos) == CONST_INT
6128               && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
6129             inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
6130
6131           if (BITS_BIG_ENDIAN)
6132             {
6133               if (GET_CODE (pos) == CONST_INT)
6134                 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
6135                                - INTVAL (pos));
6136               else if (GET_CODE (pos) == MINUS
6137                        && GET_CODE (XEXP (pos, 1)) == CONST_INT
6138                        && (INTVAL (XEXP (pos, 1))
6139                            == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
6140                 /* If position is ADJUST - X, new position is X.  */
6141                 pos = XEXP (pos, 0);
6142               else
6143                 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6144                                            GEN_INT (GET_MODE_BITSIZE (
6145                                                     GET_MODE (inner))
6146                                                     - len),
6147                                            pos);
6148             }
6149         }
6150
6151       /* A SUBREG between two modes that occupy the same numbers of words
6152          can be done by moving the SUBREG to the source.  */
6153       else if (GET_CODE (SET_DEST (x)) == SUBREG
6154                /* We need SUBREGs to compute nonzero_bits properly.  */
6155                && nonzero_sign_valid
6156                && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6157                      + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6158                    == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6159                         + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6160         {
6161           x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6162                            gen_lowpart
6163                            (GET_MODE (SUBREG_REG (SET_DEST (x))),
6164                             SET_SRC (x)));
6165           continue;
6166         }
6167       else
6168         break;
6169
6170       while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6171         inner = SUBREG_REG (inner);
6172
6173       compute_mode = GET_MODE (inner);
6174
6175       /* Don't attempt bitwise arithmetic on non scalar integer modes.  */
6176       if (! SCALAR_INT_MODE_P (compute_mode))
6177         {
6178           enum machine_mode imode;
6179
6180           /* Don't do anything for vector or complex integral types.  */
6181           if (! FLOAT_MODE_P (compute_mode))
6182             break;
6183
6184           /* Try to find an integral mode to pun with.  */
6185           imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6186           if (imode == BLKmode)
6187             break;
6188
6189           compute_mode = imode;
6190           inner = gen_lowpart (imode, inner);
6191         }
6192
6193       /* Compute a mask of LEN bits, if we can do this on the host machine.  */
6194       if (len >= HOST_BITS_PER_WIDE_INT)
6195         break;
6196
6197       /* Now compute the equivalent expression.  Make a copy of INNER
6198          for the SET_DEST in case it is a MEM into which we will substitute;
6199          we don't want shared RTL in that case.  */
6200       mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
6201       cleared = simplify_gen_binary (AND, compute_mode,
6202                                      simplify_gen_unary (NOT, compute_mode,
6203                                        simplify_gen_binary (ASHIFT,
6204                                                             compute_mode,
6205                                                             mask, pos),
6206                                        compute_mode),
6207                                      inner);
6208       masked = simplify_gen_binary (ASHIFT, compute_mode,
6209                                     simplify_gen_binary (
6210                                       AND, compute_mode,
6211                                       gen_lowpart (compute_mode, SET_SRC (x)),
6212                                       mask),
6213                                     pos);
6214
6215       x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6216                        simplify_gen_binary (IOR, compute_mode,
6217                                             cleared, masked));
6218     }
6219
6220   return x;
6221 }
6222 \f
6223 /* Return an RTX for a reference to LEN bits of INNER.  If POS_RTX is nonzero,
6224    it is an RTX that represents a variable starting position; otherwise,
6225    POS is the (constant) starting bit position (counted from the LSB).
6226
6227    INNER may be a USE.  This will occur when we started with a bitfield
6228    that went outside the boundary of the object in memory, which is
6229    allowed on most machines.  To isolate this case, we produce a USE
6230    whose mode is wide enough and surround the MEM with it.  The only
6231    code that understands the USE is this routine.  If it is not removed,
6232    it will cause the resulting insn not to match.
6233
6234    UNSIGNEDP is nonzero for an unsigned reference and zero for a
6235    signed reference.
6236
6237    IN_DEST is nonzero if this is a reference in the destination of a
6238    SET.  This is used when a ZERO_ or SIGN_EXTRACT isn't needed.  If nonzero,
6239    a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6240    be used.
6241
6242    IN_COMPARE is nonzero if we are in a COMPARE.  This means that a
6243    ZERO_EXTRACT should be built even for bits starting at bit 0.
6244
6245    MODE is the desired mode of the result (if IN_DEST == 0).
6246
6247    The result is an RTX for the extraction or NULL_RTX if the target
6248    can't handle it.  */
6249
6250 static rtx
6251 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6252                  rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6253                  int in_dest, int in_compare)
6254 {
6255   /* This mode describes the size of the storage area
6256      to fetch the overall value from.  Within that, we
6257      ignore the POS lowest bits, etc.  */
6258   enum machine_mode is_mode = GET_MODE (inner);
6259   enum machine_mode inner_mode;
6260   enum machine_mode wanted_inner_mode = byte_mode;
6261   enum machine_mode wanted_inner_reg_mode = word_mode;
6262   enum machine_mode pos_mode = word_mode;
6263   enum machine_mode extraction_mode = word_mode;
6264   enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6265   int spans_byte = 0;
6266   rtx new = 0;
6267   rtx orig_pos_rtx = pos_rtx;
6268   HOST_WIDE_INT orig_pos;
6269
6270   /* Get some information about INNER and get the innermost object.  */
6271   if (GET_CODE (inner) == USE)
6272     /* (use:SI (mem:QI foo)) stands for (mem:SI foo).  */
6273     /* We don't need to adjust the position because we set up the USE
6274        to pretend that it was a full-word object.  */
6275     spans_byte = 1, inner = XEXP (inner, 0);
6276   else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6277     {
6278       /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6279          consider just the QI as the memory to extract from.
6280          The subreg adds or removes high bits; its mode is
6281          irrelevant to the meaning of this extraction,
6282          since POS and LEN count from the lsb.  */
6283       if (MEM_P (SUBREG_REG (inner)))
6284         is_mode = GET_MODE (SUBREG_REG (inner));
6285       inner = SUBREG_REG (inner);
6286     }
6287   else if (GET_CODE (inner) == ASHIFT
6288            && GET_CODE (XEXP (inner, 1)) == CONST_INT
6289            && pos_rtx == 0 && pos == 0
6290            && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6291     {
6292       /* We're extracting the least significant bits of an rtx
6293          (ashift X (const_int C)), where LEN > C.  Extract the
6294          least significant (LEN - C) bits of X, giving an rtx
6295          whose mode is MODE, then shift it left C times.  */
6296       new = make_extraction (mode, XEXP (inner, 0),
6297                              0, 0, len - INTVAL (XEXP (inner, 1)),
6298                              unsignedp, in_dest, in_compare);
6299       if (new != 0)
6300         return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
6301     }
6302
6303   inner_mode = GET_MODE (inner);
6304
6305   if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
6306     pos = INTVAL (pos_rtx), pos_rtx = 0;
6307
6308   /* See if this can be done without an extraction.  We never can if the
6309      width of the field is not the same as that of some integer mode. For
6310      registers, we can only avoid the extraction if the position is at the
6311      low-order bit and this is either not in the destination or we have the
6312      appropriate STRICT_LOW_PART operation available.
6313
6314      For MEM, we can avoid an extract if the field starts on an appropriate
6315      boundary and we can change the mode of the memory reference.  However,
6316      we cannot directly access the MEM if we have a USE and the underlying
6317      MEM is not TMODE.  This combination means that MEM was being used in a
6318      context where bits outside its mode were being referenced; that is only
6319      valid in bit-field insns.  */
6320
6321   if (tmode != BLKmode
6322       && ! (spans_byte && inner_mode != tmode)
6323       && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6324            && !MEM_P (inner)
6325            && (! in_dest
6326                || (REG_P (inner)
6327                    && have_insn_for (STRICT_LOW_PART, tmode))))
6328           || (MEM_P (inner) && pos_rtx == 0
6329               && (pos
6330                   % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6331                      : BITS_PER_UNIT)) == 0
6332               /* We can't do this if we are widening INNER_MODE (it
6333                  may not be aligned, for one thing).  */
6334               && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6335               && (inner_mode == tmode
6336                   || (! mode_dependent_address_p (XEXP (inner, 0))
6337                       && ! MEM_VOLATILE_P (inner))))))
6338     {
6339       /* If INNER is a MEM, make a new MEM that encompasses just the desired
6340          field.  If the original and current mode are the same, we need not
6341          adjust the offset.  Otherwise, we do if bytes big endian.
6342
6343          If INNER is not a MEM, get a piece consisting of just the field
6344          of interest (in this case POS % BITS_PER_WORD must be 0).  */
6345
6346       if (MEM_P (inner))
6347         {
6348           HOST_WIDE_INT offset;
6349
6350           /* POS counts from lsb, but make OFFSET count in memory order.  */
6351           if (BYTES_BIG_ENDIAN)
6352             offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6353           else
6354             offset = pos / BITS_PER_UNIT;
6355
6356           new = adjust_address_nv (inner, tmode, offset);
6357         }
6358       else if (REG_P (inner))
6359         {
6360           if (tmode != inner_mode)
6361             {
6362               /* We can't call gen_lowpart in a DEST since we
6363                  always want a SUBREG (see below) and it would sometimes
6364                  return a new hard register.  */
6365               if (pos || in_dest)
6366                 {
6367                   HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6368
6369                   if (WORDS_BIG_ENDIAN
6370                       && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6371                     final_word = ((GET_MODE_SIZE (inner_mode)
6372                                    - GET_MODE_SIZE (tmode))
6373                                   / UNITS_PER_WORD) - final_word;
6374
6375                   final_word *= UNITS_PER_WORD;
6376                   if (BYTES_BIG_ENDIAN &&
6377                       GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6378                     final_word += (GET_MODE_SIZE (inner_mode)
6379                                    - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6380
6381                   /* Avoid creating invalid subregs, for example when
6382                      simplifying (x>>32)&255.  */
6383                   if (!validate_subreg (tmode, inner_mode, inner, final_word))
6384                     return NULL_RTX;
6385
6386                   new = gen_rtx_SUBREG (tmode, inner, final_word);
6387                 }
6388               else
6389                 new = gen_lowpart (tmode, inner);
6390             }
6391           else
6392             new = inner;
6393         }
6394       else
6395         new = force_to_mode (inner, tmode,
6396                              len >= HOST_BITS_PER_WIDE_INT
6397                              ? ~(unsigned HOST_WIDE_INT) 0
6398                              : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6399                              NULL_RTX, 0);
6400
6401       /* If this extraction is going into the destination of a SET,
6402          make a STRICT_LOW_PART unless we made a MEM.  */
6403
6404       if (in_dest)
6405         return (MEM_P (new) ? new
6406                 : (GET_CODE (new) != SUBREG
6407                    ? gen_rtx_CLOBBER (tmode, const0_rtx)
6408                    : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6409
6410       if (mode == tmode)
6411         return new;
6412
6413       if (GET_CODE (new) == CONST_INT)
6414         return gen_int_mode (INTVAL (new), mode);
6415
6416       /* If we know that no extraneous bits are set, and that the high
6417          bit is not set, convert the extraction to the cheaper of
6418          sign and zero extension, that are equivalent in these cases.  */
6419       if (flag_expensive_optimizations
6420           && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6421               && ((nonzero_bits (new, tmode)
6422                    & ~(((unsigned HOST_WIDE_INT)
6423                         GET_MODE_MASK (tmode))
6424                        >> 1))
6425                   == 0)))
6426         {
6427           rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6428           rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6429
6430           /* Prefer ZERO_EXTENSION, since it gives more information to
6431              backends.  */
6432           if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6433             return temp;
6434           return temp1;
6435         }
6436
6437       /* Otherwise, sign- or zero-extend unless we already are in the
6438          proper mode.  */
6439
6440       return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6441                              mode, new));
6442     }
6443
6444   /* Unless this is a COMPARE or we have a funny memory reference,
6445      don't do anything with zero-extending field extracts starting at
6446      the low-order bit since they are simple AND operations.  */
6447   if (pos_rtx == 0 && pos == 0 && ! in_dest
6448       && ! in_compare && ! spans_byte && unsignedp)
6449     return 0;
6450
6451   /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6452      we would be spanning bytes or if the position is not a constant and the
6453      length is not 1.  In all other cases, we would only be going outside
6454      our object in cases when an original shift would have been
6455      undefined.  */
6456   if (! spans_byte && MEM_P (inner)
6457       && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6458           || (pos_rtx != 0 && len != 1)))
6459     return 0;
6460
6461   /* Get the mode to use should INNER not be a MEM, the mode for the position,
6462      and the mode for the result.  */
6463   if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6464     {
6465       wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6466       pos_mode = mode_for_extraction (EP_insv, 2);
6467       extraction_mode = mode_for_extraction (EP_insv, 3);
6468     }
6469
6470   if (! in_dest && unsignedp
6471       && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6472     {
6473       wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6474       pos_mode = mode_for_extraction (EP_extzv, 3);
6475       extraction_mode = mode_for_extraction (EP_extzv, 0);
6476     }
6477
6478   if (! in_dest && ! unsignedp
6479       && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6480     {
6481       wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6482       pos_mode = mode_for_extraction (EP_extv, 3);
6483       extraction_mode = mode_for_extraction (EP_extv, 0);
6484     }
6485
6486   /* Never narrow an object, since that might not be safe.  */
6487
6488   if (mode != VOIDmode
6489       && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6490     extraction_mode = mode;
6491
6492   if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6493       && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6494     pos_mode = GET_MODE (pos_rtx);
6495
6496   /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6497      if we have to change the mode of memory and cannot, the desired mode is
6498      EXTRACTION_MODE.  */
6499   if (!MEM_P (inner))
6500     wanted_inner_mode = wanted_inner_reg_mode;
6501   else if (inner_mode != wanted_inner_mode
6502            && (mode_dependent_address_p (XEXP (inner, 0))
6503                || MEM_VOLATILE_P (inner)))
6504     wanted_inner_mode = extraction_mode;
6505
6506   orig_pos = pos;
6507
6508   if (BITS_BIG_ENDIAN)
6509     {
6510       /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6511          BITS_BIG_ENDIAN style.  If position is constant, compute new
6512          position.  Otherwise, build subtraction.
6513          Note that POS is relative to the mode of the original argument.
6514          If it's a MEM we need to recompute POS relative to that.
6515          However, if we're extracting from (or inserting into) a register,
6516          we want to recompute POS relative to wanted_inner_mode.  */
6517       int width = (MEM_P (inner)
6518                    ? GET_MODE_BITSIZE (is_mode)
6519                    : GET_MODE_BITSIZE (wanted_inner_mode));
6520
6521       if (pos_rtx == 0)
6522         pos = width - len - pos;
6523       else
6524         pos_rtx
6525           = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6526       /* POS may be less than 0 now, but we check for that below.
6527          Note that it can only be less than 0 if !MEM_P (inner).  */
6528     }
6529
6530   /* If INNER has a wider mode, make it smaller.  If this is a constant
6531      extract, try to adjust the byte to point to the byte containing
6532      the value.  */
6533   if (wanted_inner_mode != VOIDmode
6534       && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6535       && ((MEM_P (inner)
6536            && (inner_mode == wanted_inner_mode
6537                || (! mode_dependent_address_p (XEXP (inner, 0))
6538                    && ! MEM_VOLATILE_P (inner))))))
6539     {
6540       int offset = 0;
6541
6542       /* The computations below will be correct if the machine is big
6543          endian in both bits and bytes or little endian in bits and bytes.
6544          If it is mixed, we must adjust.  */
6545
6546       /* If bytes are big endian and we had a paradoxical SUBREG, we must
6547          adjust OFFSET to compensate.  */
6548       if (BYTES_BIG_ENDIAN
6549           && ! spans_byte
6550           && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6551         offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6552
6553       /* If this is a constant position, we can move to the desired byte.
6554          Be careful not to go beyond the original object and maintain the
6555          natural alignment of the memory.  */
6556       if (pos_rtx == 0)
6557         {
6558           enum machine_mode bfmode = smallest_mode_for_size (len, MODE_INT);
6559           offset += (pos / GET_MODE_BITSIZE (bfmode)) * GET_MODE_SIZE (bfmode);
6560           pos %= GET_MODE_BITSIZE (bfmode);
6561         }
6562
6563       if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6564           && ! spans_byte
6565           && is_mode != wanted_inner_mode)
6566         offset = (GET_MODE_SIZE (is_mode)
6567                   - GET_MODE_SIZE (wanted_inner_mode) - offset);
6568
6569       if (offset != 0 || inner_mode != wanted_inner_mode)
6570         inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6571     }
6572
6573   /* If INNER is not memory, we can always get it into the proper mode.  If we
6574      are changing its mode, POS must be a constant and smaller than the size
6575      of the new mode.  */
6576   else if (!MEM_P (inner))
6577     {
6578       if (GET_MODE (inner) != wanted_inner_mode
6579           && (pos_rtx != 0
6580               || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6581         return 0;
6582
6583       if (orig_pos < 0)
6584         return 0;
6585
6586       inner = force_to_mode (inner, wanted_inner_mode,
6587                              pos_rtx
6588                              || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6589                              ? ~(unsigned HOST_WIDE_INT) 0
6590                              : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6591                                 << orig_pos),
6592                              NULL_RTX, 0);
6593     }
6594
6595   /* Adjust mode of POS_RTX, if needed.  If we want a wider mode, we
6596      have to zero extend.  Otherwise, we can just use a SUBREG.  */
6597   if (pos_rtx != 0
6598       && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6599     {
6600       rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6601
6602       /* If we know that no extraneous bits are set, and that the high
6603          bit is not set, convert extraction to cheaper one - either
6604          SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6605          cases.  */
6606       if (flag_expensive_optimizations
6607           && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6608               && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6609                    & ~(((unsigned HOST_WIDE_INT)
6610                         GET_MODE_MASK (GET_MODE (pos_rtx)))
6611                        >> 1))
6612                   == 0)))
6613         {
6614           rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6615
6616           /* Prefer ZERO_EXTENSION, since it gives more information to
6617              backends.  */
6618           if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6619             temp = temp1;
6620         }
6621       pos_rtx = temp;
6622     }
6623   else if (pos_rtx != 0
6624            && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6625     pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6626
6627   /* Make POS_RTX unless we already have it and it is correct.  If we don't
6628      have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6629      be a CONST_INT.  */
6630   if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6631     pos_rtx = orig_pos_rtx;
6632
6633   else if (pos_rtx == 0)
6634     pos_rtx = GEN_INT (pos);
6635
6636   /* Make the required operation.  See if we can use existing rtx.  */
6637   new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6638                          extraction_mode, inner, GEN_INT (len), pos_rtx);
6639   if (! in_dest)
6640     new = gen_lowpart (mode, new);
6641
6642   return new;
6643 }
6644 \f
6645 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6646    with any other operations in X.  Return X without that shift if so.  */
6647
6648 static rtx
6649 extract_left_shift (rtx x, int count)
6650 {
6651   enum rtx_code code = GET_CODE (x);
6652   enum machine_mode mode = GET_MODE (x);
6653   rtx tem;
6654
6655   switch (code)
6656     {
6657     case ASHIFT:
6658       /* This is the shift itself.  If it is wide enough, we will return
6659          either the value being shifted if the shift count is equal to
6660          COUNT or a shift for the difference.  */
6661       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6662           && INTVAL (XEXP (x, 1)) >= count)
6663         return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6664                                      INTVAL (XEXP (x, 1)) - count);
6665       break;
6666
6667     case NEG:  case NOT:
6668       if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6669         return simplify_gen_unary (code, mode, tem, mode);
6670
6671       break;
6672
6673     case PLUS:  case IOR:  case XOR:  case AND:
6674       /* If we can safely shift this constant and we find the inner shift,
6675          make a new operation.  */
6676       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6677           && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6678           && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6679         return simplify_gen_binary (code, mode, tem,
6680                                     GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6681
6682       break;
6683
6684     default:
6685       break;
6686     }
6687
6688   return 0;
6689 }
6690 \f
6691 /* Look at the expression rooted at X.  Look for expressions
6692    equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6693    Form these expressions.
6694
6695    Return the new rtx, usually just X.
6696
6697    Also, for machines like the VAX that don't have logical shift insns,
6698    try to convert logical to arithmetic shift operations in cases where
6699    they are equivalent.  This undoes the canonicalizations to logical
6700    shifts done elsewhere.
6701
6702    We try, as much as possible, to re-use rtl expressions to save memory.
6703
6704    IN_CODE says what kind of expression we are processing.  Normally, it is
6705    SET.  In a memory address (inside a MEM, PLUS or minus, the latter two
6706    being kludges), it is MEM.  When processing the arguments of a comparison
6707    or a COMPARE against zero, it is COMPARE.  */
6708
6709 static rtx
6710 make_compound_operation (rtx x, enum rtx_code in_code)
6711 {
6712   enum rtx_code code = GET_CODE (x);
6713   enum machine_mode mode = GET_MODE (x);
6714   int mode_width = GET_MODE_BITSIZE (mode);
6715   rtx rhs, lhs;
6716   enum rtx_code next_code;
6717   int i;
6718   rtx new = 0;
6719   rtx tem;
6720   const char *fmt;
6721
6722   /* Select the code to be used in recursive calls.  Once we are inside an
6723      address, we stay there.  If we have a comparison, set to COMPARE,
6724      but once inside, go back to our default of SET.  */
6725
6726   next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6727                : ((code == COMPARE || COMPARISON_P (x))
6728                   && XEXP (x, 1) == const0_rtx) ? COMPARE
6729                : in_code == COMPARE ? SET : in_code);
6730
6731   /* Process depending on the code of this operation.  If NEW is set
6732      nonzero, it will be returned.  */
6733
6734   switch (code)
6735     {
6736     case ASHIFT:
6737       /* Convert shifts by constants into multiplications if inside
6738          an address.  */
6739       if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6740           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6741           && INTVAL (XEXP (x, 1)) >= 0)
6742         {
6743           new = make_compound_operation (XEXP (x, 0), next_code);
6744           new = gen_rtx_MULT (mode, new,
6745                               GEN_INT ((HOST_WIDE_INT) 1
6746                                        << INTVAL (XEXP (x, 1))));
6747         }
6748       break;
6749
6750     case AND:
6751       /* If the second operand is not a constant, we can't do anything
6752          with it.  */
6753       if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6754         break;
6755
6756       /* If the constant is a power of two minus one and the first operand
6757          is a logical right shift, make an extraction.  */
6758       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6759           && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6760         {
6761           new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6762           new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6763                                  0, in_code == COMPARE);
6764         }
6765
6766       /* Same as previous, but for (subreg (lshiftrt ...)) in first op.  */
6767       else if (GET_CODE (XEXP (x, 0)) == SUBREG
6768                && subreg_lowpart_p (XEXP (x, 0))
6769                && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6770                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6771         {
6772           new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6773                                          next_code);
6774           new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6775                                  XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6776                                  0, in_code == COMPARE);
6777         }
6778       /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)).  */
6779       else if ((GET_CODE (XEXP (x, 0)) == XOR
6780                 || GET_CODE (XEXP (x, 0)) == IOR)
6781                && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6782                && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6783                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6784         {
6785           /* Apply the distributive law, and then try to make extractions.  */
6786           new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6787                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6788                                              XEXP (x, 1)),
6789                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6790                                              XEXP (x, 1)));
6791           new = make_compound_operation (new, in_code);
6792         }
6793
6794       /* If we are have (and (rotate X C) M) and C is larger than the number
6795          of bits in M, this is an extraction.  */
6796
6797       else if (GET_CODE (XEXP (x, 0)) == ROTATE
6798                && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6799                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6800                && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6801         {
6802           new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6803           new = make_extraction (mode, new,
6804                                  (GET_MODE_BITSIZE (mode)
6805                                   - INTVAL (XEXP (XEXP (x, 0), 1))),
6806                                  NULL_RTX, i, 1, 0, in_code == COMPARE);
6807         }
6808
6809       /* On machines without logical shifts, if the operand of the AND is
6810          a logical shift and our mask turns off all the propagated sign
6811          bits, we can replace the logical shift with an arithmetic shift.  */
6812       else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6813                && !have_insn_for (LSHIFTRT, mode)
6814                && have_insn_for (ASHIFTRT, mode)
6815                && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6816                && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6817                && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6818                && mode_width <= HOST_BITS_PER_WIDE_INT)
6819         {
6820           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6821
6822           mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6823           if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6824             SUBST (XEXP (x, 0),
6825                    gen_rtx_ASHIFTRT (mode,
6826                                      make_compound_operation
6827                                      (XEXP (XEXP (x, 0), 0), next_code),
6828                                      XEXP (XEXP (x, 0), 1)));
6829         }
6830
6831       /* If the constant is one less than a power of two, this might be
6832          representable by an extraction even if no shift is present.
6833          If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6834          we are in a COMPARE.  */
6835       else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6836         new = make_extraction (mode,
6837                                make_compound_operation (XEXP (x, 0),
6838                                                         next_code),
6839                                0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6840
6841       /* If we are in a comparison and this is an AND with a power of two,
6842          convert this into the appropriate bit extract.  */
6843       else if (in_code == COMPARE
6844                && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6845         new = make_extraction (mode,
6846                                make_compound_operation (XEXP (x, 0),
6847                                                         next_code),
6848                                i, NULL_RTX, 1, 1, 0, 1);
6849
6850       break;
6851
6852     case LSHIFTRT:
6853       /* If the sign bit is known to be zero, replace this with an
6854          arithmetic shift.  */
6855       if (have_insn_for (ASHIFTRT, mode)
6856           && ! have_insn_for (LSHIFTRT, mode)
6857           && mode_width <= HOST_BITS_PER_WIDE_INT
6858           && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6859         {
6860           new = gen_rtx_ASHIFTRT (mode,
6861                                   make_compound_operation (XEXP (x, 0),
6862                                                            next_code),
6863                                   XEXP (x, 1));
6864           break;
6865         }
6866
6867       /* ... fall through ...  */
6868
6869     case ASHIFTRT:
6870       lhs = XEXP (x, 0);
6871       rhs = XEXP (x, 1);
6872
6873       /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6874          this is a SIGN_EXTRACT.  */
6875       if (GET_CODE (rhs) == CONST_INT
6876           && GET_CODE (lhs) == ASHIFT
6877           && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6878           && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6879         {
6880           new = make_compound_operation (XEXP (lhs, 0), next_code);
6881           new = make_extraction (mode, new,
6882                                  INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6883                                  NULL_RTX, mode_width - INTVAL (rhs),
6884                                  code == LSHIFTRT, 0, in_code == COMPARE);
6885           break;
6886         }
6887
6888       /* See if we have operations between an ASHIFTRT and an ASHIFT.
6889          If so, try to merge the shifts into a SIGN_EXTEND.  We could
6890          also do this for some cases of SIGN_EXTRACT, but it doesn't
6891          seem worth the effort; the case checked for occurs on Alpha.  */
6892
6893       if (!OBJECT_P (lhs)
6894           && ! (GET_CODE (lhs) == SUBREG
6895                 && (OBJECT_P (SUBREG_REG (lhs))))
6896           && GET_CODE (rhs) == CONST_INT
6897           && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6898           && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6899         new = make_extraction (mode, make_compound_operation (new, next_code),
6900                                0, NULL_RTX, mode_width - INTVAL (rhs),
6901                                code == LSHIFTRT, 0, in_code == COMPARE);
6902
6903       break;
6904
6905     case SUBREG:
6906       /* Call ourselves recursively on the inner expression.  If we are
6907          narrowing the object and it has a different RTL code from
6908          what it originally did, do this SUBREG as a force_to_mode.  */
6909
6910       tem = make_compound_operation (SUBREG_REG (x), in_code);
6911
6912       {
6913         rtx simplified;
6914         simplified = simplify_subreg (GET_MODE (x), tem, GET_MODE (tem),
6915                                       SUBREG_BYTE (x));
6916
6917         if (simplified)
6918           tem = simplified;
6919
6920         if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6921             && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6922             && subreg_lowpart_p (x))
6923           {
6924             rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6925                                        NULL_RTX, 0);
6926
6927             /* If we have something other than a SUBREG, we might have
6928                done an expansion, so rerun ourselves.  */
6929             if (GET_CODE (newer) != SUBREG)
6930               newer = make_compound_operation (newer, in_code);
6931
6932             return newer;
6933           }
6934
6935         if (simplified)
6936           return tem;
6937       }
6938       break;
6939
6940     default:
6941       break;
6942     }
6943
6944   if (new)
6945     {
6946       x = gen_lowpart (mode, new);
6947       code = GET_CODE (x);
6948     }
6949
6950   /* Now recursively process each operand of this operation.  */
6951   fmt = GET_RTX_FORMAT (code);
6952   for (i = 0; i < GET_RTX_LENGTH (code); i++)
6953     if (fmt[i] == 'e')
6954       {
6955         new = make_compound_operation (XEXP (x, i), next_code);
6956         SUBST (XEXP (x, i), new);
6957       }
6958
6959   return x;
6960 }
6961 \f
6962 /* Given M see if it is a value that would select a field of bits
6963    within an item, but not the entire word.  Return -1 if not.
6964    Otherwise, return the starting position of the field, where 0 is the
6965    low-order bit.
6966
6967    *PLEN is set to the length of the field.  */
6968
6969 static int
6970 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
6971 {
6972   /* Get the bit number of the first 1 bit from the right, -1 if none.  */
6973   int pos = exact_log2 (m & -m);
6974   int len = 0;
6975
6976   if (pos >= 0)
6977     /* Now shift off the low-order zero bits and see if we have a
6978        power of two minus 1.  */
6979     len = exact_log2 ((m >> pos) + 1);
6980
6981   if (len <= 0)
6982     pos = -1;
6983
6984   *plen = len;
6985   return pos;
6986 }
6987 \f
6988 /* See if X can be simplified knowing that we will only refer to it in
6989    MODE and will only refer to those bits that are nonzero in MASK.
6990    If other bits are being computed or if masking operations are done
6991    that select a superset of the bits in MASK, they can sometimes be
6992    ignored.
6993
6994    Return a possibly simplified expression, but always convert X to
6995    MODE.  If X is a CONST_INT, AND the CONST_INT with MASK.
6996
6997    Also, if REG is nonzero and X is a register equal in value to REG,
6998    replace X with REG.
6999
7000    If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7001    are all off in X.  This is used when X will be complemented, by either
7002    NOT, NEG, or XOR.  */
7003
7004 static rtx
7005 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
7006                rtx reg, int just_select)
7007 {
7008   enum rtx_code code = GET_CODE (x);
7009   int next_select = just_select || code == XOR || code == NOT || code == NEG;
7010   enum machine_mode op_mode;
7011   unsigned HOST_WIDE_INT fuller_mask, nonzero;
7012   rtx op0, op1, temp;
7013
7014   /* If this is a CALL or ASM_OPERANDS, don't do anything.  Some of the
7015      code below will do the wrong thing since the mode of such an
7016      expression is VOIDmode.
7017
7018      Also do nothing if X is a CLOBBER; this can happen if X was
7019      the return value from a call to gen_lowpart.  */
7020   if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
7021     return x;
7022
7023   /* We want to perform the operation is its present mode unless we know
7024      that the operation is valid in MODE, in which case we do the operation
7025      in MODE.  */
7026   op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
7027               && have_insn_for (code, mode))
7028              ? mode : GET_MODE (x));
7029
7030   /* It is not valid to do a right-shift in a narrower mode
7031      than the one it came in with.  */
7032   if ((code == LSHIFTRT || code == ASHIFTRT)
7033       && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
7034     op_mode = GET_MODE (x);
7035
7036   /* Truncate MASK to fit OP_MODE.  */
7037   if (op_mode)
7038     mask &= GET_MODE_MASK (op_mode);
7039
7040   /* When we have an arithmetic operation, or a shift whose count we
7041      do not know, we need to assume that all bits up to the highest-order
7042      bit in MASK will be needed.  This is how we form such a mask.  */
7043   if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
7044     fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
7045   else
7046     fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
7047                    - 1);
7048
7049   /* Determine what bits of X are guaranteed to be (non)zero.  */
7050   nonzero = nonzero_bits (x, mode);
7051
7052   /* If none of the bits in X are needed, return a zero.  */
7053   if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
7054     x = const0_rtx;
7055
7056   /* If X is a CONST_INT, return a new one.  Do this here since the
7057      test below will fail.  */
7058   if (GET_CODE (x) == CONST_INT)
7059     {
7060       if (SCALAR_INT_MODE_P (mode))
7061         return gen_int_mode (INTVAL (x) & mask, mode);
7062       else
7063         {
7064           x = GEN_INT (INTVAL (x) & mask);
7065           return gen_lowpart_common (mode, x);
7066         }
7067     }
7068
7069   /* If X is narrower than MODE and we want all the bits in X's mode, just
7070      get X in the proper mode.  */
7071   if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
7072       && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
7073     return gen_lowpart (mode, x);
7074
7075   switch (code)
7076     {
7077     case CLOBBER:
7078       /* If X is a (clobber (const_int)), return it since we know we are
7079          generating something that won't match.  */
7080       return x;
7081
7082     case USE:
7083       /* X is a (use (mem ..)) that was made from a bit-field extraction that
7084          spanned the boundary of the MEM.  If we are now masking so it is
7085          within that boundary, we don't need the USE any more.  */
7086       if (! BITS_BIG_ENDIAN
7087           && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
7088         return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7089       break;
7090
7091     case SIGN_EXTEND:
7092     case ZERO_EXTEND:
7093     case ZERO_EXTRACT:
7094     case SIGN_EXTRACT:
7095       x = expand_compound_operation (x);
7096       if (GET_CODE (x) != code)
7097         return force_to_mode (x, mode, mask, reg, next_select);
7098       break;
7099
7100     case REG:
7101       if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
7102                        || rtx_equal_p (reg, get_last_value (x))))
7103         x = reg;
7104       break;
7105
7106     case SUBREG:
7107       if (subreg_lowpart_p (x)
7108           /* We can ignore the effect of this SUBREG if it narrows the mode or
7109              if the constant masks to zero all the bits the mode doesn't
7110              have.  */
7111           && ((GET_MODE_SIZE (GET_MODE (x))
7112                < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7113               || (0 == (mask
7114                         & GET_MODE_MASK (GET_MODE (x))
7115                         & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
7116         return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
7117       break;
7118
7119     case AND:
7120       /* If this is an AND with a constant, convert it into an AND
7121          whose constant is the AND of that constant with MASK.  If it
7122          remains an AND of MASK, delete it since it is redundant.  */
7123
7124       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
7125         {
7126           x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
7127                                       mask & INTVAL (XEXP (x, 1)));
7128
7129           /* If X is still an AND, see if it is an AND with a mask that
7130              is just some low-order bits.  If so, and it is MASK, we don't
7131              need it.  */
7132
7133           if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
7134               && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
7135                   == mask))
7136             x = XEXP (x, 0);
7137
7138           /* If it remains an AND, try making another AND with the bits
7139              in the mode mask that aren't in MASK turned on.  If the
7140              constant in the AND is wide enough, this might make a
7141              cheaper constant.  */
7142
7143           if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
7144               && GET_MODE_MASK (GET_MODE (x)) != mask
7145               && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
7146             {
7147               HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
7148                                     | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
7149               int width = GET_MODE_BITSIZE (GET_MODE (x));
7150               rtx y;
7151
7152               /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
7153                  number, sign extend it.  */
7154               if (width > 0 && width < HOST_BITS_PER_WIDE_INT
7155                   && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7156                 cval |= (HOST_WIDE_INT) -1 << width;
7157
7158               y = simplify_gen_binary (AND, GET_MODE (x),
7159                                        XEXP (x, 0), GEN_INT (cval));
7160               if (rtx_cost (y, SET) < rtx_cost (x, SET))
7161                 x = y;
7162             }
7163
7164           break;
7165         }
7166
7167       goto binop;
7168
7169     case PLUS:
7170       /* In (and (plus FOO C1) M), if M is a mask that just turns off
7171          low-order bits (as in an alignment operation) and FOO is already
7172          aligned to that boundary, mask C1 to that boundary as well.
7173          This may eliminate that PLUS and, later, the AND.  */
7174
7175       {
7176         unsigned int width = GET_MODE_BITSIZE (mode);
7177         unsigned HOST_WIDE_INT smask = mask;
7178
7179         /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7180            number, sign extend it.  */
7181
7182         if (width < HOST_BITS_PER_WIDE_INT
7183             && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7184           smask |= (HOST_WIDE_INT) -1 << width;
7185
7186         if (GET_CODE (XEXP (x, 1)) == CONST_INT
7187             && exact_log2 (- smask) >= 0
7188             && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
7189             && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
7190           return force_to_mode (plus_constant (XEXP (x, 0),
7191                                                (INTVAL (XEXP (x, 1)) & smask)),
7192                                 mode, smask, reg, next_select);
7193       }
7194
7195       /* ... fall through ...  */
7196
7197     case MULT:
7198       /* For PLUS, MINUS and MULT, we need any bits less significant than the
7199          most significant bit in MASK since carries from those bits will
7200          affect the bits we are interested in.  */
7201       mask = fuller_mask;
7202       goto binop;
7203
7204     case MINUS:
7205       /* If X is (minus C Y) where C's least set bit is larger than any bit
7206          in the mask, then we may replace with (neg Y).  */
7207       if (GET_CODE (XEXP (x, 0)) == CONST_INT
7208           && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7209                                         & -INTVAL (XEXP (x, 0))))
7210               > mask))
7211         {
7212           x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7213                                   GET_MODE (x));
7214           return force_to_mode (x, mode, mask, reg, next_select);
7215         }
7216
7217       /* Similarly, if C contains every bit in the fuller_mask, then we may
7218          replace with (not Y).  */
7219       if (GET_CODE (XEXP (x, 0)) == CONST_INT
7220           && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7221               == INTVAL (XEXP (x, 0))))
7222         {
7223           x = simplify_gen_unary (NOT, GET_MODE (x),
7224                                   XEXP (x, 1), GET_MODE (x));
7225           return force_to_mode (x, mode, mask, reg, next_select);
7226         }
7227
7228       mask = fuller_mask;
7229       goto binop;
7230
7231     case IOR:
7232     case XOR:
7233       /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7234          LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7235          operation which may be a bitfield extraction.  Ensure that the
7236          constant we form is not wider than the mode of X.  */
7237
7238       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7239           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7240           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7241           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7242           && GET_CODE (XEXP (x, 1)) == CONST_INT
7243           && ((INTVAL (XEXP (XEXP (x, 0), 1))
7244                + floor_log2 (INTVAL (XEXP (x, 1))))
7245               < GET_MODE_BITSIZE (GET_MODE (x)))
7246           && (INTVAL (XEXP (x, 1))
7247               & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7248         {
7249           temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7250                           << INTVAL (XEXP (XEXP (x, 0), 1)));
7251           temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
7252                                       XEXP (XEXP (x, 0), 0), temp);
7253           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
7254                                    XEXP (XEXP (x, 0), 1));
7255           return force_to_mode (x, mode, mask, reg, next_select);
7256         }
7257
7258     binop:
7259       /* For most binary operations, just propagate into the operation and
7260          change the mode if we have an operation of that mode.  */
7261
7262       op0 = gen_lowpart (op_mode,
7263                          force_to_mode (XEXP (x, 0), mode, mask,
7264                                         reg, next_select));
7265       op1 = gen_lowpart (op_mode,
7266                          force_to_mode (XEXP (x, 1), mode, mask,
7267                                         reg, next_select));
7268
7269       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7270         x = simplify_gen_binary (code, op_mode, op0, op1);
7271       break;
7272
7273     case ASHIFT:
7274       /* For left shifts, do the same, but just for the first operand.
7275          However, we cannot do anything with shifts where we cannot
7276          guarantee that the counts are smaller than the size of the mode
7277          because such a count will have a different meaning in a
7278          wider mode.  */
7279
7280       if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7281              && INTVAL (XEXP (x, 1)) >= 0
7282              && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7283           && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7284                 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7285                     < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7286         break;
7287
7288       /* If the shift count is a constant and we can do arithmetic in
7289          the mode of the shift, refine which bits we need.  Otherwise, use the
7290          conservative form of the mask.  */
7291       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7292           && INTVAL (XEXP (x, 1)) >= 0
7293           && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7294           && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7295         mask >>= INTVAL (XEXP (x, 1));
7296       else
7297         mask = fuller_mask;
7298
7299       op0 = gen_lowpart (op_mode,
7300                          force_to_mode (XEXP (x, 0), op_mode,
7301                                         mask, reg, next_select));
7302
7303       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7304         x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7305       break;
7306
7307     case LSHIFTRT:
7308       /* Here we can only do something if the shift count is a constant,
7309          this shift constant is valid for the host, and we can do arithmetic
7310          in OP_MODE.  */
7311
7312       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7313           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7314           && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7315         {
7316           rtx inner = XEXP (x, 0);
7317           unsigned HOST_WIDE_INT inner_mask;
7318
7319           /* Select the mask of the bits we need for the shift operand.  */
7320           inner_mask = mask << INTVAL (XEXP (x, 1));
7321
7322           /* We can only change the mode of the shift if we can do arithmetic
7323              in the mode of the shift and INNER_MASK is no wider than the
7324              width of X's mode.  */
7325           if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7326             op_mode = GET_MODE (x);
7327
7328           inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
7329
7330           if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7331             x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7332         }
7333
7334       /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7335          shift and AND produces only copies of the sign bit (C2 is one less
7336          than a power of two), we can do this with just a shift.  */
7337
7338       if (GET_CODE (x) == LSHIFTRT
7339           && GET_CODE (XEXP (x, 1)) == CONST_INT
7340           /* The shift puts one of the sign bit copies in the least significant
7341              bit.  */
7342           && ((INTVAL (XEXP (x, 1))
7343                + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7344               >= GET_MODE_BITSIZE (GET_MODE (x)))
7345           && exact_log2 (mask + 1) >= 0
7346           /* Number of bits left after the shift must be more than the mask
7347              needs.  */
7348           && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7349               <= GET_MODE_BITSIZE (GET_MODE (x)))
7350           /* Must be more sign bit copies than the mask needs.  */
7351           && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7352               >= exact_log2 (mask + 1)))
7353         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7354                                  GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7355                                           - exact_log2 (mask + 1)));
7356
7357       goto shiftrt;
7358
7359     case ASHIFTRT:
7360       /* If we are just looking for the sign bit, we don't need this shift at
7361          all, even if it has a variable count.  */
7362       if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7363           && (mask == ((unsigned HOST_WIDE_INT) 1
7364                        << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7365         return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7366
7367       /* If this is a shift by a constant, get a mask that contains those bits
7368          that are not copies of the sign bit.  We then have two cases:  If
7369          MASK only includes those bits, this can be a logical shift, which may
7370          allow simplifications.  If MASK is a single-bit field not within
7371          those bits, we are requesting a copy of the sign bit and hence can
7372          shift the sign bit to the appropriate location.  */
7373
7374       if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7375           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7376         {
7377           int i = -1;
7378
7379           /* If the considered data is wider than HOST_WIDE_INT, we can't
7380              represent a mask for all its bits in a single scalar.
7381              But we only care about the lower bits, so calculate these.  */
7382
7383           if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7384             {
7385               nonzero = ~(HOST_WIDE_INT) 0;
7386
7387               /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7388                  is the number of bits a full-width mask would have set.
7389                  We need only shift if these are fewer than nonzero can
7390                  hold.  If not, we must keep all bits set in nonzero.  */
7391
7392               if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7393                   < HOST_BITS_PER_WIDE_INT)
7394                 nonzero >>= INTVAL (XEXP (x, 1))
7395                             + HOST_BITS_PER_WIDE_INT
7396                             - GET_MODE_BITSIZE (GET_MODE (x)) ;
7397             }
7398           else
7399             {
7400               nonzero = GET_MODE_MASK (GET_MODE (x));
7401               nonzero >>= INTVAL (XEXP (x, 1));
7402             }
7403
7404           if ((mask & ~nonzero) == 0
7405               || (i = exact_log2 (mask)) >= 0)
7406             {
7407               x = simplify_shift_const
7408                 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7409                  i < 0 ? INTVAL (XEXP (x, 1))
7410                  : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7411
7412               if (GET_CODE (x) != ASHIFTRT)
7413                 return force_to_mode (x, mode, mask, reg, next_select);
7414             }
7415         }
7416
7417       /* If MASK is 1, convert this to an LSHIFTRT.  This can be done
7418          even if the shift count isn't a constant.  */
7419       if (mask == 1)
7420         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7421                                  XEXP (x, 0), XEXP (x, 1));
7422
7423     shiftrt:
7424
7425       /* If this is a zero- or sign-extension operation that just affects bits
7426          we don't care about, remove it.  Be sure the call above returned
7427          something that is still a shift.  */
7428
7429       if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7430           && GET_CODE (XEXP (x, 1)) == CONST_INT
7431           && INTVAL (XEXP (x, 1)) >= 0
7432           && (INTVAL (XEXP (x, 1))
7433               <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7434           && GET_CODE (XEXP (x, 0)) == ASHIFT
7435           && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7436         return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7437                               reg, next_select);
7438
7439       break;
7440
7441     case ROTATE:
7442     case ROTATERT:
7443       /* If the shift count is constant and we can do computations
7444          in the mode of X, compute where the bits we care about are.
7445          Otherwise, we can't do anything.  Don't change the mode of
7446          the shift or propagate MODE into the shift, though.  */
7447       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7448           && INTVAL (XEXP (x, 1)) >= 0)
7449         {
7450           temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7451                                             GET_MODE (x), GEN_INT (mask),
7452                                             XEXP (x, 1));
7453           if (temp && GET_CODE (temp) == CONST_INT)
7454             SUBST (XEXP (x, 0),
7455                    force_to_mode (XEXP (x, 0), GET_MODE (x),
7456                                   INTVAL (temp), reg, next_select));
7457         }
7458       break;
7459
7460     case NEG:
7461       /* If we just want the low-order bit, the NEG isn't needed since it
7462          won't change the low-order bit.  */
7463       if (mask == 1)
7464         return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7465
7466       /* We need any bits less significant than the most significant bit in
7467          MASK since carries from those bits will affect the bits we are
7468          interested in.  */
7469       mask = fuller_mask;
7470       goto unop;
7471
7472     case NOT:
7473       /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7474          same as the XOR case above.  Ensure that the constant we form is not
7475          wider than the mode of X.  */
7476
7477       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7478           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7479           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7480           && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7481               < GET_MODE_BITSIZE (GET_MODE (x)))
7482           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7483         {
7484           temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7485                                GET_MODE (x));
7486           temp = simplify_gen_binary (XOR, GET_MODE (x),
7487                                       XEXP (XEXP (x, 0), 0), temp);
7488           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7489                                    temp, XEXP (XEXP (x, 0), 1));
7490
7491           return force_to_mode (x, mode, mask, reg, next_select);
7492         }
7493
7494       /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7495          use the full mask inside the NOT.  */
7496       mask = fuller_mask;
7497
7498     unop:
7499       op0 = gen_lowpart (op_mode,
7500                          force_to_mode (XEXP (x, 0), mode, mask,
7501                                         reg, next_select));
7502       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7503         x = simplify_gen_unary (code, op_mode, op0, op_mode);
7504       break;
7505
7506     case NE:
7507       /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7508          in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7509          which is equal to STORE_FLAG_VALUE.  */
7510       if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7511           && GET_MODE (XEXP (x, 0)) == mode
7512           && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7513           && (nonzero_bits (XEXP (x, 0), mode)
7514               == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7515         return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7516
7517       break;
7518
7519     case IF_THEN_ELSE:
7520       /* We have no way of knowing if the IF_THEN_ELSE can itself be
7521          written in a narrower mode.  We play it safe and do not do so.  */
7522
7523       SUBST (XEXP (x, 1),
7524              gen_lowpart (GET_MODE (x),
7525                                       force_to_mode (XEXP (x, 1), mode,
7526                                                      mask, reg, next_select)));
7527       SUBST (XEXP (x, 2),
7528              gen_lowpart (GET_MODE (x),
7529                                       force_to_mode (XEXP (x, 2), mode,
7530                                                      mask, reg, next_select)));
7531       break;
7532
7533     default:
7534       break;
7535     }
7536
7537   /* Ensure we return a value of the proper mode.  */
7538   return gen_lowpart (mode, x);
7539 }
7540 \f
7541 /* Return nonzero if X is an expression that has one of two values depending on
7542    whether some other value is zero or nonzero.  In that case, we return the
7543    value that is being tested, *PTRUE is set to the value if the rtx being
7544    returned has a nonzero value, and *PFALSE is set to the other alternative.
7545
7546    If we return zero, we set *PTRUE and *PFALSE to X.  */
7547
7548 static rtx
7549 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7550 {
7551   enum machine_mode mode = GET_MODE (x);
7552   enum rtx_code code = GET_CODE (x);
7553   rtx cond0, cond1, true0, true1, false0, false1;
7554   unsigned HOST_WIDE_INT nz;
7555
7556   /* If we are comparing a value against zero, we are done.  */
7557   if ((code == NE || code == EQ)
7558       && XEXP (x, 1) == const0_rtx)
7559     {
7560       *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7561       *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7562       return XEXP (x, 0);
7563     }
7564
7565   /* If this is a unary operation whose operand has one of two values, apply
7566      our opcode to compute those values.  */
7567   else if (UNARY_P (x)
7568            && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7569     {
7570       *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7571       *pfalse = simplify_gen_unary (code, mode, false0,
7572                                     GET_MODE (XEXP (x, 0)));
7573       return cond0;
7574     }
7575
7576   /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7577      make can't possibly match and would suppress other optimizations.  */
7578   else if (code == COMPARE)
7579     ;
7580
7581   /* If this is a binary operation, see if either side has only one of two
7582      values.  If either one does or if both do and they are conditional on
7583      the same value, compute the new true and false values.  */
7584   else if (BINARY_P (x))
7585     {
7586       cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7587       cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7588
7589       if ((cond0 != 0 || cond1 != 0)
7590           && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7591         {
7592           /* If if_then_else_cond returned zero, then true/false are the
7593              same rtl.  We must copy one of them to prevent invalid rtl
7594              sharing.  */
7595           if (cond0 == 0)
7596             true0 = copy_rtx (true0);
7597           else if (cond1 == 0)
7598             true1 = copy_rtx (true1);
7599
7600           if (COMPARISON_P (x))
7601             {
7602               *ptrue = simplify_gen_relational (code, mode, VOIDmode,
7603                                                 true0, true1);
7604               *pfalse = simplify_gen_relational (code, mode, VOIDmode,
7605                                                  false0, false1);
7606              }
7607           else
7608             {
7609               *ptrue = simplify_gen_binary (code, mode, true0, true1);
7610               *pfalse = simplify_gen_binary (code, mode, false0, false1);
7611             }
7612
7613           return cond0 ? cond0 : cond1;
7614         }
7615
7616       /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7617          operands is zero when the other is nonzero, and vice-versa,
7618          and STORE_FLAG_VALUE is 1 or -1.  */
7619
7620       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7621           && (code == PLUS || code == IOR || code == XOR || code == MINUS
7622               || code == UMAX)
7623           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7624         {
7625           rtx op0 = XEXP (XEXP (x, 0), 1);
7626           rtx op1 = XEXP (XEXP (x, 1), 1);
7627
7628           cond0 = XEXP (XEXP (x, 0), 0);
7629           cond1 = XEXP (XEXP (x, 1), 0);
7630
7631           if (COMPARISON_P (cond0)
7632               && COMPARISON_P (cond1)
7633               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7634                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7635                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7636                   || ((swap_condition (GET_CODE (cond0))
7637                        == reversed_comparison_code (cond1, NULL))
7638                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7639                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7640               && ! side_effects_p (x))
7641             {
7642               *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
7643               *pfalse = simplify_gen_binary (MULT, mode,
7644                                              (code == MINUS
7645                                               ? simplify_gen_unary (NEG, mode,
7646                                                                     op1, mode)
7647                                               : op1),
7648                                               const_true_rtx);
7649               return cond0;
7650             }
7651         }
7652
7653       /* Similarly for MULT, AND and UMIN, except that for these the result
7654          is always zero.  */
7655       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7656           && (code == MULT || code == AND || code == UMIN)
7657           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7658         {
7659           cond0 = XEXP (XEXP (x, 0), 0);
7660           cond1 = XEXP (XEXP (x, 1), 0);
7661
7662           if (COMPARISON_P (cond0)
7663               && COMPARISON_P (cond1)
7664               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7665                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7666                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7667                   || ((swap_condition (GET_CODE (cond0))
7668                        == reversed_comparison_code (cond1, NULL))
7669                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7670                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7671               && ! side_effects_p (x))
7672             {
7673               *ptrue = *pfalse = const0_rtx;
7674               return cond0;
7675             }
7676         }
7677     }
7678
7679   else if (code == IF_THEN_ELSE)
7680     {
7681       /* If we have IF_THEN_ELSE already, extract the condition and
7682          canonicalize it if it is NE or EQ.  */
7683       cond0 = XEXP (x, 0);
7684       *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7685       if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7686         return XEXP (cond0, 0);
7687       else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7688         {
7689           *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7690           return XEXP (cond0, 0);
7691         }
7692       else
7693         return cond0;
7694     }
7695
7696   /* If X is a SUBREG, we can narrow both the true and false values
7697      if the inner expression, if there is a condition.  */
7698   else if (code == SUBREG
7699            && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7700                                                &true0, &false0)))
7701     {
7702       true0 = simplify_gen_subreg (mode, true0,
7703                                    GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7704       false0 = simplify_gen_subreg (mode, false0,
7705                                     GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7706       if (true0 && false0)
7707         {
7708           *ptrue = true0;
7709           *pfalse = false0;
7710           return cond0;
7711         }
7712     }
7713
7714   /* If X is a constant, this isn't special and will cause confusions
7715      if we treat it as such.  Likewise if it is equivalent to a constant.  */
7716   else if (CONSTANT_P (x)
7717            || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7718     ;
7719
7720   /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7721      will be least confusing to the rest of the compiler.  */
7722   else if (mode == BImode)
7723     {
7724       *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7725       return x;
7726     }
7727
7728   /* If X is known to be either 0 or -1, those are the true and
7729      false values when testing X.  */
7730   else if (x == constm1_rtx || x == const0_rtx
7731            || (mode != VOIDmode
7732                && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7733     {
7734       *ptrue = constm1_rtx, *pfalse = const0_rtx;
7735       return x;
7736     }
7737
7738   /* Likewise for 0 or a single bit.  */
7739   else if (SCALAR_INT_MODE_P (mode)
7740            && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7741            && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7742     {
7743       *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7744       return x;
7745     }
7746
7747   /* Otherwise fail; show no condition with true and false values the same.  */
7748   *ptrue = *pfalse = x;
7749   return 0;
7750 }
7751 \f
7752 /* Return the value of expression X given the fact that condition COND
7753    is known to be true when applied to REG as its first operand and VAL
7754    as its second.  X is known to not be shared and so can be modified in
7755    place.
7756
7757    We only handle the simplest cases, and specifically those cases that
7758    arise with IF_THEN_ELSE expressions.  */
7759
7760 static rtx
7761 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
7762 {
7763   enum rtx_code code = GET_CODE (x);
7764   rtx temp;
7765   const char *fmt;
7766   int i, j;
7767
7768   if (side_effects_p (x))
7769     return x;
7770
7771   /* If either operand of the condition is a floating point value,
7772      then we have to avoid collapsing an EQ comparison.  */
7773   if (cond == EQ
7774       && rtx_equal_p (x, reg)
7775       && ! FLOAT_MODE_P (GET_MODE (x))
7776       && ! FLOAT_MODE_P (GET_MODE (val)))
7777     return val;
7778
7779   if (cond == UNEQ && rtx_equal_p (x, reg))
7780     return val;
7781
7782   /* If X is (abs REG) and we know something about REG's relationship
7783      with zero, we may be able to simplify this.  */
7784
7785   if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7786     switch (cond)
7787       {
7788       case GE:  case GT:  case EQ:
7789         return XEXP (x, 0);
7790       case LT:  case LE:
7791         return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7792                                    XEXP (x, 0),
7793                                    GET_MODE (XEXP (x, 0)));
7794       default:
7795         break;
7796       }
7797
7798   /* The only other cases we handle are MIN, MAX, and comparisons if the
7799      operands are the same as REG and VAL.  */
7800
7801   else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
7802     {
7803       if (rtx_equal_p (XEXP (x, 0), val))
7804         cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7805
7806       if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7807         {
7808           if (COMPARISON_P (x))
7809             {
7810               if (comparison_dominates_p (cond, code))
7811                 return const_true_rtx;
7812
7813               code = reversed_comparison_code (x, NULL);
7814               if (code != UNKNOWN
7815                   && comparison_dominates_p (cond, code))
7816                 return const0_rtx;
7817               else
7818                 return x;
7819             }
7820           else if (code == SMAX || code == SMIN
7821                    || code == UMIN || code == UMAX)
7822             {
7823               int unsignedp = (code == UMIN || code == UMAX);
7824
7825               /* Do not reverse the condition when it is NE or EQ.
7826                  This is because we cannot conclude anything about
7827                  the value of 'SMAX (x, y)' when x is not equal to y,
7828                  but we can when x equals y.  */
7829               if ((code == SMAX || code == UMAX)
7830                   && ! (cond == EQ || cond == NE))
7831                 cond = reverse_condition (cond);
7832
7833               switch (cond)
7834                 {
7835                 case GE:   case GT:
7836                   return unsignedp ? x : XEXP (x, 1);
7837                 case LE:   case LT:
7838                   return unsignedp ? x : XEXP (x, 0);
7839                 case GEU:  case GTU:
7840                   return unsignedp ? XEXP (x, 1) : x;
7841                 case LEU:  case LTU:
7842                   return unsignedp ? XEXP (x, 0) : x;
7843                 default:
7844                   break;
7845                 }
7846             }
7847         }
7848     }
7849   else if (code == SUBREG)
7850     {
7851       enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7852       rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7853
7854       if (SUBREG_REG (x) != r)
7855         {
7856           /* We must simplify subreg here, before we lose track of the
7857              original inner_mode.  */
7858           new = simplify_subreg (GET_MODE (x), r,
7859                                  inner_mode, SUBREG_BYTE (x));
7860           if (new)
7861             return new;
7862           else
7863             SUBST (SUBREG_REG (x), r);
7864         }
7865
7866       return x;
7867     }
7868   /* We don't have to handle SIGN_EXTEND here, because even in the
7869      case of replacing something with a modeless CONST_INT, a
7870      CONST_INT is already (supposed to be) a valid sign extension for
7871      its narrower mode, which implies it's already properly
7872      sign-extended for the wider mode.  Now, for ZERO_EXTEND, the
7873      story is different.  */
7874   else if (code == ZERO_EXTEND)
7875     {
7876       enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7877       rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7878
7879       if (XEXP (x, 0) != r)
7880         {
7881           /* We must simplify the zero_extend here, before we lose
7882              track of the original inner_mode.  */
7883           new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7884                                           r, inner_mode);
7885           if (new)
7886             return new;
7887           else
7888             SUBST (XEXP (x, 0), r);
7889         }
7890
7891       return x;
7892     }
7893
7894   fmt = GET_RTX_FORMAT (code);
7895   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7896     {
7897       if (fmt[i] == 'e')
7898         SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7899       else if (fmt[i] == 'E')
7900         for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7901           SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7902                                                 cond, reg, val));
7903     }
7904
7905   return x;
7906 }
7907 \f
7908 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7909    assignment as a field assignment.  */
7910
7911 static int
7912 rtx_equal_for_field_assignment_p (rtx x, rtx y)
7913 {
7914   if (x == y || rtx_equal_p (x, y))
7915     return 1;
7916
7917   if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7918     return 0;
7919
7920   /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7921      Note that all SUBREGs of MEM are paradoxical; otherwise they
7922      would have been rewritten.  */
7923   if (MEM_P (x) && GET_CODE (y) == SUBREG
7924       && MEM_P (SUBREG_REG (y))
7925       && rtx_equal_p (SUBREG_REG (y),
7926                       gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
7927     return 1;
7928
7929   if (MEM_P (y) && GET_CODE (x) == SUBREG
7930       && MEM_P (SUBREG_REG (x))
7931       && rtx_equal_p (SUBREG_REG (x),
7932                       gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
7933     return 1;
7934
7935   /* We used to see if get_last_value of X and Y were the same but that's
7936      not correct.  In one direction, we'll cause the assignment to have
7937      the wrong destination and in the case, we'll import a register into this
7938      insn that might have already have been dead.   So fail if none of the
7939      above cases are true.  */
7940   return 0;
7941 }
7942 \f
7943 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7944    Return that assignment if so.
7945
7946    We only handle the most common cases.  */
7947
7948 static rtx
7949 make_field_assignment (rtx x)
7950 {
7951   rtx dest = SET_DEST (x);
7952   rtx src = SET_SRC (x);
7953   rtx assign;
7954   rtx rhs, lhs;
7955   HOST_WIDE_INT c1;
7956   HOST_WIDE_INT pos;
7957   unsigned HOST_WIDE_INT len;
7958   rtx other;
7959   enum machine_mode mode;
7960
7961   /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7962      a clear of a one-bit field.  We will have changed it to
7963      (and (rotate (const_int -2) POS) DEST), so check for that.  Also check
7964      for a SUBREG.  */
7965
7966   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7967       && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7968       && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7969       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7970     {
7971       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7972                                 1, 1, 1, 0);
7973       if (assign != 0)
7974         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7975       return x;
7976     }
7977
7978   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7979       && subreg_lowpart_p (XEXP (src, 0))
7980       && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7981           < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7982       && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7983       && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
7984       && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7985       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7986     {
7987       assign = make_extraction (VOIDmode, dest, 0,
7988                                 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7989                                 1, 1, 1, 0);
7990       if (assign != 0)
7991         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7992       return x;
7993     }
7994
7995   /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7996      one-bit field.  */
7997   if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7998       && XEXP (XEXP (src, 0), 0) == const1_rtx
7999       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8000     {
8001       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8002                                 1, 1, 1, 0);
8003       if (assign != 0)
8004         return gen_rtx_SET (VOIDmode, assign, const1_rtx);
8005       return x;
8006     }
8007
8008   /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8009      SRC is an AND with all bits of that field set, then we can discard
8010      the AND.  */
8011   if (GET_CODE (dest) == ZERO_EXTRACT
8012       && GET_CODE (XEXP (dest, 1)) == CONST_INT
8013       && GET_CODE (src) == AND
8014       && GET_CODE (XEXP (src, 1)) == CONST_INT)
8015     {
8016       HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
8017       unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
8018       unsigned HOST_WIDE_INT ze_mask;
8019
8020       if (width >= HOST_BITS_PER_WIDE_INT)
8021         ze_mask = -1;
8022       else
8023         ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
8024
8025       /* Complete overlap.  We can remove the source AND.  */
8026       if ((and_mask & ze_mask) == ze_mask)
8027         return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
8028
8029       /* Partial overlap.  We can reduce the source AND.  */
8030       if ((and_mask & ze_mask) != and_mask)
8031         {
8032           mode = GET_MODE (src);
8033           src = gen_rtx_AND (mode, XEXP (src, 0),
8034                              gen_int_mode (and_mask & ze_mask, mode));
8035           return gen_rtx_SET (VOIDmode, dest, src);
8036         }
8037     }
8038
8039   /* The other case we handle is assignments into a constant-position
8040      field.  They look like (ior/xor (and DEST C1) OTHER).  If C1 represents
8041      a mask that has all one bits except for a group of zero bits and
8042      OTHER is known to have zeros where C1 has ones, this is such an
8043      assignment.  Compute the position and length from C1.  Shift OTHER
8044      to the appropriate position, force it to the required mode, and
8045      make the extraction.  Check for the AND in both operands.  */
8046
8047   if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
8048     return x;
8049
8050   rhs = expand_compound_operation (XEXP (src, 0));
8051   lhs = expand_compound_operation (XEXP (src, 1));
8052
8053   if (GET_CODE (rhs) == AND
8054       && GET_CODE (XEXP (rhs, 1)) == CONST_INT
8055       && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
8056     c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
8057   else if (GET_CODE (lhs) == AND
8058            && GET_CODE (XEXP (lhs, 1)) == CONST_INT
8059            && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
8060     c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
8061   else
8062     return x;
8063
8064   pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
8065   if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
8066       || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
8067       || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
8068     return x;
8069
8070   assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
8071   if (assign == 0)
8072     return x;
8073
8074   /* The mode to use for the source is the mode of the assignment, or of
8075      what is inside a possible STRICT_LOW_PART.  */
8076   mode = (GET_CODE (assign) == STRICT_LOW_PART
8077           ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
8078
8079   /* Shift OTHER right POS places and make it the source, restricting it
8080      to the proper length and mode.  */
8081
8082   src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
8083                                              GET_MODE (src), other, pos),
8084                        mode,
8085                        GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
8086                        ? ~(unsigned HOST_WIDE_INT) 0
8087                        : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
8088                        dest, 0);
8089
8090   /* If SRC is masked by an AND that does not make a difference in
8091      the value being stored, strip it.  */
8092   if (GET_CODE (assign) == ZERO_EXTRACT
8093       && GET_CODE (XEXP (assign, 1)) == CONST_INT
8094       && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
8095       && GET_CODE (src) == AND
8096       && GET_CODE (XEXP (src, 1)) == CONST_INT
8097       && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
8098           == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
8099     src = XEXP (src, 0);
8100
8101   return gen_rtx_SET (VOIDmode, assign, src);
8102 }
8103 \f
8104 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
8105    if so.  */
8106
8107 static rtx
8108 apply_distributive_law (rtx x)
8109 {
8110   enum rtx_code code = GET_CODE (x);
8111   enum rtx_code inner_code;
8112   rtx lhs, rhs, other;
8113   rtx tem;
8114
8115   /* Distributivity is not true for floating point as it can change the
8116      value.  So we don't do it unless -funsafe-math-optimizations.  */
8117   if (FLOAT_MODE_P (GET_MODE (x))
8118       && ! flag_unsafe_math_optimizations)
8119     return x;
8120
8121   /* The outer operation can only be one of the following:  */
8122   if (code != IOR && code != AND && code != XOR
8123       && code != PLUS && code != MINUS)
8124     return x;
8125
8126   lhs = XEXP (x, 0);
8127   rhs = XEXP (x, 1);
8128
8129   /* If either operand is a primitive we can't do anything, so get out
8130      fast.  */
8131   if (OBJECT_P (lhs) || OBJECT_P (rhs))
8132     return x;
8133
8134   lhs = expand_compound_operation (lhs);
8135   rhs = expand_compound_operation (rhs);
8136   inner_code = GET_CODE (lhs);
8137   if (inner_code != GET_CODE (rhs))
8138     return x;
8139
8140   /* See if the inner and outer operations distribute.  */
8141   switch (inner_code)
8142     {
8143     case LSHIFTRT:
8144     case ASHIFTRT:
8145     case AND:
8146     case IOR:
8147       /* These all distribute except over PLUS.  */
8148       if (code == PLUS || code == MINUS)
8149         return x;
8150       break;
8151
8152     case MULT:
8153       if (code != PLUS && code != MINUS)
8154         return x;
8155       break;
8156
8157     case ASHIFT:
8158       /* This is also a multiply, so it distributes over everything.  */
8159       break;
8160
8161     case SUBREG:
8162       /* Non-paradoxical SUBREGs distributes over all operations,
8163          provided the inner modes and byte offsets are the same, this
8164          is an extraction of a low-order part, we don't convert an fp
8165          operation to int or vice versa, this is not a vector mode,
8166          and we would not be converting a single-word operation into a
8167          multi-word operation.  The latter test is not required, but
8168          it prevents generating unneeded multi-word operations.  Some
8169          of the previous tests are redundant given the latter test,
8170          but are retained because they are required for correctness.
8171
8172          We produce the result slightly differently in this case.  */
8173
8174       if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
8175           || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
8176           || ! subreg_lowpart_p (lhs)
8177           || (GET_MODE_CLASS (GET_MODE (lhs))
8178               != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
8179           || (GET_MODE_SIZE (GET_MODE (lhs))
8180               > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
8181           || VECTOR_MODE_P (GET_MODE (lhs))
8182           || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
8183         return x;
8184
8185       tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
8186                                  SUBREG_REG (lhs), SUBREG_REG (rhs));
8187       return gen_lowpart (GET_MODE (x), tem);
8188
8189     default:
8190       return x;
8191     }
8192
8193   /* Set LHS and RHS to the inner operands (A and B in the example
8194      above) and set OTHER to the common operand (C in the example).
8195      There is only one way to do this unless the inner operation is
8196      commutative.  */
8197   if (COMMUTATIVE_ARITH_P (lhs)
8198       && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
8199     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
8200   else if (COMMUTATIVE_ARITH_P (lhs)
8201            && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
8202     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
8203   else if (COMMUTATIVE_ARITH_P (lhs)
8204            && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8205     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8206   else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8207     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8208   else
8209     return x;
8210
8211   /* Form the new inner operation, seeing if it simplifies first.  */
8212   tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
8213
8214   /* There is one exception to the general way of distributing:
8215      (a | c) ^ (b | c) -> (a ^ b) & ~c  */
8216   if (code == XOR && inner_code == IOR)
8217     {
8218       inner_code = AND;
8219       other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8220     }
8221
8222   /* We may be able to continuing distributing the result, so call
8223      ourselves recursively on the inner operation before forming the
8224      outer operation, which we return.  */
8225   return simplify_gen_binary (inner_code, GET_MODE (x),
8226                               apply_distributive_law (tem), other);
8227 }
8228
8229 /* See if X is of the form (* (+ A B) C), and if so convert to
8230    (+ (* A C) (* B C)) and try to simplify.
8231
8232    Most of the time, this results in no change.  However, if some of
8233    the operands are the same or inverses of each other, simplifications
8234    will result.
8235
8236    For example, (and (ior A B) (not B)) can occur as the result of
8237    expanding a bit field assignment.  When we apply the distributive
8238    law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8239    which then simplifies to (and (A (not B))).
8240
8241    Note that no checks happen on the validity of applying the inverse
8242    distributive law.  This is pointless since we can do it in the
8243    few places where this routine is called.
8244
8245    N is the index of the term that is decomposed (the arithmetic operation,
8246    i.e. (+ A B) in the first example above).  !N is the index of the term that
8247    is distributed, i.e. of C in the first example above.  */
8248 static rtx
8249 distribute_and_simplify_rtx (rtx x, int n)
8250 {
8251   enum machine_mode mode;
8252   enum rtx_code outer_code, inner_code;
8253   rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
8254
8255   decomposed = XEXP (x, n);
8256   if (!ARITHMETIC_P (decomposed))
8257     return NULL_RTX;
8258
8259   mode = GET_MODE (x);
8260   outer_code = GET_CODE (x);
8261   distributed = XEXP (x, !n);
8262
8263   inner_code = GET_CODE (decomposed);
8264   inner_op0 = XEXP (decomposed, 0);
8265   inner_op1 = XEXP (decomposed, 1);
8266
8267   /* Special case (and (xor B C) (not A)), which is equivalent to
8268      (xor (ior A B) (ior A C))  */
8269   if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
8270     {
8271       distributed = XEXP (distributed, 0);
8272       outer_code = IOR;
8273     }
8274
8275   if (n == 0)
8276     {
8277       /* Distribute the second term.  */
8278       new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
8279       new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
8280     }
8281   else
8282     {
8283       /* Distribute the first term.  */
8284       new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
8285       new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
8286     }
8287
8288   tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8289                                                      new_op0, new_op1));
8290   if (GET_CODE (tmp) != outer_code
8291       && rtx_cost (tmp, SET) < rtx_cost (x, SET))
8292     return tmp;
8293
8294   return NULL_RTX;
8295 }
8296 \f
8297 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8298    in MODE.
8299
8300    Return an equivalent form, if different from X.  Otherwise, return X.  If
8301    X is zero, we are to always construct the equivalent form.  */
8302
8303 static rtx
8304 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8305                         unsigned HOST_WIDE_INT constop)
8306 {
8307   unsigned HOST_WIDE_INT nonzero;
8308   int i;
8309
8310   /* Simplify VAROP knowing that we will be only looking at some of the
8311      bits in it.
8312
8313      Note by passing in CONSTOP, we guarantee that the bits not set in
8314      CONSTOP are not significant and will never be examined.  We must
8315      ensure that is the case by explicitly masking out those bits
8316      before returning.  */
8317   varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
8318
8319   /* If VAROP is a CLOBBER, we will fail so return it.  */
8320   if (GET_CODE (varop) == CLOBBER)
8321     return varop;
8322
8323   /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8324      to VAROP and return the new constant.  */
8325   if (GET_CODE (varop) == CONST_INT)
8326     return gen_int_mode (INTVAL (varop) & constop, mode);
8327
8328   /* See what bits may be nonzero in VAROP.  Unlike the general case of
8329      a call to nonzero_bits, here we don't care about bits outside
8330      MODE.  */
8331
8332   nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8333
8334   /* Turn off all bits in the constant that are known to already be zero.
8335      Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8336      which is tested below.  */
8337
8338   constop &= nonzero;
8339
8340   /* If we don't have any bits left, return zero.  */
8341   if (constop == 0)
8342     return const0_rtx;
8343
8344   /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8345      a power of two, we can replace this with an ASHIFT.  */
8346   if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8347       && (i = exact_log2 (constop)) >= 0)
8348     return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8349
8350   /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8351      or XOR, then try to apply the distributive law.  This may eliminate
8352      operations if either branch can be simplified because of the AND.
8353      It may also make some cases more complex, but those cases probably
8354      won't match a pattern either with or without this.  */
8355
8356   if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8357     return
8358       gen_lowpart
8359         (mode,
8360          apply_distributive_law
8361          (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8362                                simplify_and_const_int (NULL_RTX,
8363                                                        GET_MODE (varop),
8364                                                        XEXP (varop, 0),
8365                                                        constop),
8366                                simplify_and_const_int (NULL_RTX,
8367                                                        GET_MODE (varop),
8368                                                        XEXP (varop, 1),
8369                                                        constop))));
8370
8371   /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
8372      the AND and see if one of the operands simplifies to zero.  If so, we
8373      may eliminate it.  */
8374
8375   if (GET_CODE (varop) == PLUS
8376       && exact_log2 (constop + 1) >= 0)
8377     {
8378       rtx o0, o1;
8379
8380       o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8381       o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8382       if (o0 == const0_rtx)
8383         return o1;
8384       if (o1 == const0_rtx)
8385         return o0;
8386     }
8387
8388   /* Get VAROP in MODE.  Try to get a SUBREG if not.  Don't make a new SUBREG
8389      if we already had one (just check for the simplest cases).  */
8390   if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8391       && GET_MODE (XEXP (x, 0)) == mode
8392       && SUBREG_REG (XEXP (x, 0)) == varop)
8393     varop = XEXP (x, 0);
8394   else
8395     varop = gen_lowpart (mode, varop);
8396
8397   /* If we can't make the SUBREG, try to return what we were given.  */
8398   if (GET_CODE (varop) == CLOBBER)
8399     return x ? x : varop;
8400
8401   /* If we are only masking insignificant bits, return VAROP.  */
8402   if (constop == nonzero)
8403     x = varop;
8404   else
8405     {
8406       /* Otherwise, return an AND.  */
8407       constop = trunc_int_for_mode (constop, mode);
8408       /* See how much, if any, of X we can use.  */
8409       if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
8410         x = simplify_gen_binary (AND, mode, varop, GEN_INT (constop));
8411
8412       else
8413         {
8414           if (GET_CODE (XEXP (x, 1)) != CONST_INT
8415               || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
8416             SUBST (XEXP (x, 1), GEN_INT (constop));
8417
8418           SUBST (XEXP (x, 0), varop);
8419         }
8420     }
8421
8422   return x;
8423 }
8424 \f
8425 /* Given a REG, X, compute which bits in X can be nonzero.
8426    We don't care about bits outside of those defined in MODE.
8427
8428    For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8429    a shift, AND, or zero_extract, we can do better.  */
8430
8431 static rtx
8432 reg_nonzero_bits_for_combine (rtx x, enum machine_mode mode,
8433                               rtx known_x ATTRIBUTE_UNUSED,
8434                               enum machine_mode known_mode ATTRIBUTE_UNUSED,
8435                               unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8436                               unsigned HOST_WIDE_INT *nonzero)
8437 {
8438   rtx tem;
8439
8440   /* If X is a register whose nonzero bits value is current, use it.
8441      Otherwise, if X is a register whose value we can find, use that
8442      value.  Otherwise, use the previously-computed global nonzero bits
8443      for this register.  */
8444
8445   if (reg_stat[REGNO (x)].last_set_value != 0
8446       && (reg_stat[REGNO (x)].last_set_mode == mode
8447           || (GET_MODE_CLASS (reg_stat[REGNO (x)].last_set_mode) == MODE_INT
8448               && GET_MODE_CLASS (mode) == MODE_INT))
8449       && (reg_stat[REGNO (x)].last_set_label == label_tick
8450           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8451               && REG_N_SETS (REGNO (x)) == 1
8452               && ! REGNO_REG_SET_P
8453                  (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8454                   REGNO (x))))
8455       && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8456     {
8457       *nonzero &= reg_stat[REGNO (x)].last_set_nonzero_bits;
8458       return NULL;
8459     }
8460
8461   tem = get_last_value (x);
8462
8463   if (tem)
8464     {
8465 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8466       /* If X is narrower than MODE and TEM is a non-negative
8467          constant that would appear negative in the mode of X,
8468          sign-extend it for use in reg_nonzero_bits because some
8469          machines (maybe most) will actually do the sign-extension
8470          and this is the conservative approach.
8471
8472          ??? For 2.5, try to tighten up the MD files in this regard
8473          instead of this kludge.  */
8474
8475       if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
8476           && GET_CODE (tem) == CONST_INT
8477           && INTVAL (tem) > 0
8478           && 0 != (INTVAL (tem)
8479                    & ((HOST_WIDE_INT) 1
8480                       << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8481         tem = GEN_INT (INTVAL (tem)
8482                        | ((HOST_WIDE_INT) (-1)
8483                           << GET_MODE_BITSIZE (GET_MODE (x))));
8484 #endif
8485       return tem;
8486     }
8487   else if (nonzero_sign_valid && reg_stat[REGNO (x)].nonzero_bits)
8488     {
8489       unsigned HOST_WIDE_INT mask = reg_stat[REGNO (x)].nonzero_bits;
8490
8491       if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
8492         /* We don't know anything about the upper bits.  */
8493         mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8494       *nonzero &= mask;
8495     }
8496
8497   return NULL;
8498 }
8499
8500 /* Return the number of bits at the high-order end of X that are known to
8501    be equal to the sign bit.  X will be used in mode MODE; if MODE is
8502    VOIDmode, X will be used in its own mode.  The returned value  will always
8503    be between 1 and the number of bits in MODE.  */
8504
8505 static rtx
8506 reg_num_sign_bit_copies_for_combine (rtx x, enum machine_mode mode,
8507                                      rtx known_x ATTRIBUTE_UNUSED,
8508                                      enum machine_mode known_mode
8509                                      ATTRIBUTE_UNUSED,
8510                                      unsigned int known_ret ATTRIBUTE_UNUSED,
8511                                      unsigned int *result)
8512 {
8513   rtx tem;
8514
8515   if (reg_stat[REGNO (x)].last_set_value != 0
8516       && reg_stat[REGNO (x)].last_set_mode == mode
8517       && (reg_stat[REGNO (x)].last_set_label == label_tick
8518           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8519               && REG_N_SETS (REGNO (x)) == 1
8520               && ! REGNO_REG_SET_P
8521                  (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8522                   REGNO (x))))
8523       && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8524     {
8525       *result = reg_stat[REGNO (x)].last_set_sign_bit_copies;
8526       return NULL;
8527     }
8528
8529   tem = get_last_value (x);
8530   if (tem != 0)
8531     return tem;
8532
8533   if (nonzero_sign_valid && reg_stat[REGNO (x)].sign_bit_copies != 0
8534       && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
8535     *result = reg_stat[REGNO (x)].sign_bit_copies;
8536
8537   return NULL;
8538 }
8539 \f
8540 /* Return the number of "extended" bits there are in X, when interpreted
8541    as a quantity in MODE whose signedness is indicated by UNSIGNEDP.  For
8542    unsigned quantities, this is the number of high-order zero bits.
8543    For signed quantities, this is the number of copies of the sign bit
8544    minus 1.  In both case, this function returns the number of "spare"
8545    bits.  For example, if two quantities for which this function returns
8546    at least 1 are added, the addition is known not to overflow.
8547
8548    This function will always return 0 unless called during combine, which
8549    implies that it must be called from a define_split.  */
8550
8551 unsigned int
8552 extended_count (rtx x, enum machine_mode mode, int unsignedp)
8553 {
8554   if (nonzero_sign_valid == 0)
8555     return 0;
8556
8557   return (unsignedp
8558           ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8559              ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8560                                - floor_log2 (nonzero_bits (x, mode)))
8561              : 0)
8562           : num_sign_bit_copies (x, mode) - 1);
8563 }
8564 \f
8565 /* This function is called from `simplify_shift_const' to merge two
8566    outer operations.  Specifically, we have already found that we need
8567    to perform operation *POP0 with constant *PCONST0 at the outermost
8568    position.  We would now like to also perform OP1 with constant CONST1
8569    (with *POP0 being done last).
8570
8571    Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8572    the resulting operation.  *PCOMP_P is set to 1 if we would need to
8573    complement the innermost operand, otherwise it is unchanged.
8574
8575    MODE is the mode in which the operation will be done.  No bits outside
8576    the width of this mode matter.  It is assumed that the width of this mode
8577    is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8578
8579    If *POP0 or OP1 are UNKNOWN, it means no operation is required.  Only NEG, PLUS,
8580    IOR, XOR, and AND are supported.  We may set *POP0 to SET if the proper
8581    result is simply *PCONST0.
8582
8583    If the resulting operation cannot be expressed as one operation, we
8584    return 0 and do not change *POP0, *PCONST0, and *PCOMP_P.  */
8585
8586 static int
8587 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8588 {
8589   enum rtx_code op0 = *pop0;
8590   HOST_WIDE_INT const0 = *pconst0;
8591
8592   const0 &= GET_MODE_MASK (mode);
8593   const1 &= GET_MODE_MASK (mode);
8594
8595   /* If OP0 is an AND, clear unimportant bits in CONST1.  */
8596   if (op0 == AND)
8597     const1 &= const0;
8598
8599   /* If OP0 or OP1 is UNKNOWN, this is easy.  Similarly if they are the same or
8600      if OP0 is SET.  */
8601
8602   if (op1 == UNKNOWN || op0 == SET)
8603     return 1;
8604
8605   else if (op0 == UNKNOWN)
8606     op0 = op1, const0 = const1;
8607
8608   else if (op0 == op1)
8609     {
8610       switch (op0)
8611         {
8612         case AND:
8613           const0 &= const1;
8614           break;
8615         case IOR:
8616           const0 |= const1;
8617           break;
8618         case XOR:
8619           const0 ^= const1;
8620           break;
8621         case PLUS:
8622           const0 += const1;
8623           break;
8624         case NEG:
8625           op0 = UNKNOWN;
8626           break;
8627         default:
8628           break;
8629         }
8630     }
8631
8632   /* Otherwise, if either is a PLUS or NEG, we can't do anything.  */
8633   else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8634     return 0;
8635
8636   /* If the two constants aren't the same, we can't do anything.  The
8637      remaining six cases can all be done.  */
8638   else if (const0 != const1)
8639     return 0;
8640
8641   else
8642     switch (op0)
8643       {
8644       case IOR:
8645         if (op1 == AND)
8646           /* (a & b) | b == b */
8647           op0 = SET;
8648         else /* op1 == XOR */
8649           /* (a ^ b) | b == a | b */
8650           {;}
8651         break;
8652
8653       case XOR:
8654         if (op1 == AND)
8655           /* (a & b) ^ b == (~a) & b */
8656           op0 = AND, *pcomp_p = 1;
8657         else /* op1 == IOR */
8658           /* (a | b) ^ b == a & ~b */
8659           op0 = AND, const0 = ~const0;
8660         break;
8661
8662       case AND:
8663         if (op1 == IOR)
8664           /* (a | b) & b == b */
8665         op0 = SET;
8666         else /* op1 == XOR */
8667           /* (a ^ b) & b) == (~a) & b */
8668           *pcomp_p = 1;
8669         break;
8670       default:
8671         break;
8672       }
8673
8674   /* Check for NO-OP cases.  */
8675   const0 &= GET_MODE_MASK (mode);
8676   if (const0 == 0
8677       && (op0 == IOR || op0 == XOR || op0 == PLUS))
8678     op0 = UNKNOWN;
8679   else if (const0 == 0 && op0 == AND)
8680     op0 = SET;
8681   else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8682            && op0 == AND)
8683     op0 = UNKNOWN;
8684
8685   /* ??? Slightly redundant with the above mask, but not entirely.
8686      Moving this above means we'd have to sign-extend the mode mask
8687      for the final test.  */
8688   const0 = trunc_int_for_mode (const0, mode);
8689
8690   *pop0 = op0;
8691   *pconst0 = const0;
8692
8693   return 1;
8694 }
8695 \f
8696 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
8697    The result of the shift is RESULT_MODE.  X, if nonzero, is an expression
8698    that we started with.
8699
8700    The shift is normally computed in the widest mode we find in VAROP, as
8701    long as it isn't a different number of words than RESULT_MODE.  Exceptions
8702    are ASHIFTRT and ROTATE, which are always done in their original mode,  */
8703
8704 static rtx
8705 simplify_shift_const (rtx x, enum rtx_code code,
8706                       enum machine_mode result_mode, rtx varop,
8707                       int orig_count)
8708 {
8709   enum rtx_code orig_code = code;
8710   unsigned int count;
8711   int signed_count;
8712   enum machine_mode mode = result_mode;
8713   enum machine_mode shift_mode, tmode;
8714   unsigned int mode_words
8715     = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8716   /* We form (outer_op (code varop count) (outer_const)).  */
8717   enum rtx_code outer_op = UNKNOWN;
8718   HOST_WIDE_INT outer_const = 0;
8719   rtx const_rtx;
8720   int complement_p = 0;
8721   rtx new;
8722
8723   /* Make sure and truncate the "natural" shift on the way in.  We don't
8724      want to do this inside the loop as it makes it more difficult to
8725      combine shifts.  */
8726   if (SHIFT_COUNT_TRUNCATED)
8727     orig_count &= GET_MODE_BITSIZE (mode) - 1;
8728
8729   /* If we were given an invalid count, don't do anything except exactly
8730      what was requested.  */
8731
8732   if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8733     {
8734       if (x)
8735         return x;
8736
8737       return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count));
8738     }
8739
8740   count = orig_count;
8741
8742   /* Unless one of the branches of the `if' in this loop does a `continue',
8743      we will `break' the loop after the `if'.  */
8744
8745   while (count != 0)
8746     {
8747       /* If we have an operand of (clobber (const_int 0)), just return that
8748          value.  */
8749       if (GET_CODE (varop) == CLOBBER)
8750         return varop;
8751
8752       /* If we discovered we had to complement VAROP, leave.  Making a NOT
8753          here would cause an infinite loop.  */
8754       if (complement_p)
8755         break;
8756
8757       /* Convert ROTATERT to ROTATE.  */
8758       if (code == ROTATERT)
8759         {
8760           unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
8761           code = ROTATE;
8762           if (VECTOR_MODE_P (result_mode))
8763             count = bitsize / GET_MODE_NUNITS (result_mode) - count;
8764           else
8765             count = bitsize - count;
8766         }
8767
8768       /* We need to determine what mode we will do the shift in.  If the
8769          shift is a right shift or a ROTATE, we must always do it in the mode
8770          it was originally done in.  Otherwise, we can do it in MODE, the
8771          widest mode encountered.  */
8772       shift_mode
8773         = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8774            ? result_mode : mode);
8775
8776       /* Handle cases where the count is greater than the size of the mode
8777          minus 1.  For ASHIFT, use the size minus one as the count (this can
8778          occur when simplifying (lshiftrt (ashiftrt ..))).  For rotates,
8779          take the count modulo the size.  For other shifts, the result is
8780          zero.
8781
8782          Since these shifts are being produced by the compiler by combining
8783          multiple operations, each of which are defined, we know what the
8784          result is supposed to be.  */
8785
8786       if (count > (unsigned int) (GET_MODE_BITSIZE (shift_mode) - 1))
8787         {
8788           if (code == ASHIFTRT)
8789             count = GET_MODE_BITSIZE (shift_mode) - 1;
8790           else if (code == ROTATE || code == ROTATERT)
8791             count %= GET_MODE_BITSIZE (shift_mode);
8792           else
8793             {
8794               /* We can't simply return zero because there may be an
8795                  outer op.  */
8796               varop = const0_rtx;
8797               count = 0;
8798               break;
8799             }
8800         }
8801
8802       /* An arithmetic right shift of a quantity known to be -1 or 0
8803          is a no-op.  */
8804       if (code == ASHIFTRT
8805           && (num_sign_bit_copies (varop, shift_mode)
8806               == GET_MODE_BITSIZE (shift_mode)))
8807         {
8808           count = 0;
8809           break;
8810         }
8811
8812       /* If we are doing an arithmetic right shift and discarding all but
8813          the sign bit copies, this is equivalent to doing a shift by the
8814          bitsize minus one.  Convert it into that shift because it will often
8815          allow other simplifications.  */
8816
8817       if (code == ASHIFTRT
8818           && (count + num_sign_bit_copies (varop, shift_mode)
8819               >= GET_MODE_BITSIZE (shift_mode)))
8820         count = GET_MODE_BITSIZE (shift_mode) - 1;
8821
8822       /* We simplify the tests below and elsewhere by converting
8823          ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8824          `make_compound_operation' will convert it to an ASHIFTRT for
8825          those machines (such as VAX) that don't have an LSHIFTRT.  */
8826       if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8827           && code == ASHIFTRT
8828           && ((nonzero_bits (varop, shift_mode)
8829                & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8830               == 0))
8831         code = LSHIFTRT;
8832
8833       if (((code == LSHIFTRT
8834             && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8835             && !(nonzero_bits (varop, shift_mode) >> count))
8836            || (code == ASHIFT
8837                && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8838                && !((nonzero_bits (varop, shift_mode) << count)
8839                     & GET_MODE_MASK (shift_mode))))
8840           && !side_effects_p (varop))
8841         varop = const0_rtx;
8842
8843       switch (GET_CODE (varop))
8844         {
8845         case SIGN_EXTEND:
8846         case ZERO_EXTEND:
8847         case SIGN_EXTRACT:
8848         case ZERO_EXTRACT:
8849           new = expand_compound_operation (varop);
8850           if (new != varop)
8851             {
8852               varop = new;
8853               continue;
8854             }
8855           break;
8856
8857         case MEM:
8858           /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8859              minus the width of a smaller mode, we can do this with a
8860              SIGN_EXTEND or ZERO_EXTEND from the narrower memory location.  */
8861           if ((code == ASHIFTRT || code == LSHIFTRT)
8862               && ! mode_dependent_address_p (XEXP (varop, 0))
8863               && ! MEM_VOLATILE_P (varop)
8864               && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8865                                          MODE_INT, 1)) != BLKmode)
8866             {
8867               new = adjust_address_nv (varop, tmode,
8868                                        BYTES_BIG_ENDIAN ? 0
8869                                        : count / BITS_PER_UNIT);
8870
8871               varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8872                                      : ZERO_EXTEND, mode, new);
8873               count = 0;
8874               continue;
8875             }
8876           break;
8877
8878         case USE:
8879           /* Similar to the case above, except that we can only do this if
8880              the resulting mode is the same as that of the underlying
8881              MEM and adjust the address depending on the *bits* endianness
8882              because of the way that bit-field extract insns are defined.  */
8883           if ((code == ASHIFTRT || code == LSHIFTRT)
8884               && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8885                                          MODE_INT, 1)) != BLKmode
8886               && tmode == GET_MODE (XEXP (varop, 0)))
8887             {
8888               if (BITS_BIG_ENDIAN)
8889                 new = XEXP (varop, 0);
8890               else
8891                 {
8892                   new = copy_rtx (XEXP (varop, 0));
8893                   SUBST (XEXP (new, 0),
8894                          plus_constant (XEXP (new, 0),
8895                                         count / BITS_PER_UNIT));
8896                 }
8897
8898               varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8899                                      : ZERO_EXTEND, mode, new);
8900               count = 0;
8901               continue;
8902             }
8903           break;
8904
8905         case SUBREG:
8906           /* If VAROP is a SUBREG, strip it as long as the inner operand has
8907              the same number of words as what we've seen so far.  Then store
8908              the widest mode in MODE.  */
8909           if (subreg_lowpart_p (varop)
8910               && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8911                   > GET_MODE_SIZE (GET_MODE (varop)))
8912               && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8913                                   + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8914                  == mode_words)
8915             {
8916               varop = SUBREG_REG (varop);
8917               if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8918                 mode = GET_MODE (varop);
8919               continue;
8920             }
8921           break;
8922
8923         case MULT:
8924           /* Some machines use MULT instead of ASHIFT because MULT
8925              is cheaper.  But it is still better on those machines to
8926              merge two shifts into one.  */
8927           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8928               && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8929             {
8930               varop
8931                 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
8932                                        XEXP (varop, 0),
8933                                        GEN_INT (exact_log2 (
8934                                                 INTVAL (XEXP (varop, 1)))));
8935               continue;
8936             }
8937           break;
8938
8939         case UDIV:
8940           /* Similar, for when divides are cheaper.  */
8941           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8942               && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8943             {
8944               varop
8945                 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
8946                                        XEXP (varop, 0),
8947                                        GEN_INT (exact_log2 (
8948                                                 INTVAL (XEXP (varop, 1)))));
8949               continue;
8950             }
8951           break;
8952
8953         case ASHIFTRT:
8954           /* If we are extracting just the sign bit of an arithmetic
8955              right shift, that shift is not needed.  However, the sign
8956              bit of a wider mode may be different from what would be
8957              interpreted as the sign bit in a narrower mode, so, if
8958              the result is narrower, don't discard the shift.  */
8959           if (code == LSHIFTRT
8960               && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
8961               && (GET_MODE_BITSIZE (result_mode)
8962                   >= GET_MODE_BITSIZE (GET_MODE (varop))))
8963             {
8964               varop = XEXP (varop, 0);
8965               continue;
8966             }
8967
8968           /* ... fall through ...  */
8969
8970         case LSHIFTRT:
8971         case ASHIFT:
8972         case ROTATE:
8973           /* Here we have two nested shifts.  The result is usually the
8974              AND of a new shift with a mask.  We compute the result below.  */
8975           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8976               && INTVAL (XEXP (varop, 1)) >= 0
8977               && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8978               && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8979               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8980               && !VECTOR_MODE_P (result_mode))
8981             {
8982               enum rtx_code first_code = GET_CODE (varop);
8983               unsigned int first_count = INTVAL (XEXP (varop, 1));
8984               unsigned HOST_WIDE_INT mask;
8985               rtx mask_rtx;
8986
8987               /* We have one common special case.  We can't do any merging if
8988                  the inner code is an ASHIFTRT of a smaller mode.  However, if
8989                  we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8990                  with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8991                  we can convert it to
8992                  (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8993                  This simplifies certain SIGN_EXTEND operations.  */
8994               if (code == ASHIFT && first_code == ASHIFTRT
8995                   && count == (unsigned int)
8996                               (GET_MODE_BITSIZE (result_mode)
8997                                - GET_MODE_BITSIZE (GET_MODE (varop))))
8998                 {
8999                   /* C3 has the low-order C1 bits zero.  */
9000
9001                   mask = (GET_MODE_MASK (mode)
9002                           & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9003
9004                   varop = simplify_and_const_int (NULL_RTX, result_mode,
9005                                                   XEXP (varop, 0), mask);
9006                   varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9007                                                 varop, count);
9008                   count = first_count;
9009                   code = ASHIFTRT;
9010                   continue;
9011                 }
9012
9013               /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9014                  than C1 high-order bits equal to the sign bit, we can convert
9015                  this to either an ASHIFT or an ASHIFTRT depending on the
9016                  two counts.
9017
9018                  We cannot do this if VAROP's mode is not SHIFT_MODE.  */
9019
9020               if (code == ASHIFTRT && first_code == ASHIFT
9021                   && GET_MODE (varop) == shift_mode
9022                   && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9023                       > first_count))
9024                 {
9025                   varop = XEXP (varop, 0);
9026
9027                   signed_count = count - first_count;
9028                   if (signed_count < 0)
9029                     count = -signed_count, code = ASHIFT;
9030                   else
9031                     count = signed_count;
9032
9033                   continue;
9034                 }
9035
9036               /* There are some cases we can't do.  If CODE is ASHIFTRT,
9037                  we can only do this if FIRST_CODE is also ASHIFTRT.
9038
9039                  We can't do the case when CODE is ROTATE and FIRST_CODE is
9040                  ASHIFTRT.
9041
9042                  If the mode of this shift is not the mode of the outer shift,
9043                  we can't do this if either shift is a right shift or ROTATE.
9044
9045                  Finally, we can't do any of these if the mode is too wide
9046                  unless the codes are the same.
9047
9048                  Handle the case where the shift codes are the same
9049                  first.  */
9050
9051               if (code == first_code)
9052                 {
9053                   if (GET_MODE (varop) != result_mode
9054                       && (code == ASHIFTRT || code == LSHIFTRT
9055                           || code == ROTATE))
9056                     break;
9057
9058                   count += first_count;
9059                   varop = XEXP (varop, 0);
9060                   continue;
9061                 }
9062
9063               if (code == ASHIFTRT
9064                   || (code == ROTATE && first_code == ASHIFTRT)
9065                   || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9066                   || (GET_MODE (varop) != result_mode
9067                       && (first_code == ASHIFTRT || first_code == LSHIFTRT
9068                           || first_code == ROTATE
9069                           || code == ROTATE)))
9070                 break;
9071
9072               /* To compute the mask to apply after the shift, shift the
9073                  nonzero bits of the inner shift the same way the
9074                  outer shift will.  */
9075
9076               mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9077
9078               mask_rtx
9079                 = simplify_binary_operation (code, result_mode, mask_rtx,
9080                                              GEN_INT (count));
9081
9082               /* Give up if we can't compute an outer operation to use.  */
9083               if (mask_rtx == 0
9084                   || GET_CODE (mask_rtx) != CONST_INT
9085                   || ! merge_outer_ops (&outer_op, &outer_const, AND,
9086                                         INTVAL (mask_rtx),
9087                                         result_mode, &complement_p))
9088                 break;
9089
9090               /* If the shifts are in the same direction, we add the
9091                  counts.  Otherwise, we subtract them.  */
9092               signed_count = count;
9093               if ((code == ASHIFTRT || code == LSHIFTRT)
9094                   == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9095                 signed_count += first_count;
9096               else
9097                 signed_count -= first_count;
9098
9099               /* If COUNT is positive, the new shift is usually CODE,
9100                  except for the two exceptions below, in which case it is
9101                  FIRST_CODE.  If the count is negative, FIRST_CODE should
9102                  always be used  */
9103               if (signed_count > 0
9104                   && ((first_code == ROTATE && code == ASHIFT)
9105                       || (first_code == ASHIFTRT && code == LSHIFTRT)))
9106                 code = first_code, count = signed_count;
9107               else if (signed_count < 0)
9108                 code = first_code, count = -signed_count;
9109               else
9110                 count = signed_count;
9111
9112               varop = XEXP (varop, 0);
9113               continue;
9114             }
9115
9116           /* If we have (A << B << C) for any shift, we can convert this to
9117              (A << C << B).  This wins if A is a constant.  Only try this if
9118              B is not a constant.  */
9119
9120           else if (GET_CODE (varop) == code
9121                    && GET_CODE (XEXP (varop, 1)) != CONST_INT
9122                    && 0 != (new
9123                             = simplify_binary_operation (code, mode,
9124                                                          XEXP (varop, 0),
9125                                                          GEN_INT (count))))
9126             {
9127               varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
9128               count = 0;
9129               continue;
9130             }
9131           break;
9132
9133         case NOT:
9134           /* Make this fit the case below.  */
9135           varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9136                                GEN_INT (GET_MODE_MASK (mode)));
9137           continue;
9138
9139         case IOR:
9140         case AND:
9141         case XOR:
9142           /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9143              with C the size of VAROP - 1 and the shift is logical if
9144              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9145              we have an (le X 0) operation.   If we have an arithmetic shift
9146              and STORE_FLAG_VALUE is 1 or we have a logical shift with
9147              STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation.  */
9148
9149           if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9150               && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9151               && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9152               && (code == LSHIFTRT || code == ASHIFTRT)
9153               && count == (unsigned int)
9154                           (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9155               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9156             {
9157               count = 0;
9158               varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9159                                   const0_rtx);
9160
9161               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9162                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9163
9164               continue;
9165             }
9166
9167           /* If we have (shift (logical)), move the logical to the outside
9168              to allow it to possibly combine with another logical and the
9169              shift to combine with another shift.  This also canonicalizes to
9170              what a ZERO_EXTRACT looks like.  Also, some machines have
9171              (and (shift)) insns.  */
9172
9173           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9174               /* We can't do this if we have (ashiftrt (xor))  and the
9175                  constant has its sign bit set in shift_mode.  */
9176               && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9177                    && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9178                                               shift_mode))
9179               && (new = simplify_binary_operation (code, result_mode,
9180                                                    XEXP (varop, 1),
9181                                                    GEN_INT (count))) != 0
9182               && GET_CODE (new) == CONST_INT
9183               && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9184                                   INTVAL (new), result_mode, &complement_p))
9185             {
9186               varop = XEXP (varop, 0);
9187               continue;
9188             }
9189
9190           /* If we can't do that, try to simplify the shift in each arm of the
9191              logical expression, make a new logical expression, and apply
9192              the inverse distributive law.  This also can't be done
9193              for some (ashiftrt (xor)).  */
9194           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9195              && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9196                   && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9197                                              shift_mode)))
9198             {
9199               rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9200                                               XEXP (varop, 0), count);
9201               rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9202                                               XEXP (varop, 1), count);
9203
9204               varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
9205                                            lhs, rhs);
9206               varop = apply_distributive_law (varop);
9207
9208               count = 0;
9209               continue;
9210             }
9211           break;
9212
9213         case EQ:
9214           /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9215              says that the sign bit can be tested, FOO has mode MODE, C is
9216              GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9217              that may be nonzero.  */
9218           if (code == LSHIFTRT
9219               && XEXP (varop, 1) == const0_rtx
9220               && GET_MODE (XEXP (varop, 0)) == result_mode
9221               && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9222               && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9223               && ((STORE_FLAG_VALUE
9224                    & ((HOST_WIDE_INT) 1
9225                       < (GET_MODE_BITSIZE (result_mode) - 1))))
9226               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9227               && merge_outer_ops (&outer_op, &outer_const, XOR,
9228                                   (HOST_WIDE_INT) 1, result_mode,
9229                                   &complement_p))
9230             {
9231               varop = XEXP (varop, 0);
9232               count = 0;
9233               continue;
9234             }
9235           break;
9236
9237         case NEG:
9238           /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9239              than the number of bits in the mode is equivalent to A.  */
9240           if (code == LSHIFTRT
9241               && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9242               && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9243             {
9244               varop = XEXP (varop, 0);
9245               count = 0;
9246               continue;
9247             }
9248
9249           /* NEG commutes with ASHIFT since it is multiplication.  Move the
9250              NEG outside to allow shifts to combine.  */
9251           if (code == ASHIFT
9252               && merge_outer_ops (&outer_op, &outer_const, NEG,
9253                                   (HOST_WIDE_INT) 0, result_mode,
9254                                   &complement_p))
9255             {
9256               varop = XEXP (varop, 0);
9257               continue;
9258             }
9259           break;
9260
9261         case PLUS:
9262           /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9263              is one less than the number of bits in the mode is
9264              equivalent to (xor A 1).  */
9265           if (code == LSHIFTRT
9266               && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9267               && XEXP (varop, 1) == constm1_rtx
9268               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9269               && merge_outer_ops (&outer_op, &outer_const, XOR,
9270                                   (HOST_WIDE_INT) 1, result_mode,
9271                                   &complement_p))
9272             {
9273               count = 0;
9274               varop = XEXP (varop, 0);
9275               continue;
9276             }
9277
9278           /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9279              that might be nonzero in BAR are those being shifted out and those
9280              bits are known zero in FOO, we can replace the PLUS with FOO.
9281              Similarly in the other operand order.  This code occurs when
9282              we are computing the size of a variable-size array.  */
9283
9284           if ((code == ASHIFTRT || code == LSHIFTRT)
9285               && count < HOST_BITS_PER_WIDE_INT
9286               && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9287               && (nonzero_bits (XEXP (varop, 1), result_mode)
9288                   & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9289             {
9290               varop = XEXP (varop, 0);
9291               continue;
9292             }
9293           else if ((code == ASHIFTRT || code == LSHIFTRT)
9294                    && count < HOST_BITS_PER_WIDE_INT
9295                    && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9296                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9297                             >> count)
9298                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9299                             & nonzero_bits (XEXP (varop, 1),
9300                                                  result_mode)))
9301             {
9302               varop = XEXP (varop, 1);
9303               continue;
9304             }
9305
9306           /* (ashift (plus foo C) N) is (plus (ashift foo N) C').  */
9307           if (code == ASHIFT
9308               && GET_CODE (XEXP (varop, 1)) == CONST_INT
9309               && (new = simplify_binary_operation (ASHIFT, result_mode,
9310                                                    XEXP (varop, 1),
9311                                                    GEN_INT (count))) != 0
9312               && GET_CODE (new) == CONST_INT
9313               && merge_outer_ops (&outer_op, &outer_const, PLUS,
9314                                   INTVAL (new), result_mode, &complement_p))
9315             {
9316               varop = XEXP (varop, 0);
9317               continue;
9318             }
9319
9320           /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9321              signbit', and attempt to change the PLUS to an XOR and move it to
9322              the outer operation as is done above in the AND/IOR/XOR case
9323              leg for shift(logical). See details in logical handling above
9324              for reasoning in doing so.  */
9325           if (code == LSHIFTRT
9326               && GET_CODE (XEXP (varop, 1)) == CONST_INT
9327               && mode_signbit_p (result_mode, XEXP (varop, 1))
9328               && (new = simplify_binary_operation (code, result_mode,
9329                                                    XEXP (varop, 1),
9330                                                    GEN_INT (count))) != 0
9331               && GET_CODE (new) == CONST_INT
9332               && merge_outer_ops (&outer_op, &outer_const, XOR,
9333                                   INTVAL (new), result_mode, &complement_p))
9334             {
9335               varop = XEXP (varop, 0);
9336               continue;
9337             }
9338
9339           break;
9340
9341         case MINUS:
9342           /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9343              with C the size of VAROP - 1 and the shift is logical if
9344              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9345              we have a (gt X 0) operation.  If the shift is arithmetic with
9346              STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9347              we have a (neg (gt X 0)) operation.  */
9348
9349           if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9350               && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9351               && count == (unsigned int)
9352                           (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9353               && (code == LSHIFTRT || code == ASHIFTRT)
9354               && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9355               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (varop, 0), 1))
9356                  == count
9357               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9358             {
9359               count = 0;
9360               varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9361                                   const0_rtx);
9362
9363               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9364                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9365
9366               continue;
9367             }
9368           break;
9369
9370         case TRUNCATE:
9371           /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9372              if the truncate does not affect the value.  */
9373           if (code == LSHIFTRT
9374               && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9375               && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9376               && (INTVAL (XEXP (XEXP (varop, 0), 1))
9377                   >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9378                       - GET_MODE_BITSIZE (GET_MODE (varop)))))
9379             {
9380               rtx varop_inner = XEXP (varop, 0);
9381
9382               varop_inner
9383                 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9384                                     XEXP (varop_inner, 0),
9385                                     GEN_INT
9386                                     (count + INTVAL (XEXP (varop_inner, 1))));
9387               varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9388               count = 0;
9389               continue;
9390             }
9391           break;
9392
9393         default:
9394           break;
9395         }
9396
9397       break;
9398     }
9399
9400   /* We need to determine what mode to do the shift in.  If the shift is
9401      a right shift or ROTATE, we must always do it in the mode it was
9402      originally done in.  Otherwise, we can do it in MODE, the widest mode
9403      encountered.  The code we care about is that of the shift that will
9404      actually be done, not the shift that was originally requested.  */
9405   shift_mode
9406     = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9407        ? result_mode : mode);
9408
9409   /* We have now finished analyzing the shift.  The result should be
9410      a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places.  If
9411      OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9412      to the result of the shift.  OUTER_CONST is the relevant constant,
9413      but we must turn off all bits turned off in the shift.
9414
9415      If we were passed a value for X, see if we can use any pieces of
9416      it.  If not, make new rtx.  */
9417
9418   if (x && GET_RTX_CLASS (GET_CODE (x)) == RTX_BIN_ARITH
9419       && GET_CODE (XEXP (x, 1)) == CONST_INT
9420       && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == count)
9421     const_rtx = XEXP (x, 1);
9422   else
9423     const_rtx = GEN_INT (count);
9424
9425   if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9426       && GET_MODE (XEXP (x, 0)) == shift_mode
9427       && SUBREG_REG (XEXP (x, 0)) == varop)
9428     varop = XEXP (x, 0);
9429   else if (GET_MODE (varop) != shift_mode)
9430     varop = gen_lowpart (shift_mode, varop);
9431
9432   /* If we can't make the SUBREG, try to return what we were given.  */
9433   if (GET_CODE (varop) == CLOBBER)
9434     return x ? x : varop;
9435
9436   new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9437   if (new != 0)
9438     x = new;
9439   else
9440     x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
9441
9442   /* If we have an outer operation and we just made a shift, it is
9443      possible that we could have simplified the shift were it not
9444      for the outer operation.  So try to do the simplification
9445      recursively.  */
9446
9447   if (outer_op != UNKNOWN && GET_CODE (x) == code
9448       && GET_CODE (XEXP (x, 1)) == CONST_INT)
9449     x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9450                               INTVAL (XEXP (x, 1)));
9451
9452   /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9453      turn off all the bits that the shift would have turned off.  */
9454   if (orig_code == LSHIFTRT && result_mode != shift_mode)
9455     x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9456                                 GET_MODE_MASK (result_mode) >> orig_count);
9457
9458   /* Do the remainder of the processing in RESULT_MODE.  */
9459   x = gen_lowpart (result_mode, x);
9460
9461   /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9462      operation.  */
9463   if (complement_p)
9464     x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9465
9466   if (outer_op != UNKNOWN)
9467     {
9468       if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9469         outer_const = trunc_int_for_mode (outer_const, result_mode);
9470
9471       if (outer_op == AND)
9472         x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9473       else if (outer_op == SET)
9474         {
9475           /* This means that we have determined that the result is
9476              equivalent to a constant.  This should be rare.  */
9477           if (!side_effects_p (x))
9478             x = GEN_INT (outer_const);
9479         }
9480       else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
9481         x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9482       else
9483         x = simplify_gen_binary (outer_op, result_mode, x,
9484                                  GEN_INT (outer_const));
9485     }
9486
9487   return x;
9488 }
9489 \f
9490 /* Like recog, but we receive the address of a pointer to a new pattern.
9491    We try to match the rtx that the pointer points to.
9492    If that fails, we may try to modify or replace the pattern,
9493    storing the replacement into the same pointer object.
9494
9495    Modifications include deletion or addition of CLOBBERs.
9496
9497    PNOTES is a pointer to a location where any REG_UNUSED notes added for
9498    the CLOBBERs are placed.
9499
9500    The value is the final insn code from the pattern ultimately matched,
9501    or -1.  */
9502
9503 static int
9504 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9505 {
9506   rtx pat = *pnewpat;
9507   int insn_code_number;
9508   int num_clobbers_to_add = 0;
9509   int i;
9510   rtx notes = 0;
9511   rtx old_notes, old_pat;
9512
9513   /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9514      we use to indicate that something didn't match.  If we find such a
9515      thing, force rejection.  */
9516   if (GET_CODE (pat) == PARALLEL)
9517     for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9518       if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9519           && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9520         return -1;
9521
9522   old_pat = PATTERN (insn);
9523   old_notes = REG_NOTES (insn);
9524   PATTERN (insn) = pat;
9525   REG_NOTES (insn) = 0;
9526
9527   insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9528
9529   /* If it isn't, there is the possibility that we previously had an insn
9530      that clobbered some register as a side effect, but the combined
9531      insn doesn't need to do that.  So try once more without the clobbers
9532      unless this represents an ASM insn.  */
9533
9534   if (insn_code_number < 0 && ! check_asm_operands (pat)
9535       && GET_CODE (pat) == PARALLEL)
9536     {
9537       int pos;
9538
9539       for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9540         if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9541           {
9542             if (i != pos)
9543               SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9544             pos++;
9545           }
9546
9547       SUBST_INT (XVECLEN (pat, 0), pos);
9548
9549       if (pos == 1)
9550         pat = XVECEXP (pat, 0, 0);
9551
9552       PATTERN (insn) = pat;
9553       insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9554     }
9555   PATTERN (insn) = old_pat;
9556   REG_NOTES (insn) = old_notes;
9557
9558   /* Recognize all noop sets, these will be killed by followup pass.  */
9559   if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9560     insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9561
9562   /* If we had any clobbers to add, make a new pattern than contains
9563      them.  Then check to make sure that all of them are dead.  */
9564   if (num_clobbers_to_add)
9565     {
9566       rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9567                                      rtvec_alloc (GET_CODE (pat) == PARALLEL
9568                                                   ? (XVECLEN (pat, 0)
9569                                                      + num_clobbers_to_add)
9570                                                   : num_clobbers_to_add + 1));
9571
9572       if (GET_CODE (pat) == PARALLEL)
9573         for (i = 0; i < XVECLEN (pat, 0); i++)
9574           XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9575       else
9576         XVECEXP (newpat, 0, 0) = pat;
9577
9578       add_clobbers (newpat, insn_code_number);
9579
9580       for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9581            i < XVECLEN (newpat, 0); i++)
9582         {
9583           if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
9584               && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9585             return -1;
9586           notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9587                                      XEXP (XVECEXP (newpat, 0, i), 0), notes);
9588         }
9589       pat = newpat;
9590     }
9591
9592   *pnewpat = pat;
9593   *pnotes = notes;
9594
9595   return insn_code_number;
9596 }
9597 \f
9598 /* Like gen_lowpart_general but for use by combine.  In combine it
9599    is not possible to create any new pseudoregs.  However, it is
9600    safe to create invalid memory addresses, because combine will
9601    try to recognize them and all they will do is make the combine
9602    attempt fail.
9603
9604    If for some reason this cannot do its job, an rtx
9605    (clobber (const_int 0)) is returned.
9606    An insn containing that will not be recognized.  */
9607
9608 static rtx
9609 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
9610 {
9611   enum machine_mode imode = GET_MODE (x);
9612   unsigned int osize = GET_MODE_SIZE (omode);
9613   unsigned int isize = GET_MODE_SIZE (imode);
9614   rtx result;
9615
9616   if (omode == imode)
9617     return x;
9618
9619   /* Return identity if this is a CONST or symbolic reference.  */
9620   if (omode == Pmode
9621       && (GET_CODE (x) == CONST
9622           || GET_CODE (x) == SYMBOL_REF
9623           || GET_CODE (x) == LABEL_REF))
9624     return x;
9625
9626   /* We can only support MODE being wider than a word if X is a
9627      constant integer or has a mode the same size.  */
9628   if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
9629       && ! ((imode == VOIDmode
9630              && (GET_CODE (x) == CONST_INT
9631                  || GET_CODE (x) == CONST_DOUBLE))
9632             || isize == osize))
9633     goto fail;
9634
9635   /* X might be a paradoxical (subreg (mem)).  In that case, gen_lowpart
9636      won't know what to do.  So we will strip off the SUBREG here and
9637      process normally.  */
9638   if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
9639     {
9640       x = SUBREG_REG (x);
9641
9642       /* For use in case we fall down into the address adjustments
9643          further below, we need to adjust the known mode and size of
9644          x; imode and isize, since we just adjusted x.  */
9645       imode = GET_MODE (x);
9646
9647       if (imode == omode)
9648         return x;
9649
9650       isize = GET_MODE_SIZE (imode);
9651     }
9652
9653   result = gen_lowpart_common (omode, x);
9654
9655 #ifdef CANNOT_CHANGE_MODE_CLASS
9656   if (result != 0 && GET_CODE (result) == SUBREG)
9657     record_subregs_of_mode (result);
9658 #endif
9659
9660   if (result)
9661     return result;
9662
9663   if (MEM_P (x))
9664     {
9665       int offset = 0;
9666
9667       /* Refuse to work on a volatile memory ref or one with a mode-dependent
9668          address.  */
9669       if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9670         goto fail;
9671
9672       /* If we want to refer to something bigger than the original memref,
9673          generate a paradoxical subreg instead.  That will force a reload
9674          of the original memref X.  */
9675       if (isize < osize)
9676         return gen_rtx_SUBREG (omode, x, 0);
9677
9678       if (WORDS_BIG_ENDIAN)
9679         offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
9680
9681       /* Adjust the address so that the address-after-the-data is
9682          unchanged.  */
9683       if (BYTES_BIG_ENDIAN)
9684         offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
9685
9686       return adjust_address_nv (x, omode, offset);
9687     }
9688
9689   /* If X is a comparison operator, rewrite it in a new mode.  This
9690      probably won't match, but may allow further simplifications.  */
9691   else if (COMPARISON_P (x))
9692     return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
9693
9694   /* If we couldn't simplify X any other way, just enclose it in a
9695      SUBREG.  Normally, this SUBREG won't match, but some patterns may
9696      include an explicit SUBREG or we may simplify it further in combine.  */
9697   else
9698     {
9699       int offset = 0;
9700       rtx res;
9701
9702       offset = subreg_lowpart_offset (omode, imode);
9703       if (imode == VOIDmode)
9704         {
9705           imode = int_mode_for_mode (omode);
9706           x = gen_lowpart_common (imode, x);
9707           if (x == NULL)
9708             goto fail;
9709         }
9710       res = simplify_gen_subreg (omode, x, imode, offset);
9711       if (res)
9712         return res;
9713     }
9714
9715  fail:
9716   return gen_rtx_CLOBBER (imode, const0_rtx);
9717 }
9718 \f
9719 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9720    comparison code that will be tested.
9721
9722    The result is a possibly different comparison code to use.  *POP0 and
9723    *POP1 may be updated.
9724
9725    It is possible that we might detect that a comparison is either always
9726    true or always false.  However, we do not perform general constant
9727    folding in combine, so this knowledge isn't useful.  Such tautologies
9728    should have been detected earlier.  Hence we ignore all such cases.  */
9729
9730 static enum rtx_code
9731 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
9732 {
9733   rtx op0 = *pop0;
9734   rtx op1 = *pop1;
9735   rtx tem, tem1;
9736   int i;
9737   enum machine_mode mode, tmode;
9738
9739   /* Try a few ways of applying the same transformation to both operands.  */
9740   while (1)
9741     {
9742 #ifndef WORD_REGISTER_OPERATIONS
9743       /* The test below this one won't handle SIGN_EXTENDs on these machines,
9744          so check specially.  */
9745       if (code != GTU && code != GEU && code != LTU && code != LEU
9746           && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9747           && GET_CODE (XEXP (op0, 0)) == ASHIFT
9748           && GET_CODE (XEXP (op1, 0)) == ASHIFT
9749           && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9750           && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9751           && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9752               == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9753           && GET_CODE (XEXP (op0, 1)) == CONST_INT
9754           && XEXP (op0, 1) == XEXP (op1, 1)
9755           && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
9756           && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
9757           && (INTVAL (XEXP (op0, 1))
9758               == (GET_MODE_BITSIZE (GET_MODE (op0))
9759                   - (GET_MODE_BITSIZE
9760                      (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9761         {
9762           op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9763           op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9764         }
9765 #endif
9766
9767       /* If both operands are the same constant shift, see if we can ignore the
9768          shift.  We can if the shift is a rotate or if the bits shifted out of
9769          this shift are known to be zero for both inputs and if the type of
9770          comparison is compatible with the shift.  */
9771       if (GET_CODE (op0) == GET_CODE (op1)
9772           && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9773           && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9774               || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9775                   && (code != GT && code != LT && code != GE && code != LE))
9776               || (GET_CODE (op0) == ASHIFTRT
9777                   && (code != GTU && code != LTU
9778                       && code != GEU && code != LEU)))
9779           && GET_CODE (XEXP (op0, 1)) == CONST_INT
9780           && INTVAL (XEXP (op0, 1)) >= 0
9781           && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9782           && XEXP (op0, 1) == XEXP (op1, 1))
9783         {
9784           enum machine_mode mode = GET_MODE (op0);
9785           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9786           int shift_count = INTVAL (XEXP (op0, 1));
9787
9788           if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9789             mask &= (mask >> shift_count) << shift_count;
9790           else if (GET_CODE (op0) == ASHIFT)
9791             mask = (mask & (mask << shift_count)) >> shift_count;
9792
9793           if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
9794               && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
9795             op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9796           else
9797             break;
9798         }
9799
9800       /* If both operands are AND's of a paradoxical SUBREG by constant, the
9801          SUBREGs are of the same mode, and, in both cases, the AND would
9802          be redundant if the comparison was done in the narrower mode,
9803          do the comparison in the narrower mode (e.g., we are AND'ing with 1
9804          and the operand's possibly nonzero bits are 0xffffff01; in that case
9805          if we only care about QImode, we don't need the AND).  This case
9806          occurs if the output mode of an scc insn is not SImode and
9807          STORE_FLAG_VALUE == 1 (e.g., the 386).
9808
9809          Similarly, check for a case where the AND's are ZERO_EXTEND
9810          operations from some narrower mode even though a SUBREG is not
9811          present.  */
9812
9813       else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9814                && GET_CODE (XEXP (op0, 1)) == CONST_INT
9815                && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9816         {
9817           rtx inner_op0 = XEXP (op0, 0);
9818           rtx inner_op1 = XEXP (op1, 0);
9819           HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9820           HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9821           int changed = 0;
9822
9823           if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9824               && (GET_MODE_SIZE (GET_MODE (inner_op0))
9825                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9826               && (GET_MODE (SUBREG_REG (inner_op0))
9827                   == GET_MODE (SUBREG_REG (inner_op1)))
9828               && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
9829                   <= HOST_BITS_PER_WIDE_INT)
9830               && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9831                                              GET_MODE (SUBREG_REG (inner_op0)))))
9832               && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9833                                              GET_MODE (SUBREG_REG (inner_op1))))))
9834             {
9835               op0 = SUBREG_REG (inner_op0);
9836               op1 = SUBREG_REG (inner_op1);
9837
9838               /* The resulting comparison is always unsigned since we masked
9839                  off the original sign bit.  */
9840               code = unsigned_condition (code);
9841
9842               changed = 1;
9843             }
9844
9845           else if (c0 == c1)
9846             for (tmode = GET_CLASS_NARROWEST_MODE
9847                  (GET_MODE_CLASS (GET_MODE (op0)));
9848                  tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9849               if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
9850                 {
9851                   op0 = gen_lowpart (tmode, inner_op0);
9852                   op1 = gen_lowpart (tmode, inner_op1);
9853                   code = unsigned_condition (code);
9854                   changed = 1;
9855                   break;
9856                 }
9857
9858           if (! changed)
9859             break;
9860         }
9861
9862       /* If both operands are NOT, we can strip off the outer operation
9863          and adjust the comparison code for swapped operands; similarly for
9864          NEG, except that this must be an equality comparison.  */
9865       else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9866                || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9867                    && (code == EQ || code == NE)))
9868         op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9869
9870       else
9871         break;
9872     }
9873
9874   /* If the first operand is a constant, swap the operands and adjust the
9875      comparison code appropriately, but don't do this if the second operand
9876      is already a constant integer.  */
9877   if (swap_commutative_operands_p (op0, op1))
9878     {
9879       tem = op0, op0 = op1, op1 = tem;
9880       code = swap_condition (code);
9881     }
9882
9883   /* We now enter a loop during which we will try to simplify the comparison.
9884      For the most part, we only are concerned with comparisons with zero,
9885      but some things may really be comparisons with zero but not start
9886      out looking that way.  */
9887
9888   while (GET_CODE (op1) == CONST_INT)
9889     {
9890       enum machine_mode mode = GET_MODE (op0);
9891       unsigned int mode_width = GET_MODE_BITSIZE (mode);
9892       unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9893       int equality_comparison_p;
9894       int sign_bit_comparison_p;
9895       int unsigned_comparison_p;
9896       HOST_WIDE_INT const_op;
9897
9898       /* We only want to handle integral modes.  This catches VOIDmode,
9899          CCmode, and the floating-point modes.  An exception is that we
9900          can handle VOIDmode if OP0 is a COMPARE or a comparison
9901          operation.  */
9902
9903       if (GET_MODE_CLASS (mode) != MODE_INT
9904           && ! (mode == VOIDmode
9905                 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
9906         break;
9907
9908       /* Get the constant we are comparing against and turn off all bits
9909          not on in our mode.  */
9910       const_op = INTVAL (op1);
9911       if (mode != VOIDmode)
9912         const_op = trunc_int_for_mode (const_op, mode);
9913       op1 = GEN_INT (const_op);
9914
9915       /* If we are comparing against a constant power of two and the value
9916          being compared can only have that single bit nonzero (e.g., it was
9917          `and'ed with that bit), we can replace this with a comparison
9918          with zero.  */
9919       if (const_op
9920           && (code == EQ || code == NE || code == GE || code == GEU
9921               || code == LT || code == LTU)
9922           && mode_width <= HOST_BITS_PER_WIDE_INT
9923           && exact_log2 (const_op) >= 0
9924           && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
9925         {
9926           code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9927           op1 = const0_rtx, const_op = 0;
9928         }
9929
9930       /* Similarly, if we are comparing a value known to be either -1 or
9931          0 with -1, change it to the opposite comparison against zero.  */
9932
9933       if (const_op == -1
9934           && (code == EQ || code == NE || code == GT || code == LE
9935               || code == GEU || code == LTU)
9936           && num_sign_bit_copies (op0, mode) == mode_width)
9937         {
9938           code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9939           op1 = const0_rtx, const_op = 0;
9940         }
9941
9942       /* Do some canonicalizations based on the comparison code.  We prefer
9943          comparisons against zero and then prefer equality comparisons.
9944          If we can reduce the size of a constant, we will do that too.  */
9945
9946       switch (code)
9947         {
9948         case LT:
9949           /* < C is equivalent to <= (C - 1) */
9950           if (const_op > 0)
9951             {
9952               const_op -= 1;
9953               op1 = GEN_INT (const_op);
9954               code = LE;
9955               /* ... fall through to LE case below.  */
9956             }
9957           else
9958             break;
9959
9960         case LE:
9961           /* <= C is equivalent to < (C + 1); we do this for C < 0  */
9962           if (const_op < 0)
9963             {
9964               const_op += 1;
9965               op1 = GEN_INT (const_op);
9966               code = LT;
9967             }
9968
9969           /* If we are doing a <= 0 comparison on a value known to have
9970              a zero sign bit, we can replace this with == 0.  */
9971           else if (const_op == 0
9972                    && mode_width <= HOST_BITS_PER_WIDE_INT
9973                    && (nonzero_bits (op0, mode)
9974                        & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9975             code = EQ;
9976           break;
9977
9978         case GE:
9979           /* >= C is equivalent to > (C - 1).  */
9980           if (const_op > 0)
9981             {
9982               const_op -= 1;
9983               op1 = GEN_INT (const_op);
9984               code = GT;
9985               /* ... fall through to GT below.  */
9986             }
9987           else
9988             break;
9989
9990         case GT:
9991           /* > C is equivalent to >= (C + 1); we do this for C < 0.  */
9992           if (const_op < 0)
9993             {
9994               const_op += 1;
9995               op1 = GEN_INT (const_op);
9996               code = GE;
9997             }
9998
9999           /* If we are doing a > 0 comparison on a value known to have
10000              a zero sign bit, we can replace this with != 0.  */
10001           else if (const_op == 0
10002                    && mode_width <= HOST_BITS_PER_WIDE_INT
10003                    && (nonzero_bits (op0, mode)
10004                        & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10005             code = NE;
10006           break;
10007
10008         case LTU:
10009           /* < C is equivalent to <= (C - 1).  */
10010           if (const_op > 0)
10011             {
10012               const_op -= 1;
10013               op1 = GEN_INT (const_op);
10014               code = LEU;
10015               /* ... fall through ...  */
10016             }
10017
10018           /* (unsigned) < 0x80000000 is equivalent to >= 0.  */
10019           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10020                    && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10021             {
10022               const_op = 0, op1 = const0_rtx;
10023               code = GE;
10024               break;
10025             }
10026           else
10027             break;
10028
10029         case LEU:
10030           /* unsigned <= 0 is equivalent to == 0 */
10031           if (const_op == 0)
10032             code = EQ;
10033
10034           /* (unsigned) <= 0x7fffffff is equivalent to >= 0.  */
10035           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10036                    && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10037             {
10038               const_op = 0, op1 = const0_rtx;
10039               code = GE;
10040             }
10041           break;
10042
10043         case GEU:
10044           /* >= C is equivalent to > (C - 1).  */
10045           if (const_op > 1)
10046             {
10047               const_op -= 1;
10048               op1 = GEN_INT (const_op);
10049               code = GTU;
10050               /* ... fall through ...  */
10051             }
10052
10053           /* (unsigned) >= 0x80000000 is equivalent to < 0.  */
10054           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10055                    && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10056             {
10057               const_op = 0, op1 = const0_rtx;
10058               code = LT;
10059               break;
10060             }
10061           else
10062             break;
10063
10064         case GTU:
10065           /* unsigned > 0 is equivalent to != 0 */
10066           if (const_op == 0)
10067             code = NE;
10068
10069           /* (unsigned) > 0x7fffffff is equivalent to < 0.  */
10070           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10071                    && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10072             {
10073               const_op = 0, op1 = const0_rtx;
10074               code = LT;
10075             }
10076           break;
10077
10078         default:
10079           break;
10080         }
10081
10082       /* Compute some predicates to simplify code below.  */
10083
10084       equality_comparison_p = (code == EQ || code == NE);
10085       sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10086       unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10087                                || code == GEU);
10088
10089       /* If this is a sign bit comparison and we can do arithmetic in
10090          MODE, say that we will only be needing the sign bit of OP0.  */
10091       if (sign_bit_comparison_p
10092           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10093         op0 = force_to_mode (op0, mode,
10094                              ((HOST_WIDE_INT) 1
10095                               << (GET_MODE_BITSIZE (mode) - 1)),
10096                              NULL_RTX, 0);
10097
10098       /* Now try cases based on the opcode of OP0.  If none of the cases
10099          does a "continue", we exit this loop immediately after the
10100          switch.  */
10101
10102       switch (GET_CODE (op0))
10103         {
10104         case ZERO_EXTRACT:
10105           /* If we are extracting a single bit from a variable position in
10106              a constant that has only a single bit set and are comparing it
10107              with zero, we can convert this into an equality comparison
10108              between the position and the location of the single bit.  */
10109           /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10110              have already reduced the shift count modulo the word size.  */
10111           if (!SHIFT_COUNT_TRUNCATED
10112               && GET_CODE (XEXP (op0, 0)) == CONST_INT
10113               && XEXP (op0, 1) == const1_rtx
10114               && equality_comparison_p && const_op == 0
10115               && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10116             {
10117               if (BITS_BIG_ENDIAN)
10118                 {
10119                   enum machine_mode new_mode
10120                     = mode_for_extraction (EP_extzv, 1);
10121                   if (new_mode == MAX_MACHINE_MODE)
10122                     i = BITS_PER_WORD - 1 - i;
10123                   else
10124                     {
10125                       mode = new_mode;
10126                       i = (GET_MODE_BITSIZE (mode) - 1 - i);
10127                     }
10128                 }
10129
10130               op0 = XEXP (op0, 2);
10131               op1 = GEN_INT (i);
10132               const_op = i;
10133
10134               /* Result is nonzero iff shift count is equal to I.  */
10135               code = reverse_condition (code);
10136               continue;
10137             }
10138
10139           /* ... fall through ...  */
10140
10141         case SIGN_EXTRACT:
10142           tem = expand_compound_operation (op0);
10143           if (tem != op0)
10144             {
10145               op0 = tem;
10146               continue;
10147             }
10148           break;
10149
10150         case NOT:
10151           /* If testing for equality, we can take the NOT of the constant.  */
10152           if (equality_comparison_p
10153               && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10154             {
10155               op0 = XEXP (op0, 0);
10156               op1 = tem;
10157               continue;
10158             }
10159
10160           /* If just looking at the sign bit, reverse the sense of the
10161              comparison.  */
10162           if (sign_bit_comparison_p)
10163             {
10164               op0 = XEXP (op0, 0);
10165               code = (code == GE ? LT : GE);
10166               continue;
10167             }
10168           break;
10169
10170         case NEG:
10171           /* If testing for equality, we can take the NEG of the constant.  */
10172           if (equality_comparison_p
10173               && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10174             {
10175               op0 = XEXP (op0, 0);
10176               op1 = tem;
10177               continue;
10178             }
10179
10180           /* The remaining cases only apply to comparisons with zero.  */
10181           if (const_op != 0)
10182             break;
10183
10184           /* When X is ABS or is known positive,
10185              (neg X) is < 0 if and only if X != 0.  */
10186
10187           if (sign_bit_comparison_p
10188               && (GET_CODE (XEXP (op0, 0)) == ABS
10189                   || (mode_width <= HOST_BITS_PER_WIDE_INT
10190                       && (nonzero_bits (XEXP (op0, 0), mode)
10191                           & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10192             {
10193               op0 = XEXP (op0, 0);
10194               code = (code == LT ? NE : EQ);
10195               continue;
10196             }
10197
10198           /* If we have NEG of something whose two high-order bits are the
10199              same, we know that "(-a) < 0" is equivalent to "a > 0".  */
10200           if (num_sign_bit_copies (op0, mode) >= 2)
10201             {
10202               op0 = XEXP (op0, 0);
10203               code = swap_condition (code);
10204               continue;
10205             }
10206           break;
10207
10208         case ROTATE:
10209           /* If we are testing equality and our count is a constant, we
10210              can perform the inverse operation on our RHS.  */
10211           if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10212               && (tem = simplify_binary_operation (ROTATERT, mode,
10213                                                    op1, XEXP (op0, 1))) != 0)
10214             {
10215               op0 = XEXP (op0, 0);
10216               op1 = tem;
10217               continue;
10218             }
10219
10220           /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10221              a particular bit.  Convert it to an AND of a constant of that
10222              bit.  This will be converted into a ZERO_EXTRACT.  */
10223           if (const_op == 0 && sign_bit_comparison_p
10224               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10225               && mode_width <= HOST_BITS_PER_WIDE_INT)
10226             {
10227               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10228                                             ((HOST_WIDE_INT) 1
10229                                              << (mode_width - 1
10230                                                  - INTVAL (XEXP (op0, 1)))));
10231               code = (code == LT ? NE : EQ);
10232               continue;
10233             }
10234
10235           /* Fall through.  */
10236
10237         case ABS:
10238           /* ABS is ignorable inside an equality comparison with zero.  */
10239           if (const_op == 0 && equality_comparison_p)
10240             {
10241               op0 = XEXP (op0, 0);
10242               continue;
10243             }
10244           break;
10245
10246         case SIGN_EXTEND:
10247           /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10248              (compare FOO CONST) if CONST fits in FOO's mode and we
10249              are either testing inequality or have an unsigned
10250              comparison with ZERO_EXTEND or a signed comparison with
10251              SIGN_EXTEND.  But don't do it if we don't have a compare
10252              insn of the given mode, since we'd have to revert it
10253              later on, and then we wouldn't know whether to sign- or
10254              zero-extend.  */
10255           mode = GET_MODE (XEXP (op0, 0));
10256           if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10257               && ! unsigned_comparison_p
10258               && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10259               && ((unsigned HOST_WIDE_INT) const_op
10260                   < (((unsigned HOST_WIDE_INT) 1
10261                       << (GET_MODE_BITSIZE (mode) - 1))))
10262               && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10263             {
10264               op0 = XEXP (op0, 0);
10265               continue;
10266             }
10267           break;
10268
10269         case SUBREG:
10270           /* Check for the case where we are comparing A - C1 with C2, that is
10271
10272                (subreg:MODE (plus (A) (-C1))) op (C2)
10273
10274              with C1 a constant, and try to lift the SUBREG, i.e. to do the
10275              comparison in the wider mode.  One of the following two conditions
10276              must be true in order for this to be valid:
10277
10278                1. The mode extension results in the same bit pattern being added
10279                   on both sides and the comparison is equality or unsigned.  As
10280                   C2 has been truncated to fit in MODE, the pattern can only be
10281                   all 0s or all 1s.
10282
10283                2. The mode extension results in the sign bit being copied on
10284                   each side.
10285
10286              The difficulty here is that we have predicates for A but not for
10287              (A - C1) so we need to check that C1 is within proper bounds so
10288              as to perturbate A as little as possible.  */
10289
10290           if (mode_width <= HOST_BITS_PER_WIDE_INT
10291               && subreg_lowpart_p (op0)
10292               && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10293               && GET_CODE (SUBREG_REG (op0)) == PLUS
10294               && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT)
10295             {
10296               enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10297               rtx a = XEXP (SUBREG_REG (op0), 0);
10298               HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10299
10300               if ((c1 > 0
10301                    && (unsigned HOST_WIDE_INT) c1
10302                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10303                    && (equality_comparison_p || unsigned_comparison_p)
10304                    /* (A - C1) zero-extends if it is positive and sign-extends
10305                       if it is negative, C2 both zero- and sign-extends.  */
10306                    && ((0 == (nonzero_bits (a, inner_mode)
10307                               & ~GET_MODE_MASK (mode))
10308                         && const_op >= 0)
10309                        /* (A - C1) sign-extends if it is positive and 1-extends
10310                           if it is negative, C2 both sign- and 1-extends.  */
10311                        || (num_sign_bit_copies (a, inner_mode)
10312                            > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10313                                              - mode_width)
10314                            && const_op < 0)))
10315                   || ((unsigned HOST_WIDE_INT) c1
10316                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10317                       /* (A - C1) always sign-extends, like C2.  */
10318                       && num_sign_bit_copies (a, inner_mode)
10319                          > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10320                                            - (mode_width - 1))))
10321                 {
10322                   op0 = SUBREG_REG (op0);
10323                   continue;
10324                 }
10325             }
10326
10327           /* If the inner mode is narrower and we are extracting the low part,
10328              we can treat the SUBREG as if it were a ZERO_EXTEND.  */
10329           if (subreg_lowpart_p (op0)
10330               && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10331             /* Fall through */ ;
10332           else
10333             break;
10334
10335           /* ... fall through ...  */
10336
10337         case ZERO_EXTEND:
10338           mode = GET_MODE (XEXP (op0, 0));
10339           if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10340               && (unsigned_comparison_p || equality_comparison_p)
10341               && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10342               && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10343               && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10344             {
10345               op0 = XEXP (op0, 0);
10346               continue;
10347             }
10348           break;
10349
10350         case PLUS:
10351           /* (eq (plus X A) B) -> (eq X (minus B A)).  We can only do
10352              this for equality comparisons due to pathological cases involving
10353              overflows.  */
10354           if (equality_comparison_p
10355               && 0 != (tem = simplify_binary_operation (MINUS, mode,
10356                                                         op1, XEXP (op0, 1))))
10357             {
10358               op0 = XEXP (op0, 0);
10359               op1 = tem;
10360               continue;
10361             }
10362
10363           /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0.  */
10364           if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10365               && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10366             {
10367               op0 = XEXP (XEXP (op0, 0), 0);
10368               code = (code == LT ? EQ : NE);
10369               continue;
10370             }
10371           break;
10372
10373         case MINUS:
10374           /* We used to optimize signed comparisons against zero, but that
10375              was incorrect.  Unsigned comparisons against zero (GTU, LEU)
10376              arrive here as equality comparisons, or (GEU, LTU) are
10377              optimized away.  No need to special-case them.  */
10378
10379           /* (eq (minus A B) C) -> (eq A (plus B C)) or
10380              (eq B (minus A C)), whichever simplifies.  We can only do
10381              this for equality comparisons due to pathological cases involving
10382              overflows.  */
10383           if (equality_comparison_p
10384               && 0 != (tem = simplify_binary_operation (PLUS, mode,
10385                                                         XEXP (op0, 1), op1)))
10386             {
10387               op0 = XEXP (op0, 0);
10388               op1 = tem;
10389               continue;
10390             }
10391
10392           if (equality_comparison_p
10393               && 0 != (tem = simplify_binary_operation (MINUS, mode,
10394                                                         XEXP (op0, 0), op1)))
10395             {
10396               op0 = XEXP (op0, 1);
10397               op1 = tem;
10398               continue;
10399             }
10400
10401           /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10402              of bits in X minus 1, is one iff X > 0.  */
10403           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10404               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10405               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10406                  == mode_width - 1
10407               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10408             {
10409               op0 = XEXP (op0, 1);
10410               code = (code == GE ? LE : GT);
10411               continue;
10412             }
10413           break;
10414
10415         case XOR:
10416           /* (eq (xor A B) C) -> (eq A (xor B C)).  This is a simplification
10417              if C is zero or B is a constant.  */
10418           if (equality_comparison_p
10419               && 0 != (tem = simplify_binary_operation (XOR, mode,
10420                                                         XEXP (op0, 1), op1)))
10421             {
10422               op0 = XEXP (op0, 0);
10423               op1 = tem;
10424               continue;
10425             }
10426           break;
10427
10428         case EQ:  case NE:
10429         case UNEQ:  case LTGT:
10430         case LT:  case LTU:  case UNLT:  case LE:  case LEU:  case UNLE:
10431         case GT:  case GTU:  case UNGT:  case GE:  case GEU:  case UNGE:
10432         case UNORDERED: case ORDERED:
10433           /* We can't do anything if OP0 is a condition code value, rather
10434              than an actual data value.  */
10435           if (const_op != 0
10436               || CC0_P (XEXP (op0, 0))
10437               || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10438             break;
10439
10440           /* Get the two operands being compared.  */
10441           if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10442             tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10443           else
10444             tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10445
10446           /* Check for the cases where we simply want the result of the
10447              earlier test or the opposite of that result.  */
10448           if (code == NE || code == EQ
10449               || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10450                   && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10451                   && (STORE_FLAG_VALUE
10452                       & (((HOST_WIDE_INT) 1
10453                           << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10454                   && (code == LT || code == GE)))
10455             {
10456               enum rtx_code new_code;
10457               if (code == LT || code == NE)
10458                 new_code = GET_CODE (op0);
10459               else
10460                 new_code = reversed_comparison_code (op0, NULL);
10461
10462               if (new_code != UNKNOWN)
10463                 {
10464                   code = new_code;
10465                   op0 = tem;
10466                   op1 = tem1;
10467                   continue;
10468                 }
10469             }
10470           break;
10471
10472         case IOR:
10473           /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10474              iff X <= 0.  */
10475           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10476               && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10477               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10478             {
10479               op0 = XEXP (op0, 1);
10480               code = (code == GE ? GT : LE);
10481               continue;
10482             }
10483           break;
10484
10485         case AND:
10486           /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1).  This
10487              will be converted to a ZERO_EXTRACT later.  */
10488           if (const_op == 0 && equality_comparison_p
10489               && GET_CODE (XEXP (op0, 0)) == ASHIFT
10490               && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10491             {
10492               op0 = simplify_and_const_int
10493                 (op0, mode, gen_rtx_LSHIFTRT (mode,
10494                                               XEXP (op0, 1),
10495                                               XEXP (XEXP (op0, 0), 1)),
10496                  (HOST_WIDE_INT) 1);
10497               continue;
10498             }
10499
10500           /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10501              zero and X is a comparison and C1 and C2 describe only bits set
10502              in STORE_FLAG_VALUE, we can compare with X.  */
10503           if (const_op == 0 && equality_comparison_p
10504               && mode_width <= HOST_BITS_PER_WIDE_INT
10505               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10506               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10507               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10508               && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10509               && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10510             {
10511               mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10512                       << INTVAL (XEXP (XEXP (op0, 0), 1)));
10513               if ((~STORE_FLAG_VALUE & mask) == 0
10514                   && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
10515                       || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10516                           && COMPARISON_P (tem))))
10517                 {
10518                   op0 = XEXP (XEXP (op0, 0), 0);
10519                   continue;
10520                 }
10521             }
10522
10523           /* If we are doing an equality comparison of an AND of a bit equal
10524              to the sign bit, replace this with a LT or GE comparison of
10525              the underlying value.  */
10526           if (equality_comparison_p
10527               && const_op == 0
10528               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10529               && mode_width <= HOST_BITS_PER_WIDE_INT
10530               && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10531                   == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10532             {
10533               op0 = XEXP (op0, 0);
10534               code = (code == EQ ? GE : LT);
10535               continue;
10536             }
10537
10538           /* If this AND operation is really a ZERO_EXTEND from a narrower
10539              mode, the constant fits within that mode, and this is either an
10540              equality or unsigned comparison, try to do this comparison in
10541              the narrower mode.  */
10542           if ((equality_comparison_p || unsigned_comparison_p)
10543               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10544               && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10545                                    & GET_MODE_MASK (mode))
10546                                   + 1)) >= 0
10547               && const_op >> i == 0
10548               && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10549             {
10550               op0 = gen_lowpart (tmode, XEXP (op0, 0));
10551               continue;
10552             }
10553
10554           /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10555              fits in both M1 and M2 and the SUBREG is either paradoxical
10556              or represents the low part, permute the SUBREG and the AND
10557              and try again.  */
10558           if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10559             {
10560               unsigned HOST_WIDE_INT c1;
10561               tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10562               /* Require an integral mode, to avoid creating something like
10563                  (AND:SF ...).  */
10564               if (SCALAR_INT_MODE_P (tmode)
10565                   /* It is unsafe to commute the AND into the SUBREG if the
10566                      SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10567                      not defined.  As originally written the upper bits
10568                      have a defined value due to the AND operation.
10569                      However, if we commute the AND inside the SUBREG then
10570                      they no longer have defined values and the meaning of
10571                      the code has been changed.  */
10572                   && (0
10573 #ifdef WORD_REGISTER_OPERATIONS
10574                       || (mode_width > GET_MODE_BITSIZE (tmode)
10575                           && mode_width <= BITS_PER_WORD)
10576 #endif
10577                       || (mode_width <= GET_MODE_BITSIZE (tmode)
10578                           && subreg_lowpart_p (XEXP (op0, 0))))
10579                   && GET_CODE (XEXP (op0, 1)) == CONST_INT
10580                   && mode_width <= HOST_BITS_PER_WIDE_INT
10581                   && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10582                   && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10583                   && (c1 & ~GET_MODE_MASK (tmode)) == 0
10584                   && c1 != mask
10585                   && c1 != GET_MODE_MASK (tmode))
10586                 {
10587                   op0 = simplify_gen_binary (AND, tmode,
10588                                              SUBREG_REG (XEXP (op0, 0)),
10589                                              gen_int_mode (c1, tmode));
10590                   op0 = gen_lowpart (mode, op0);
10591                   continue;
10592                 }
10593             }
10594
10595           /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0).  */
10596           if (const_op == 0 && equality_comparison_p
10597               && XEXP (op0, 1) == const1_rtx
10598               && GET_CODE (XEXP (op0, 0)) == NOT)
10599             {
10600               op0 = simplify_and_const_int
10601                 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10602               code = (code == NE ? EQ : NE);
10603               continue;
10604             }
10605
10606           /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10607              (eq (and (lshiftrt X) 1) 0).
10608              Also handle the case where (not X) is expressed using xor.  */
10609           if (const_op == 0 && equality_comparison_p
10610               && XEXP (op0, 1) == const1_rtx
10611               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
10612             {
10613               rtx shift_op = XEXP (XEXP (op0, 0), 0);
10614               rtx shift_count = XEXP (XEXP (op0, 0), 1);
10615
10616               if (GET_CODE (shift_op) == NOT
10617                   || (GET_CODE (shift_op) == XOR
10618                       && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
10619                       && GET_CODE (shift_count) == CONST_INT
10620                       && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10621                       && (INTVAL (XEXP (shift_op, 1))
10622                           == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
10623                 {
10624                   op0 = simplify_and_const_int
10625                     (NULL_RTX, mode,
10626                      gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
10627                      (HOST_WIDE_INT) 1);
10628                   code = (code == NE ? EQ : NE);
10629                   continue;
10630                 }
10631             }
10632           break;
10633
10634         case ASHIFT:
10635           /* If we have (compare (ashift FOO N) (const_int C)) and
10636              the high order N bits of FOO (N+1 if an inequality comparison)
10637              are known to be zero, we can do this by comparing FOO with C
10638              shifted right N bits so long as the low-order N bits of C are
10639              zero.  */
10640           if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10641               && INTVAL (XEXP (op0, 1)) >= 0
10642               && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10643                   < HOST_BITS_PER_WIDE_INT)
10644               && ((const_op
10645                    & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10646               && mode_width <= HOST_BITS_PER_WIDE_INT
10647               && (nonzero_bits (XEXP (op0, 0), mode)
10648                   & ~(mask >> (INTVAL (XEXP (op0, 1))
10649                                + ! equality_comparison_p))) == 0)
10650             {
10651               /* We must perform a logical shift, not an arithmetic one,
10652                  as we want the top N bits of C to be zero.  */
10653               unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10654
10655               temp >>= INTVAL (XEXP (op0, 1));
10656               op1 = gen_int_mode (temp, mode);
10657               op0 = XEXP (op0, 0);
10658               continue;
10659             }
10660
10661           /* If we are doing a sign bit comparison, it means we are testing
10662              a particular bit.  Convert it to the appropriate AND.  */
10663           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10664               && mode_width <= HOST_BITS_PER_WIDE_INT)
10665             {
10666               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10667                                             ((HOST_WIDE_INT) 1
10668                                              << (mode_width - 1
10669                                                  - INTVAL (XEXP (op0, 1)))));
10670               code = (code == LT ? NE : EQ);
10671               continue;
10672             }
10673
10674           /* If this an equality comparison with zero and we are shifting
10675              the low bit to the sign bit, we can convert this to an AND of the
10676              low-order bit.  */
10677           if (const_op == 0 && equality_comparison_p
10678               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10679               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10680                  == mode_width - 1)
10681             {
10682               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10683                                             (HOST_WIDE_INT) 1);
10684               continue;
10685             }
10686           break;
10687
10688         case ASHIFTRT:
10689           /* If this is an equality comparison with zero, we can do this
10690              as a logical shift, which might be much simpler.  */
10691           if (equality_comparison_p && const_op == 0
10692               && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10693             {
10694               op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10695                                           XEXP (op0, 0),
10696                                           INTVAL (XEXP (op0, 1)));
10697               continue;
10698             }
10699
10700           /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10701              do the comparison in a narrower mode.  */
10702           if (! unsigned_comparison_p
10703               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10704               && GET_CODE (XEXP (op0, 0)) == ASHIFT
10705               && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10706               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10707                                          MODE_INT, 1)) != BLKmode
10708               && (((unsigned HOST_WIDE_INT) const_op
10709                    + (GET_MODE_MASK (tmode) >> 1) + 1)
10710                   <= GET_MODE_MASK (tmode)))
10711             {
10712               op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
10713               continue;
10714             }
10715
10716           /* Likewise if OP0 is a PLUS of a sign extension with a
10717              constant, which is usually represented with the PLUS
10718              between the shifts.  */
10719           if (! unsigned_comparison_p
10720               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10721               && GET_CODE (XEXP (op0, 0)) == PLUS
10722               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10723               && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10724               && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10725               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10726                                          MODE_INT, 1)) != BLKmode
10727               && (((unsigned HOST_WIDE_INT) const_op
10728                    + (GET_MODE_MASK (tmode) >> 1) + 1)
10729                   <= GET_MODE_MASK (tmode)))
10730             {
10731               rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10732               rtx add_const = XEXP (XEXP (op0, 0), 1);
10733               rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
10734                                                    add_const, XEXP (op0, 1));
10735
10736               op0 = simplify_gen_binary (PLUS, tmode,
10737                                          gen_lowpart (tmode, inner),
10738                                          new_const);
10739               continue;
10740             }
10741
10742           /* ... fall through ...  */
10743         case LSHIFTRT:
10744           /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10745              the low order N bits of FOO are known to be zero, we can do this
10746              by comparing FOO with C shifted left N bits so long as no
10747              overflow occurs.  */
10748           if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10749               && INTVAL (XEXP (op0, 1)) >= 0
10750               && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10751               && mode_width <= HOST_BITS_PER_WIDE_INT
10752               && (nonzero_bits (XEXP (op0, 0), mode)
10753                   & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10754               && (((unsigned HOST_WIDE_INT) const_op
10755                    + (GET_CODE (op0) != LSHIFTRT
10756                       ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
10757                          + 1)
10758                       : 0))
10759                   <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
10760             {
10761               /* If the shift was logical, then we must make the condition
10762                  unsigned.  */
10763               if (GET_CODE (op0) == LSHIFTRT)
10764                 code = unsigned_condition (code);
10765
10766               const_op <<= INTVAL (XEXP (op0, 1));
10767               op1 = GEN_INT (const_op);
10768               op0 = XEXP (op0, 0);
10769               continue;
10770             }
10771
10772           /* If we are using this shift to extract just the sign bit, we
10773              can replace this with an LT or GE comparison.  */
10774           if (const_op == 0
10775               && (equality_comparison_p || sign_bit_comparison_p)
10776               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10777               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10778                  == mode_width - 1)
10779             {
10780               op0 = XEXP (op0, 0);
10781               code = (code == NE || code == GT ? LT : GE);
10782               continue;
10783             }
10784           break;
10785
10786         default:
10787           break;
10788         }
10789
10790       break;
10791     }
10792
10793   /* Now make any compound operations involved in this comparison.  Then,
10794      check for an outmost SUBREG on OP0 that is not doing anything or is
10795      paradoxical.  The latter transformation must only be performed when
10796      it is known that the "extra" bits will be the same in op0 and op1 or
10797      that they don't matter.  There are three cases to consider:
10798
10799      1. SUBREG_REG (op0) is a register.  In this case the bits are don't
10800      care bits and we can assume they have any convenient value.  So
10801      making the transformation is safe.
10802
10803      2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10804      In this case the upper bits of op0 are undefined.  We should not make
10805      the simplification in that case as we do not know the contents of
10806      those bits.
10807
10808      3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10809      UNKNOWN.  In that case we know those bits are zeros or ones.  We must
10810      also be sure that they are the same as the upper bits of op1.
10811
10812      We can never remove a SUBREG for a non-equality comparison because
10813      the sign bit is in a different place in the underlying object.  */
10814
10815   op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10816   op1 = make_compound_operation (op1, SET);
10817
10818   if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10819       && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10820       && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
10821       && (code == NE || code == EQ))
10822     {
10823       if (GET_MODE_SIZE (GET_MODE (op0))
10824           > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
10825         {
10826           /* For paradoxical subregs, allow case 1 as above.  Case 3 isn't
10827              implemented.  */
10828           if (REG_P (SUBREG_REG (op0)))
10829             {
10830               op0 = SUBREG_REG (op0);
10831               op1 = gen_lowpart (GET_MODE (op0), op1);
10832             }
10833         }
10834       else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10835                 <= HOST_BITS_PER_WIDE_INT)
10836                && (nonzero_bits (SUBREG_REG (op0),
10837                                  GET_MODE (SUBREG_REG (op0)))
10838                    & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10839         {
10840           tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
10841
10842           if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10843                & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10844             op0 = SUBREG_REG (op0), op1 = tem;
10845         }
10846     }
10847
10848   /* We now do the opposite procedure: Some machines don't have compare
10849      insns in all modes.  If OP0's mode is an integer mode smaller than a
10850      word and we can't do a compare in that mode, see if there is a larger
10851      mode for which we can do the compare.  There are a number of cases in
10852      which we can use the wider mode.  */
10853
10854   mode = GET_MODE (op0);
10855   if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10856       && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10857       && ! have_insn_for (COMPARE, mode))
10858     for (tmode = GET_MODE_WIDER_MODE (mode);
10859          (tmode != VOIDmode
10860           && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10861          tmode = GET_MODE_WIDER_MODE (tmode))
10862       if (have_insn_for (COMPARE, tmode))
10863         {
10864           int zero_extended;
10865
10866           /* If the only nonzero bits in OP0 and OP1 are those in the
10867              narrower mode and this is an equality or unsigned comparison,
10868              we can use the wider mode.  Similarly for sign-extended
10869              values, in which case it is true for all comparisons.  */
10870           zero_extended = ((code == EQ || code == NE
10871                             || code == GEU || code == GTU
10872                             || code == LEU || code == LTU)
10873                            && (nonzero_bits (op0, tmode)
10874                                & ~GET_MODE_MASK (mode)) == 0
10875                            && ((GET_CODE (op1) == CONST_INT
10876                                 || (nonzero_bits (op1, tmode)
10877                                     & ~GET_MODE_MASK (mode)) == 0)));
10878
10879           if (zero_extended
10880               || ((num_sign_bit_copies (op0, tmode)
10881                    > (unsigned int) (GET_MODE_BITSIZE (tmode)
10882                                      - GET_MODE_BITSIZE (mode)))
10883                   && (num_sign_bit_copies (op1, tmode)
10884                       > (unsigned int) (GET_MODE_BITSIZE (tmode)
10885                                         - GET_MODE_BITSIZE (mode)))))
10886             {
10887               /* If OP0 is an AND and we don't have an AND in MODE either,
10888                  make a new AND in the proper mode.  */
10889               if (GET_CODE (op0) == AND
10890                   && !have_insn_for (AND, mode))
10891                 op0 = simplify_gen_binary (AND, tmode,
10892                                            gen_lowpart (tmode,
10893                                                         XEXP (op0, 0)),
10894                                            gen_lowpart (tmode,
10895                                                         XEXP (op0, 1)));
10896
10897               op0 = gen_lowpart (tmode, op0);
10898               if (zero_extended && GET_CODE (op1) == CONST_INT)
10899                 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
10900               op1 = gen_lowpart (tmode, op1);
10901               break;
10902             }
10903
10904           /* If this is a test for negative, we can make an explicit
10905              test of the sign bit.  */
10906
10907           if (op1 == const0_rtx && (code == LT || code == GE)
10908               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10909             {
10910               op0 = simplify_gen_binary (AND, tmode,
10911                                          gen_lowpart (tmode, op0),
10912                                          GEN_INT ((HOST_WIDE_INT) 1
10913                                                   << (GET_MODE_BITSIZE (mode)
10914                                                       - 1)));
10915               code = (code == LT) ? NE : EQ;
10916               break;
10917             }
10918         }
10919
10920 #ifdef CANONICALIZE_COMPARISON
10921   /* If this machine only supports a subset of valid comparisons, see if we
10922      can convert an unsupported one into a supported one.  */
10923   CANONICALIZE_COMPARISON (code, op0, op1);
10924 #endif
10925
10926   *pop0 = op0;
10927   *pop1 = op1;
10928
10929   return code;
10930 }
10931 \f
10932 /* Utility function for record_value_for_reg.  Count number of
10933    rtxs in X.  */
10934 static int
10935 count_rtxs (rtx x)
10936 {
10937   enum rtx_code code = GET_CODE (x);
10938   const char *fmt;
10939   int i, ret = 1;
10940
10941   if (GET_RTX_CLASS (code) == '2'
10942       || GET_RTX_CLASS (code) == 'c')
10943     {
10944       rtx x0 = XEXP (x, 0);
10945       rtx x1 = XEXP (x, 1);
10946
10947       if (x0 == x1)
10948         return 1 + 2 * count_rtxs (x0);
10949
10950       if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
10951            || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
10952           && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10953         return 2 + 2 * count_rtxs (x0)
10954                + count_rtxs (x == XEXP (x1, 0)
10955                              ? XEXP (x1, 1) : XEXP (x1, 0));
10956
10957       if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
10958            || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
10959           && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10960         return 2 + 2 * count_rtxs (x1)
10961                + count_rtxs (x == XEXP (x0, 0)
10962                              ? XEXP (x0, 1) : XEXP (x0, 0));
10963     }
10964
10965   fmt = GET_RTX_FORMAT (code);
10966   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10967     if (fmt[i] == 'e')
10968       ret += count_rtxs (XEXP (x, i));
10969
10970   return ret;
10971 }
10972 \f
10973 /* Utility function for following routine.  Called when X is part of a value
10974    being stored into last_set_value.  Sets last_set_table_tick
10975    for each register mentioned.  Similar to mention_regs in cse.c  */
10976
10977 static void
10978 update_table_tick (rtx x)
10979 {
10980   enum rtx_code code = GET_CODE (x);
10981   const char *fmt = GET_RTX_FORMAT (code);
10982   int i;
10983
10984   if (code == REG)
10985     {
10986       unsigned int regno = REGNO (x);
10987       unsigned int endregno
10988         = regno + (regno < FIRST_PSEUDO_REGISTER
10989                    ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
10990       unsigned int r;
10991
10992       for (r = regno; r < endregno; r++)
10993         reg_stat[r].last_set_table_tick = label_tick;
10994
10995       return;
10996     }
10997
10998   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10999     /* Note that we can't have an "E" in values stored; see
11000        get_last_value_validate.  */
11001     if (fmt[i] == 'e')
11002       {
11003         /* Check for identical subexpressions.  If x contains
11004            identical subexpression we only have to traverse one of
11005            them.  */
11006         if (i == 0 && ARITHMETIC_P (x))
11007           {
11008             /* Note that at this point x1 has already been
11009                processed.  */
11010             rtx x0 = XEXP (x, 0);
11011             rtx x1 = XEXP (x, 1);
11012
11013             /* If x0 and x1 are identical then there is no need to
11014                process x0.  */
11015             if (x0 == x1)
11016               break;
11017
11018             /* If x0 is identical to a subexpression of x1 then while
11019                processing x1, x0 has already been processed.  Thus we
11020                are done with x.  */
11021             if (ARITHMETIC_P (x1)
11022                 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11023               break;
11024
11025             /* If x1 is identical to a subexpression of x0 then we
11026                still have to process the rest of x0.  */
11027             if (ARITHMETIC_P (x0)
11028                 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11029               {
11030                 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
11031                 break;
11032               }
11033           }
11034
11035         update_table_tick (XEXP (x, i));
11036       }
11037 }
11038
11039 /* Record that REG is set to VALUE in insn INSN.  If VALUE is zero, we
11040    are saying that the register is clobbered and we no longer know its
11041    value.  If INSN is zero, don't update reg_stat[].last_set; this is
11042    only permitted with VALUE also zero and is used to invalidate the
11043    register.  */
11044
11045 static void
11046 record_value_for_reg (rtx reg, rtx insn, rtx value)
11047 {
11048   unsigned int regno = REGNO (reg);
11049   unsigned int endregno
11050     = regno + (regno < FIRST_PSEUDO_REGISTER
11051                ? hard_regno_nregs[regno][GET_MODE (reg)] : 1);
11052   unsigned int i;
11053
11054   /* If VALUE contains REG and we have a previous value for REG, substitute
11055      the previous value.  */
11056   if (value && insn && reg_overlap_mentioned_p (reg, value))
11057     {
11058       rtx tem;
11059
11060       /* Set things up so get_last_value is allowed to see anything set up to
11061          our insn.  */
11062       subst_low_cuid = INSN_CUID (insn);
11063       tem = get_last_value (reg);
11064
11065       /* If TEM is simply a binary operation with two CLOBBERs as operands,
11066          it isn't going to be useful and will take a lot of time to process,
11067          so just use the CLOBBER.  */
11068
11069       if (tem)
11070         {
11071           if (ARITHMETIC_P (tem)
11072               && GET_CODE (XEXP (tem, 0)) == CLOBBER
11073               && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11074             tem = XEXP (tem, 0);
11075           else if (count_occurrences (value, reg, 1) >= 2)
11076             {
11077               /* If there are two or more occurrences of REG in VALUE,
11078                  prevent the value from growing too much.  */
11079               if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
11080                 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
11081             }
11082
11083           value = replace_rtx (copy_rtx (value), reg, tem);
11084         }
11085     }
11086
11087   /* For each register modified, show we don't know its value, that
11088      we don't know about its bitwise content, that its value has been
11089      updated, and that we don't know the location of the death of the
11090      register.  */
11091   for (i = regno; i < endregno; i++)
11092     {
11093       if (insn)
11094         reg_stat[i].last_set = insn;
11095
11096       reg_stat[i].last_set_value = 0;
11097       reg_stat[i].last_set_mode = 0;
11098       reg_stat[i].last_set_nonzero_bits = 0;
11099       reg_stat[i].last_set_sign_bit_copies = 0;
11100       reg_stat[i].last_death = 0;
11101     }
11102
11103   /* Mark registers that are being referenced in this value.  */
11104   if (value)
11105     update_table_tick (value);
11106
11107   /* Now update the status of each register being set.
11108      If someone is using this register in this block, set this register
11109      to invalid since we will get confused between the two lives in this
11110      basic block.  This makes using this register always invalid.  In cse, we
11111      scan the table to invalidate all entries using this register, but this
11112      is too much work for us.  */
11113
11114   for (i = regno; i < endregno; i++)
11115     {
11116       reg_stat[i].last_set_label = label_tick;
11117       if (value && reg_stat[i].last_set_table_tick == label_tick)
11118         reg_stat[i].last_set_invalid = 1;
11119       else
11120         reg_stat[i].last_set_invalid = 0;
11121     }
11122
11123   /* The value being assigned might refer to X (like in "x++;").  In that
11124      case, we must replace it with (clobber (const_int 0)) to prevent
11125      infinite loops.  */
11126   if (value && ! get_last_value_validate (&value, insn,
11127                                           reg_stat[regno].last_set_label, 0))
11128     {
11129       value = copy_rtx (value);
11130       if (! get_last_value_validate (&value, insn,
11131                                      reg_stat[regno].last_set_label, 1))
11132         value = 0;
11133     }
11134
11135   /* For the main register being modified, update the value, the mode, the
11136      nonzero bits, and the number of sign bit copies.  */
11137
11138   reg_stat[regno].last_set_value = value;
11139
11140   if (value)
11141     {
11142       enum machine_mode mode = GET_MODE (reg);
11143       subst_low_cuid = INSN_CUID (insn);
11144       reg_stat[regno].last_set_mode = mode;
11145       if (GET_MODE_CLASS (mode) == MODE_INT
11146           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11147         mode = nonzero_bits_mode;
11148       reg_stat[regno].last_set_nonzero_bits = nonzero_bits (value, mode);
11149       reg_stat[regno].last_set_sign_bit_copies
11150         = num_sign_bit_copies (value, GET_MODE (reg));
11151     }
11152 }
11153
11154 /* Called via note_stores from record_dead_and_set_regs to handle one
11155    SET or CLOBBER in an insn.  DATA is the instruction in which the
11156    set is occurring.  */
11157
11158 static void
11159 record_dead_and_set_regs_1 (rtx dest, rtx setter, void *data)
11160 {
11161   rtx record_dead_insn = (rtx) data;
11162
11163   if (GET_CODE (dest) == SUBREG)
11164     dest = SUBREG_REG (dest);
11165
11166   if (REG_P (dest))
11167     {
11168       /* If we are setting the whole register, we know its value.  Otherwise
11169          show that we don't know the value.  We can handle SUBREG in
11170          some cases.  */
11171       if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11172         record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11173       else if (GET_CODE (setter) == SET
11174                && GET_CODE (SET_DEST (setter)) == SUBREG
11175                && SUBREG_REG (SET_DEST (setter)) == dest
11176                && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11177                && subreg_lowpart_p (SET_DEST (setter)))
11178         record_value_for_reg (dest, record_dead_insn,
11179                               gen_lowpart (GET_MODE (dest),
11180                                                        SET_SRC (setter)));
11181       else
11182         record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11183     }
11184   else if (MEM_P (dest)
11185            /* Ignore pushes, they clobber nothing.  */
11186            && ! push_operand (dest, GET_MODE (dest)))
11187     mem_last_set = INSN_CUID (record_dead_insn);
11188 }
11189
11190 /* Update the records of when each REG was most recently set or killed
11191    for the things done by INSN.  This is the last thing done in processing
11192    INSN in the combiner loop.
11193
11194    We update reg_stat[], in particular fields last_set, last_set_value,
11195    last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11196    last_death, and also the similar information mem_last_set (which insn
11197    most recently modified memory) and last_call_cuid (which insn was the
11198    most recent subroutine call).  */
11199
11200 static void
11201 record_dead_and_set_regs (rtx insn)
11202 {
11203   rtx link;
11204   unsigned int i;
11205
11206   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11207     {
11208       if (REG_NOTE_KIND (link) == REG_DEAD
11209           && REG_P (XEXP (link, 0)))
11210         {
11211           unsigned int regno = REGNO (XEXP (link, 0));
11212           unsigned int endregno
11213             = regno + (regno < FIRST_PSEUDO_REGISTER
11214                        ? hard_regno_nregs[regno][GET_MODE (XEXP (link, 0))]
11215                        : 1);
11216
11217           for (i = regno; i < endregno; i++)
11218             reg_stat[i].last_death = insn;
11219         }
11220       else if (REG_NOTE_KIND (link) == REG_INC)
11221         record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11222     }
11223
11224   if (CALL_P (insn))
11225     {
11226       for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11227         if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11228           {
11229             reg_stat[i].last_set_value = 0;
11230             reg_stat[i].last_set_mode = 0;
11231             reg_stat[i].last_set_nonzero_bits = 0;
11232             reg_stat[i].last_set_sign_bit_copies = 0;
11233             reg_stat[i].last_death = 0;
11234           }
11235
11236       last_call_cuid = mem_last_set = INSN_CUID (insn);
11237
11238       /* Don't bother recording what this insn does.  It might set the
11239          return value register, but we can't combine into a call
11240          pattern anyway, so there's no point trying (and it may cause
11241          a crash, if e.g. we wind up asking for last_set_value of a
11242          SUBREG of the return value register).  */
11243       return;
11244     }
11245
11246   note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11247 }
11248
11249 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11250    register present in the SUBREG, so for each such SUBREG go back and
11251    adjust nonzero and sign bit information of the registers that are
11252    known to have some zero/sign bits set.
11253
11254    This is needed because when combine blows the SUBREGs away, the
11255    information on zero/sign bits is lost and further combines can be
11256    missed because of that.  */
11257
11258 static void
11259 record_promoted_value (rtx insn, rtx subreg)
11260 {
11261   rtx links, set;
11262   unsigned int regno = REGNO (SUBREG_REG (subreg));
11263   enum machine_mode mode = GET_MODE (subreg);
11264
11265   if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11266     return;
11267
11268   for (links = LOG_LINKS (insn); links;)
11269     {
11270       insn = XEXP (links, 0);
11271       set = single_set (insn);
11272
11273       if (! set || !REG_P (SET_DEST (set))
11274           || REGNO (SET_DEST (set)) != regno
11275           || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11276         {
11277           links = XEXP (links, 1);
11278           continue;
11279         }
11280
11281       if (reg_stat[regno].last_set == insn)
11282         {
11283           if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11284             reg_stat[regno].last_set_nonzero_bits &= GET_MODE_MASK (mode);
11285         }
11286
11287       if (REG_P (SET_SRC (set)))
11288         {
11289           regno = REGNO (SET_SRC (set));
11290           links = LOG_LINKS (insn);
11291         }
11292       else
11293         break;
11294     }
11295 }
11296
11297 /* Scan X for promoted SUBREGs.  For each one found,
11298    note what it implies to the registers used in it.  */
11299
11300 static void
11301 check_promoted_subreg (rtx insn, rtx x)
11302 {
11303   if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11304       && REG_P (SUBREG_REG (x)))
11305     record_promoted_value (insn, x);
11306   else
11307     {
11308       const char *format = GET_RTX_FORMAT (GET_CODE (x));
11309       int i, j;
11310
11311       for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11312         switch (format[i])
11313           {
11314           case 'e':
11315             check_promoted_subreg (insn, XEXP (x, i));
11316             break;
11317           case 'V':
11318           case 'E':
11319             if (XVEC (x, i) != 0)
11320               for (j = 0; j < XVECLEN (x, i); j++)
11321                 check_promoted_subreg (insn, XVECEXP (x, i, j));
11322             break;
11323           }
11324     }
11325 }
11326 \f
11327 /* Utility routine for the following function.  Verify that all the registers
11328    mentioned in *LOC are valid when *LOC was part of a value set when
11329    label_tick == TICK.  Return 0 if some are not.
11330
11331    If REPLACE is nonzero, replace the invalid reference with
11332    (clobber (const_int 0)) and return 1.  This replacement is useful because
11333    we often can get useful information about the form of a value (e.g., if
11334    it was produced by a shift that always produces -1 or 0) even though
11335    we don't know exactly what registers it was produced from.  */
11336
11337 static int
11338 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11339 {
11340   rtx x = *loc;
11341   const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11342   int len = GET_RTX_LENGTH (GET_CODE (x));
11343   int i;
11344
11345   if (REG_P (x))
11346     {
11347       unsigned int regno = REGNO (x);
11348       unsigned int endregno
11349         = regno + (regno < FIRST_PSEUDO_REGISTER
11350                    ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11351       unsigned int j;
11352
11353       for (j = regno; j < endregno; j++)
11354         if (reg_stat[j].last_set_invalid
11355             /* If this is a pseudo-register that was only set once and not
11356                live at the beginning of the function, it is always valid.  */
11357             || (! (regno >= FIRST_PSEUDO_REGISTER
11358                    && REG_N_SETS (regno) == 1
11359                    && (! REGNO_REG_SET_P
11360                        (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
11361                         regno)))
11362                 && reg_stat[j].last_set_label > tick))
11363           {
11364             if (replace)
11365               *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11366             return replace;
11367           }
11368
11369       return 1;
11370     }
11371   /* If this is a memory reference, make sure that there were
11372      no stores after it that might have clobbered the value.  We don't
11373      have alias info, so we assume any store invalidates it.  */
11374   else if (MEM_P (x) && !MEM_READONLY_P (x)
11375            && INSN_CUID (insn) <= mem_last_set)
11376     {
11377       if (replace)
11378         *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11379       return replace;
11380     }
11381
11382   for (i = 0; i < len; i++)
11383     {
11384       if (fmt[i] == 'e')
11385         {
11386           /* Check for identical subexpressions.  If x contains
11387              identical subexpression we only have to traverse one of
11388              them.  */
11389           if (i == 1 && ARITHMETIC_P (x))
11390             {
11391               /* Note that at this point x0 has already been checked
11392                  and found valid.  */
11393               rtx x0 = XEXP (x, 0);
11394               rtx x1 = XEXP (x, 1);
11395
11396               /* If x0 and x1 are identical then x is also valid.  */
11397               if (x0 == x1)
11398                 return 1;
11399
11400               /* If x1 is identical to a subexpression of x0 then
11401                  while checking x0, x1 has already been checked.  Thus
11402                  it is valid and so as x.  */
11403               if (ARITHMETIC_P (x0)
11404                   && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11405                 return 1;
11406
11407               /* If x0 is identical to a subexpression of x1 then x is
11408                  valid iff the rest of x1 is valid.  */
11409               if (ARITHMETIC_P (x1)
11410                   && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11411                 return
11412                   get_last_value_validate (&XEXP (x1,
11413                                                   x0 == XEXP (x1, 0) ? 1 : 0),
11414                                            insn, tick, replace);
11415             }
11416
11417           if (get_last_value_validate (&XEXP (x, i), insn, tick,
11418                                        replace) == 0)
11419             return 0;
11420         }
11421       /* Don't bother with these.  They shouldn't occur anyway.  */
11422       else if (fmt[i] == 'E')
11423         return 0;
11424     }
11425
11426   /* If we haven't found a reason for it to be invalid, it is valid.  */
11427   return 1;
11428 }
11429
11430 /* Get the last value assigned to X, if known.  Some registers
11431    in the value may be replaced with (clobber (const_int 0)) if their value
11432    is known longer known reliably.  */
11433
11434 static rtx
11435 get_last_value (rtx x)
11436 {
11437   unsigned int regno;
11438   rtx value;
11439
11440   /* If this is a non-paradoxical SUBREG, get the value of its operand and
11441      then convert it to the desired mode.  If this is a paradoxical SUBREG,
11442      we cannot predict what values the "extra" bits might have.  */
11443   if (GET_CODE (x) == SUBREG
11444       && subreg_lowpart_p (x)
11445       && (GET_MODE_SIZE (GET_MODE (x))
11446           <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11447       && (value = get_last_value (SUBREG_REG (x))) != 0)
11448     return gen_lowpart (GET_MODE (x), value);
11449
11450   if (!REG_P (x))
11451     return 0;
11452
11453   regno = REGNO (x);
11454   value = reg_stat[regno].last_set_value;
11455
11456   /* If we don't have a value, or if it isn't for this basic block and
11457      it's either a hard register, set more than once, or it's a live
11458      at the beginning of the function, return 0.
11459
11460      Because if it's not live at the beginning of the function then the reg
11461      is always set before being used (is never used without being set).
11462      And, if it's set only once, and it's always set before use, then all
11463      uses must have the same last value, even if it's not from this basic
11464      block.  */
11465
11466   if (value == 0
11467       || (reg_stat[regno].last_set_label != label_tick
11468           && (regno < FIRST_PSEUDO_REGISTER
11469               || REG_N_SETS (regno) != 1
11470               || (REGNO_REG_SET_P
11471                   (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
11472                    regno)))))
11473     return 0;
11474
11475   /* If the value was set in a later insn than the ones we are processing,
11476      we can't use it even if the register was only set once.  */
11477   if (INSN_CUID (reg_stat[regno].last_set) >= subst_low_cuid)
11478     return 0;
11479
11480   /* If the value has all its registers valid, return it.  */
11481   if (get_last_value_validate (&value, reg_stat[regno].last_set,
11482                                reg_stat[regno].last_set_label, 0))
11483     return value;
11484
11485   /* Otherwise, make a copy and replace any invalid register with
11486      (clobber (const_int 0)).  If that fails for some reason, return 0.  */
11487
11488   value = copy_rtx (value);
11489   if (get_last_value_validate (&value, reg_stat[regno].last_set,
11490                                reg_stat[regno].last_set_label, 1))
11491     return value;
11492
11493   return 0;
11494 }
11495 \f
11496 /* Return nonzero if expression X refers to a REG or to memory
11497    that is set in an instruction more recent than FROM_CUID.  */
11498
11499 static int
11500 use_crosses_set_p (rtx x, int from_cuid)
11501 {
11502   const char *fmt;
11503   int i;
11504   enum rtx_code code = GET_CODE (x);
11505
11506   if (code == REG)
11507     {
11508       unsigned int regno = REGNO (x);
11509       unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11510                                  ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11511
11512 #ifdef PUSH_ROUNDING
11513       /* Don't allow uses of the stack pointer to be moved,
11514          because we don't know whether the move crosses a push insn.  */
11515       if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11516         return 1;
11517 #endif
11518       for (; regno < endreg; regno++)
11519         if (reg_stat[regno].last_set
11520             && INSN_CUID (reg_stat[regno].last_set) > from_cuid)
11521           return 1;
11522       return 0;
11523     }
11524
11525   if (code == MEM && mem_last_set > from_cuid)
11526     return 1;
11527
11528   fmt = GET_RTX_FORMAT (code);
11529
11530   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11531     {
11532       if (fmt[i] == 'E')
11533         {
11534           int j;
11535           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11536             if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11537               return 1;
11538         }
11539       else if (fmt[i] == 'e'
11540                && use_crosses_set_p (XEXP (x, i), from_cuid))
11541         return 1;
11542     }
11543   return 0;
11544 }
11545 \f
11546 /* Define three variables used for communication between the following
11547    routines.  */
11548
11549 static unsigned int reg_dead_regno, reg_dead_endregno;
11550 static int reg_dead_flag;
11551
11552 /* Function called via note_stores from reg_dead_at_p.
11553
11554    If DEST is within [reg_dead_regno, reg_dead_endregno), set
11555    reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET.  */
11556
11557 static void
11558 reg_dead_at_p_1 (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
11559 {
11560   unsigned int regno, endregno;
11561
11562   if (!REG_P (dest))
11563     return;
11564
11565   regno = REGNO (dest);
11566   endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11567                       ? hard_regno_nregs[regno][GET_MODE (dest)] : 1);
11568
11569   if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11570     reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11571 }
11572
11573 /* Return nonzero if REG is known to be dead at INSN.
11574
11575    We scan backwards from INSN.  If we hit a REG_DEAD note or a CLOBBER
11576    referencing REG, it is dead.  If we hit a SET referencing REG, it is
11577    live.  Otherwise, see if it is live or dead at the start of the basic
11578    block we are in.  Hard regs marked as being live in NEWPAT_USED_REGS
11579    must be assumed to be always live.  */
11580
11581 static int
11582 reg_dead_at_p (rtx reg, rtx insn)
11583 {
11584   basic_block block;
11585   unsigned int i;
11586
11587   /* Set variables for reg_dead_at_p_1.  */
11588   reg_dead_regno = REGNO (reg);
11589   reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11590                                         ? hard_regno_nregs[reg_dead_regno]
11591                                                           [GET_MODE (reg)]
11592                                         : 1);
11593
11594   reg_dead_flag = 0;
11595
11596   /* Check that reg isn't mentioned in NEWPAT_USED_REGS.  For fixed registers
11597      we allow the machine description to decide whether use-and-clobber
11598      patterns are OK.  */
11599   if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11600     {
11601       for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11602         if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
11603           return 0;
11604     }
11605
11606   /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11607      beginning of function.  */
11608   for (; insn && !LABEL_P (insn) && !BARRIER_P (insn);
11609        insn = prev_nonnote_insn (insn))
11610     {
11611       note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11612       if (reg_dead_flag)
11613         return reg_dead_flag == 1 ? 1 : 0;
11614
11615       if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11616         return 1;
11617     }
11618
11619   /* Get the basic block that we were in.  */
11620   if (insn == 0)
11621     block = ENTRY_BLOCK_PTR->next_bb;
11622   else
11623     {
11624       FOR_EACH_BB (block)
11625         if (insn == BB_HEAD (block))
11626           break;
11627
11628       if (block == EXIT_BLOCK_PTR)
11629         return 0;
11630     }
11631
11632   for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11633     if (REGNO_REG_SET_P (block->il.rtl->global_live_at_start, i))
11634       return 0;
11635
11636   return 1;
11637 }
11638 \f
11639 /* Note hard registers in X that are used.  This code is similar to
11640    that in flow.c, but much simpler since we don't care about pseudos.  */
11641
11642 static void
11643 mark_used_regs_combine (rtx x)
11644 {
11645   RTX_CODE code = GET_CODE (x);
11646   unsigned int regno;
11647   int i;
11648
11649   switch (code)
11650     {
11651     case LABEL_REF:
11652     case SYMBOL_REF:
11653     case CONST_INT:
11654     case CONST:
11655     case CONST_DOUBLE:
11656     case CONST_VECTOR:
11657     case PC:
11658     case ADDR_VEC:
11659     case ADDR_DIFF_VEC:
11660     case ASM_INPUT:
11661 #ifdef HAVE_cc0
11662     /* CC0 must die in the insn after it is set, so we don't need to take
11663        special note of it here.  */
11664     case CC0:
11665 #endif
11666       return;
11667
11668     case CLOBBER:
11669       /* If we are clobbering a MEM, mark any hard registers inside the
11670          address as used.  */
11671       if (MEM_P (XEXP (x, 0)))
11672         mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11673       return;
11674
11675     case REG:
11676       regno = REGNO (x);
11677       /* A hard reg in a wide mode may really be multiple registers.
11678          If so, mark all of them just like the first.  */
11679       if (regno < FIRST_PSEUDO_REGISTER)
11680         {
11681           unsigned int endregno, r;
11682
11683           /* None of this applies to the stack, frame or arg pointers.  */
11684           if (regno == STACK_POINTER_REGNUM
11685 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11686               || regno == HARD_FRAME_POINTER_REGNUM
11687 #endif
11688 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11689               || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11690 #endif
11691               || regno == FRAME_POINTER_REGNUM)
11692             return;
11693
11694           endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11695           for (r = regno; r < endregno; r++)
11696             SET_HARD_REG_BIT (newpat_used_regs, r);
11697         }
11698       return;
11699
11700     case SET:
11701       {
11702         /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11703            the address.  */
11704         rtx testreg = SET_DEST (x);
11705
11706         while (GET_CODE (testreg) == SUBREG
11707                || GET_CODE (testreg) == ZERO_EXTRACT
11708                || GET_CODE (testreg) == STRICT_LOW_PART)
11709           testreg = XEXP (testreg, 0);
11710
11711         if (MEM_P (testreg))
11712           mark_used_regs_combine (XEXP (testreg, 0));
11713
11714         mark_used_regs_combine (SET_SRC (x));
11715       }
11716       return;
11717
11718     default:
11719       break;
11720     }
11721
11722   /* Recursively scan the operands of this expression.  */
11723
11724   {
11725     const char *fmt = GET_RTX_FORMAT (code);
11726
11727     for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11728       {
11729         if (fmt[i] == 'e')
11730           mark_used_regs_combine (XEXP (x, i));
11731         else if (fmt[i] == 'E')
11732           {
11733             int j;
11734
11735             for (j = 0; j < XVECLEN (x, i); j++)
11736               mark_used_regs_combine (XVECEXP (x, i, j));
11737           }
11738       }
11739   }
11740 }
11741 \f
11742 /* Remove register number REGNO from the dead registers list of INSN.
11743
11744    Return the note used to record the death, if there was one.  */
11745
11746 rtx
11747 remove_death (unsigned int regno, rtx insn)
11748 {
11749   rtx note = find_regno_note (insn, REG_DEAD, regno);
11750
11751   if (note)
11752     {
11753       REG_N_DEATHS (regno)--;
11754       remove_note (insn, note);
11755     }
11756
11757   return note;
11758 }
11759
11760 /* For each register (hardware or pseudo) used within expression X, if its
11761    death is in an instruction with cuid between FROM_CUID (inclusive) and
11762    TO_INSN (exclusive), put a REG_DEAD note for that register in the
11763    list headed by PNOTES.
11764
11765    That said, don't move registers killed by maybe_kill_insn.
11766
11767    This is done when X is being merged by combination into TO_INSN.  These
11768    notes will then be distributed as needed.  */
11769
11770 static void
11771 move_deaths (rtx x, rtx maybe_kill_insn, int from_cuid, rtx to_insn,
11772              rtx *pnotes)
11773 {
11774   const char *fmt;
11775   int len, i;
11776   enum rtx_code code = GET_CODE (x);
11777
11778   if (code == REG)
11779     {
11780       unsigned int regno = REGNO (x);
11781       rtx where_dead = reg_stat[regno].last_death;
11782       rtx before_dead, after_dead;
11783
11784       /* Don't move the register if it gets killed in between from and to.  */
11785       if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11786           && ! reg_referenced_p (x, maybe_kill_insn))
11787         return;
11788
11789       /* WHERE_DEAD could be a USE insn made by combine, so first we
11790          make sure that we have insns with valid INSN_CUID values.  */
11791       before_dead = where_dead;
11792       while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11793         before_dead = PREV_INSN (before_dead);
11794
11795       after_dead = where_dead;
11796       while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11797         after_dead = NEXT_INSN (after_dead);
11798
11799       if (before_dead && after_dead
11800           && INSN_CUID (before_dead) >= from_cuid
11801           && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11802               || (where_dead != after_dead
11803                   && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11804         {
11805           rtx note = remove_death (regno, where_dead);
11806
11807           /* It is possible for the call above to return 0.  This can occur
11808              when last_death points to I2 or I1 that we combined with.
11809              In that case make a new note.
11810
11811              We must also check for the case where X is a hard register
11812              and NOTE is a death note for a range of hard registers
11813              including X.  In that case, we must put REG_DEAD notes for
11814              the remaining registers in place of NOTE.  */
11815
11816           if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11817               && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11818                   > GET_MODE_SIZE (GET_MODE (x))))
11819             {
11820               unsigned int deadregno = REGNO (XEXP (note, 0));
11821               unsigned int deadend
11822                 = (deadregno + hard_regno_nregs[deadregno]
11823                                                [GET_MODE (XEXP (note, 0))]);
11824               unsigned int ourend
11825                 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11826               unsigned int i;
11827
11828               for (i = deadregno; i < deadend; i++)
11829                 if (i < regno || i >= ourend)
11830                   REG_NOTES (where_dead)
11831                     = gen_rtx_EXPR_LIST (REG_DEAD,
11832                                          regno_reg_rtx[i],
11833                                          REG_NOTES (where_dead));
11834             }
11835
11836           /* If we didn't find any note, or if we found a REG_DEAD note that
11837              covers only part of the given reg, and we have a multi-reg hard
11838              register, then to be safe we must check for REG_DEAD notes
11839              for each register other than the first.  They could have
11840              their own REG_DEAD notes lying around.  */
11841           else if ((note == 0
11842                     || (note != 0
11843                         && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11844                             < GET_MODE_SIZE (GET_MODE (x)))))
11845                    && regno < FIRST_PSEUDO_REGISTER
11846                    && hard_regno_nregs[regno][GET_MODE (x)] > 1)
11847             {
11848               unsigned int ourend
11849                 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11850               unsigned int i, offset;
11851               rtx oldnotes = 0;
11852
11853               if (note)
11854                 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
11855               else
11856                 offset = 1;
11857
11858               for (i = regno + offset; i < ourend; i++)
11859                 move_deaths (regno_reg_rtx[i],
11860                              maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11861             }
11862
11863           if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11864             {
11865               XEXP (note, 1) = *pnotes;
11866               *pnotes = note;
11867             }
11868           else
11869             *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11870
11871           REG_N_DEATHS (regno)++;
11872         }
11873
11874       return;
11875     }
11876
11877   else if (GET_CODE (x) == SET)
11878     {
11879       rtx dest = SET_DEST (x);
11880
11881       move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11882
11883       /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11884          that accesses one word of a multi-word item, some
11885          piece of everything register in the expression is used by
11886          this insn, so remove any old death.  */
11887       /* ??? So why do we test for equality of the sizes?  */
11888
11889       if (GET_CODE (dest) == ZERO_EXTRACT
11890           || GET_CODE (dest) == STRICT_LOW_PART
11891           || (GET_CODE (dest) == SUBREG
11892               && (((GET_MODE_SIZE (GET_MODE (dest))
11893                     + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11894                   == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11895                        + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11896         {
11897           move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11898           return;
11899         }
11900
11901       /* If this is some other SUBREG, we know it replaces the entire
11902          value, so use that as the destination.  */
11903       if (GET_CODE (dest) == SUBREG)
11904         dest = SUBREG_REG (dest);
11905
11906       /* If this is a MEM, adjust deaths of anything used in the address.
11907          For a REG (the only other possibility), the entire value is
11908          being replaced so the old value is not used in this insn.  */
11909
11910       if (MEM_P (dest))
11911         move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11912                      to_insn, pnotes);
11913       return;
11914     }
11915
11916   else if (GET_CODE (x) == CLOBBER)
11917     return;
11918
11919   len = GET_RTX_LENGTH (code);
11920   fmt = GET_RTX_FORMAT (code);
11921
11922   for (i = 0; i < len; i++)
11923     {
11924       if (fmt[i] == 'E')
11925         {
11926           int j;
11927           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11928             move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11929                          to_insn, pnotes);
11930         }
11931       else if (fmt[i] == 'e')
11932         move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11933     }
11934 }
11935 \f
11936 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11937    pattern of an insn.  X must be a REG.  */
11938
11939 static int
11940 reg_bitfield_target_p (rtx x, rtx body)
11941 {
11942   int i;
11943
11944   if (GET_CODE (body) == SET)
11945     {
11946       rtx dest = SET_DEST (body);
11947       rtx target;
11948       unsigned int regno, tregno, endregno, endtregno;
11949
11950       if (GET_CODE (dest) == ZERO_EXTRACT)
11951         target = XEXP (dest, 0);
11952       else if (GET_CODE (dest) == STRICT_LOW_PART)
11953         target = SUBREG_REG (XEXP (dest, 0));
11954       else
11955         return 0;
11956
11957       if (GET_CODE (target) == SUBREG)
11958         target = SUBREG_REG (target);
11959
11960       if (!REG_P (target))
11961         return 0;
11962
11963       tregno = REGNO (target), regno = REGNO (x);
11964       if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11965         return target == x;
11966
11967       endtregno = tregno + hard_regno_nregs[tregno][GET_MODE (target)];
11968       endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11969
11970       return endregno > tregno && regno < endtregno;
11971     }
11972
11973   else if (GET_CODE (body) == PARALLEL)
11974     for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11975       if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11976         return 1;
11977
11978   return 0;
11979 }
11980 \f
11981 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11982    as appropriate.  I3 and I2 are the insns resulting from the combination
11983    insns including FROM (I2 may be zero).
11984
11985    ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11986    not need REG_DEAD notes because they are being substituted for.  This
11987    saves searching in the most common cases.
11988
11989    Each note in the list is either ignored or placed on some insns, depending
11990    on the type of note.  */
11991
11992 static void
11993 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
11994                   rtx elim_i1)
11995 {
11996   rtx note, next_note;
11997   rtx tem;
11998
11999   for (note = notes; note; note = next_note)
12000     {
12001       rtx place = 0, place2 = 0;
12002
12003       /* If this NOTE references a pseudo register, ensure it references
12004          the latest copy of that register.  */
12005       if (XEXP (note, 0) && REG_P (XEXP (note, 0))
12006           && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
12007         XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
12008
12009       next_note = XEXP (note, 1);
12010       switch (REG_NOTE_KIND (note))
12011         {
12012         case REG_BR_PROB:
12013         case REG_BR_PRED:
12014           /* Doesn't matter much where we put this, as long as it's somewhere.
12015              It is preferable to keep these notes on branches, which is most
12016              likely to be i3.  */
12017           place = i3;
12018           break;
12019
12020         case REG_VALUE_PROFILE:
12021           /* Just get rid of this note, as it is unused later anyway.  */
12022           break;
12023
12024         case REG_NON_LOCAL_GOTO:
12025           if (JUMP_P (i3))
12026             place = i3;
12027           else
12028             {
12029               gcc_assert (i2 && JUMP_P (i2));
12030               place = i2;
12031             }
12032           break;
12033
12034         case REG_EH_REGION:
12035           /* These notes must remain with the call or trapping instruction.  */
12036           if (CALL_P (i3))
12037             place = i3;
12038           else if (i2 && CALL_P (i2))
12039             place = i2;
12040           else
12041             {
12042               gcc_assert (flag_non_call_exceptions);
12043               if (may_trap_p (i3))
12044                 place = i3;
12045               else if (i2 && may_trap_p (i2))
12046                 place = i2;
12047               /* ??? Otherwise assume we've combined things such that we
12048                  can now prove that the instructions can't trap.  Drop the
12049                  note in this case.  */
12050             }
12051           break;
12052
12053         case REG_NORETURN:
12054         case REG_SETJMP:
12055           /* These notes must remain with the call.  It should not be
12056              possible for both I2 and I3 to be a call.  */
12057           if (CALL_P (i3))
12058             place = i3;
12059           else
12060             {
12061               gcc_assert (i2 && CALL_P (i2));
12062               place = i2;
12063             }
12064           break;
12065
12066         case REG_UNUSED:
12067           /* Any clobbers for i3 may still exist, and so we must process
12068              REG_UNUSED notes from that insn.
12069
12070              Any clobbers from i2 or i1 can only exist if they were added by
12071              recog_for_combine.  In that case, recog_for_combine created the
12072              necessary REG_UNUSED notes.  Trying to keep any original
12073              REG_UNUSED notes from these insns can cause incorrect output
12074              if it is for the same register as the original i3 dest.
12075              In that case, we will notice that the register is set in i3,
12076              and then add a REG_UNUSED note for the destination of i3, which
12077              is wrong.  However, it is possible to have REG_UNUSED notes from
12078              i2 or i1 for register which were both used and clobbered, so
12079              we keep notes from i2 or i1 if they will turn into REG_DEAD
12080              notes.  */
12081
12082           /* If this register is set or clobbered in I3, put the note there
12083              unless there is one already.  */
12084           if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12085             {
12086               if (from_insn != i3)
12087                 break;
12088
12089               if (! (REG_P (XEXP (note, 0))
12090                      ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12091                      : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12092                 place = i3;
12093             }
12094           /* Otherwise, if this register is used by I3, then this register
12095              now dies here, so we must put a REG_DEAD note here unless there
12096              is one already.  */
12097           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12098                    && ! (REG_P (XEXP (note, 0))
12099                          ? find_regno_note (i3, REG_DEAD,
12100                                             REGNO (XEXP (note, 0)))
12101                          : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12102             {
12103               PUT_REG_NOTE_KIND (note, REG_DEAD);
12104               place = i3;
12105             }
12106           break;
12107
12108         case REG_EQUAL:
12109         case REG_EQUIV:
12110         case REG_NOALIAS:
12111           /* These notes say something about results of an insn.  We can
12112              only support them if they used to be on I3 in which case they
12113              remain on I3.  Otherwise they are ignored.
12114
12115              If the note refers to an expression that is not a constant, we
12116              must also ignore the note since we cannot tell whether the
12117              equivalence is still true.  It might be possible to do
12118              slightly better than this (we only have a problem if I2DEST
12119              or I1DEST is present in the expression), but it doesn't
12120              seem worth the trouble.  */
12121
12122           if (from_insn == i3
12123               && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12124             place = i3;
12125           break;
12126
12127         case REG_INC:
12128         case REG_NO_CONFLICT:
12129           /* These notes say something about how a register is used.  They must
12130              be present on any use of the register in I2 or I3.  */
12131           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12132             place = i3;
12133
12134           if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12135             {
12136               if (place)
12137                 place2 = i2;
12138               else
12139                 place = i2;
12140             }
12141           break;
12142
12143         case REG_LABEL:
12144           /* This can show up in several ways -- either directly in the
12145              pattern, or hidden off in the constant pool with (or without?)
12146              a REG_EQUAL note.  */
12147           /* ??? Ignore the without-reg_equal-note problem for now.  */
12148           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12149               || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12150                   && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12151                   && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12152             place = i3;
12153
12154           if (i2
12155               && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12156                   || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12157                       && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12158                       && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12159             {
12160               if (place)
12161                 place2 = i2;
12162               else
12163                 place = i2;
12164             }
12165
12166           /* Don't attach REG_LABEL note to a JUMP_INSN.  Add
12167              a JUMP_LABEL instead or decrement LABEL_NUSES.  */
12168           if (place && JUMP_P (place))
12169             {
12170               rtx label = JUMP_LABEL (place);
12171
12172               if (!label)
12173                 JUMP_LABEL (place) = XEXP (note, 0);
12174               else
12175                 {
12176                   gcc_assert (label == XEXP (note, 0));
12177                   if (LABEL_P (label))
12178                     LABEL_NUSES (label)--;
12179                 }
12180               place = 0;
12181             }
12182           if (place2 && JUMP_P (place2))
12183             {
12184               rtx label = JUMP_LABEL (place2);
12185
12186               if (!label)
12187                 JUMP_LABEL (place2) = XEXP (note, 0);
12188               else
12189                 {
12190                   gcc_assert (label == XEXP (note, 0));
12191                   if (LABEL_P (label))
12192                     LABEL_NUSES (label)--;
12193                 }
12194               place2 = 0;
12195             }
12196           break;
12197
12198         case REG_NONNEG:
12199           /* This note says something about the value of a register prior
12200              to the execution of an insn.  It is too much trouble to see
12201              if the note is still correct in all situations.  It is better
12202              to simply delete it.  */
12203           break;
12204
12205         case REG_RETVAL:
12206           /* If the insn previously containing this note still exists,
12207              put it back where it was.  Otherwise move it to the previous
12208              insn.  Adjust the corresponding REG_LIBCALL note.  */
12209           if (!NOTE_P (from_insn))
12210             place = from_insn;
12211           else
12212             {
12213               tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12214               place = prev_real_insn (from_insn);
12215               if (tem && place)
12216                 XEXP (tem, 0) = place;
12217               /* If we're deleting the last remaining instruction of a
12218                  libcall sequence, don't add the notes.  */
12219               else if (XEXP (note, 0) == from_insn)
12220                 tem = place = 0;
12221               /* Don't add the dangling REG_RETVAL note.  */
12222               else if (! tem)
12223                 place = 0;
12224             }
12225           break;
12226
12227         case REG_LIBCALL:
12228           /* This is handled similarly to REG_RETVAL.  */
12229           if (!NOTE_P (from_insn))
12230             place = from_insn;
12231           else
12232             {
12233               tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12234               place = next_real_insn (from_insn);
12235               if (tem && place)
12236                 XEXP (tem, 0) = place;
12237               /* If we're deleting the last remaining instruction of a
12238                  libcall sequence, don't add the notes.  */
12239               else if (XEXP (note, 0) == from_insn)
12240                 tem = place = 0;
12241               /* Don't add the dangling REG_LIBCALL note.  */
12242               else if (! tem)
12243                 place = 0;
12244             }
12245           break;
12246
12247         case REG_DEAD:
12248           /* If we replaced the right hand side of FROM_INSN with a
12249              REG_EQUAL note, the original use of the dying register
12250              will not have been combined into I3 and I2.  In such cases,
12251              FROM_INSN is guaranteed to be the first of the combined
12252              instructions, so we simply need to search back before
12253              FROM_INSN for the previous use or set of this register,
12254              then alter the notes there appropriately.
12255
12256              If the register is used as an input in I3, it dies there.
12257              Similarly for I2, if it is nonzero and adjacent to I3.
12258
12259              If the register is not used as an input in either I3 or I2
12260              and it is not one of the registers we were supposed to eliminate,
12261              there are two possibilities.  We might have a non-adjacent I2
12262              or we might have somehow eliminated an additional register
12263              from a computation.  For example, we might have had A & B where
12264              we discover that B will always be zero.  In this case we will
12265              eliminate the reference to A.
12266
12267              In both cases, we must search to see if we can find a previous
12268              use of A and put the death note there.  */
12269
12270           if (from_insn
12271               && from_insn == i2mod
12272               && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
12273             tem = from_insn;
12274           else
12275             {
12276               if (from_insn
12277                   && CALL_P (from_insn)
12278                   && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12279                 place = from_insn;
12280               else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12281                 place = i3;
12282               else if (i2 != 0 && next_nonnote_insn (i2) == i3
12283                        && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12284                 place = i2;
12285               else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
12286                         && !(i2mod
12287                              && reg_overlap_mentioned_p (XEXP (note, 0),
12288                                                          i2mod_old_rhs)))
12289                        || rtx_equal_p (XEXP (note, 0), elim_i1))
12290                 break;
12291               tem = i3;
12292             }
12293
12294           if (place == 0)
12295             {
12296               basic_block bb = this_basic_block;
12297
12298               for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
12299                 {
12300                   if (! INSN_P (tem))
12301                     {
12302                       if (tem == BB_HEAD (bb))
12303                         break;
12304                       continue;
12305                     }
12306
12307                   /* If the register is being set at TEM, see if that is all
12308                      TEM is doing.  If so, delete TEM.  Otherwise, make this
12309                      into a REG_UNUSED note instead. Don't delete sets to
12310                      global register vars.  */
12311                   if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12312                        || !global_regs[REGNO (XEXP (note, 0))])
12313                       && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12314                     {
12315                       rtx set = single_set (tem);
12316                       rtx inner_dest = 0;
12317 #ifdef HAVE_cc0
12318                       rtx cc0_setter = NULL_RTX;
12319 #endif
12320
12321                       if (set != 0)
12322                         for (inner_dest = SET_DEST (set);
12323                              (GET_CODE (inner_dest) == STRICT_LOW_PART
12324                               || GET_CODE (inner_dest) == SUBREG
12325                               || GET_CODE (inner_dest) == ZERO_EXTRACT);
12326                              inner_dest = XEXP (inner_dest, 0))
12327                           ;
12328
12329                       /* Verify that it was the set, and not a clobber that
12330                          modified the register.
12331
12332                          CC0 targets must be careful to maintain setter/user
12333                          pairs.  If we cannot delete the setter due to side
12334                          effects, mark the user with an UNUSED note instead
12335                          of deleting it.  */
12336
12337                       if (set != 0 && ! side_effects_p (SET_SRC (set))
12338                           && rtx_equal_p (XEXP (note, 0), inner_dest)
12339 #ifdef HAVE_cc0
12340                           && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12341                               || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12342                                   && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12343 #endif
12344                           )
12345                         {
12346                           /* Move the notes and links of TEM elsewhere.
12347                              This might delete other dead insns recursively.
12348                              First set the pattern to something that won't use
12349                              any register.  */
12350                           rtx old_notes = REG_NOTES (tem);
12351
12352                           PATTERN (tem) = pc_rtx;
12353                           REG_NOTES (tem) = NULL;
12354
12355                           distribute_notes (old_notes, tem, tem, NULL_RTX,
12356                                             NULL_RTX, NULL_RTX);
12357                           distribute_links (LOG_LINKS (tem));
12358
12359                           SET_INSN_DELETED (tem);
12360
12361 #ifdef HAVE_cc0
12362                           /* Delete the setter too.  */
12363                           if (cc0_setter)
12364                             {
12365                               PATTERN (cc0_setter) = pc_rtx;
12366                               old_notes = REG_NOTES (cc0_setter);
12367                               REG_NOTES (cc0_setter) = NULL;
12368
12369                               distribute_notes (old_notes, cc0_setter,
12370                                                 cc0_setter, NULL_RTX,
12371                                                 NULL_RTX, NULL_RTX);
12372                               distribute_links (LOG_LINKS (cc0_setter));
12373
12374                               SET_INSN_DELETED (cc0_setter);
12375                             }
12376 #endif
12377                         }
12378                       else
12379                         {
12380                           PUT_REG_NOTE_KIND (note, REG_UNUSED);
12381
12382                           /*  If there isn't already a REG_UNUSED note, put one
12383                               here.  Do not place a REG_DEAD note, even if
12384                               the register is also used here; that would not
12385                               match the algorithm used in lifetime analysis
12386                               and can cause the consistency check in the
12387                               scheduler to fail.  */
12388                           if (! find_regno_note (tem, REG_UNUSED,
12389                                                  REGNO (XEXP (note, 0))))
12390                             place = tem;
12391                           break;
12392                         }
12393                     }
12394                   else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12395                            || (CALL_P (tem)
12396                                && find_reg_fusage (tem, USE, XEXP (note, 0))))
12397                     {
12398                       place = tem;
12399
12400                       /* If we are doing a 3->2 combination, and we have a
12401                          register which formerly died in i3 and was not used
12402                          by i2, which now no longer dies in i3 and is used in
12403                          i2 but does not die in i2, and place is between i2
12404                          and i3, then we may need to move a link from place to
12405                          i2.  */
12406                       if (i2 && INSN_UID (place) <= max_uid_cuid
12407                           && INSN_CUID (place) > INSN_CUID (i2)
12408                           && from_insn
12409                           && INSN_CUID (from_insn) > INSN_CUID (i2)
12410                           && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12411                         {
12412                           rtx links = LOG_LINKS (place);
12413                           LOG_LINKS (place) = 0;
12414                           distribute_links (links);
12415                         }
12416                       break;
12417                     }
12418
12419                   if (tem == BB_HEAD (bb))
12420                     break;
12421                 }
12422
12423               /* We haven't found an insn for the death note and it
12424                  is still a REG_DEAD note, but we have hit the beginning
12425                  of the block.  If the existing life info says the reg
12426                  was dead, there's nothing left to do.  Otherwise, we'll
12427                  need to do a global life update after combine.  */
12428               if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12429                   && REGNO_REG_SET_P (bb->il.rtl->global_live_at_start,
12430                                       REGNO (XEXP (note, 0))))
12431                 SET_BIT (refresh_blocks, this_basic_block->index);
12432             }
12433
12434           /* If the register is set or already dead at PLACE, we needn't do
12435              anything with this note if it is still a REG_DEAD note.
12436              We check here if it is set at all, not if is it totally replaced,
12437              which is what `dead_or_set_p' checks, so also check for it being
12438              set partially.  */
12439
12440           if (place && REG_NOTE_KIND (note) == REG_DEAD)
12441             {
12442               unsigned int regno = REGNO (XEXP (note, 0));
12443
12444               /* Similarly, if the instruction on which we want to place
12445                  the note is a noop, we'll need do a global live update
12446                  after we remove them in delete_noop_moves.  */
12447               if (noop_move_p (place))
12448                 SET_BIT (refresh_blocks, this_basic_block->index);
12449
12450               if (dead_or_set_p (place, XEXP (note, 0))
12451                   || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12452                 {
12453                   /* Unless the register previously died in PLACE, clear
12454                      last_death.  [I no longer understand why this is
12455                      being done.] */
12456                   if (reg_stat[regno].last_death != place)
12457                     reg_stat[regno].last_death = 0;
12458                   place = 0;
12459                 }
12460               else
12461                 reg_stat[regno].last_death = place;
12462
12463               /* If this is a death note for a hard reg that is occupying
12464                  multiple registers, ensure that we are still using all
12465                  parts of the object.  If we find a piece of the object
12466                  that is unused, we must arrange for an appropriate REG_DEAD
12467                  note to be added for it.  However, we can't just emit a USE
12468                  and tag the note to it, since the register might actually
12469                  be dead; so we recourse, and the recursive call then finds
12470                  the previous insn that used this register.  */
12471
12472               if (place && regno < FIRST_PSEUDO_REGISTER
12473                   && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
12474                 {
12475                   unsigned int endregno
12476                     = regno + hard_regno_nregs[regno]
12477                                               [GET_MODE (XEXP (note, 0))];
12478                   int all_used = 1;
12479                   unsigned int i;
12480
12481                   for (i = regno; i < endregno; i++)
12482                     if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12483                          && ! find_regno_fusage (place, USE, i))
12484                         || dead_or_set_regno_p (place, i))
12485                       all_used = 0;
12486
12487                   if (! all_used)
12488                     {
12489                       /* Put only REG_DEAD notes for pieces that are
12490                          not already dead or set.  */
12491
12492                       for (i = regno; i < endregno;
12493                            i += hard_regno_nregs[i][reg_raw_mode[i]])
12494                         {
12495                           rtx piece = regno_reg_rtx[i];
12496                           basic_block bb = this_basic_block;
12497
12498                           if (! dead_or_set_p (place, piece)
12499                               && ! reg_bitfield_target_p (piece,
12500                                                           PATTERN (place)))
12501                             {
12502                               rtx new_note
12503                                 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12504
12505                               distribute_notes (new_note, place, place,
12506                                                 NULL_RTX, NULL_RTX, NULL_RTX);
12507                             }
12508                           else if (! refers_to_regno_p (i, i + 1,
12509                                                         PATTERN (place), 0)
12510                                    && ! find_regno_fusage (place, USE, i))
12511                             for (tem = PREV_INSN (place); ;
12512                                  tem = PREV_INSN (tem))
12513                               {
12514                                 if (! INSN_P (tem))
12515                                   {
12516                                     if (tem == BB_HEAD (bb))
12517                                       {
12518                                         SET_BIT (refresh_blocks,
12519                                                  this_basic_block->index);
12520                                         break;
12521                                       }
12522                                     continue;
12523                                   }
12524                                 if (dead_or_set_p (tem, piece)
12525                                     || reg_bitfield_target_p (piece,
12526                                                               PATTERN (tem)))
12527                                   {
12528                                     REG_NOTES (tem)
12529                                       = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12530                                                            REG_NOTES (tem));
12531                                     break;
12532                                   }
12533                               }
12534
12535                         }
12536
12537                       place = 0;
12538                     }
12539                 }
12540             }
12541           break;
12542
12543         default:
12544           /* Any other notes should not be present at this point in the
12545              compilation.  */
12546           gcc_unreachable ();
12547         }
12548
12549       if (place)
12550         {
12551           XEXP (note, 1) = REG_NOTES (place);
12552           REG_NOTES (place) = note;
12553         }
12554       else if ((REG_NOTE_KIND (note) == REG_DEAD
12555                 || REG_NOTE_KIND (note) == REG_UNUSED)
12556                && REG_P (XEXP (note, 0)))
12557         REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12558
12559       if (place2)
12560         {
12561           if ((REG_NOTE_KIND (note) == REG_DEAD
12562                || REG_NOTE_KIND (note) == REG_UNUSED)
12563               && REG_P (XEXP (note, 0)))
12564             REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12565
12566           REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12567                                                REG_NOTE_KIND (note),
12568                                                XEXP (note, 0),
12569                                                REG_NOTES (place2));
12570         }
12571     }
12572 }
12573 \f
12574 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12575    I3, I2, and I1 to new locations.  This is also called to add a link
12576    pointing at I3 when I3's destination is changed.  */
12577
12578 static void
12579 distribute_links (rtx links)
12580 {
12581   rtx link, next_link;
12582
12583   for (link = links; link; link = next_link)
12584     {
12585       rtx place = 0;
12586       rtx insn;
12587       rtx set, reg;
12588
12589       next_link = XEXP (link, 1);
12590
12591       /* If the insn that this link points to is a NOTE or isn't a single
12592          set, ignore it.  In the latter case, it isn't clear what we
12593          can do other than ignore the link, since we can't tell which
12594          register it was for.  Such links wouldn't be used by combine
12595          anyway.
12596
12597          It is not possible for the destination of the target of the link to
12598          have been changed by combine.  The only potential of this is if we
12599          replace I3, I2, and I1 by I3 and I2.  But in that case the
12600          destination of I2 also remains unchanged.  */
12601
12602       if (NOTE_P (XEXP (link, 0))
12603           || (set = single_set (XEXP (link, 0))) == 0)
12604         continue;
12605
12606       reg = SET_DEST (set);
12607       while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12608              || GET_CODE (reg) == STRICT_LOW_PART)
12609         reg = XEXP (reg, 0);
12610
12611       /* A LOG_LINK is defined as being placed on the first insn that uses
12612          a register and points to the insn that sets the register.  Start
12613          searching at the next insn after the target of the link and stop
12614          when we reach a set of the register or the end of the basic block.
12615
12616          Note that this correctly handles the link that used to point from
12617          I3 to I2.  Also note that not much searching is typically done here
12618          since most links don't point very far away.  */
12619
12620       for (insn = NEXT_INSN (XEXP (link, 0));
12621            (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12622                      || BB_HEAD (this_basic_block->next_bb) != insn));
12623            insn = NEXT_INSN (insn))
12624         if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12625           {
12626             if (reg_referenced_p (reg, PATTERN (insn)))
12627               place = insn;
12628             break;
12629           }
12630         else if (CALL_P (insn)
12631                  && find_reg_fusage (insn, USE, reg))
12632           {
12633             place = insn;
12634             break;
12635           }
12636         else if (INSN_P (insn) && reg_set_p (reg, insn))
12637           break;
12638
12639       /* If we found a place to put the link, place it there unless there
12640          is already a link to the same insn as LINK at that point.  */
12641
12642       if (place)
12643         {
12644           rtx link2;
12645
12646           for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12647             if (XEXP (link2, 0) == XEXP (link, 0))
12648               break;
12649
12650           if (link2 == 0)
12651             {
12652               XEXP (link, 1) = LOG_LINKS (place);
12653               LOG_LINKS (place) = link;
12654
12655               /* Set added_links_insn to the earliest insn we added a
12656                  link to.  */
12657               if (added_links_insn == 0
12658                   || INSN_CUID (added_links_insn) > INSN_CUID (place))
12659                 added_links_insn = place;
12660             }
12661         }
12662     }
12663 }
12664 \f
12665 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12666    Check whether the expression pointer to by LOC is a register or
12667    memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12668    Otherwise return zero.  */
12669
12670 static int
12671 unmentioned_reg_p_1 (rtx *loc, void *expr)
12672 {
12673   rtx x = *loc;
12674
12675   if (x != NULL_RTX
12676       && (REG_P (x) || MEM_P (x))
12677       && ! reg_mentioned_p (x, (rtx) expr))
12678     return 1;
12679   return 0;
12680 }
12681
12682 /* Check for any register or memory mentioned in EQUIV that is not
12683    mentioned in EXPR.  This is used to restrict EQUIV to "specializations"
12684    of EXPR where some registers may have been replaced by constants.  */
12685
12686 static bool
12687 unmentioned_reg_p (rtx equiv, rtx expr)
12688 {
12689   return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
12690 }
12691 \f
12692 /* Compute INSN_CUID for INSN, which is an insn made by combine.  */
12693
12694 static int
12695 insn_cuid (rtx insn)
12696 {
12697   while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12698          && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE)
12699     insn = NEXT_INSN (insn);
12700
12701   gcc_assert (INSN_UID (insn) <= max_uid_cuid);
12702
12703   return INSN_CUID (insn);
12704 }
12705 \f
12706 void
12707 dump_combine_stats (FILE *file)
12708 {
12709   fprintf
12710     (file,
12711      ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12712      combine_attempts, combine_merges, combine_extras, combine_successes);
12713 }
12714
12715 void
12716 dump_combine_total_stats (FILE *file)
12717 {
12718   fprintf
12719     (file,
12720      "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12721      total_attempts, total_merges, total_extras, total_successes);
12722 }
12723 \f
12724
12725 static bool
12726 gate_handle_combine (void)
12727 {
12728   return (optimize > 0);
12729 }
12730
12731 /* Try combining insns through substitution.  */
12732 static void
12733 rest_of_handle_combine (void)
12734 {
12735   int rebuild_jump_labels_after_combine
12736     = combine_instructions (get_insns (), max_reg_num ());
12737
12738   /* Combining insns may have turned an indirect jump into a
12739      direct jump.  Rebuild the JUMP_LABEL fields of jumping
12740      instructions.  */
12741   if (rebuild_jump_labels_after_combine)
12742     {
12743       timevar_push (TV_JUMP);
12744       rebuild_jump_labels (get_insns ());
12745       timevar_pop (TV_JUMP);
12746
12747       delete_dead_jumptables ();
12748       cleanup_cfg (CLEANUP_EXPENSIVE | CLEANUP_UPDATE_LIFE);
12749     }
12750 }
12751
12752 struct tree_opt_pass pass_combine =
12753 {
12754   "combine",                            /* name */
12755   gate_handle_combine,                  /* gate */
12756   rest_of_handle_combine,               /* execute */
12757   NULL,                                 /* sub */
12758   NULL,                                 /* next */
12759   0,                                    /* static_pass_number */
12760   TV_COMBINE,                           /* tv_id */
12761   0,                                    /* properties_required */
12762   0,                                    /* properties_provided */
12763   0,                                    /* properties_destroyed */
12764   0,                                    /* todo_flags_start */
12765   TODO_dump_func |
12766   TODO_ggc_collect,                     /* todo_flags_finish */
12767   'c'                                   /* letter */
12768 };
12769