| blob | 6cc25e79671db0b99e604a5d2896a1e46b6b5674 |
1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 ;; 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;;
6 ;; This file is part of GCC.
7 ;;
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; any later version.
12 ;;
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
17 ;;
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 ;; Boston, MA 02110-1301, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; Uses of UNSPEC in this file:
27 (define_constants
28 [(UNSPEC_ARG_HOME 0)
29 (UNSPEC_INSXH 2)
30 (UNSPEC_MSKXH 3)
31 (UNSPEC_CVTQL 4)
32 (UNSPEC_CVTLQ 5)
33 (UNSPEC_UMK_LAUM 6)
34 (UNSPEC_UMK_LALM 7)
35 (UNSPEC_UMK_LAL 8)
36 (UNSPEC_UMK_LOAD_CIW 9)
37 (UNSPEC_LDGP2 10)
38 (UNSPEC_LITERAL 11)
39 (UNSPEC_LITUSE 12)
40 (UNSPEC_SIBCALL 13)
41 (UNSPEC_SYMBOL 14)
43 ;; TLS Support
44 (UNSPEC_TLSGD_CALL 15)
45 (UNSPEC_TLSLDM_CALL 16)
46 (UNSPEC_TLSGD 17)
47 (UNSPEC_TLSLDM 18)
48 (UNSPEC_DTPREL 19)
49 (UNSPEC_TPREL 20)
50 (UNSPEC_TP 21)
52 ;; Builtins
53 (UNSPEC_CMPBGE 22)
54 (UNSPEC_ZAP 23)
55 (UNSPEC_AMASK 24)
56 (UNSPEC_IMPLVER 25)
57 (UNSPEC_PERR 26)
58 (UNSPEC_COPYSIGN 27)
60 ;; Atomic operations
61 (UNSPEC_MB 28)
62 (UNSPEC_ATOMIC 31)
63 (UNSPEC_CMPXCHG 32)
64 (UNSPEC_XCHG 33)
65 ])
67 ;; UNSPEC_VOLATILE:
69 (define_constants
70 [(UNSPECV_IMB 0)
71 (UNSPECV_BLOCKAGE 1)
72 (UNSPECV_SETJMPR 2) ; builtin_setjmp_receiver
73 (UNSPECV_LONGJMP 3) ; builtin_longjmp
74 (UNSPECV_TRAPB 4)
75 (UNSPECV_PSPL 5) ; prologue_stack_probe_loop
76 (UNSPECV_REALIGN 6)
77 (UNSPECV_EHR 7) ; exception_receiver
78 (UNSPECV_MCOUNT 8)
79 (UNSPECV_FORCE_MOV 9)
80 (UNSPECV_LDGP1 10)
81 (UNSPECV_PLDGP2 11) ; prologue ldgp
82 (UNSPECV_SET_TP 12)
83 (UNSPECV_RPCC 13)
84 (UNSPECV_SETJMPR_ER 14) ; builtin_setjmp_receiver fragment
85 (UNSPECV_LL 15) ; load-locked
86 (UNSPECV_SC 16) ; store-conditional
87 ])
89 ;; Where necessary, the suffixes _le and _be are used to distinguish between
90 ;; little-endian and big-endian patterns.
91 ;;
92 ;; Note that the Unicos/Mk assembler does not support the following
93 ;; opcodes: mov, fmov, nop, fnop, unop.
94 \f
95 ;; Processor type -- this attribute must exactly match the processor_type
96 ;; enumeration in alpha.h.
98 (define_attr "tune" "ev4,ev5,ev6"
99 (const (symbol_ref "alpha_tune")))
101 ;; Define an insn type attribute. This is used in function unit delay
102 ;; computations, among other purposes. For the most part, we use the names
103 ;; defined in the EV4 documentation, but add a few that we have to know about
104 ;; separately.
106 (define_attr "type"
107 "ild,fld,ldsym,ist,fst,ibr,callpal,fbr,jsr,iadd,ilog,shift,icmov,fcmov,
108 icmp,imul,fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,mb,ld_l,st_c,
109 multi,none"
110 (const_string "iadd"))
112 ;; Describe a user's asm statement.
113 (define_asm_attributes
114 [(set_attr "type" "multi")])
116 ;; Define the operand size an insn operates on. Used primarily by mul
117 ;; and div operations that have size dependent timings.
119 (define_attr "opsize" "si,di,udi"
120 (const_string "di"))
122 ;; The TRAP attribute marks instructions that may generate traps
123 ;; (which are imprecise and may need a trapb if software completion
124 ;; is desired).
126 (define_attr "trap" "no,yes"
127 (const_string "no"))
129 ;; The ROUND_SUFFIX attribute marks which instructions require a
130 ;; rounding-mode suffix. The value NONE indicates no suffix,
131 ;; the value NORMAL indicates a suffix controlled by alpha_fprm.
133 (define_attr "round_suffix" "none,normal,c"
134 (const_string "none"))
136 ;; The TRAP_SUFFIX attribute marks instructions requiring a trap-mode suffix:
137 ;; NONE no suffix
138 ;; SU accepts only /su (cmpt et al)
139 ;; SUI accepts only /sui (cvtqt and cvtqs)
140 ;; V_SV accepts /v and /sv (cvtql only)
141 ;; V_SV_SVI accepts /v, /sv and /svi (cvttq only)
142 ;; U_SU_SUI accepts /u, /su and /sui (most fp instructions)
143 ;;
144 ;; The actual suffix emitted is controlled by alpha_fptm.
146 (define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui"
147 (const_string "none"))
149 ;; The length of an instruction sequence in bytes.
151 (define_attr "length" ""
152 (const_int 4))
154 ;; The USEGP attribute marks instructions that have relocations that use
155 ;; the GP.
157 (define_attr "usegp" "no,yes"
158 (cond [(eq_attr "type" "ldsym,jsr")
159 (const_string "yes")
160 (eq_attr "type" "ild,fld,ist,fst")
161 (symbol_ref "alpha_find_lo_sum_using_gp(insn)")
162 ]
163 (const_string "no")))
165 ;; The CANNOT_COPY attribute marks instructions with relocations that
166 ;; cannot easily be duplicated. This includes insns with gpdisp relocs
167 ;; since they have to stay in 1-1 correspondence with one another. This
168 ;; also includes jsr insns, since they must stay in correspondence with
169 ;; the immediately following gpdisp instructions.
171 (define_attr "cannot_copy" "false,true"
172 (const_string "false"))
173 \f
174 ;; Include scheduling descriptions.
176 (include "ev4.md")
177 (include "ev5.md")
178 (include "ev6.md")
180 \f
181 ;; Include predicate definitions
183 (include "predicates.md")
185 \f
186 ;; First define the arithmetic insns. Note that the 32-bit forms also
187 ;; sign-extend.
189 ;; Handle 32-64 bit extension from memory to a floating point register
190 ;; specially, since this occurs frequently in int->double conversions.
191 ;;
192 ;; Note that while we must retain the =f case in the insn for reload's
193 ;; benefit, it should be eliminated after reload, so we should never emit
194 ;; code for that case. But we don't reject the possibility.
196 (define_expand "extendsidi2"
197 [(set (match_operand:DI 0 "register_operand" "")
198 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
199 ""
200 "")
202 (define_insn "*cvtlq"
203 [(set (match_operand:DI 0 "register_operand" "=f")
204 (unspec:DI [(match_operand:SF 1 "reg_or_0_operand" "fG")]
205 UNSPEC_CVTLQ))]
206 ""
207 "cvtlq %1,%0"
208 [(set_attr "type" "fadd")])
210 (define_insn "*extendsidi2_1"
211 [(set (match_operand:DI 0 "register_operand" "=r,r,!*f")
212 (sign_extend:DI
213 (match_operand:SI 1 "nonimmediate_operand" "r,m,m")))]
214 ""
215 "@
216 addl $31,%1,%0
217 ldl %0,%1
218 lds %0,%1\;cvtlq %0,%0"
219 [(set_attr "type" "iadd,ild,fld")
220 (set_attr "length" "*,*,8")])
222 (define_split
223 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
224 (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
225 "reload_completed"
226 [(set (match_dup 2) (match_dup 1))
227 (set (match_dup 0) (unspec:DI [(match_dup 2)] UNSPEC_CVTLQ))]
228 {
229 operands[1] = adjust_address (operands[1], SFmode, 0);
230 operands[2] = gen_rtx_REG (SFmode, REGNO (operands[0]));
231 })
233 ;; Optimize sign-extension of SImode loads. This shows up in the wake of
234 ;; reload when converting fp->int.
236 (define_peephole2
237 [(set (match_operand:SI 0 "hard_int_register_operand" "")
238 (match_operand:SI 1 "memory_operand" ""))
239 (set (match_operand:DI 2 "hard_int_register_operand" "")
240 (sign_extend:DI (match_dup 0)))]
241 "true_regnum (operands[0]) == true_regnum (operands[2])
242 || peep2_reg_dead_p (2, operands[0])"
243 [(set (match_dup 2)
244 (sign_extend:DI (match_dup 1)))]
245 "")
247 ;; Don't say we have addsi3 if optimizing. This generates better code. We
248 ;; have the anonymous addsi3 pattern below in case combine wants to make it.
249 (define_expand "addsi3"
250 [(set (match_operand:SI 0 "register_operand" "")
251 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
252 (match_operand:SI 2 "add_operand" "")))]
253 "! optimize"
254 "")
256 (define_insn "*addsi_internal"
257 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
258 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
259 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
260 ""
261 "@
262 addl %r1,%2,%0
263 subl %r1,%n2,%0
264 lda %0,%2(%r1)
265 ldah %0,%h2(%r1)")
267 (define_split
268 [(set (match_operand:SI 0 "register_operand" "")
269 (plus:SI (match_operand:SI 1 "register_operand" "")
270 (match_operand:SI 2 "const_int_operand" "")))]
271 "! add_operand (operands[2], SImode)"
272 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
273 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
274 {
275 HOST_WIDE_INT val = INTVAL (operands[2]);
276 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
277 HOST_WIDE_INT rest = val - low;
279 operands[3] = GEN_INT (rest);
280 operands[4] = GEN_INT (low);
281 })
283 (define_insn "*addsi_se"
284 [(set (match_operand:DI 0 "register_operand" "=r,r")
285 (sign_extend:DI
286 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
287 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
288 ""
289 "@
290 addl %r1,%2,%0
291 subl %r1,%n2,%0")
293 (define_insn "*addsi_se2"
294 [(set (match_operand:DI 0 "register_operand" "=r,r")
295 (sign_extend:DI
296 (subreg:SI (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
297 (match_operand:DI 2 "sext_add_operand" "rI,O"))
298 0)))]
299 ""
300 "@
301 addl %r1,%2,%0
302 subl %r1,%n2,%0")
304 (define_split
305 [(set (match_operand:DI 0 "register_operand" "")
306 (sign_extend:DI
307 (plus:SI (match_operand:SI 1 "reg_not_elim_operand" "")
308 (match_operand:SI 2 "const_int_operand" ""))))
309 (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
310 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
311 && INTVAL (operands[2]) % 4 == 0"
312 [(set (match_dup 3) (match_dup 4))
313 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
314 (match_dup 5))
315 (match_dup 1))))]
316 {
317 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
318 int mult = 4;
320 if (val % 2 == 0)
321 val /= 2, mult = 8;
323 operands[4] = GEN_INT (val);
324 operands[5] = GEN_INT (mult);
325 })
327 (define_split
328 [(set (match_operand:DI 0 "register_operand" "")
329 (sign_extend:DI
330 (plus:SI (match_operator:SI 1 "comparison_operator"
331 [(match_operand 2 "" "")
332 (match_operand 3 "" "")])
333 (match_operand:SI 4 "add_operand" ""))))
334 (clobber (match_operand:DI 5 "register_operand" ""))]
335 ""
336 [(set (match_dup 5) (match_dup 6))
337 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
338 {
339 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
340 operands[2], operands[3]);
341 operands[7] = gen_lowpart (SImode, operands[5]);
342 })
344 (define_insn "addvsi3"
345 [(set (match_operand:SI 0 "register_operand" "=r,r")
346 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
347 (match_operand:SI 2 "sext_add_operand" "rI,O")))
348 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
349 (sign_extend:DI (match_dup 2)))
350 (sign_extend:DI (plus:SI (match_dup 1)
351 (match_dup 2))))
352 (const_int 0))]
353 ""
354 "@
355 addlv %r1,%2,%0
356 sublv %r1,%n2,%0")
358 (define_expand "adddi3"
359 [(set (match_operand:DI 0 "register_operand" "")
360 (plus:DI (match_operand:DI 1 "register_operand" "")
361 (match_operand:DI 2 "add_operand" "")))]
362 ""
363 "")
365 (define_insn "*adddi_er_lo16_dtp"
366 [(set (match_operand:DI 0 "register_operand" "=r")
367 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
368 (match_operand:DI 2 "dtp16_symbolic_operand" "")))]
369 "HAVE_AS_TLS"
370 "lda %0,%2(%1)\t\t!dtprel")
372 (define_insn "*adddi_er_hi32_dtp"
373 [(set (match_operand:DI 0 "register_operand" "=r")
374 (plus:DI (match_operand:DI 1 "register_operand" "r")
375 (high:DI (match_operand:DI 2 "dtp32_symbolic_operand" ""))))]
376 "HAVE_AS_TLS"
377 "ldah %0,%2(%1)\t\t!dtprelhi")
379 (define_insn "*adddi_er_lo32_dtp"
380 [(set (match_operand:DI 0 "register_operand" "=r")
381 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
382 (match_operand:DI 2 "dtp32_symbolic_operand" "")))]
383 "HAVE_AS_TLS"
384 "lda %0,%2(%1)\t\t!dtprello")
386 (define_insn "*adddi_er_lo16_tp"
387 [(set (match_operand:DI 0 "register_operand" "=r")
388 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
389 (match_operand:DI 2 "tp16_symbolic_operand" "")))]
390 "HAVE_AS_TLS"
391 "lda %0,%2(%1)\t\t!tprel")
393 (define_insn "*adddi_er_hi32_tp"
394 [(set (match_operand:DI 0 "register_operand" "=r")
395 (plus:DI (match_operand:DI 1 "register_operand" "r")
396 (high:DI (match_operand:DI 2 "tp32_symbolic_operand" ""))))]
397 "HAVE_AS_TLS"
398 "ldah %0,%2(%1)\t\t!tprelhi")
400 (define_insn "*adddi_er_lo32_tp"
401 [(set (match_operand:DI 0 "register_operand" "=r")
402 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
403 (match_operand:DI 2 "tp32_symbolic_operand" "")))]
404 "HAVE_AS_TLS"
405 "lda %0,%2(%1)\t\t!tprello")
407 (define_insn "*adddi_er_high_l"
408 [(set (match_operand:DI 0 "register_operand" "=r")
409 (plus:DI (match_operand:DI 1 "register_operand" "r")
410 (high:DI (match_operand:DI 2 "local_symbolic_operand" ""))))]
411 "TARGET_EXPLICIT_RELOCS && reload_completed"
412 "ldah %0,%2(%1)\t\t!gprelhigh"
413 [(set_attr "usegp" "yes")])
415 (define_split
416 [(set (match_operand:DI 0 "register_operand" "")
417 (high:DI (match_operand:DI 1 "local_symbolic_operand" "")))]
418 "TARGET_EXPLICIT_RELOCS && reload_completed"
419 [(set (match_dup 0)
420 (plus:DI (match_dup 2) (high:DI (match_dup 1))))]
421 "operands[2] = pic_offset_table_rtx;")
423 ;; We used to expend quite a lot of effort choosing addq/subq/lda.
424 ;; With complications like
425 ;;
426 ;; The NT stack unwind code can't handle a subq to adjust the stack
427 ;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3,
428 ;; the exception handling code will loop if a subq is used and an
429 ;; exception occurs.
430 ;;
431 ;; The 19980616 change to emit prologues as RTL also confused some
432 ;; versions of GDB, which also interprets prologues. This has been
433 ;; fixed as of GDB 4.18, but it does not harm to unconditionally
434 ;; use lda here.
435 ;;
436 ;; and the fact that the three insns schedule exactly the same, it's
437 ;; just not worth the effort.
439 (define_insn "*adddi_internal"
440 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
441 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r")
442 (match_operand:DI 2 "add_operand" "r,K,L")))]
443 ""
444 "@
445 addq %1,%2,%0
446 lda %0,%2(%1)
447 ldah %0,%h2(%1)")
449 ;; ??? Allow large constants when basing off the frame pointer or some
450 ;; virtual register that may eliminate to the frame pointer. This is
451 ;; done because register elimination offsets will change the hi/lo split,
452 ;; and if we split before reload, we will require additional instructions.
454 (define_insn "*adddi_fp_hack"
455 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
456 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r,r,r")
457 (match_operand:DI 2 "const_int_operand" "K,L,n")))]
458 "NONSTRICT_REG_OK_FP_BASE_P (operands[1])
459 && INTVAL (operands[2]) >= 0
460 /* This is the largest constant an lda+ldah pair can add, minus
461 an upper bound on the displacement between SP and AP during
462 register elimination. See INITIAL_ELIMINATION_OFFSET. */
463 && INTVAL (operands[2])
464 < (0x7fff8000
465 - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD
466 - ALPHA_ROUND(current_function_outgoing_args_size)
467 - (ALPHA_ROUND (get_frame_size ()
468 + max_reg_num () * UNITS_PER_WORD
469 + current_function_pretend_args_size)
470 - current_function_pretend_args_size))"
471 "@
472 lda %0,%2(%1)
473 ldah %0,%h2(%1)
474 #")
476 ;; Don't do this if we are adjusting SP since we don't want to do it
477 ;; in two steps. Don't split FP sources for the reason listed above.
478 (define_split
479 [(set (match_operand:DI 0 "register_operand" "")
480 (plus:DI (match_operand:DI 1 "register_operand" "")
481 (match_operand:DI 2 "const_int_operand" "")))]
482 "! add_operand (operands[2], DImode)
483 && operands[0] != stack_pointer_rtx
484 && operands[1] != frame_pointer_rtx
485 && operands[1] != arg_pointer_rtx"
486 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
487 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
488 {
489 HOST_WIDE_INT val = INTVAL (operands[2]);
490 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
491 HOST_WIDE_INT rest = val - low;
493 operands[4] = GEN_INT (low);
494 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
495 operands[3] = GEN_INT (rest);
496 else if (! no_new_pseudos)
497 {
498 operands[3] = gen_reg_rtx (DImode);
499 emit_move_insn (operands[3], operands[2]);
500 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
501 DONE;
502 }
503 else
504 FAIL;
505 })
507 (define_insn "*saddl"
508 [(set (match_operand:SI 0 "register_operand" "=r,r")
509 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
510 (match_operand:SI 2 "const48_operand" "I,I"))
511 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
512 ""
513 "@
514 s%2addl %1,%3,%0
515 s%2subl %1,%n3,%0")
517 (define_insn "*saddl_se"
518 [(set (match_operand:DI 0 "register_operand" "=r,r")
519 (sign_extend:DI
520 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
521 (match_operand:SI 2 "const48_operand" "I,I"))
522 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
523 ""
524 "@
525 s%2addl %1,%3,%0
526 s%2subl %1,%n3,%0")
528 (define_split
529 [(set (match_operand:DI 0 "register_operand" "")
530 (sign_extend:DI
531 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
532 [(match_operand 2 "" "")
533 (match_operand 3 "" "")])
534 (match_operand:SI 4 "const48_operand" ""))
535 (match_operand:SI 5 "sext_add_operand" ""))))
536 (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))]
537 ""
538 [(set (match_dup 6) (match_dup 7))
539 (set (match_dup 0)
540 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
541 (match_dup 5))))]
542 {
543 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
544 operands[2], operands[3]);
545 operands[8] = gen_lowpart (SImode, operands[6]);
546 })
548 (define_insn "*saddq"
549 [(set (match_operand:DI 0 "register_operand" "=r,r")
550 (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
551 (match_operand:DI 2 "const48_operand" "I,I"))
552 (match_operand:DI 3 "sext_add_operand" "rI,O")))]
553 ""
554 "@
555 s%2addq %1,%3,%0
556 s%2subq %1,%n3,%0")
558 (define_insn "addvdi3"
559 [(set (match_operand:DI 0 "register_operand" "=r,r")
560 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
561 (match_operand:DI 2 "sext_add_operand" "rI,O")))
562 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
563 (sign_extend:TI (match_dup 2)))
564 (sign_extend:TI (plus:DI (match_dup 1)
565 (match_dup 2))))
566 (const_int 0))]
567 ""
568 "@
569 addqv %r1,%2,%0
570 subqv %r1,%n2,%0")
572 (define_insn "negsi2"
573 [(set (match_operand:SI 0 "register_operand" "=r")
574 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
575 ""
576 "subl $31,%1,%0")
578 (define_insn "*negsi_se"
579 [(set (match_operand:DI 0 "register_operand" "=r")
580 (sign_extend:DI (neg:SI
581 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
582 ""
583 "subl $31,%1,%0")
585 (define_insn "negvsi2"
586 [(set (match_operand:SI 0 "register_operand" "=r")
587 (neg:SI (match_operand:SI 1 "register_operand" "r")))
588 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
589 (sign_extend:DI (neg:SI (match_dup 1))))
590 (const_int 0))]
591 ""
592 "sublv $31,%1,%0")
594 (define_insn "negdi2"
595 [(set (match_operand:DI 0 "register_operand" "=r")
596 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
597 ""
598 "subq $31,%1,%0")
600 (define_insn "negvdi2"
601 [(set (match_operand:DI 0 "register_operand" "=r")
602 (neg:DI (match_operand:DI 1 "register_operand" "r")))
603 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
604 (sign_extend:TI (neg:DI (match_dup 1))))
605 (const_int 0))]
606 ""
607 "subqv $31,%1,%0")
609 (define_expand "subsi3"
610 [(set (match_operand:SI 0 "register_operand" "")
611 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
612 (match_operand:SI 2 "reg_or_8bit_operand" "")))]
613 "! optimize"
614 "")
616 (define_insn "*subsi_internal"
617 [(set (match_operand:SI 0 "register_operand" "=r")
618 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
619 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
620 ""
621 "subl %r1,%2,%0")
623 (define_insn "*subsi_se"
624 [(set (match_operand:DI 0 "register_operand" "=r")
625 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
626 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
627 ""
628 "subl %r1,%2,%0")
630 (define_insn "*subsi_se2"
631 [(set (match_operand:DI 0 "register_operand" "=r")
632 (sign_extend:DI
633 (subreg:SI (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
634 (match_operand:DI 2 "reg_or_8bit_operand" "rI"))
635 0)))]
636 ""
637 "subl %r1,%2,%0")
639 (define_insn "subvsi3"
640 [(set (match_operand:SI 0 "register_operand" "=r")
641 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
642 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
643 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
644 (sign_extend:DI (match_dup 2)))
645 (sign_extend:DI (minus:SI (match_dup 1)
646 (match_dup 2))))
647 (const_int 0))]
648 ""
649 "sublv %r1,%2,%0")
651 (define_insn "subdi3"
652 [(set (match_operand:DI 0 "register_operand" "=r")
653 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
654 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
655 ""
656 "subq %r1,%2,%0")
658 (define_insn "*ssubl"
659 [(set (match_operand:SI 0 "register_operand" "=r")
660 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
661 (match_operand:SI 2 "const48_operand" "I"))
662 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
663 ""
664 "s%2subl %1,%3,%0")
666 (define_insn "*ssubl_se"
667 [(set (match_operand:DI 0 "register_operand" "=r")
668 (sign_extend:DI
669 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
670 (match_operand:SI 2 "const48_operand" "I"))
671 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
672 ""
673 "s%2subl %1,%3,%0")
675 (define_insn "*ssubq"
676 [(set (match_operand:DI 0 "register_operand" "=r")
677 (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
678 (match_operand:DI 2 "const48_operand" "I"))
679 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
680 ""
681 "s%2subq %1,%3,%0")
683 (define_insn "subvdi3"
684 [(set (match_operand:DI 0 "register_operand" "=r")
685 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
686 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
687 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
688 (sign_extend:TI (match_dup 2)))
689 (sign_extend:TI (minus:DI (match_dup 1)
690 (match_dup 2))))
691 (const_int 0))]
692 ""
693 "subqv %r1,%2,%0")
695 ;; The Unicos/Mk assembler doesn't support mull.
697 (define_insn "mulsi3"
698 [(set (match_operand:SI 0 "register_operand" "=r")
699 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
700 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
701 "!TARGET_ABI_UNICOSMK"
702 "mull %r1,%2,%0"
703 [(set_attr "type" "imul")
704 (set_attr "opsize" "si")])
706 (define_insn "*mulsi_se"
707 [(set (match_operand:DI 0 "register_operand" "=r")
708 (sign_extend:DI
709 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
710 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
711 "!TARGET_ABI_UNICOSMK"
712 "mull %r1,%2,%0"
713 [(set_attr "type" "imul")
714 (set_attr "opsize" "si")])
716 (define_insn "mulvsi3"
717 [(set (match_operand:SI 0 "register_operand" "=r")
718 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
719 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
720 (trap_if (ne (mult:DI (sign_extend:DI (match_dup 1))
721 (sign_extend:DI (match_dup 2)))
722 (sign_extend:DI (mult:SI (match_dup 1)
723 (match_dup 2))))
724 (const_int 0))]
725 "!TARGET_ABI_UNICOSMK"
726 "mullv %r1,%2,%0"
727 [(set_attr "type" "imul")
728 (set_attr "opsize" "si")])
730 (define_insn "muldi3"
731 [(set (match_operand:DI 0 "register_operand" "=r")
732 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
733 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
734 ""
735 "mulq %r1,%2,%0"
736 [(set_attr "type" "imul")])
738 (define_insn "mulvdi3"
739 [(set (match_operand:DI 0 "register_operand" "=r")
740 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
741 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
742 (trap_if (ne (mult:TI (sign_extend:TI (match_dup 1))
743 (sign_extend:TI (match_dup 2)))
744 (sign_extend:TI (mult:DI (match_dup 1)
745 (match_dup 2))))
746 (const_int 0))]
747 ""
748 "mulqv %r1,%2,%0"
749 [(set_attr "type" "imul")])
751 (define_expand "umuldi3_highpart"
752 [(set (match_operand:DI 0 "register_operand" "")
753 (truncate:DI
754 (lshiftrt:TI
755 (mult:TI (zero_extend:TI
756 (match_operand:DI 1 "register_operand" ""))
757 (match_operand:DI 2 "reg_or_8bit_operand" ""))
758 (const_int 64))))]
759 ""
760 {
761 if (REG_P (operands[2]))
762 operands[2] = gen_rtx_ZERO_EXTEND (TImode, operands[2]);
763 })
765 (define_insn "*umuldi3_highpart_reg"
766 [(set (match_operand:DI 0 "register_operand" "=r")
767 (truncate:DI
768 (lshiftrt:TI
769 (mult:TI (zero_extend:TI
770 (match_operand:DI 1 "register_operand" "r"))
771 (zero_extend:TI
772 (match_operand:DI 2 "register_operand" "r")))
773 (const_int 64))))]
774 ""
775 "umulh %1,%2,%0"
776 [(set_attr "type" "imul")
777 (set_attr "opsize" "udi")])
779 (define_insn "*umuldi3_highpart_const"
780 [(set (match_operand:DI 0 "register_operand" "=r")
781 (truncate:DI
782 (lshiftrt:TI
783 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
784 (match_operand:TI 2 "cint8_operand" "I"))
785 (const_int 64))))]
786 ""
787 "umulh %1,%2,%0"
788 [(set_attr "type" "imul")
789 (set_attr "opsize" "udi")])
790 \f
791 ;; The divide and remainder operations take their inputs from r24 and
792 ;; r25, put their output in r27, and clobber r23 and r28 on all
793 ;; systems except Unicos/Mk. On Unicos, the standard library provides
794 ;; subroutines which use the standard calling convention and work on
795 ;; DImode operands.
797 ;; ??? Force sign-extension here because some versions of OSF/1 and
798 ;; Interix/NT don't do the right thing if the inputs are not properly
799 ;; sign-extended. But Linux, for instance, does not have this
800 ;; problem. Is it worth the complication here to eliminate the sign
801 ;; extension?
803 (define_expand "divsi3"
804 [(set (match_dup 3)
805 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
806 (set (match_dup 4)
807 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
808 (parallel [(set (match_dup 5)
809 (sign_extend:DI (div:SI (match_dup 3) (match_dup 4))))
810 (clobber (reg:DI 23))
811 (clobber (reg:DI 28))])
812 (set (match_operand:SI 0 "nonimmediate_operand" "")
813 (subreg:SI (match_dup 5) 0))]
814 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
815 {
816 operands[3] = gen_reg_rtx (DImode);
817 operands[4] = gen_reg_rtx (DImode);
818 operands[5] = gen_reg_rtx (DImode);
819 })
821 (define_expand "udivsi3"
822 [(set (match_dup 3)
823 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
824 (set (match_dup 4)
825 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
826 (parallel [(set (match_dup 5)
827 (sign_extend:DI (udiv:SI (match_dup 3) (match_dup 4))))
828 (clobber (reg:DI 23))
829 (clobber (reg:DI 28))])
830 (set (match_operand:SI 0 "nonimmediate_operand" "")
831 (subreg:SI (match_dup 5) 0))]
832 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
833 {
834 operands[3] = gen_reg_rtx (DImode);
835 operands[4] = gen_reg_rtx (DImode);
836 operands[5] = gen_reg_rtx (DImode);
837 })
839 (define_expand "modsi3"
840 [(set (match_dup 3)
841 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
842 (set (match_dup 4)
843 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
844 (parallel [(set (match_dup 5)
845 (sign_extend:DI (mod:SI (match_dup 3) (match_dup 4))))
846 (clobber (reg:DI 23))
847 (clobber (reg:DI 28))])
848 (set (match_operand:SI 0 "nonimmediate_operand" "")
849 (subreg:SI (match_dup 5) 0))]
850 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
851 {
852 operands[3] = gen_reg_rtx (DImode);
853 operands[4] = gen_reg_rtx (DImode);
854 operands[5] = gen_reg_rtx (DImode);
855 })
857 (define_expand "umodsi3"
858 [(set (match_dup 3)
859 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
860 (set (match_dup 4)
861 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
862 (parallel [(set (match_dup 5)
863 (sign_extend:DI (umod:SI (match_dup 3) (match_dup 4))))
864 (clobber (reg:DI 23))
865 (clobber (reg:DI 28))])
866 (set (match_operand:SI 0 "nonimmediate_operand" "")
867 (subreg:SI (match_dup 5) 0))]
868 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
869 {
870 operands[3] = gen_reg_rtx (DImode);
871 operands[4] = gen_reg_rtx (DImode);
872 operands[5] = gen_reg_rtx (DImode);
873 })
875 (define_expand "divdi3"
876 [(parallel [(set (match_operand:DI 0 "register_operand" "")
877 (div:DI (match_operand:DI 1 "register_operand" "")
878 (match_operand:DI 2 "register_operand" "")))
879 (clobber (reg:DI 23))
880 (clobber (reg:DI 28))])]
881 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
882 "")
884 (define_expand "udivdi3"
885 [(parallel [(set (match_operand:DI 0 "register_operand" "")
886 (udiv:DI (match_operand:DI 1 "register_operand" "")
887 (match_operand:DI 2 "register_operand" "")))
888 (clobber (reg:DI 23))
889 (clobber (reg:DI 28))])]
890 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
891 "")
893 (define_expand "moddi3"
894 [(use (match_operand:DI 0 "register_operand" ""))
895 (use (match_operand:DI 1 "register_operand" ""))
896 (use (match_operand:DI 2 "register_operand" ""))]
897 "!TARGET_ABI_OPEN_VMS"
898 {
899 if (TARGET_ABI_UNICOSMK)
900 emit_insn (gen_moddi3_umk (operands[0], operands[1], operands[2]));
901 else
902 emit_insn (gen_moddi3_dft (operands[0], operands[1], operands[2]));
903 DONE;
904 })
906 (define_expand "moddi3_dft"
907 [(parallel [(set (match_operand:DI 0 "register_operand" "")
908 (mod:DI (match_operand:DI 1 "register_operand" "")
909 (match_operand:DI 2 "register_operand" "")))
910 (clobber (reg:DI 23))
911 (clobber (reg:DI 28))])]
912 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
913 "")
915 ;; On Unicos/Mk, we do as the system's C compiler does:
916 ;; compute the quotient, multiply and subtract.
918 (define_expand "moddi3_umk"
919 [(use (match_operand:DI 0 "register_operand" ""))
920 (use (match_operand:DI 1 "register_operand" ""))
921 (use (match_operand:DI 2 "register_operand" ""))]
922 "TARGET_ABI_UNICOSMK"
923 {
924 rtx div, mul = gen_reg_rtx (DImode);
926 div = expand_binop (DImode, sdiv_optab, operands[1], operands[2],
927 NULL_RTX, 0, OPTAB_LIB);
928 div = force_reg (DImode, div);
929 emit_insn (gen_muldi3 (mul, operands[2], div));
930 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
931 DONE;
932 })
934 (define_expand "umoddi3"
935 [(use (match_operand:DI 0 "register_operand" ""))
936 (use (match_operand:DI 1 "register_operand" ""))
937 (use (match_operand:DI 2 "register_operand" ""))]
938 "! TARGET_ABI_OPEN_VMS"
939 {
940 if (TARGET_ABI_UNICOSMK)
941 emit_insn (gen_umoddi3_umk (operands[0], operands[1], operands[2]));
942 else
943 emit_insn (gen_umoddi3_dft (operands[0], operands[1], operands[2]));
944 DONE;
945 })
947 (define_expand "umoddi3_dft"
948 [(parallel [(set (match_operand:DI 0 "register_operand" "")
949 (umod:DI (match_operand:DI 1 "register_operand" "")
950 (match_operand:DI 2 "register_operand" "")))
951 (clobber (reg:DI 23))
952 (clobber (reg:DI 28))])]
953 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
954 "")
956 (define_expand "umoddi3_umk"
957 [(use (match_operand:DI 0 "register_operand" ""))
958 (use (match_operand:DI 1 "register_operand" ""))
959 (use (match_operand:DI 2 "register_operand" ""))]
960 "TARGET_ABI_UNICOSMK"
961 {
962 rtx div, mul = gen_reg_rtx (DImode);
964 div = expand_binop (DImode, udiv_optab, operands[1], operands[2],
965 NULL_RTX, 1, OPTAB_LIB);
966 div = force_reg (DImode, div);
967 emit_insn (gen_muldi3 (mul, operands[2], div));
968 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
969 DONE;
970 })
972 ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
973 ;; expanded by the assembler.
975 (define_insn_and_split "*divmodsi_internal_er"
976 [(set (match_operand:DI 0 "register_operand" "=c")
977 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
978 [(match_operand:DI 1 "register_operand" "a")
979 (match_operand:DI 2 "register_operand" "b")])))
980 (clobber (reg:DI 23))
981 (clobber (reg:DI 28))]
982 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
983 "#"
984 "&& reload_completed"
985 [(parallel [(set (match_dup 0)
986 (sign_extend:DI (match_dup 3)))
987 (use (match_dup 0))
988 (use (match_dup 4))
989 (clobber (reg:DI 23))
990 (clobber (reg:DI 28))])]
991 {
992 const char *str;
993 switch (GET_CODE (operands[3]))
994 {
995 case DIV:
996 str = "__divl";
997 break;
998 case UDIV:
999 str = "__divlu";
1000 break;
1001 case MOD:
1002 str = "__reml";
1003 break;
1004 case UMOD:
1005 str = "__remlu";
1006 break;
1007 default:
1008 gcc_unreachable ();
1009 }
1010 operands[4] = GEN_INT (alpha_next_sequence_number++);
1011 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
1012 gen_rtx_SYMBOL_REF (DImode, str),
1013 operands[4]));
1014 }
1015 [(set_attr "type" "jsr")
1016 (set_attr "length" "8")])
1018 (define_insn "*divmodsi_internal_er_1"
1019 [(set (match_operand:DI 0 "register_operand" "=c")
1020 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1021 [(match_operand:DI 1 "register_operand" "a")
1022 (match_operand:DI 2 "register_operand" "b")])))
1023 (use (match_operand:DI 4 "register_operand" "c"))
1024 (use (match_operand 5 "const_int_operand" ""))
1025 (clobber (reg:DI 23))
1026 (clobber (reg:DI 28))]
1027 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1028 "jsr $23,($27),__%E3%j5"
1029 [(set_attr "type" "jsr")
1030 (set_attr "length" "4")])
1032 (define_insn "*divmodsi_internal"
1033 [(set (match_operand:DI 0 "register_operand" "=c")
1034 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1035 [(match_operand:DI 1 "register_operand" "a")
1036 (match_operand:DI 2 "register_operand" "b")])))
1037 (clobber (reg:DI 23))
1038 (clobber (reg:DI 28))]
1039 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1040 "%E3 %1,%2,%0"
1041 [(set_attr "type" "jsr")
1042 (set_attr "length" "8")])
1044 (define_insn_and_split "*divmoddi_internal_er"
1045 [(set (match_operand:DI 0 "register_operand" "=c")
1046 (match_operator:DI 3 "divmod_operator"
1047 [(match_operand:DI 1 "register_operand" "a")
1048 (match_operand:DI 2 "register_operand" "b")]))
1049 (clobber (reg:DI 23))
1050 (clobber (reg:DI 28))]
1051 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1052 "#"
1053 "&& reload_completed"
1054 [(parallel [(set (match_dup 0) (match_dup 3))
1055 (use (match_dup 0))
1056 (use (match_dup 4))
1057 (clobber (reg:DI 23))
1058 (clobber (reg:DI 28))])]
1059 {
1060 const char *str;
1061 switch (GET_CODE (operands[3]))
1062 {
1063 case DIV:
1064 str = "__divq";
1065 break;
1066 case UDIV:
1067 str = "__divqu";
1068 break;
1069 case MOD:
1070 str = "__remq";
1071 break;
1072 case UMOD:
1073 str = "__remqu";
1074 break;
1075 default:
1076 gcc_unreachable ();
1077 }
1078 operands[4] = GEN_INT (alpha_next_sequence_number++);
1079 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
1080 gen_rtx_SYMBOL_REF (DImode, str),
1081 operands[4]));
1082 }
1083 [(set_attr "type" "jsr")
1084 (set_attr "length" "8")])
1086 (define_insn "*divmoddi_internal_er_1"
1087 [(set (match_operand:DI 0 "register_operand" "=c")
1088 (match_operator:DI 3 "divmod_operator"
1089 [(match_operand:DI 1 "register_operand" "a")
1090 (match_operand:DI 2 "register_operand" "b")]))
1091 (use (match_operand:DI 4 "register_operand" "c"))
1092 (use (match_operand 5 "const_int_operand" ""))
1093 (clobber (reg:DI 23))
1094 (clobber (reg:DI 28))]
1095 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1096 "jsr $23,($27),__%E3%j5"
1097 [(set_attr "type" "jsr")
1098 (set_attr "length" "4")])
1100 (define_insn "*divmoddi_internal"
1101 [(set (match_operand:DI 0 "register_operand" "=c")
1102 (match_operator:DI 3 "divmod_operator"
1103 [(match_operand:DI 1 "register_operand" "a")
1104 (match_operand:DI 2 "register_operand" "b")]))
1105 (clobber (reg:DI 23))
1106 (clobber (reg:DI 28))]
1107 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1108 "%E3 %1,%2,%0"
1109 [(set_attr "type" "jsr")
1110 (set_attr "length" "8")])
1111 \f
1112 ;; Next are the basic logical operations. We only expose the DImode operations
1113 ;; to the rtl expanders, but SImode versions exist for combine as well as for
1114 ;; the atomic operation splitters.
1116 (define_insn "*andsi_internal"
1117 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1118 (and:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
1119 (match_operand:SI 2 "and_operand" "rI,N,MH")))]
1120 ""
1121 "@
1122 and %r1,%2,%0
1123 bic %r1,%N2,%0
1124 zapnot %r1,%m2,%0"
1125 [(set_attr "type" "ilog,ilog,shift")])
1127 (define_insn "anddi3"
1128 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1129 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
1130 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
1131 ""
1132 "@
1133 and %r1,%2,%0
1134 bic %r1,%N2,%0
1135 zapnot %r1,%m2,%0"
1136 [(set_attr "type" "ilog,ilog,shift")])
1138 ;; There are times when we can split an AND into two AND insns. This occurs
1139 ;; when we can first clear any bytes and then clear anything else. For
1140 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
1141 ;; Only do this when running on 64-bit host since the computations are
1142 ;; too messy otherwise.
1144 (define_split
1145 [(set (match_operand:DI 0 "register_operand" "")
1146 (and:DI (match_operand:DI 1 "register_operand" "")
1147 (match_operand:DI 2 "const_int_operand" "")))]
1148 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
1149 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
1150 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
1151 {
1152 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
1153 unsigned HOST_WIDE_INT mask2 = mask1;
1154 int i;
1156 /* For each byte that isn't all zeros, make it all ones. */
1157 for (i = 0; i < 64; i += 8)
1158 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
1159 mask1 |= (HOST_WIDE_INT) 0xff << i;
1161 /* Now turn on any bits we've just turned off. */
1162 mask2 |= ~ mask1;
1164 operands[3] = GEN_INT (mask1);
1165 operands[4] = GEN_INT (mask2);
1166 })
1168 (define_expand "zero_extendqihi2"
1169 [(set (match_operand:HI 0 "register_operand" "")
1170 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
1171 ""
1172 {
1173 if (! TARGET_BWX)
1174 operands[1] = force_reg (QImode, operands[1]);
1175 })
1177 (define_insn "*zero_extendqihi2_bwx"
1178 [(set (match_operand:HI 0 "register_operand" "=r,r")
1179 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1180 "TARGET_BWX"
1181 "@
1182 and %1,0xff,%0
1183 ldbu %0,%1"
1184 [(set_attr "type" "ilog,ild")])
1186 (define_insn "*zero_extendqihi2_nobwx"
1187 [(set (match_operand:HI 0 "register_operand" "=r")
1188 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1189 "! TARGET_BWX"
1190 "and %1,0xff,%0"
1191 [(set_attr "type" "ilog")])
1193 (define_expand "zero_extendqisi2"
1194 [(set (match_operand:SI 0 "register_operand" "")
1195 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1196 ""
1197 {
1198 if (! TARGET_BWX)
1199 operands[1] = force_reg (QImode, operands[1]);
1200 })
1202 (define_insn "*zero_extendqisi2_bwx"
1203 [(set (match_operand:SI 0 "register_operand" "=r,r")
1204 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1205 "TARGET_BWX"
1206 "@
1207 and %1,0xff,%0
1208 ldbu %0,%1"
1209 [(set_attr "type" "ilog,ild")])
1211 (define_insn "*zero_extendqisi2_nobwx"
1212 [(set (match_operand:SI 0 "register_operand" "=r")
1213 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1214 "! TARGET_BWX"
1215 "and %1,0xff,%0"
1216 [(set_attr "type" "ilog")])
1218 (define_expand "zero_extendqidi2"
1219 [(set (match_operand:DI 0 "register_operand" "")
1220 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
1221 ""
1222 {
1223 if (! TARGET_BWX)
1224 operands[1] = force_reg (QImode, operands[1]);
1225 })
1227 (define_insn "*zero_extendqidi2_bwx"
1228 [(set (match_operand:DI 0 "register_operand" "=r,r")
1229 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1230 "TARGET_BWX"
1231 "@
1232 and %1,0xff,%0
1233 ldbu %0,%1"
1234 [(set_attr "type" "ilog,ild")])
1236 (define_insn "*zero_extendqidi2_nobwx"
1237 [(set (match_operand:DI 0 "register_operand" "=r")
1238 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1239 "! TARGET_BWX"
1240 "and %1,0xff,%0"
1241 [(set_attr "type" "ilog")])
1243 (define_expand "zero_extendhisi2"
1244 [(set (match_operand:SI 0 "register_operand" "")
1245 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
1246 ""
1247 {
1248 if (! TARGET_BWX)
1249 operands[1] = force_reg (HImode, operands[1]);
1250 })
1252 (define_insn "*zero_extendhisi2_bwx"
1253 [(set (match_operand:SI 0 "register_operand" "=r,r")
1254 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1255 "TARGET_BWX"
1256 "@
1257 zapnot %1,3,%0
1258 ldwu %0,%1"
1259 [(set_attr "type" "shift,ild")])
1261 (define_insn "*zero_extendhisi2_nobwx"
1262 [(set (match_operand:SI 0 "register_operand" "=r")
1263 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1264 "! TARGET_BWX"
1265 "zapnot %1,3,%0"
1266 [(set_attr "type" "shift")])
1268 (define_expand "zero_extendhidi2"
1269 [(set (match_operand:DI 0 "register_operand" "")
1270 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
1271 ""
1272 {
1273 if (! TARGET_BWX)
1274 operands[1] = force_reg (HImode, operands[1]);
1275 })
1277 (define_insn "*zero_extendhidi2_bwx"
1278 [(set (match_operand:DI 0 "register_operand" "=r,r")
1279 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1280 "TARGET_BWX"
1281 "@
1282 zapnot %1,3,%0
1283 ldwu %0,%1"
1284 [(set_attr "type" "shift,ild")])
1286 (define_insn "*zero_extendhidi2_nobwx"
1287 [(set (match_operand:DI 0 "register_operand" "=r")
1288 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1289 ""
1290 "zapnot %1,3,%0"
1291 [(set_attr "type" "shift")])
1293 (define_insn "zero_extendsidi2"
1294 [(set (match_operand:DI 0 "register_operand" "=r")
1295 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
1296 ""
1297 "zapnot %1,15,%0"
1298 [(set_attr "type" "shift")])
1300 (define_insn "*andnotsi3"
1301 [(set (match_operand:SI 0 "register_operand" "=r")
1302 (and:SI (not:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI"))
1303 (match_operand:SI 2 "reg_or_0_operand" "rJ")))]
1304 ""
1305 "bic %r2,%1,%0"
1306 [(set_attr "type" "ilog")])
1308 (define_insn "andnotdi3"
1309 [(set (match_operand:DI 0 "register_operand" "=r")
1310 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1311 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1312 ""
1313 "bic %r2,%1,%0"
1314 [(set_attr "type" "ilog")])
1316 (define_insn "*iorsi_internal"
1317 [(set (match_operand:SI 0 "register_operand" "=r,r")
1318 (ior:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
1319 (match_operand:SI 2 "or_operand" "rI,N")))]
1320 ""
1321 "@
1322 bis %r1,%2,%0
1323 ornot %r1,%N2,%0"
1324 [(set_attr "type" "ilog")])
1326 (define_insn "iordi3"
1327 [(set (match_operand:DI 0 "register_operand" "=r,r")
1328 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1329 (match_operand:DI 2 "or_operand" "rI,N")))]
1330 ""
1331 "@
1332 bis %r1,%2,%0
1333 ornot %r1,%N2,%0"
1334 [(set_attr "type" "ilog")])
1336 (define_insn "*one_cmplsi_internal"
1337 [(set (match_operand:SI 0 "register_operand" "=r")
1338 (not:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
1339 ""
1340 "ornot $31,%1,%0"
1341 [(set_attr "type" "ilog")])
1343 (define_insn "one_cmpldi2"
1344 [(set (match_operand:DI 0 "register_operand" "=r")
1345 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
1346 ""
1347 "ornot $31,%1,%0"
1348 [(set_attr "type" "ilog")])
1350 (define_insn "*iornotsi3"
1351 [(set (match_operand:SI 0 "register_operand" "=r")
1352 (ior:SI (not:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI"))
1353 (match_operand:SI 2 "reg_or_0_operand" "rJ")))]
1354 ""
1355 "ornot %r2,%1,%0"
1356 [(set_attr "type" "ilog")])
1358 (define_insn "*iornotdi3"
1359 [(set (match_operand:DI 0 "register_operand" "=r")
1360 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1361 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1362 ""
1363 "ornot %r2,%1,%0"
1364 [(set_attr "type" "ilog")])
1366 (define_insn "*xorsi_internal"
1367 [(set (match_operand:SI 0 "register_operand" "=r,r")
1368 (xor:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
1369 (match_operand:SI 2 "or_operand" "rI,N")))]
1370 ""
1371 "@
1372 xor %r1,%2,%0
1373 eqv %r1,%N2,%0"
1374 [(set_attr "type" "ilog")])
1376 (define_insn "xordi3"
1377 [(set (match_operand:DI 0 "register_operand" "=r,r")
1378 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1379 (match_operand:DI 2 "or_operand" "rI,N")))]
1380 ""
1381 "@
1382 xor %r1,%2,%0
1383 eqv %r1,%N2,%0"
1384 [(set_attr "type" "ilog")])
1386 (define_insn "*xornotsi3"
1387 [(set (match_operand:SI 0 "register_operand" "=r")
1388 (not:SI (xor:SI (match_operand:SI 1 "register_operand" "%rJ")
1389 (match_operand:SI 2 "register_operand" "rI"))))]
1390 ""
1391 "eqv %r1,%2,%0"
1392 [(set_attr "type" "ilog")])
1394 (define_insn "*xornotdi3"
1395 [(set (match_operand:DI 0 "register_operand" "=r")
1396 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
1397 (match_operand:DI 2 "register_operand" "rI"))))]
1398 ""
1399 "eqv %r1,%2,%0"
1400 [(set_attr "type" "ilog")])
1401 \f
1402 ;; Handle FFS and related insns iff we support CIX.
1404 (define_expand "ffsdi2"
1405 [(set (match_dup 2)
1406 (ctz:DI (match_operand:DI 1 "register_operand" "")))
1407 (set (match_dup 3)
1408 (plus:DI (match_dup 2) (const_int 1)))
1409 (set (match_operand:DI 0 "register_operand" "")
1410 (if_then_else:DI (eq (match_dup 1) (const_int 0))
1411 (const_int 0) (match_dup 3)))]
1412 "TARGET_CIX"
1413 {
1414 operands[2] = gen_reg_rtx (DImode);
1415 operands[3] = gen_reg_rtx (DImode);
1416 })
1418 (define_insn "clzdi2"
1419 [(set (match_operand:DI 0 "register_operand" "=r")
1420 (clz:DI (match_operand:DI 1 "register_operand" "r")))]
1421 "TARGET_CIX"
1422 "ctlz %1,%0"
1423 [(set_attr "type" "mvi")])
1425 (define_insn "ctzdi2"
1426 [(set (match_operand:DI 0 "register_operand" "=r")
1427 (ctz:DI (match_operand:DI 1 "register_operand" "r")))]
1428 "TARGET_CIX"
1429 "cttz %1,%0"
1430 [(set_attr "type" "mvi")])
1432 (define_insn "popcountdi2"
1433 [(set (match_operand:DI 0 "register_operand" "=r")
1434 (popcount:DI (match_operand:DI 1 "register_operand" "r")))]
1435 "TARGET_CIX"
1436 "ctpop %1,%0"
1437 [(set_attr "type" "mvi")])
1438 \f
1439 ;; Next come the shifts and the various extract and insert operations.
1441 (define_insn "ashldi3"
1442 [(set (match_operand:DI 0 "register_operand" "=r,r")
1443 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
1444 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
1445 ""
1446 {
1447 switch (which_alternative)
1448 {
1449 case 0:
1450 if (operands[2] == const1_rtx)
1451 return "addq %r1,%r1,%0";
1452 else
1453 return "s%P2addq %r1,0,%0";
1454 case 1:
1455 return "sll %r1,%2,%0";
1456 default:
1457 gcc_unreachable ();
1458 }
1459 }
1460 [(set_attr "type" "iadd,shift")])
1462 (define_insn "*ashldi_se"
1463 [(set (match_operand:DI 0 "register_operand" "=r")
1464 (sign_extend:DI
1465 (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1466 (match_operand:DI 2 "const_int_operand" "P"))
1467 0)))]
1468 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
1469 {
1470 if (operands[2] == const1_rtx)
1471 return "addl %r1,%r1,%0";
1472 else
1473 return "s%P2addl %r1,0,%0";
1474 }
1475 [(set_attr "type" "iadd")])
1477 (define_insn "lshrdi3"
1478 [(set (match_operand:DI 0 "register_operand" "=r")
1479 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1480 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1481 ""
1482 "srl %r1,%2,%0"
1483 [(set_attr "type" "shift")])
1485 (define_insn "ashrdi3"
1486 [(set (match_operand:DI 0 "register_operand" "=r")
1487 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1488 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1489 ""
1490 "sra %r1,%2,%0"
1491 [(set_attr "type" "shift")])
1493 (define_expand "extendqihi2"
1494 [(set (match_dup 2)
1495 (ashift:DI (match_operand:QI 1 "some_operand" "")
1496 (const_int 56)))
1497 (set (match_operand:HI 0 "register_operand" "")
1498 (ashiftrt:DI (match_dup 2)
1499 (const_int 56)))]
1500 ""
1501 {
1502 if (TARGET_BWX)
1503 {
1504 emit_insn (gen_extendqihi2x (operands[0],
1505 force_reg (QImode, operands[1])));
1506 DONE;
1507 }
1509 /* If we have an unaligned MEM, extend to DImode (which we do
1510 specially) and then copy to the result. */
1511 if (unaligned_memory_operand (operands[1], HImode))
1512 {
1513 rtx temp = gen_reg_rtx (DImode);
1515 emit_insn (gen_extendqidi2 (temp, operands[1]));
1516 emit_move_insn (operands[0], gen_lowpart (HImode, temp));
1517 DONE;
1518 }
1520 operands[0] = gen_lowpart (DImode, operands[0]);
1521 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1522 operands[2] = gen_reg_rtx (DImode);
1523 })
1525 (define_insn "extendqidi2x"
1526 [(set (match_operand:DI 0 "register_operand" "=r")
1527 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1528 "TARGET_BWX"
1529 "sextb %1,%0"
1530 [(set_attr "type" "shift")])
1532 (define_insn "extendhidi2x"
1533 [(set (match_operand:DI 0 "register_operand" "=r")
1534 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1535 "TARGET_BWX"
1536 "sextw %1,%0"
1537 [(set_attr "type" "shift")])
1539 (define_insn "extendqisi2x"
1540 [(set (match_operand:SI 0 "register_operand" "=r")
1541 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1542 "TARGET_BWX"
1543 "sextb %1,%0"
1544 [(set_attr "type" "shift")])
1546 (define_insn "extendhisi2x"
1547 [(set (match_operand:SI 0 "register_operand" "=r")
1548 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1549 "TARGET_BWX"
1550 "sextw %1,%0"
1551 [(set_attr "type" "shift")])
1553 (define_insn "extendqihi2x"
1554 [(set (match_operand:HI 0 "register_operand" "=r")
1555 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1556 "TARGET_BWX"
1557 "sextb %1,%0"
1558 [(set_attr "type" "shift")])
1560 (define_expand "extendqisi2"
1561 [(set (match_dup 2)
1562 (ashift:DI (match_operand:QI 1 "some_operand" "")
1563 (const_int 56)))
1564 (set (match_operand:SI 0 "register_operand" "")
1565 (ashiftrt:DI (match_dup 2)
1566 (const_int 56)))]
1567 ""
1568 {
1569 if (TARGET_BWX)
1570 {
1571 emit_insn (gen_extendqisi2x (operands[0],
1572 force_reg (QImode, operands[1])));
1573 DONE;
1574 }
1576 /* If we have an unaligned MEM, extend to a DImode form of
1577 the result (which we do specially). */
1578 if (unaligned_memory_operand (operands[1], QImode))
1579 {
1580 rtx temp = gen_reg_rtx (DImode);
1582 emit_insn (gen_extendqidi2 (temp, operands[1]));
1583 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1584 DONE;
1585 }
1587 operands[0] = gen_lowpart (DImode, operands[0]);
1588 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1589 operands[2] = gen_reg_rtx (DImode);
1590 })
1592 (define_expand "extendqidi2"
1593 [(set (match_dup 2)
1594 (ashift:DI (match_operand:QI 1 "some_operand" "")
1595 (const_int 56)))
1596 (set (match_operand:DI 0 "register_operand" "")
1597 (ashiftrt:DI (match_dup 2)
1598 (const_int 56)))]
1599 ""
1600 {
1601 if (TARGET_BWX)
1602 {
1603 emit_insn (gen_extendqidi2x (operands[0],
1604 force_reg (QImode, operands[1])));
1605 DONE;
1606 }
1608 if (unaligned_memory_operand (operands[1], QImode))
1609 {
1610 rtx seq = gen_unaligned_extendqidi (operands[0], XEXP (operands[1], 0));
1611 alpha_set_memflags (seq, operands[1]);
1612 emit_insn (seq);
1613 DONE;
1614 }
1616 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1617 operands[2] = gen_reg_rtx (DImode);
1618 })
1620 (define_expand "extendhisi2"
1621 [(set (match_dup 2)
1622 (ashift:DI (match_operand:HI 1 "some_operand" "")
1623 (const_int 48)))
1624 (set (match_operand:SI 0 "register_operand" "")
1625 (ashiftrt:DI (match_dup 2)
1626 (const_int 48)))]
1627 ""
1628 {
1629 if (TARGET_BWX)
1630 {
1631 emit_insn (gen_extendhisi2x (operands[0],
1632 force_reg (HImode, operands[1])));
1633 DONE;
1634 }
1636 /* If we have an unaligned MEM, extend to a DImode form of
1637 the result (which we do specially). */
1638 if (unaligned_memory_operand (operands[1], HImode))
1639 {
1640 rtx temp = gen_reg_rtx (DImode);
1642 emit_insn (gen_extendhidi2 (temp, operands[1]));
1643 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1644 DONE;
1645 }
1647 operands[0] = gen_lowpart (DImode, operands[0]);
1648 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1649 operands[2] = gen_reg_rtx (DImode);
1650 })
1652 (define_expand "extendhidi2"
1653 [(set (match_dup 2)
1654 (ashift:DI (match_operand:HI 1 "some_operand" "")
1655 (const_int 48)))
1656 (set (match_operand:DI 0 "register_operand" "")
1657 (ashiftrt:DI (match_dup 2)
1658 (const_int 48)))]
1659 ""
1660 {
1661 if (TARGET_BWX)
1662 {
1663 emit_insn (gen_extendhidi2x (operands[0],
1664 force_reg (HImode, operands[1])));
1665 DONE;
1666 }
1668 if (unaligned_memory_operand (operands[1], HImode))
1669 {
1670 rtx seq = gen_unaligned_extendhidi (operands[0], XEXP (operands[1], 0));
1672 alpha_set_memflags (seq, operands[1]);
1673 emit_insn (seq);
1674 DONE;
1675 }
1677 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1678 operands[2] = gen_reg_rtx (DImode);
1679 })
1681 ;; Here's how we sign extend an unaligned byte and halfword. Doing this
1682 ;; as a pattern saves one instruction. The code is similar to that for
1683 ;; the unaligned loads (see below).
1684 ;;
1685 ;; Operand 1 is the address, operand 0 is the result.
1686 (define_expand "unaligned_extendqidi"
1687 [(use (match_operand:QI 0 "register_operand" ""))
1688 (use (match_operand:DI 1 "address_operand" ""))]
1689 ""
1690 {
1691 operands[0] = gen_lowpart (DImode, operands[0]);
1692 if (WORDS_BIG_ENDIAN)
1693 emit_insn (gen_unaligned_extendqidi_be (operands[0], operands[1]));
1694 else
1695 emit_insn (gen_unaligned_extendqidi_le (operands[0], operands[1]));
1696 DONE;
1697 })
1699 (define_expand "unaligned_extendqidi_le"
1700 [(set (match_dup 3)
1701 (mem:DI (and:DI (match_operand:DI 1 "" "") (const_int -8))))
1702 (set (match_dup 4)
1703 (ashift:DI (match_dup 3)
1704 (minus:DI (const_int 64)
1705 (ashift:DI
1706 (and:DI (match_dup 2) (const_int 7))
1707 (const_int 3)))))
1708 (set (match_operand:DI 0 "register_operand" "")
1709 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1710 "! WORDS_BIG_ENDIAN"
1711 {
1712 operands[2] = get_unaligned_offset (operands[1], 1);
1713 operands[3] = gen_reg_rtx (DImode);
1714 operands[4] = gen_reg_rtx (DImode);
1715 })
1717 (define_expand "unaligned_extendqidi_be"
1718 [(set (match_dup 3)
1719 (mem:DI (and:DI (match_operand:DI 1 "" "") (const_int -8))))
1720 (set (match_dup 4)
1721 (ashift:DI (match_dup 3)
1722 (ashift:DI
1723 (and:DI
1724 (plus:DI (match_dup 2) (const_int 1))
1725 (const_int 7))
1726 (const_int 3))))
1727 (set (match_operand:DI 0 "register_operand" "")
1728 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1729 "WORDS_BIG_ENDIAN"
1730 {
1731 operands[2] = get_unaligned_offset (operands[1], -1);
1732 operands[3] = gen_reg_rtx (DImode);
1733 operands[4] = gen_reg_rtx (DImode);
1734 })
1736 (define_expand "unaligned_extendhidi"
1737 [(use (match_operand:QI 0 "register_operand" ""))
1738 (use (match_operand:DI 1 "address_operand" ""))]
1739 ""
1740 {
1741 operands[0] = gen_lowpart (DImode, operands[0]);
1742 if (WORDS_BIG_ENDIAN)
1743 emit_insn (gen_unaligned_extendhidi_be (operands[0], operands[1]));
1744 else
1745 emit_insn (gen_unaligned_extendhidi_le (operands[0], operands[1]));
1746 DONE;
1747 })
1749 (define_expand "unaligned_extendhidi_le"
1750 [(set (match_dup 3)
1751 (mem:DI (and:DI (match_operand:DI 1 "" "") (const_int -8))))
1752 (set (match_dup 4)
1753 (ashift:DI (match_dup 3)
1754 (minus:DI (const_int 64)
1755 (ashift:DI
1756 (and:DI (match_dup 2) (const_int 7))
1757 (const_int 3)))))
1758 (set (match_operand:DI 0 "register_operand" "")
1759 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1760 "! WORDS_BIG_ENDIAN"
1761 {
1762 operands[2] = get_unaligned_offset (operands[1], 2);
1763 operands[3] = gen_reg_rtx (DImode);
1764 operands[4] = gen_reg_rtx (DImode);
1765 })
1767 (define_expand "unaligned_extendhidi_be"
1768 [(set (match_dup 3)
1769 (mem:DI (and:DI (match_operand:DI 1 "" "") (const_int -8))))
1770 (set (match_dup 4)
1771 (ashift:DI (match_dup 3)
1772 (ashift:DI
1773 (and:DI
1774 (plus:DI (match_dup 2) (const_int 1))
1775 (const_int 7))
1776 (const_int 3))))
1777 (set (match_operand:DI 0 "register_operand" "")
1778 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1779 "WORDS_BIG_ENDIAN"
1780 {
1781 operands[2] = get_unaligned_offset (operands[1], -1);
1782 operands[3] = gen_reg_rtx (DImode);
1783 operands[4] = gen_reg_rtx (DImode);
1784 })
1786 (define_insn "*extxl_const"
1787 [(set (match_operand:DI 0 "register_operand" "=r")
1788 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1789 (match_operand:DI 2 "mode_width_operand" "n")
1790 (match_operand:DI 3 "mul8_operand" "I")))]
1791 ""
1792 "ext%M2l %r1,%s3,%0"
1793 [(set_attr "type" "shift")])
1795 (define_insn "extxl_le"
1796 [(set (match_operand:DI 0 "register_operand" "=r")
1797 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1798 (match_operand:DI 2 "mode_width_operand" "n")
1799 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1800 (const_int 3))))]
1801 "! WORDS_BIG_ENDIAN"
1802 "ext%M2l %r1,%3,%0"
1803 [(set_attr "type" "shift")])
1805 (define_insn "extxl_be"
1806 [(set (match_operand:DI 0 "register_operand" "=r")
1807 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1808 (match_operand:DI 2 "mode_width_operand" "n")
1809 (minus:DI
1810 (const_int 56)
1811 (ashift:DI
1812 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1813 (const_int 3)))))]
1814 "WORDS_BIG_ENDIAN"
1815 "ext%M2l %r1,%3,%0"
1816 [(set_attr "type" "shift")])
1818 ;; Combine has some strange notion of preserving existing undefined behavior
1819 ;; in shifts larger than a word size. So capture these patterns that it
1820 ;; should have turned into zero_extracts.
1822 (define_insn "*extxl_1_le"
1823 [(set (match_operand:DI 0 "register_operand" "=r")
1824 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1825 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1826 (const_int 3)))
1827 (match_operand:DI 3 "mode_mask_operand" "n")))]
1828 "! WORDS_BIG_ENDIAN"
1829 "ext%U3l %1,%2,%0"
1830 [(set_attr "type" "shift")])
1832 (define_insn "*extxl_1_be"
1833 [(set (match_operand:DI 0 "register_operand" "=r")
1834 (and:DI (lshiftrt:DI
1835 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1836 (minus:DI (const_int 56)
1837 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1838 (const_int 3))))
1839 (match_operand:DI 3 "mode_mask_operand" "n")))]
1840 "WORDS_BIG_ENDIAN"
1841 "ext%U3l %1,%2,%0"
1842 [(set_attr "type" "shift")])
1844 (define_insn "*extql_2_le"
1845 [(set (match_operand:DI 0 "register_operand" "=r")
1846 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1847 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1848 (const_int 3))))]
1849 "! WORDS_BIG_ENDIAN"
1850 "extql %1,%2,%0"
1851 [(set_attr "type" "shift")])
1853 (define_insn "*extql_2_be"
1854 [(set (match_operand:DI 0 "register_operand" "=r")
1855 (lshiftrt:DI
1856 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1857 (minus:DI (const_int 56)
1858 (ashift:DI
1859 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1860 (const_int 3)))))]
1861 "WORDS_BIG_ENDIAN"
1862 "extql %1,%2,%0"
1863 [(set_attr "type" "shift")])
1865 (define_insn "extqh_le"
1866 [(set (match_operand:DI 0 "register_operand" "=r")
1867 (ashift:DI
1868 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1869 (minus:DI (const_int 64)
1870 (ashift:DI
1871 (and:DI
1872 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1873 (const_int 7))
1874 (const_int 3)))))]
1875 "! WORDS_BIG_ENDIAN"
1876 "extqh %r1,%2,%0"
1877 [(set_attr "type" "shift")])
1879 (define_insn "extqh_be"
1880 [(set (match_operand:DI 0 "register_operand" "=r")
1881 (ashift:DI
1882 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1883 (ashift:DI
1884 (and:DI
1885 (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1886 (const_int 1))
1887 (const_int 7))
1888 (const_int 3))))]
1889 "WORDS_BIG_ENDIAN"
1890 "extqh %r1,%2,%0"
1891 [(set_attr "type" "shift")])
1893 (define_insn "extlh_le"
1894 [(set (match_operand:DI 0 "register_operand" "=r")
1895 (ashift:DI
1896 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1897 (const_int 2147483647))
1898 (minus:DI (const_int 64)
1899 (ashift:DI
1900 (and:DI
1901 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1902 (const_int 7))
1903 (const_int 3)))))]
1904 "! WORDS_BIG_ENDIAN"
1905 "extlh %r1,%2,%0"
1906 [(set_attr "type" "shift")])
1908 (define_insn "extlh_be"
1909 [(set (match_operand:DI 0 "register_operand" "=r")
1910 (and:DI
1911 (ashift:DI
1912 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1913 (ashift:DI
1914 (and:DI
1915 (plus:DI
1916 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1917 (const_int 1))
1918 (const_int 7))
1919 (const_int 3)))
1920 (const_int 2147483647)))]
1921 "WORDS_BIG_ENDIAN"
1922 "extlh %r1,%2,%0"
1923 [(set_attr "type" "shift")])
1925 (define_insn "extwh_le"
1926 [(set (match_operand:DI 0 "register_operand" "=r")
1927 (ashift:DI
1928 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1929 (const_int 65535))
1930 (minus:DI (const_int 64)
1931 (ashift:DI
1932 (and:DI
1933 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1934 (const_int 7))
1935 (const_int 3)))))]
1936 "! WORDS_BIG_ENDIAN"
1937 "extwh %r1,%2,%0"
1938 [(set_attr "type" "shift")])
1940 (define_insn "extwh_be"
1941 [(set (match_operand:DI 0 "register_operand" "=r")
1942 (and:DI
1943 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1944 (ashift:DI
1945 (and:DI
1946 (plus:DI
1947 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1948 (const_int 1))
1949 (const_int 7))
1950 (const_int 3)))
1951 (const_int 65535)))]
1952 "WORDS_BIG_ENDIAN"
1953 "extwh %r1,%2,%0"
1954 [(set_attr "type" "shift")])
1956 ;; This converts an extXl into an extXh with an appropriate adjustment
1957 ;; to the address calculation.
1959 ;;(define_split
1960 ;; [(set (match_operand:DI 0 "register_operand" "")
1961 ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
1962 ;; (match_operand:DI 2 "mode_width_operand" "")
1963 ;; (ashift:DI (match_operand:DI 3 "" "")
1964 ;; (const_int 3)))
1965 ;; (match_operand:DI 4 "const_int_operand" "")))
1966 ;; (clobber (match_operand:DI 5 "register_operand" ""))]
1967 ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
1968 ;; [(set (match_dup 5) (match_dup 6))
1969 ;; (set (match_dup 0)
1970 ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
1971 ;; (ashift:DI (plus:DI (match_dup 5)
1972 ;; (match_dup 7))
1973 ;; (const_int 3)))
1974 ;; (match_dup 4)))]
1975 ;; "
1976 ;;{
1977 ;; operands[6] = plus_constant (operands[3],
1978 ;; INTVAL (operands[2]) / BITS_PER_UNIT);
1979 ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
1980 ;;}")
1982 (define_insn "*insbl_const"
1983 [(set (match_operand:DI 0 "register_operand" "=r")
1984 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1985 (match_operand:DI 2 "mul8_operand" "I")))]
1986 ""
1987 "insbl %1,%s2,%0"
1988 [(set_attr "type" "shift")])
1990 (define_insn "*inswl_const"
1991 [(set (match_operand:DI 0 "register_operand" "=r")
1992 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1993 (match_operand:DI 2 "mul8_operand" "I")))]
1994 ""
1995 "inswl %1,%s2,%0"
1996 [(set_attr "type" "shift")])
1998 (define_insn "*insll_const"
1999 [(set (match_operand:DI 0 "register_operand" "=r")
2000 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2001 (match_operand:DI 2 "mul8_operand" "I")))]
2002 ""
2003 "insll %1,%s2,%0"
2004 [(set_attr "type" "shift")])
2006 (define_insn "insbl_le"
2007 [(set (match_operand:DI 0 "register_operand" "=r")
2008 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
2009 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2010 (const_int 3))))]
2011 "! WORDS_BIG_ENDIAN"
2012 "insbl %1,%2,%0"
2013 [(set_attr "type" "shift")])
2015 (define_insn "insbl_be"
2016 [(set (match_operand:DI 0 "register_operand" "=r")
2017 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
2018 (minus:DI (const_int 56)
2019 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2020 (const_int 3)))))]
2021 "WORDS_BIG_ENDIAN"
2022 "insbl %1,%2,%0"
2023 [(set_attr "type" "shift")])
2025 (define_insn "inswl_le"
2026 [(set (match_operand:DI 0 "register_operand" "=r")
2027 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2028 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2029 (const_int 3))))]
2030 "! WORDS_BIG_ENDIAN"
2031 "inswl %1,%2,%0"
2032 [(set_attr "type" "shift")])
2034 (define_insn "inswl_be"
2035 [(set (match_operand:DI 0 "register_operand" "=r")
2036 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2037 (minus:DI (const_int 56)
2038 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2039 (const_int 3)))))]
2040 "WORDS_BIG_ENDIAN"
2041 "inswl %1,%2,%0"
2042 [(set_attr "type" "shift")])
2044 (define_insn "insll_le"
2045 [(set (match_operand:DI 0 "register_operand" "=r")
2046 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2047 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2048 (const_int 3))))]
2049 "! WORDS_BIG_ENDIAN"
2050 "insll %1,%2,%0"
2051 [(set_attr "type" "shift")])
2053 (define_insn "insll_be"
2054 [(set (match_operand:DI 0 "register_operand" "=r")
2055 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2056 (minus:DI (const_int 56)
2057 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2058 (const_int 3)))))]
2059 "WORDS_BIG_ENDIAN"
2060 "insll %1,%2,%0"
2061 [(set_attr "type" "shift")])
2063 (define_insn "insql_le"
2064 [(set (match_operand:DI 0 "register_operand" "=r")
2065 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2066 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2067 (const_int 3))))]
2068 "! WORDS_BIG_ENDIAN"
2069 "insql %1,%2,%0"
2070 [(set_attr "type" "shift")])
2072 (define_insn "insql_be"
2073 [(set (match_operand:DI 0 "register_operand" "=r")
2074 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2075 (minus:DI (const_int 56)
2076 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2077 (const_int 3)))))]
2078 "WORDS_BIG_ENDIAN"
2079 "insql %1,%2,%0"
2080 [(set_attr "type" "shift")])
2082 ;; Combine has this sometimes habit of moving the and outside of the
2083 ;; shift, making life more interesting.
2085 (define_insn "*insxl"
2086 [(set (match_operand:DI 0 "register_operand" "=r")
2087 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
2088 (match_operand:DI 2 "mul8_operand" "I"))
2089 (match_operand:DI 3 "immediate_operand" "i")))]
2090 "HOST_BITS_PER_WIDE_INT == 64
2091 && GET_CODE (operands[3]) == CONST_INT
2092 && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2093 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2094 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2095 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2096 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2097 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])))"
2098 {
2099 #if HOST_BITS_PER_WIDE_INT == 64
2100 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2101 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2102 return "insbl %1,%s2,%0";
2103 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2104 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2105 return "inswl %1,%s2,%0";
2106 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2107 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2108 return "insll %1,%s2,%0";
2109 #endif
2110 gcc_unreachable ();
2111 }
2112 [(set_attr "type" "shift")])
2114 ;; We do not include the insXh insns because they are complex to express
2115 ;; and it does not appear that we would ever want to generate them.
2116 ;;
2117 ;; Since we need them for block moves, though, cop out and use unspec.
2119 (define_insn "insxh"
2120 [(set (match_operand:DI 0 "register_operand" "=r")
2121 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2122 (match_operand:DI 2 "mode_width_operand" "n")
2123 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2124 UNSPEC_INSXH))]
2125 ""
2126 "ins%M2h %1,%3,%0"
2127 [(set_attr "type" "shift")])
2129 (define_insn "mskxl_le"
2130 [(set (match_operand:DI 0 "register_operand" "=r")
2131 (and:DI (not:DI (ashift:DI
2132 (match_operand:DI 2 "mode_mask_operand" "n")
2133 (ashift:DI
2134 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2135 (const_int 3))))
2136 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2137 "! WORDS_BIG_ENDIAN"
2138 "msk%U2l %r1,%3,%0"
2139 [(set_attr "type" "shift")])
2141 (define_insn "mskxl_be"
2142 [(set (match_operand:DI 0 "register_operand" "=r")
2143 (and:DI (not:DI (ashift:DI
2144 (match_operand:DI 2 "mode_mask_operand" "n")
2145 (minus:DI (const_int 56)
2146 (ashift:DI
2147 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2148 (const_int 3)))))
2149 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2150 "WORDS_BIG_ENDIAN"
2151 "msk%U2l %r1,%3,%0"
2152 [(set_attr "type" "shift")])
2154 ;; We do not include the mskXh insns because it does not appear we would
2155 ;; ever generate one.
2156 ;;
2157 ;; Again, we do for block moves and we use unspec again.
2159 (define_insn "mskxh"
2160 [(set (match_operand:DI 0 "register_operand" "=r")
2161 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2162 (match_operand:DI 2 "mode_width_operand" "n")
2163 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2164 UNSPEC_MSKXH))]
2165 ""
2166 "msk%M2h %1,%3,%0"
2167 [(set_attr "type" "shift")])
2169 ;; Prefer AND + NE over LSHIFTRT + AND.
2171 (define_insn_and_split "*ze_and_ne"
2172 [(set (match_operand:DI 0 "register_operand" "=r")
2173 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2174 (const_int 1)
2175 (match_operand 2 "const_int_operand" "I")))]
2176 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2177 "#"
2178 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2179 [(set (match_dup 0)
2180 (and:DI (match_dup 1) (match_dup 3)))
2181 (set (match_dup 0)
2182 (ne:DI (match_dup 0) (const_int 0)))]
2183 "operands[3] = GEN_INT (1 << INTVAL (operands[2]));")
2184 \f
2185 ;; Floating-point operations. All the double-precision insns can extend
2186 ;; from single, so indicate that. The exception are the ones that simply
2187 ;; play with the sign bits; it's not clear what to do there.
2189 (define_insn "abssf2"
2190 [(set (match_operand:SF 0 "register_operand" "=f")
2191 (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2192 "TARGET_FP"
2193 "cpys $f31,%R1,%0"
2194 [(set_attr "type" "fcpys")])
2196 (define_insn "*nabssf2"
2197 [(set (match_operand:SF 0 "register_operand" "=f")
2198 (neg:SF (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG"))))]
2199 "TARGET_FP"
2200 "cpysn $f31,%R1,%0"
2201 [(set_attr "type" "fadd")])
2203 (define_insn "absdf2"
2204 [(set (match_operand:DF 0 "register_operand" "=f")
2205 (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2206 "TARGET_FP"
2207 "cpys $f31,%R1,%0"
2208 [(set_attr "type" "fcpys")])
2210 (define_insn "*nabsdf2"
2211 [(set (match_operand:DF 0 "register_operand" "=f")
2212 (neg:DF (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG"))))]
2213 "TARGET_FP"
2214 "cpysn $f31,%R1,%0"
2215 [(set_attr "type" "fadd")])
2217 (define_expand "abstf2"
2218 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2219 (abs:TF (match_operand:TF 1 "reg_or_0_operand" "")))
2220 (use (match_dup 2))])]
2221 "TARGET_HAS_XFLOATING_LIBS"
2222 {
2223 #if HOST_BITS_PER_WIDE_INT >= 64
2224 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2225 #else
2226 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2227 #endif
2228 })
2230 (define_insn_and_split "*abstf_internal"
2231 [(set (match_operand:TF 0 "register_operand" "=r")
2232 (abs:TF (match_operand:TF 1 "reg_or_0_operand" "rG")))
2233 (use (match_operand:DI 2 "register_operand" "r"))]
2234 "TARGET_HAS_XFLOATING_LIBS"
2235 "#"
2236 "&& reload_completed"
2237 [(const_int 0)]
2238 "alpha_split_tfmode_frobsign (operands, gen_andnotdi3); DONE;")
2240 (define_insn "negsf2"
2241 [(set (match_operand:SF 0 "register_operand" "=f")
2242 (neg:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2243 "TARGET_FP"
2244 "cpysn %R1,%R1,%0"
2245 [(set_attr "type" "fadd")])
2247 (define_insn "negdf2"
2248 [(set (match_operand:DF 0 "register_operand" "=f")
2249 (neg:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2250 "TARGET_FP"
2251 "cpysn %R1,%R1,%0"
2252 [(set_attr "type" "fadd")])
2254 (define_expand "negtf2"
2255 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2256 (neg:TF (match_operand:TF 1 "reg_or_0_operand" "")))
2257 (use (match_dup 2))])]
2258 "TARGET_HAS_XFLOATING_LIBS"
2259 {
2260 #if HOST_BITS_PER_WIDE_INT >= 64
2261 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2262 #else
2263 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2264 #endif
2265 })
2267 (define_insn_and_split "*negtf_internal"
2268 [(set (match_operand:TF 0 "register_operand" "=r")
2269 (neg:TF (match_operand:TF 1 "reg_or_0_operand" "rG")))
2270 (use (match_operand:DI 2 "register_operand" "r"))]
2271 "TARGET_HAS_XFLOATING_LIBS"
2272 "#"
2273 "&& reload_completed"
2274 [(const_int 0)]
2275 "alpha_split_tfmode_frobsign (operands, gen_xordi3); DONE;")
2277 (define_insn "copysignsf3"
2278 [(set (match_operand:SF 0 "register_operand" "=f")
2279 (unspec:SF [(match_operand:SF 1 "reg_or_0_operand" "fG")
2280 (match_operand:SF 2 "reg_or_0_operand" "fG")]
2281 UNSPEC_COPYSIGN))]
2282 "TARGET_FP"
2283 "cpys %R2,%R1,%0"
2284 [(set_attr "type" "fadd")])
2286 (define_insn "*ncopysignsf3"
2287 [(set (match_operand:SF 0 "register_operand" "=f")
2288 (neg:SF (unspec:SF [(match_operand:SF 1 "reg_or_0_operand" "fG")
2289 (match_operand:SF 2 "reg_or_0_operand" "fG")]
2290 UNSPEC_COPYSIGN)))]
2291 "TARGET_FP"
2292 "cpysn %R2,%R1,%0"
2293 [(set_attr "type" "fadd")])
2295 (define_insn "copysigndf3"
2296 [(set (match_operand:DF 0 "register_operand" "=f")
2297 (unspec:DF [(match_operand:DF 1 "reg_or_0_operand" "fG")
2298 (match_operand:DF 2 "reg_or_0_operand" "fG")]
2299 UNSPEC_COPYSIGN))]
2300 "TARGET_FP"
2301 "cpys %R2,%R1,%0"
2302 [(set_attr "type" "fadd")])
2304 (define_insn "*ncopysigndf3"
2305 [(set (match_operand:DF 0 "register_operand" "=f")
2306 (neg:DF (unspec:DF [(match_operand:DF 1 "reg_or_0_operand" "fG")
2307 (match_operand:DF 2 "reg_or_0_operand" "fG")]
2308 UNSPEC_COPYSIGN)))]
2309 "TARGET_FP"
2310 "cpysn %R2,%R1,%0"
2311 [(set_attr "type" "fadd")])
2313 (define_insn "*addsf_ieee"
2314 [(set (match_operand:SF 0 "register_operand" "=&f")
2315 (plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2316 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2317 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2318 "add%,%/ %R1,%R2,%0"
2319 [(set_attr "type" "fadd")
2320 (set_attr "trap" "yes")
2321 (set_attr "round_suffix" "normal")
2322 (set_attr "trap_suffix" "u_su_sui")])
2324 (define_insn "addsf3"
2325 [(set (match_operand:SF 0 "register_operand" "=f")
2326 (plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2327 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2328 "TARGET_FP"
2329 "add%,%/ %R1,%R2,%0"
2330 [(set_attr "type" "fadd")
2331 (set_attr "trap" "yes")
2332 (set_attr "round_suffix" "normal")
2333 (set_attr "trap_suffix" "u_su_sui")])
2335 (define_insn "*adddf_ieee"
2336 [(set (match_operand:DF 0 "register_operand" "=&f")
2337 (plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2338 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2339 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2340 "add%-%/ %R1,%R2,%0"
2341 [(set_attr "type" "fadd")
2342 (set_attr "trap" "yes")
2343 (set_attr "round_suffix" "normal")
2344 (set_attr "trap_suffix" "u_su_sui")])
2346 (define_insn "adddf3"
2347 [(set (match_operand:DF 0 "register_operand" "=f")
2348 (plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2349 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2350 "TARGET_FP"
2351 "add%-%/ %R1,%R2,%0"
2352 [(set_attr "type" "fadd")
2353 (set_attr "trap" "yes")
2354 (set_attr "round_suffix" "normal")
2355 (set_attr "trap_suffix" "u_su_sui")])
2357 (define_insn "*adddf_ext1"
2358 [(set (match_operand:DF 0 "register_operand" "=f")
2359 (plus:DF (float_extend:DF
2360 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2361 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2362 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2363 "add%-%/ %R1,%R2,%0"
2364 [(set_attr "type" "fadd")
2365 (set_attr "trap" "yes")
2366 (set_attr "round_suffix" "normal")
2367 (set_attr "trap_suffix" "u_su_sui")])
2369 (define_insn "*adddf_ext2"
2370 [(set (match_operand:DF 0 "register_operand" "=f")
2371 (plus:DF (float_extend:DF
2372 (match_operand:SF 1 "reg_or_0_operand" "%fG"))
2373 (float_extend:DF
2374 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2375 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2376 "add%-%/ %R1,%R2,%0"
2377 [(set_attr "type" "fadd")
2378 (set_attr "trap" "yes")
2379 (set_attr "round_suffix" "normal")
2380 (set_attr "trap_suffix" "u_su_sui")])
2382 (define_expand "addtf3"
2383 [(use (match_operand 0 "register_operand" ""))
2384 (use (match_operand 1 "general_operand" ""))
2385 (use (match_operand 2 "general_operand" ""))]
2386 "TARGET_HAS_XFLOATING_LIBS"
2387 "alpha_emit_xfloating_arith (PLUS, operands); DONE;")
2389 ;; Define conversion operators between DFmode and SImode, using the cvtql
2390 ;; instruction. To allow combine et al to do useful things, we keep the
2391 ;; operation as a unit until after reload, at which point we split the
2392 ;; instructions.
2393 ;;
2394 ;; Note that we (attempt to) only consider this optimization when the
2395 ;; ultimate destination is memory. If we will be doing further integer
2396 ;; processing, it is cheaper to do the truncation in the int regs.
2398 (define_insn "*cvtql"
2399 [(set (match_operand:SF 0 "register_operand" "=f")
2400 (unspec:SF [(match_operand:DI 1 "reg_or_0_operand" "fG")]
2401 UNSPEC_CVTQL))]
2402 "TARGET_FP"
2403 "cvtql%/ %R1,%0"
2404 [(set_attr "type" "fadd")
2405 (set_attr "trap" "yes")
2406 (set_attr "trap_suffix" "v_sv")])
2408 (define_insn_and_split "*fix_truncdfsi_ieee"
2409 [(set (match_operand:SI 0 "memory_operand" "=m")
2410 (subreg:SI
2411 (match_operator:DI 4 "fix_operator"
2412 [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0))
2413 (clobber (match_scratch:DI 2 "=&f"))
2414 (clobber (match_scratch:SF 3 "=&f"))]
2415 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2416 "#"
2417 "&& reload_completed"
2418 [(set (match_dup 2) (match_op_dup 4 [(match_dup 1)]))
2419 (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2420 (set (match_dup 5) (match_dup 3))]
2421 {
2422 operands[5] = adjust_address (operands[0], SFmode, 0);
2423 }
2424 [(set_attr "type" "fadd")
2425 (set_attr "trap" "yes")])
2427 (define_insn_and_split "*fix_truncdfsi_internal"
2428 [(set (match_operand:SI 0 "memory_operand" "=m")
2429 (subreg:SI
2430 (match_operator:DI 3 "fix_operator"
2431 [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0))
2432 (clobber (match_scratch:DI 2 "=f"))]
2433 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2434 "#"
2435 "&& reload_completed"
2436 [(set (match_dup 2) (match_op_dup 3 [(match_dup 1)]))
2437 (set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2438 (set (match_dup 5) (match_dup 4))]
2439 {
2440 operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2]));
2441 operands[5] = adjust_address (operands[0], SFmode, 0);
2442 }
2443 [(set_attr "type" "fadd")
2444 (set_attr "trap" "yes")])
2446 (define_insn "*fix_truncdfdi_ieee"
2447 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2448 (match_operator:DI 2 "fix_operator"
2449 [(match_operand:DF 1 "reg_or_0_operand" "fG")]))]
2450 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2451 "cvt%-q%/ %R1,%0"
2452 [(set_attr "type" "fadd")
2453 (set_attr "trap" "yes")
2454 (set_attr "round_suffix" "c")
2455 (set_attr "trap_suffix" "v_sv_svi")])
2457 (define_insn "*fix_truncdfdi2"
2458 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2459 (match_operator:DI 2 "fix_operator"
2460 [(match_operand:DF 1 "reg_or_0_operand" "fG")]))]
2461 "TARGET_FP"
2462 "cvt%-q%/ %R1,%0"
2463 [(set_attr "type" "fadd")
2464 (set_attr "trap" "yes")
2465 (set_attr "round_suffix" "c")
2466 (set_attr "trap_suffix" "v_sv_svi")])
2468 (define_expand "fix_truncdfdi2"
2469 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2470 (fix:DI (match_operand:DF 1 "reg_or_0_operand" "")))]
2471 "TARGET_FP"
2472 "")
2474 (define_expand "fixuns_truncdfdi2"
2475 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2476 (unsigned_fix:DI (match_operand:DF 1 "reg_or_0_operand" "")))]
2477 "TARGET_FP"
2478 "")
2480 ;; Likewise between SFmode and SImode.
2482 (define_insn_and_split "*fix_truncsfsi_ieee"
2483 [(set (match_operand:SI 0 "memory_operand" "=m")
2484 (subreg:SI
2485 (match_operator:DI 4 "fix_operator"
2486 [(float_extend:DF
2487 (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0))
2488 (clobber (match_scratch:DI 2 "=&f"))
2489 (clobber (match_scratch:SF 3 "=&f"))]
2490 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2491 "#"
2492 "&& reload_completed"
2493 [(set (match_dup 2) (match_op_dup 4 [(float_extend:DF (match_dup 1))]))
2494 (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2495 (set (match_dup 5) (match_dup 3))]
2496 {
2497 operands[5] = adjust_address (operands[0], SFmode, 0);
2498 }
2499 [(set_attr "type" "fadd")
2500 (set_attr "trap" "yes")])
2502 (define_insn_and_split "*fix_truncsfsi_internal"
2503 [(set (match_operand:SI 0 "memory_operand" "=m")
2504 (subreg:SI
2505 (match_operator:DI 3 "fix_operator"
2506 [(float_extend:DF
2507 (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0))
2508 (clobber (match_scratch:DI 2 "=f"))]
2509 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2510 "#"
2511 "&& reload_completed"
2512 [(set (match_dup 2) (match_op_dup 3 [(float_extend:DF (match_dup 1))]))
2513 (set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2514 (set (match_dup 5) (match_dup 4))]
2515 {
2516 operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2]));
2517 operands[5] = adjust_address (operands[0], SFmode, 0);
2518 }
2519 [(set_attr "type" "fadd")
2520 (set_attr "trap" "yes")])
2522 (define_insn "*fix_truncsfdi_ieee"
2523 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2524 (match_operator:DI 2 "fix_operator"
2525 [(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))]))]
2526 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2527 "cvt%-q%/ %R1,%0"
2528 [(set_attr "type" "fadd")
2529 (set_attr "trap" "yes")
2530 (set_attr "round_suffix" "c")
2531 (set_attr "trap_suffix" "v_sv_svi")])
2533 (define_insn "*fix_truncsfdi2"
2534 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2535 (match_operator:DI 2 "fix_operator"
2536 [(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))]))]
2537 "TARGET_FP"
2538 "cvt%-q%/ %R1,%0"
2539 [(set_attr "type" "fadd")
2540 (set_attr "trap" "yes")
2541 (set_attr "round_suffix" "c")
2542 (set_attr "trap_suffix" "v_sv_svi")])
2544 (define_expand "fix_truncsfdi2"
2545 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2546 (fix:DI (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))))]
2547 "TARGET_FP"
2548 "")
2550 (define_expand "fixuns_truncsfdi2"
2551 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2552 (unsigned_fix:DI
2553 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))))]
2554 "TARGET_FP"
2555 "")
2557 (define_expand "fix_trunctfdi2"
2558 [(use (match_operand:DI 0 "register_operand" ""))
2559 (use (match_operand:TF 1 "general_operand" ""))]
2560 "TARGET_HAS_XFLOATING_LIBS"
2561 "alpha_emit_xfloating_cvt (FIX, operands); DONE;")
2563 (define_expand "fixuns_trunctfdi2"
2564 [(use (match_operand:DI 0 "register_operand" ""))
2565 (use (match_operand:TF 1 "general_operand" ""))]
2566 "TARGET_HAS_XFLOATING_LIBS"
2567 "alpha_emit_xfloating_cvt (UNSIGNED_FIX, operands); DONE;")
2569 (define_insn "*floatdisf_ieee"
2570 [(set (match_operand:SF 0 "register_operand" "=&f")
2571 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2572 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2573 "cvtq%,%/ %1,%0"
2574 [(set_attr "type" "fadd")
2575 (set_attr "trap" "yes")
2576 (set_attr "round_suffix" "normal")
2577 (set_attr "trap_suffix" "sui")])
2579 (define_insn "floatdisf2"
2580 [(set (match_operand:SF 0 "register_operand" "=f")
2581 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2582 "TARGET_FP"
2583 "cvtq%,%/ %1,%0"
2584 [(set_attr "type" "fadd")
2585 (set_attr "trap" "yes")
2586 (set_attr "round_suffix" "normal")
2587 (set_attr "trap_suffix" "sui")])
2589 (define_insn_and_split "*floatsisf2_ieee"
2590 [(set (match_operand:SF 0 "register_operand" "=&f")
2591 (float:SF (match_operand:SI 1 "memory_operand" "m")))
2592 (clobber (match_scratch:DI 2 "=&f"))
2593 (clobber (match_scratch:SF 3 "=&f"))]
2594 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2595 "#"
2596 "&& reload_completed"
2597 [(set (match_dup 3) (match_dup 1))
2598 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
2599 (set (match_dup 0) (float:SF (match_dup 2)))]
2600 {
2601 operands[1] = adjust_address (operands[1], SFmode, 0);
2602 })
2604 (define_insn_and_split "*floatsisf2"
2605 [(set (match_operand:SF 0 "register_operand" "=f")
2606 (float:SF (match_operand:SI 1 "memory_operand" "m")))]
2607 "TARGET_FP"
2608 "#"
2609 "&& reload_completed"
2610 [(set (match_dup 0) (match_dup 1))
2611 (set (match_dup 2) (unspec:DI [(match_dup 0)] UNSPEC_CVTLQ))
2612 (set (match_dup 0) (float:SF (match_dup 2)))]
2613 {
2614 operands[1] = adjust_address (operands[1], SFmode, 0);
2615 operands[2] = gen_rtx_REG (DImode, REGNO (operands[0]));
2616 })
2618 (define_insn "*floatdidf_ieee"
2619 [(set (match_operand:DF 0 "register_operand" "=&f")
2620 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2621 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2622 "cvtq%-%/ %1,%0"
2623 [(set_attr "type" "fadd")
2624 (set_attr "trap" "yes")
2625 (set_attr "round_suffix" "normal")
2626 (set_attr "trap_suffix" "sui")])
2628 (define_insn "floatdidf2"
2629 [(set (match_operand:DF 0 "register_operand" "=f")
2630 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2631 "TARGET_FP"
2632 "cvtq%-%/ %1,%0"
2633 [(set_attr "type" "fadd")
2634 (set_attr "trap" "yes")
2635 (set_attr "round_suffix" "normal")
2636 (set_attr "trap_suffix" "sui")])
2638 (define_insn_and_split "*floatsidf2_ieee"
2639 [(set (match_operand:DF 0 "register_operand" "=&f")
2640 (float:DF (match_operand:SI 1 "memory_operand" "m")))
2641 (clobber (match_scratch:DI 2 "=&f"))
2642 (clobber (match_scratch:SF 3 "=&f"))]
2643 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2644 "#"
2645 "&& reload_completed"
2646 [(set (match_dup 3) (match_dup 1))
2647 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
2648 (set (match_dup 0) (float:DF (match_dup 2)))]
2649 {
2650 operands[1] = adjust_address (operands[1], SFmode, 0);
2651 })
2653 (define_insn_and_split "*floatsidf2"
2654 [(set (match_operand:DF 0 "register_operand" "=f")
2655 (float:DF (match_operand:SI 1 "memory_operand" "m")))]
2656 "TARGET_FP"
2657 "#"
2658 "&& reload_completed"
2659 [(set (match_dup 3) (match_dup 1))
2660 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
2661 (set (match_dup 0) (float:DF (match_dup 2)))]
2662 {
2663 operands[1] = adjust_address (operands[1], SFmode, 0);
2664 operands[2] = gen_rtx_REG (DImode, REGNO (operands[0]));
2665 operands[3] = gen_rtx_REG (SFmode, REGNO (operands[0]));
2666 })
2668 (define_expand "floatditf2"
2669 [(use (match_operand:TF 0 "register_operand" ""))
2670 (use (match_operand:DI 1 "general_operand" ""))]
2671 "TARGET_HAS_XFLOATING_LIBS"
2672 "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
2674 (define_expand "floatunsdisf2"
2675 [(use (match_operand:SF 0 "register_operand" ""))
2676 (use (match_operand:DI 1 "register_operand" ""))]
2677 "TARGET_FP"
2678 "alpha_emit_floatuns (operands); DONE;")
2680 (define_expand "floatunsdidf2"
2681 [(use (match_operand:DF 0 "register_operand" ""))
2682 (use (match_operand:DI 1 "register_operand" ""))]
2683 "TARGET_FP"
2684 "alpha_emit_floatuns (operands); DONE;")
2686 (define_expand "floatunsditf2"
2687 [(use (match_operand:TF 0 "register_operand" ""))
2688 (use (match_operand:DI 1 "general_operand" ""))]
2689 "TARGET_HAS_XFLOATING_LIBS"
2690 "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
2692 (define_expand "extendsfdf2"
2693 [(set (match_operand:DF 0 "register_operand" "")
2694 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2695 "TARGET_FP"
2696 {
2697 if (alpha_fptm >= ALPHA_FPTM_SU)
2698 operands[1] = force_reg (SFmode, operands[1]);
2699 })
2701 ;; The Unicos/Mk assembler doesn't support cvtst, but we've already
2702 ;; asserted that alpha_fptm == ALPHA_FPTM_N.
2704 (define_insn "*extendsfdf2_ieee"
2705 [(set (match_operand:DF 0 "register_operand" "=&f")
2706 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2707 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2708 "cvtsts %1,%0"
2709 [(set_attr "type" "fadd")
2710 (set_attr "trap" "yes")])
2712 (define_insn "*extendsfdf2_internal"
2713 [(set (match_operand:DF 0 "register_operand" "=f,f,m")
2714 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
2715 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2716 "@
2717 cpys %1,%1,%0
2718 ld%, %0,%1
2719 st%- %1,%0"
2720 [(set_attr "type" "fcpys,fld,fst")])
2722 ;; Use register_operand for operand 1 to prevent compress_float_constant
2723 ;; from doing something silly. When optimizing we'll put things back
2724 ;; together anyway.
2725 (define_expand "extendsftf2"
2726 [(use (match_operand:TF 0 "register_operand" ""))
2727 (use (match_operand:SF 1 "register_operand" ""))]
2728 "TARGET_HAS_XFLOATING_LIBS"
2729 {
2730 rtx tmp = gen_reg_rtx (DFmode);
2731 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
2732 emit_insn (gen_extenddftf2 (operands[0], tmp));
2733 DONE;
2734 })
2736 (define_expand "extenddftf2"
2737 [(use (match_operand:TF 0 "register_operand" ""))
2738 (use (match_operand:DF 1 "register_operand" ""))]
2739 "TARGET_HAS_XFLOATING_LIBS"
2740 "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
2742 (define_insn "*truncdfsf2_ieee"
2743 [(set (match_operand:SF 0 "register_operand" "=&f")
2744 (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2745 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2746 "cvt%-%,%/ %R1,%0"
2747 [(set_attr "type" "fadd")
2748 (set_attr "trap" "yes")
2749 (set_attr "round_suffix" "normal")
2750 (set_attr "trap_suffix" "u_su_sui")])
2752 (define_insn "truncdfsf2"
2753 [(set (match_operand:SF 0 "register_operand" "=f")
2754 (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2755 "TARGET_FP"
2756 "cvt%-%,%/ %R1,%0"
2757 [(set_attr "type" "fadd")
2758 (set_attr "trap" "yes")
2759 (set_attr "round_suffix" "normal")
2760 (set_attr "trap_suffix" "u_su_sui")])
2762 (define_expand "trunctfdf2"
2763 [(use (match_operand:DF 0 "register_operand" ""))
2764 (use (match_operand:TF 1 "general_operand" ""))]
2765 "TARGET_HAS_XFLOATING_LIBS"
2766 "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
2768 (define_expand "trunctfsf2"
2769 [(use (match_operand:SF 0 "register_operand" ""))
2770 (use (match_operand:TF 1 "general_operand" ""))]
2771 "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
2772 {
2773 rtx tmpf, sticky, arg, lo, hi;
2775 tmpf = gen_reg_rtx (DFmode);
2776 sticky = gen_reg_rtx (DImode);
2777 arg = copy_to_mode_reg (TFmode, operands[1]);
2778 lo = gen_lowpart (DImode, arg);
2779 hi = gen_highpart (DImode, arg);
2781 /* Convert the low word of the TFmode value into a sticky rounding bit,
2782 then or it into the low bit of the high word. This leaves the sticky
2783 bit at bit 48 of the fraction, which is representable in DFmode,
2784 which prevents rounding error in the final conversion to SFmode. */
2786 emit_insn (gen_rtx_SET (VOIDmode, sticky,
2787 gen_rtx_NE (DImode, lo, const0_rtx)));
2788 emit_insn (gen_iordi3 (hi, hi, sticky));
2789 emit_insn (gen_trunctfdf2 (tmpf, arg));
2790 emit_insn (gen_truncdfsf2 (operands[0], tmpf));
2791 DONE;
2792 })
2794 (define_insn "*divsf3_ieee"
2795 [(set (match_operand:SF 0 "register_operand" "=&f")
2796 (div:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2797 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2798 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2799 "div%,%/ %R1,%R2,%0"
2800 [(set_attr "type" "fdiv")
2801 (set_attr "opsize" "si")
2802 (set_attr "trap" "yes")
2803 (set_attr "round_suffix" "normal")
2804 (set_attr "trap_suffix" "u_su_sui")])
2806 (define_insn "divsf3"
2807 [(set (match_operand:SF 0 "register_operand" "=f")
2808 (div:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2809 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2810 "TARGET_FP"
2811 "div%,%/ %R1,%R2,%0"
2812 [(set_attr "type" "fdiv")
2813 (set_attr "opsize" "si")
2814 (set_attr "trap" "yes")
2815 (set_attr "round_suffix" "normal")
2816 (set_attr "trap_suffix" "u_su_sui")])
2818 (define_insn "*divdf3_ieee"
2819 [(set (match_operand:DF 0 "register_operand" "=&f")
2820 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2821 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2822 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2823 "div%-%/ %R1,%R2,%0"
2824 [(set_attr "type" "fdiv")
2825 (set_attr "trap" "yes")
2826 (set_attr "round_suffix" "normal")
2827 (set_attr "trap_suffix" "u_su_sui")])
2829 (define_insn "divdf3"
2830 [(set (match_operand:DF 0 "register_operand" "=f")
2831 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2832 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2833 "TARGET_FP"
2834 "div%-%/ %R1,%R2,%0"
2835 [(set_attr "type" "fdiv")
2836 (set_attr "trap" "yes")
2837 (set_attr "round_suffix" "normal")
2838 (set_attr "trap_suffix" "u_su_sui")])
2840 (define_insn "*divdf_ext1"
2841 [(set (match_operand:DF 0 "register_operand" "=f")
2842 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
2843 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2844 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2845 "div%-%/ %R1,%R2,%0"
2846 [(set_attr "type" "fdiv")
2847 (set_attr "trap" "yes")
2848 (set_attr "round_suffix" "normal")
2849 (set_attr "trap_suffix" "u_su_sui")])
2851 (define_insn "*divdf_ext2"
2852 [(set (match_operand:DF 0 "register_operand" "=f")
2853 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2854 (float_extend:DF
2855 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2856 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2857 "div%-%/ %R1,%R2,%0"
2858 [(set_attr "type" "fdiv")
2859 (set_attr "trap" "yes")
2860 (set_attr "round_suffix" "normal")
2861 (set_attr "trap_suffix" "u_su_sui")])
2863 (define_insn "*divdf_ext3"
2864 [(set (match_operand:DF 0 "register_operand" "=f")
2865 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
2866 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2867 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2868 "div%-%/ %R1,%R2,%0"
2869 [(set_attr "type" "fdiv")
2870 (set_attr "trap" "yes")
2871 (set_attr "round_suffix" "normal")
2872 (set_attr "trap_suffix" "u_su_sui")])
2874 (define_expand "divtf3"
2875 [(use (match_operand 0 "register_operand" ""))
2876 (use (match_operand 1 "general_operand" ""))
2877 (use (match_operand 2 "general_operand" ""))]
2878 "TARGET_HAS_XFLOATING_LIBS"
2879 "alpha_emit_xfloating_arith (DIV, operands); DONE;")
2881 (define_insn "*mulsf3_ieee"
2882 [(set (match_operand:SF 0 "register_operand" "=&f")
2883 (mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2884 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2885 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2886 "mul%,%/ %R1,%R2,%0"
2887 [(set_attr "type" "fmul")
2888 (set_attr "trap" "yes")
2889 (set_attr "round_suffix" "normal")
2890 (set_attr "trap_suffix" "u_su_sui")])
2892 (define_insn "mulsf3"
2893 [(set (match_operand:SF 0 "register_operand" "=f")
2894 (mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2895 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2896 "TARGET_FP"
2897 "mul%,%/ %R1,%R2,%0"
2898 [(set_attr "type" "fmul")
2899 (set_attr "trap" "yes")
2900 (set_attr "round_suffix" "normal")
2901 (set_attr "trap_suffix" "u_su_sui")])
2903 (define_insn "*muldf3_ieee"
2904 [(set (match_operand:DF 0 "register_operand" "=&f")
2905 (mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2906 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2907 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2908 "mul%-%/ %R1,%R2,%0"
2909 [(set_attr "type" "fmul")
2910 (set_attr "trap" "yes")
2911 (set_attr "round_suffix" "normal")
2912 (set_attr "trap_suffix" "u_su_sui")])
2914 (define_insn "muldf3"
2915 [(set (match_operand:DF 0 "register_operand" "=f")
2916 (mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2917 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2918 "TARGET_FP"
2919 "mul%-%/ %R1,%R2,%0"
2920 [(set_attr "type" "fmul")
2921 (set_attr "trap" "yes")
2922 (set_attr "round_suffix" "normal")
2923 (set_attr "trap_suffix" "u_su_sui")])
2925 (define_insn "*muldf_ext1"
2926 [(set (match_operand:DF 0 "register_operand" "=f")
2927 (mult:DF (float_extend:DF
2928 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2929 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2930 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2931 "mul%-%/ %R1,%R2,%0"
2932 [(set_attr "type" "fmul")
2933 (set_attr "trap" "yes")
2934 (set_attr "round_suffix" "normal")
2935 (set_attr "trap_suffix" "u_su_sui")])
2937 (define_insn "*muldf_ext2"
2938 [(set (match_operand:DF 0 "register_operand" "=f")
2939 (mult:DF (float_extend:DF
2940 (match_operand:SF 1 "reg_or_0_operand" "%fG"))
2941 (float_extend:DF
2942 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2943 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2944 "mul%-%/ %R1,%R2,%0"
2945 [(set_attr "type" "fmul")
2946 (set_attr "trap" "yes")
2947 (set_attr "round_suffix" "normal")
2948 (set_attr "trap_suffix" "u_su_sui")])
2950 (define_expand "multf3"
2951 [(use (match_operand 0 "register_operand" ""))
2952 (use (match_operand 1 "general_operand" ""))
2953 (use (match_operand 2 "general_operand" ""))]
2954 "TARGET_HAS_XFLOATING_LIBS"
2955 "alpha_emit_xfloating_arith (MULT, operands); DONE;")
2957 (define_insn "*subsf3_ieee"
2958 [(set (match_operand:SF 0 "register_operand" "=&f")
2959 (minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2960 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2961 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2962 "sub%,%/ %R1,%R2,%0"
2963 [(set_attr "type" "fadd")
2964 (set_attr "trap" "yes")
2965 (set_attr "round_suffix" "normal")
2966 (set_attr "trap_suffix" "u_su_sui")])
2968 (define_insn "subsf3"
2969 [(set (match_operand:SF 0 "register_operand" "=f")
2970 (minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2971 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2972 "TARGET_FP"
2973 "sub%,%/ %R1,%R2,%0"
2974 [(set_attr "type" "fadd")
2975 (set_attr "trap" "yes")
2976 (set_attr "round_suffix" "normal")
2977 (set_attr "trap_suffix" "u_su_sui")])
2979 (define_insn "*subdf3_ieee"
2980 [(set (match_operand:DF 0 "register_operand" "=&f")
2981 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2982 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2983 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2984 "sub%-%/ %R1,%R2,%0"
2985 [(set_attr "type" "fadd")
2986 (set_attr "trap" "yes")
2987 (set_attr "round_suffix" "normal")
2988 (set_attr "trap_suffix" "u_su_sui")])
2990 (define_insn "subdf3"
2991 [(set (match_operand:DF 0 "register_operand" "=f")
2992 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2993 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2994 "TARGET_FP"
2995 "sub%-%/ %R1,%R2,%0"
2996 [(set_attr "type" "fadd")
2997 (set_attr "trap" "yes")
2998 (set_attr "round_suffix" "normal")
2999 (set_attr "trap_suffix" "u_su_sui")])
3001 (define_insn "*subdf_ext1"
3002 [(set (match_operand:DF 0 "register_operand" "=f")
3003 (minus:DF (float_extend:DF
3004 (match_operand:SF 1 "reg_or_0_operand" "fG"))
3005 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
3006 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3007 "sub%-%/ %R1,%R2,%0"
3008 [(set_attr "type" "fadd")
3009 (set_attr "trap" "yes")
3010 (set_attr "round_suffix" "normal")
3011 (set_attr "trap_suffix" "u_su_sui")])
3013 (define_insn "*subdf_ext2"
3014 [(set (match_operand:DF 0 "register_operand" "=f")
3015 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
3016 (float_extend:DF
3017 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
3018 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3019 "sub%-%/ %R1,%R2,%0"
3020 [(set_attr "type" "fadd")
3021 (set_attr "trap" "yes")
3022 (set_attr "round_suffix" "normal")
3023 (set_attr "trap_suffix" "u_su_sui")])
3025 (define_insn "*subdf_ext3"
3026 [(set (match_operand:DF 0 "register_operand" "=f")
3027 (minus:DF (float_extend:DF
3028 (match_operand:SF 1 "reg_or_0_operand" "fG"))
3029 (float_extend:DF
3030 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
3031 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3032 "sub%-%/ %R1,%R2,%0"
3033 [(set_attr "type" "fadd")
3034 (set_attr "trap" "yes")
3035 (set_attr "round_suffix" "normal")
3036 (set_attr "trap_suffix" "u_su_sui")])
3038 (define_expand "subtf3"
3039 [(use (match_operand 0 "register_operand" ""))
3040 (use (match_operand 1 "general_operand" ""))
3041 (use (match_operand 2 "general_operand" ""))]
3042 "TARGET_HAS_XFLOATING_LIBS"
3043 "alpha_emit_xfloating_arith (MINUS, operands); DONE;")
3045 (define_insn "*sqrtsf2_ieee"
3046 [(set (match_operand:SF 0 "register_operand" "=&f")
3047 (sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
3048 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
3049 "sqrt%,%/ %R1,%0"
3050 [(set_attr "type" "fsqrt")
3051 (set_attr "opsize" "si")
3052 (set_attr "trap" "yes")
3053 (set_attr "round_suffix" "normal")
3054 (set_attr "trap_suffix" "u_su_sui")])
3056 (define_insn "sqrtsf2"
3057 [(set (match_operand:SF 0 "register_operand" "=f")
3058 (sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
3059 "TARGET_FP && TARGET_FIX"
3060 "sqrt%,%/ %R1,%0"
3061 [(set_attr "type" "fsqrt")
3062 (set_attr "opsize" "si")
3063 (set_attr "trap" "yes")
3064 (set_attr "round_suffix" "normal")
3065 (set_attr "trap_suffix" "u_su_sui")])
3067 (define_insn "*sqrtdf2_ieee"
3068 [(set (match_operand:DF 0 "register_operand" "=&f")
3069 (sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
3070 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
3071 "sqrt%-%/ %R1,%0"
3072 [(set_attr "type" "fsqrt")
3073 (set_attr "trap" "yes")
3074 (set_attr "round_suffix" "normal")
3075 (set_attr "trap_suffix" "u_su_sui")])
3077 (define_insn "sqrtdf2"
3078 [(set (match_operand:DF 0 "register_operand" "=f")
3079 (sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
3080 "TARGET_FP && TARGET_FIX"
3081 "sqrt%-%/ %R1,%0"
3082 [(set_attr "type" "fsqrt")
3083 (set_attr "trap" "yes")
3084 (set_attr "round_suffix" "normal")
3085 (set_attr "trap_suffix" "u_su_sui")])
3086 \f
3087 ;; Next are all the integer comparisons, and conditional moves and branches
3088 ;; and some of the related define_expand's and define_split's.
3090 (define_insn "*setcc_internal"
3091 [(set (match_operand 0 "register_operand" "=r")
3092 (match_operator 1 "alpha_comparison_operator"
3093 [(match_operand:DI 2 "register_operand" "r")
3094 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
3095 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3096 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3097 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3098 "cmp%C1 %2,%3,%0"
3099 [(set_attr "type" "icmp")])
3101 ;; Yes, we can technically support reg_or_8bit_operand in operand 2,
3102 ;; but that's non-canonical rtl and allowing that causes inefficiencies
3103 ;; from cse on.
3104 (define_insn "*setcc_swapped_internal"
3105 [(set (match_operand 0 "register_operand" "=r")
3106 (match_operator 1 "alpha_swapped_comparison_operator"
3107 [(match_operand:DI 2 "register_operand" "r")
3108 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
3109 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3110 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3111 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3112 "cmp%c1 %r3,%2,%0"
3113 [(set_attr "type" "icmp")])
3115 ;; Use match_operator rather than ne directly so that we can match
3116 ;; multiple integer modes.
3117 (define_insn "*setne_internal"
3118 [(set (match_operand 0 "register_operand" "=r")
3119 (match_operator 1 "signed_comparison_operator"
3120 [(match_operand:DI 2 "register_operand" "r")
3121 (const_int 0)]))]
3122 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3123 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3124 && GET_CODE (operands[1]) == NE
3125 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3126 "cmpult $31,%2,%0"
3127 [(set_attr "type" "icmp")])
3129 ;; The mode folding trick can't be used with const_int operands, since
3130 ;; reload needs to know the proper mode.
3131 ;;
3132 ;; Use add_operand instead of the more seemingly natural reg_or_8bit_operand
3133 ;; in order to create more pairs of constants. As long as we're allowing
3134 ;; two constants at the same time, and will have to reload one of them...
3136 (define_insn "*movqicc_internal"
3137 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r")
3138 (if_then_else:QI
3139 (match_operator 2 "signed_comparison_operator"
3140 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3141 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3142 (match_operand:QI 1 "add_operand" "rI,0,rI,0")
3143 (match_operand:QI 5 "add_operand" "0,rI,0,rI")))]
3144 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)"
3145 "@
3146 cmov%C2 %r3,%1,%0
3147 cmov%D2 %r3,%5,%0
3148 cmov%c2 %r4,%1,%0
3149 cmov%d2 %r4,%5,%0"
3150 [(set_attr "type" "icmov")])
3152 (define_insn "*movhicc_internal"
3153 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
3154 (if_then_else:HI
3155 (match_operator 2 "signed_comparison_operator"
3156 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3157 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3158 (match_operand:HI 1 "add_operand" "rI,0,rI,0")
3159 (match_operand:HI 5 "add_operand" "0,rI,0,rI")))]
3160 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)"
3161 "@
3162 cmov%C2 %r3,%1,%0
3163 cmov%D2 %r3,%5,%0
3164 cmov%c2 %r4,%1,%0
3165 cmov%d2 %r4,%5,%0"
3166 [(set_attr "type" "icmov")])
3168 (define_insn "*movsicc_internal"
3169 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
3170 (if_then_else:SI
3171 (match_operator 2 "signed_comparison_operator"
3172 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3173 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3174 (match_operand:SI 1 "add_operand" "rI,0,rI,0")
3175 (match_operand:SI 5 "add_operand" "0,rI,0,rI")))]
3176 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)"
3177 "@
3178 cmov%C2 %r3,%1,%0
3179 cmov%D2 %r3,%5,%0
3180 cmov%c2 %r4,%1,%0
3181 cmov%d2 %r4,%5,%0"
3182 [(set_attr "type" "icmov")])
3184 (define_insn "*movdicc_internal"
3185 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
3186 (if_then_else:DI
3187 (match_operator 2 "signed_comparison_operator"
3188 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3189 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3190 (match_operand:DI 1 "add_operand" "rI,0,rI,0")
3191 (match_operand:DI 5 "add_operand" "0,rI,0,rI")))]
3192 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)"
3193 "@
3194 cmov%C2 %r3,%1,%0
3195 cmov%D2 %r3,%5,%0
3196 cmov%c2 %r4,%1,%0
3197 cmov%d2 %r4,%5,%0"
3198 [(set_attr "type" "icmov")])
3200 (define_insn "*movqicc_lbc"
3201 [(set (match_operand:QI 0 "register_operand" "=r,r")
3202 (if_then_else:QI
3203 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3204 (const_int 1)
3205 (const_int 0))
3206 (const_int 0))
3207 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3208 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3209 ""
3210 "@
3211 cmovlbc %r2,%1,%0
3212 cmovlbs %r2,%3,%0"
3213 [(set_attr "type" "icmov")])
3215 (define_insn "*movhicc_lbc"
3216 [(set (match_operand:HI 0 "register_operand" "=r,r")
3217 (if_then_else:HI
3218 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3219 (const_int 1)
3220 (const_int 0))
3221 (const_int 0))
3222 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3223 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3224 ""
3225 "@
3226 cmovlbc %r2,%1,%0
3227 cmovlbs %r2,%3,%0"
3228 [(set_attr "type" "icmov")])
3230 (define_insn "*movsicc_lbc"
3231 [(set (match_operand:SI 0 "register_operand" "=r,r")
3232 (if_then_else:SI
3233 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3234 (const_int 1)
3235 (const_int 0))
3236 (const_int 0))
3237 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3238 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3239 ""
3240 "@
3241 cmovlbc %r2,%1,%0
3242 cmovlbs %r2,%3,%0"
3243 [(set_attr "type" "icmov")])
3245 (define_insn "*movdicc_lbc"
3246 [(set (match_operand:DI 0 "register_operand" "=r,r")
3247 (if_then_else:DI
3248 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3249 (const_int 1)
3250 (const_int 0))
3251 (const_int 0))
3252 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3253 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3254 ""
3255 "@
3256 cmovlbc %r2,%1,%0
3257 cmovlbs %r2,%3,%0"
3258 [(set_attr "type" "icmov")])
3260 (define_insn "*movqicc_lbs"
3261 [(set (match_operand:QI 0 "register_operand" "=r,r")
3262 (if_then_else:QI
3263 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3264 (const_int 1)
3265 (const_int 0))
3266 (const_int 0))
3267 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3268 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3269 ""
3270 "@
3271 cmovlbs %r2,%1,%0
3272 cmovlbc %r2,%3,%0"
3273 [(set_attr "type" "icmov")])
3275 (define_insn "*movhicc_lbs"
3276 [(set (match_operand:HI 0 "register_operand" "=r,r")
3277 (if_then_else:HI
3278 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3279 (const_int 1)
3280 (const_int 0))
3281 (const_int 0))
3282 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3283 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3284 ""
3285 "@
3286 cmovlbs %r2,%1,%0
3287 cmovlbc %r2,%3,%0"
3288 [(set_attr "type" "icmov")])
3290 (define_insn "*movsicc_lbs"
3291 [(set (match_operand:SI 0 "register_operand" "=r,r")
3292 (if_then_else:SI
3293 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3294 (const_int 1)
3295 (const_int 0))
3296 (const_int 0))
3297 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3298 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3299 ""
3300 "@
3301 cmovlbs %r2,%1,%0
3302 cmovlbc %r2,%3,%0"
3303 [(set_attr "type" "icmov")])
3305 (define_insn "*movdicc_lbs"
3306 [(set (match_operand:DI 0 "register_operand" "=r,r")
3307 (if_then_else:DI
3308 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3309 (const_int 1)
3310 (const_int 0))
3311 (const_int 0))
3312 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3313 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3314 ""
3315 "@
3316 cmovlbs %r2,%1,%0
3317 cmovlbc %r2,%3,%0"
3318 [(set_attr "type" "icmov")])
3320 ;; For ABS, we have two choices, depending on whether the input and output
3321 ;; registers are the same or not.
3322 (define_expand "absdi2"
3323 [(set (match_operand:DI 0 "register_operand" "")
3324 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3325 ""
3326 {
3327 if (rtx_equal_p (operands[0], operands[1]))
3328 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
3329 else
3330 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
3331 DONE;
3332 })
3334 (define_expand "absdi2_same"
3335 [(set (match_operand:DI 1 "register_operand" "")
3336 (neg:DI (match_operand:DI 0 "register_operand" "")))
3337 (set (match_dup 0)
3338 (if_then_else:DI (ge (match_dup 0) (const_int 0))
3339 (match_dup 0)
3340 (match_dup 1)))]
3341 ""
3342 "")
3344 (define_expand "absdi2_diff"
3345 [(set (match_operand:DI 0 "register_operand" "")
3346 (neg:DI (match_operand:DI 1 "register_operand" "")))
3347 (set (match_dup 0)
3348 (if_then_else:DI (lt (match_dup 1) (const_int 0))
3349 (match_dup 0)
3350 (match_dup 1)))]
3351 ""
3352 "")
3354 (define_split
3355 [(set (match_operand:DI 0 "register_operand" "")
3356 (abs:DI (match_dup 0)))
3357 (clobber (match_operand:DI 1 "register_operand" ""))]
3358 ""
3359 [(set (match_dup 1) (neg:DI (match_dup 0)))
3360 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
3361 (match_dup 0) (match_dup 1)))]
3362 "")
3364 (define_split
3365 [(set (match_operand:DI 0 "register_operand" "")
3366 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3367 "! rtx_equal_p (operands[0], operands[1])"
3368 [(set (match_dup 0) (neg:DI (match_dup 1)))
3369 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
3370 (match_dup 0) (match_dup 1)))]
3371 "")
3373 (define_split
3374 [(set (match_operand:DI 0 "register_operand" "")
3375 (neg:DI (abs:DI (match_dup 0))))
3376 (clobber (match_operand:DI 1 "register_operand" ""))]
3377 ""
3378 [(set (match_dup 1) (neg:DI (match_dup 0)))
3379 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
3380 (match_dup 0) (match_dup 1)))]
3381 "")
3383 (define_split
3384 [(set (match_operand:DI 0 "register_operand" "")
3385 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
3386 "! rtx_equal_p (operands[0], operands[1])"
3387 [(set (match_dup 0) (neg:DI (match_dup 1)))
3388 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
3389 (match_dup 0) (match_dup 1)))]
3390 "")
3392 (define_insn "sminqi3"
3393 [(set (match_operand:QI 0 "register_operand" "=r")
3394 (smin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3395 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3396 "TARGET_MAX"
3397 "minsb8 %r1,%2,%0"
3398 [(set_attr "type" "mvi")])
3400 (define_insn "uminqi3"
3401 [(set (match_operand:QI 0 "register_operand" "=r")
3402 (umin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3403 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3404 "TARGET_MAX"
3405 "minub8 %r1,%2,%0"
3406 [(set_attr "type" "mvi")])
3408 (define_insn "smaxqi3"
3409 [(set (match_operand:QI 0 "register_operand" "=r")
3410 (smax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3411 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3412 "TARGET_MAX"
3413 "maxsb8 %r1,%2,%0"
3414 [(set_attr "type" "mvi")])
3416 (define_insn "umaxqi3"
3417 [(set (match_operand:QI 0 "register_operand" "=r")
3418 (umax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3419 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3420 "TARGET_MAX"
3421 "maxub8 %r1,%2,%0"
3422 [(set_attr "type" "mvi")])
3424 (define_insn "sminhi3"
3425 [(set (match_operand:HI 0 "register_operand" "=r")
3426 (smin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3427 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3428 "TARGET_MAX"
3429 "minsw4 %r1,%2,%0"
3430 [(set_attr "type" "mvi")])
3432 (define_insn "uminhi3"
3433 [(set (match_operand:HI 0 "register_operand" "=r")
3434 (umin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3435 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3436 "TARGET_MAX"
3437 "minuw4 %r1,%2,%0"
3438 [(set_attr "type" "mvi")])
3440 (define_insn "smaxhi3"
3441 [(set (match_operand:HI 0 "register_operand" "=r")
3442 (smax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3443 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3444 "TARGET_MAX"
3445 "maxsw4 %r1,%2,%0"
3446 [(set_attr "type" "mvi")])
3448 (define_insn "umaxhi3"
3449 [(set (match_operand:HI 0 "register_operand" "=r")
3450 (umax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3451 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3452 "TARGET_MAX"
3453 "maxuw4 %r1,%2,%0"
3454 [(set_attr "type" "mvi")])
3456 (define_expand "smaxdi3"
3457 [(set (match_dup 3)
3458 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
3459 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3460 (set (match_operand:DI 0 "register_operand" "")
3461 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3462 (match_dup 1) (match_dup 2)))]
3463 ""
3464 { operands[3] = gen_reg_rtx (DImode); })
3466 (define_split
3467 [(set (match_operand:DI 0 "register_operand" "")
3468 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3469 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3470 (clobber (match_operand:DI 3 "register_operand" ""))]
3471 "operands[2] != const0_rtx"
3472 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
3473 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3474 (match_dup 1) (match_dup 2)))]
3475 "")
3477 (define_insn "*smax_const0"
3478 [(set (match_operand:DI 0 "register_operand" "=r")
3479 (smax:DI (match_operand:DI 1 "register_operand" "0")
3480 (const_int 0)))]
3481 ""
3482 "cmovlt %0,0,%0"
3483 [(set_attr "type" "icmov")])
3485 (define_expand "smindi3"
3486 [(set (match_dup 3)
3487 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
3488 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3489 (set (match_operand:DI 0 "register_operand" "")
3490 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3491 (match_dup 1) (match_dup 2)))]
3492 ""
3493 { operands[3] = gen_reg_rtx (DImode); })
3495 (define_split
3496 [(set (match_operand:DI 0 "register_operand" "")
3497 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3498 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3499 (clobber (match_operand:DI 3 "register_operand" ""))]
3500 "operands[2] != const0_rtx"
3501 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
3502 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3503 (match_dup 1) (match_dup 2)))]
3504 "")
3506 (define_insn "*smin_const0"
3507 [(set (match_operand:DI 0 "register_operand" "=r")
3508 (smin:DI (match_operand:DI 1 "register_operand" "0")
3509 (const_int 0)))]
3510 ""
3511 "cmovgt %0,0,%0"
3512 [(set_attr "type" "icmov")])
3514 (define_expand "umaxdi3"
3515 [(set (match_dup 3)
3516 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3517 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3518 (set (match_operand:DI 0 "register_operand" "")
3519 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3520 (match_dup 1) (match_dup 2)))]
3521 ""
3522 "operands[3] = gen_reg_rtx (DImode);")
3524 (define_split
3525 [(set (match_operand:DI 0 "register_operand" "")
3526 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3527 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3528 (clobber (match_operand:DI 3 "register_operand" ""))]
3529 "operands[2] != const0_rtx"
3530 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
3531 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3532 (match_dup 1) (match_dup 2)))]
3533 "")
3535 (define_expand "umindi3"
3536 [(set (match_dup 3)
3537 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3538 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3539 (set (match_operand:DI 0 "register_operand" "")
3540 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3541 (match_dup 1) (match_dup 2)))]
3542 ""
3543 "operands[3] = gen_reg_rtx (DImode);")
3545 (define_split
3546 [(set (match_operand:DI 0 "register_operand" "")
3547 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3548 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3549 (clobber (match_operand:DI 3 "register_operand" ""))]
3550 "operands[2] != const0_rtx"
3551 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
3552 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3553 (match_dup 1) (match_dup 2)))]
3554 "")
3556 (define_insn "*bcc_normal"
3557 [(set (pc)
3558 (if_then_else
3559 (match_operator 1 "signed_comparison_operator"
3560 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3561 (const_int 0)])
3562 (label_ref (match_operand 0 "" ""))
3563 (pc)))]
3564 ""
3565 "b%C1 %r2,%0"
3566 [(set_attr "type" "ibr")])
3568 (define_insn "*bcc_reverse"
3569 [(set (pc)
3570 (if_then_else
3571 (match_operator 1 "signed_comparison_operator"
3572 [(match_operand:DI 2 "register_operand" "r")
3573 (const_int 0)])
3575 (pc)
3576 (label_ref (match_operand 0 "" ""))))]
3577 ""
3578 "b%c1 %2,%0"
3579 [(set_attr "type" "ibr")])
3581 (define_insn "*blbs_normal"
3582 [(set (pc)
3583 (if_then_else
3584 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3585 (const_int 1)
3586 (const_int 0))
3587 (const_int 0))
3588 (label_ref (match_operand 0 "" ""))
3589 (pc)))]
3590 ""
3591 "blbs %r1,%0"
3592 [(set_attr "type" "ibr")])
3594 (define_insn "*blbc_normal"
3595 [(set (pc)
3596 (if_then_else
3597 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3598 (const_int 1)
3599 (const_int 0))
3600 (const_int 0))
3601 (label_ref (match_operand 0 "" ""))
3602 (pc)))]
3603 ""
3604 "blbc %r1,%0"
3605 [(set_attr "type" "ibr")])
3607 (define_split
3608 [(parallel
3609 [(set (pc)
3610 (if_then_else
3611 (match_operator 1 "comparison_operator"
3612 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
3613 (const_int 1)
3614 (match_operand:DI 3 "const_int_operand" ""))
3615 (const_int 0)])
3616 (label_ref (match_operand 0 "" ""))
3617 (pc)))
3618 (clobber (match_operand:DI 4 "register_operand" ""))])]
3619 "INTVAL (operands[3]) != 0"
3620 [(set (match_dup 4)
3621 (lshiftrt:DI (match_dup 2) (match_dup 3)))
3622 (set (pc)
3623 (if_then_else (match_op_dup 1
3624 [(zero_extract:DI (match_dup 4)
3625 (const_int 1)
3626 (const_int 0))
3627 (const_int 0)])
3628 (label_ref (match_dup 0))
3629 (pc)))]
3630 "")
3631 \f
3632 ;; The following are the corresponding floating-point insns. Recall
3633 ;; we need to have variants that expand the arguments from SFmode
3634 ;; to DFmode.
3636 (define_insn "*cmpdf_ieee"
3637 [(set (match_operand:DF 0 "register_operand" "=&f")
3638 (match_operator:DF 1 "alpha_fp_comparison_operator"
3639 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3640 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3641 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3642 "cmp%-%C1%/ %R2,%R3,%0"
3643 [(set_attr "type" "fadd")
3644 (set_attr "trap" "yes")
3645 (set_attr "trap_suffix" "su")])
3647 (define_insn "*cmpdf_internal"
3648 [(set (match_operand:DF 0 "register_operand" "=f")
3649 (match_operator:DF 1 "alpha_fp_comparison_operator"
3650 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3651 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3652 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3653 "cmp%-%C1%/ %R2,%R3,%0"
3654 [(set_attr "type" "fadd")
3655 (set_attr "trap" "yes")
3656 (set_attr "trap_suffix" "su")])
3658 (define_insn "*cmpdf_ieee_ext1"
3659 [(set (match_operand:DF 0 "register_operand" "=&f")
3660 (match_operator:DF 1 "alpha_fp_comparison_operator"
3661 [(float_extend:DF
3662 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3663 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3664 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3665 "cmp%-%C1%/ %R2,%R3,%0"
3666 [(set_attr "type" "fadd")
3667 (set_attr "trap" "yes")
3668 (set_attr "trap_suffix" "su")])
3670 (define_insn "*cmpdf_ext1"
3671 [(set (match_operand:DF 0 "register_operand" "=f")
3672 (match_operator:DF 1 "alpha_fp_comparison_operator"
3673 [(float_extend:DF
3674 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3675 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3676 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3677 "cmp%-%C1%/ %R2,%R3,%0"
3678 [(set_attr "type" "fadd")
3679 (set_attr "trap" "yes")
3680 (set_attr "trap_suffix" "su")])
3682 (define_insn "*cmpdf_ieee_ext2"
3683 [(set (match_operand:DF 0 "register_operand" "=&f")
3684 (match_operator:DF 1 "alpha_fp_comparison_operator"
3685 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3686 (float_extend:DF
3687 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3688 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3689 "cmp%-%C1%/ %R2,%R3,%0"
3690 [(set_attr "type" "fadd")
3691 (set_attr "trap" "yes")
3692 (set_attr "trap_suffix" "su")])
3694 (define_insn "*cmpdf_ext2"
3695 [(set (match_operand:DF 0 "register_operand" "=f")
3696 (match_operator:DF 1 "alpha_fp_comparison_operator"
3697 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3698 (float_extend:DF
3699 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3700 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3701 "cmp%-%C1%/ %R2,%R3,%0"
3702 [(set_attr "type" "fadd")
3703 (set_attr "trap" "yes")
3704 (set_attr "trap_suffix" "su")])
3706 (define_insn "*cmpdf_ieee_ext3"
3707 [(set (match_operand:DF 0 "register_operand" "=&f")
3708 (match_operator:DF 1 "alpha_fp_comparison_operator"
3709 [(float_extend:DF
3710 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3711 (float_extend:DF
3712 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3713 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3714 "cmp%-%C1%/ %R2,%R3,%0"
3715 [(set_attr "type" "fadd")
3716 (set_attr "trap" "yes")
3717 (set_attr "trap_suffix" "su")])
3719 (define_insn "*cmpdf_ext3"
3720 [(set (match_operand:DF 0 "register_operand" "=f")
3721 (match_operator:DF 1 "alpha_fp_comparison_operator"
3722 [(float_extend:DF
3723 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3724 (float_extend:DF
3725 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3726 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3727 "cmp%-%C1%/ %R2,%R3,%0"
3728 [(set_attr "type" "fadd")
3729 (set_attr "trap" "yes")
3730 (set_attr "trap_suffix" "su")])
3732 (define_insn "*movdfcc_internal"
3733 [(set (match_operand:DF 0 "register_operand" "=f,f")
3734 (if_then_else:DF
3735 (match_operator 3 "signed_comparison_operator"
3736 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3737 (match_operand:DF 2 "const0_operand" "G,G")])
3738 (match_operand:DF 1 "reg_or_0_operand" "fG,0")
3739 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3740 "TARGET_FP"
3741 "@
3742 fcmov%C3 %R4,%R1,%0
3743 fcmov%D3 %R4,%R5,%0"
3744 [(set_attr "type" "fcmov")])
3746 (define_insn "*movsfcc_internal"
3747 [(set (match_operand:SF 0 "register_operand" "=f,f")
3748 (if_then_else:SF
3749 (match_operator 3 "signed_comparison_operator"
3750 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3751 (match_operand:DF 2 "const0_operand" "G,G")])
3752 (match_operand:SF 1 "reg_or_0_operand" "fG,0")
3753 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
3754 "TARGET_FP"
3755 "@
3756 fcmov%C3 %R4,%R1,%0
3757 fcmov%D3 %R4,%R5,%0"
3758 [(set_attr "type" "fcmov")])
3760 (define_insn "*movdfcc_ext1"
3761 [(set (match_operand:DF 0 "register_operand" "=f,f")
3762 (if_then_else:DF
3763 (match_operator 3 "signed_comparison_operator"
3764 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3765 (match_operand:DF 2 "const0_operand" "G,G")])
3766 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
3767 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3768 "TARGET_FP"
3769 "@
3770 fcmov%C3 %R4,%R1,%0
3771 fcmov%D3 %R4,%R5,%0"
3772 [(set_attr "type" "fcmov")])
3774 (define_insn "*movdfcc_ext2"
3775 [(set (match_operand:DF 0 "register_operand" "=f,f")
3776 (if_then_else:DF
3777 (match_operator 3 "signed_comparison_operator"
3778 [(float_extend:DF
3779 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3780 (match_operand:DF 2 "const0_operand" "G,G")])
3781 (match_operand:DF 1 "reg_or_0_operand" "fG,0")
3782 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3783 "TARGET_FP"
3784 "@
3785 fcmov%C3 %R4,%R1,%0
3786 fcmov%D3 %R4,%R5,%0"
3787 [(set_attr "type" "fcmov")])
3789 (define_insn "*movdfcc_ext3"
3790 [(set (match_operand:SF 0 "register_operand" "=f,f")
3791 (if_then_else:SF
3792 (match_operator 3 "signed_comparison_operator"
3793 [(float_extend:DF
3794 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3795 (match_operand:DF 2 "const0_operand" "G,G")])
3796 (match_operand:SF 1 "reg_or_0_operand" "fG,0")
3797 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
3798 "TARGET_FP"
3799 "@
3800 fcmov%C3 %R4,%R1,%0
3801 fcmov%D3 %R4,%R5,%0"
3802 [(set_attr "type" "fcmov")])
3804 (define_insn "*movdfcc_ext4"
3805 [(set (match_operand:DF 0 "register_operand" "=f,f")
3806 (if_then_else:DF
3807 (match_operator 3 "signed_comparison_operator"
3808 [(float_extend:DF
3809 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3810 (match_operand:DF 2 "const0_operand" "G,G")])
3811 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
3812 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3813 "TARGET_FP"
3814 "@
3815 fcmov%C3 %R4,%R1,%0
3816 fcmov%D3 %R4,%R5,%0"
3817 [(set_attr "type" "fcmov")])
3819 (define_expand "smaxdf3"
3820 [(set (match_dup 3)
3821 (le:DF (match_operand:DF 1 "reg_or_0_operand" "")
3822 (match_operand:DF 2 "reg_or_0_operand" "")))
3823 (set (match_operand:DF 0 "register_operand" "")
3824 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
3825 (match_dup 1) (match_dup 2)))]
3826 "TARGET_FP"
3827 {
3828 operands[3] = gen_reg_rtx (DFmode);
3829 operands[4] = CONST0_RTX (DFmode);
3830 })
3832 (define_expand "smindf3"
3833 [(set (match_dup 3)
3834 (lt:DF (match_operand:DF 1 "reg_or_0_operand" "")
3835 (match_operand:DF 2 "reg_or_0_operand" "")))
3836 (set (match_operand:DF 0 "register_operand" "")
3837 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
3838 (match_dup 1) (match_dup 2)))]
3839 "TARGET_FP"
3840 {
3841 operands[3] = gen_reg_rtx (DFmode);
3842 operands[4] = CONST0_RTX (DFmode);
3843 })
3845 (define_expand "smaxsf3"
3846 [(set (match_dup 3)
3847 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))
3848 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" ""))))
3849 (set (match_operand:SF 0 "register_operand" "")
3850 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
3851 (match_dup 1) (match_dup 2)))]
3852 "TARGET_FP"
3853 {
3854 operands[3] = gen_reg_rtx (DFmode);
3855 operands[4] = CONST0_RTX (DFmode);
3856 })
3858 (define_expand "sminsf3"
3859 [(set (match_dup 3)
3860 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))
3861 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" ""))))
3862 (set (match_operand:SF 0 "register_operand" "")
3863 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
3864 (match_dup 1) (match_dup 2)))]
3865 "TARGET_FP"
3866 {
3867 operands[3] = gen_reg_rtx (DFmode);
3868 operands[4] = CONST0_RTX (DFmode);
3869 })
3871 (define_insn "*fbcc_normal"
3872 [(set (pc)
3873 (if_then_else
3874 (match_operator 1 "signed_comparison_operator"
3875 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3876 (match_operand:DF 3 "const0_operand" "G")])
3877 (label_ref (match_operand 0 "" ""))
3878 (pc)))]
3879 "TARGET_FP"
3880 "fb%C1 %R2,%0"
3881 [(set_attr "type" "fbr")])
3883 (define_insn "*fbcc_ext_normal"
3884 [(set (pc)
3885 (if_then_else
3886 (match_operator 1 "signed_comparison_operator"
3887 [(float_extend:DF
3888 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3889 (match_operand:DF 3 "const0_operand" "G")])
3890 (label_ref (match_operand 0 "" ""))
3891 (pc)))]
3892 "TARGET_FP"
3893 "fb%C1 %R2,%0"
3894 [(set_attr "type" "fbr")])
3895 \f
3896 ;; These are the main define_expand's used to make conditional branches
3897 ;; and compares.
3899 (define_expand "cmpdf"
3900 [(set (cc0) (compare (match_operand:DF 0 "reg_or_0_operand" "")
3901 (match_operand:DF 1 "reg_or_0_operand" "")))]
3902 "TARGET_FP"
3903 {
3904 alpha_compare.op0 = operands[0];
3905 alpha_compare.op1 = operands[1];
3906 alpha_compare.fp_p = 1;
3907 DONE;
3908 })
3910 (define_expand "cmptf"
3911 [(set (cc0) (compare (match_operand:TF 0 "general_operand" "")
3912 (match_operand:TF 1 "general_operand" "")))]
3913 "TARGET_HAS_XFLOATING_LIBS"
3914 {
3915 alpha_compare.op0 = operands[0];
3916 alpha_compare.op1 = operands[1];
3917 alpha_compare.fp_p = 1;
3918 DONE;
3919 })
3921 (define_expand "cmpdi"
3922 [(set (cc0) (compare (match_operand:DI 0 "some_operand" "")
3923 (match_operand:DI 1 "some_operand" "")))]
3924 ""
3925 {
3926 alpha_compare.op0 = operands[0];
3927 alpha_compare.op1 = operands[1];
3928 alpha_compare.fp_p = 0;
3929 DONE;
3930 })
3932 (define_expand "beq"
3933 [(set (pc)
3934 (if_then_else (match_dup 1)
3935 (label_ref (match_operand 0 "" ""))
3936 (pc)))]
3937 ""
3938 "{ operands[1] = alpha_emit_conditional_branch (EQ); }")
3940 (define_expand "bne"
3941 [(set (pc)
3942 (if_then_else (match_dup 1)
3943 (label_ref (match_operand 0 "" ""))
3944 (pc)))]
3945 ""
3946 "{ operands[1] = alpha_emit_conditional_branch (NE); }")
3948 (define_expand "blt"
3949 [(set (pc)
3950 (if_then_else (match_dup 1)
3951 (label_ref (match_operand 0 "" ""))
3952 (pc)))]
3953 ""
3954 "{ operands[1] = alpha_emit_conditional_branch (LT); }")
3956 (define_expand "ble"
3957 [(set (pc)
3958 (if_then_else (match_dup 1)
3959 (label_ref (match_operand 0 "" ""))
3960 (pc)))]
3961 ""
3962 "{ operands[1] = alpha_emit_conditional_branch (LE); }")
3964 (define_expand "bgt"
3965 [(set (pc)
3966 (if_then_else (match_dup 1)
3967 (label_ref (match_operand 0 "" ""))
3968 (pc)))]
3969 ""
3970 "{ operands[1] = alpha_emit_conditional_branch (GT); }")
3972 (define_expand "bge"
3973 [(set (pc)
3974 (if_then_else (match_dup 1)
3975 (label_ref (match_operand 0 "" ""))
3976 (pc)))]
3977 ""
3978 "{ operands[1] = alpha_emit_conditional_branch (GE); }")
3980 (define_expand "bltu"
3981 [(set (pc)
3982 (if_then_else (match_dup 1)
3983 (label_ref (match_operand 0 "" ""))
3984 (pc)))]
3985 ""
3986 "{ operands[1] = alpha_emit_conditional_branch (LTU); }")
3988 (define_expand "bleu"
3989 [(set (pc)
3990 (if_then_else (match_dup 1)
3991 (label_ref (match_operand 0 "" ""))
3992 (pc)))]
3993 ""
3994 "{ operands[1] = alpha_emit_conditional_branch (LEU); }")
3996 (define_expand "bgtu"
3997 [(set (pc)
3998 (if_then_else (match_dup 1)
3999 (label_ref (match_operand 0 "" ""))
4000 (pc)))]
4001 ""
4002 "{ operands[1] = alpha_emit_conditional_branch (GTU); }")
4004 (define_expand "bgeu"
4005 [(set (pc)
4006 (if_then_else (match_dup 1)
4007 (label_ref (match_operand 0 "" ""))
4008 (pc)))]
4009 ""
4010 "{ operands[1] = alpha_emit_conditional_branch (GEU); }")
4012 (define_expand "bunordered"
4013 [(set (pc)
4014 (if_then_else (match_dup 1)
4015 (label_ref (match_operand 0 "" ""))
4016 (pc)))]
4017 ""
4018 "{ operands[1] = alpha_emit_conditional_branch (UNORDERED); }")
4020 (define_expand "bordered"
4021 [(set (pc)
4022 (if_then_else (match_dup 1)
4023 (label_ref (match_operand 0 "" ""))
4024 (pc)))]
4025 ""
4026 "{ operands[1] = alpha_emit_conditional_branch (ORDERED); }")
4028 (define_expand "seq"
4029 [(set (match_operand:DI 0 "register_operand" "")
4030 (match_dup 1))]
4031 ""
4032 "{ if ((operands[1] = alpha_emit_setcc (EQ)) == NULL_RTX) FAIL; }")
4034 (define_expand "sne"
4035 [(set (match_operand:DI 0 "register_operand" "")
4036 (match_dup 1))]
4037 ""
4038 "{ if ((operands[1] = alpha_emit_setcc (NE)) == NULL_RTX) FAIL; }")
4040 (define_expand "slt"
4041 [(set (match_operand:DI 0 "register_operand" "")
4042 (match_dup 1))]
4043 ""
4044 "{ if ((operands[1] = alpha_emit_setcc (LT)) == NULL_RTX) FAIL; }")
4046 (define_expand "sle"
4047 [(set (match_operand:DI 0 "register_operand" "")
4048 (match_dup 1))]
4049 ""
4050 "{ if ((operands[1] = alpha_emit_setcc (LE)) == NULL_RTX) FAIL; }")
4052 (define_expand "sgt"
4053 [(set (match_operand:DI 0 "register_operand" "")
4054 (match_dup 1))]
4055 ""
4056 "{ if ((operands[1] = alpha_emit_setcc (GT)) == NULL_RTX) FAIL; }")
4058 (define_expand "sge"
4059 [(set (match_operand:DI 0 "register_operand" "")
4060 (match_dup 1))]
4061 ""
4062 "{ if ((operands[1] = alpha_emit_setcc (GE)) == NULL_RTX) FAIL; }")
4064 (define_expand "sltu"
4065 [(set (match_operand:DI 0 "register_operand" "")
4066 (match_dup 1))]
4067 ""
4068 "{ if ((operands[1] = alpha_emit_setcc (LTU)) == NULL_RTX) FAIL; }")
4070 (define_expand "sleu"
4071 [(set (match_operand:DI 0 "register_operand" "")
4072 (match_dup 1))]
4073 ""
4074 "{ if ((operands[1] = alpha_emit_setcc (LEU)) == NULL_RTX) FAIL; }")
4076 (define_expand "sgtu"
4077 [(set (match_operand:DI 0 "register_operand" "")
4078 (match_dup 1))]
4079 ""
4080 "{ if ((operands[1] = alpha_emit_setcc (GTU)) == NULL_RTX) FAIL; }")
4082 (define_expand "sgeu"
4083 [(set (match_operand:DI 0 "register_operand" "")
4084 (match_dup 1))]
4085 ""
4086 "{ if ((operands[1] = alpha_emit_setcc (GEU)) == NULL_RTX) FAIL; }")
4088 (define_expand "sunordered"
4089 [(set (match_operand:DI 0 "register_operand" "")
4090 (match_dup 1))]
4091 ""
4092 "{ if ((operands[1] = alpha_emit_setcc (UNORDERED)) == NULL_RTX) FAIL; }")
4094 (define_expand "sordered"
4095 [(set (match_operand:DI 0 "register_operand" "")
4096 (match_dup 1))]
4097 ""
4098 "{ if ((operands[1] = alpha_emit_setcc (ORDERED)) == NULL_RTX) FAIL; }")
4099 \f
4100 ;; These are the main define_expand's used to make conditional moves.
4102 (define_expand "movsicc"
4103 [(set (match_operand:SI 0 "register_operand" "")
4104 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4105 (match_operand:SI 2 "reg_or_8bit_operand" "")
4106 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
4107 ""
4108 {
4109 if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0)
4110 FAIL;
4111 })
4113 (define_expand "movdicc"
4114 [(set (match_operand:DI 0 "register_operand" "")
4115 (if_then_else:DI (match_operand 1 "comparison_operator" "")
4116 (match_operand:DI 2 "reg_or_8bit_operand" "")
4117 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
4118 ""
4119 {
4120 if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0)
4121 FAIL;
4122 })
4124 (define_expand "movsfcc"
4125 [(set (match_operand:SF 0 "register_operand" "")
4126 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4127 (match_operand:SF 2 "reg_or_8bit_operand" "")
4128 (match_operand:SF 3 "reg_or_8bit_operand" "")))]
4129 ""
4130 {
4131 if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
4132 FAIL;
4133 })
4135 (define_expand "movdfcc"
4136 [(set (match_operand:DF 0 "register_operand" "")
4137 (if_then_else:DF (match_operand 1 "comparison_operator" "")
4138 (match_operand:DF 2 "reg_or_8bit_operand" "")
4139 (match_operand:DF 3 "reg_or_8bit_operand" "")))]
4140 ""
4141 {
4142 if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0)
4143 FAIL;
4144 })
4145 \f
4146 ;; These define_split definitions are used in cases when comparisons have
4147 ;; not be stated in the correct way and we need to reverse the second
4148 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
4149 ;; comparison that tests the result being reversed. We have one define_split
4150 ;; for each use of a comparison. They do not match valid insns and need
4151 ;; not generate valid insns.
4152 ;;
4153 ;; We can also handle equality comparisons (and inequality comparisons in
4154 ;; cases where the resulting add cannot overflow) by doing an add followed by
4155 ;; a comparison with zero. This is faster since the addition takes one
4156 ;; less cycle than a compare when feeding into a conditional move.
4157 ;; For this case, we also have an SImode pattern since we can merge the add
4158 ;; and sign extend and the order doesn't matter.
4159 ;;
4160 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
4161 ;; operation could have been generated.
4163 (define_split
4164 [(set (match_operand:DI 0 "register_operand" "")
4165 (if_then_else:DI
4166 (match_operator 1 "comparison_operator"
4167 [(match_operand:DI 2 "reg_or_0_operand" "")
4168 (match_operand:DI 3 "reg_or_cint_operand" "")])
4169 (match_operand:DI 4 "reg_or_cint_operand" "")
4170 (match_operand:DI 5 "reg_or_cint_operand" "")))
4171 (clobber (match_operand:DI 6 "register_operand" ""))]
4172 "operands[3] != const0_rtx"
4173 [(set (match_dup 6) (match_dup 7))
4174 (set (match_dup 0)
4175 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
4176 {
4177 enum rtx_code code = GET_CODE (operands[1]);
4178 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4180 /* If we are comparing for equality with a constant and that constant
4181 appears in the arm when the register equals the constant, use the
4182 register since that is more likely to match (and to produce better code
4183 if both would). */
4185 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
4186 && rtx_equal_p (operands[4], operands[3]))
4187 operands[4] = operands[2];
4189 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
4190 && rtx_equal_p (operands[5], operands[3]))
4191 operands[5] = operands[2];
4193 if (code == NE || code == EQ
4194 || (extended_count (operands[2], DImode, unsignedp) >= 1
4195 && extended_count (operands[3], DImode, unsignedp) >= 1))
4196 {
4197 if (GET_CODE (operands[3]) == CONST_INT)
4198 operands[7] = gen_rtx_PLUS (DImode, operands[2],
4199 GEN_INT (- INTVAL (operands[3])));
4200 else
4201 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
4203 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
4204 }
4206 else if (code == EQ || code == LE || code == LT
4207 || code == LEU || code == LTU)
4208 {
4209 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
4210 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
4211 }
4212 else
4213 {
4214 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
4215 operands[2], operands[3]);
4216 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
4217 }
4218 })
4220 (define_split
4221 [(set (match_operand:DI 0 "register_operand" "")
4222 (if_then_else:DI
4223 (match_operator 1 "comparison_operator"
4224 [(match_operand:SI 2 "reg_or_0_operand" "")
4225 (match_operand:SI 3 "reg_or_cint_operand" "")])
4226 (match_operand:DI 4 "reg_or_8bit_operand" "")
4227 (match_operand:DI 5 "reg_or_8bit_operand" "")))
4228 (clobber (match_operand:DI 6 "register_operand" ""))]
4229 "operands[3] != const0_rtx
4230 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
4231 [(set (match_dup 6) (match_dup 7))
4232 (set (match_dup 0)
4233 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
4234 {
4235 enum rtx_code code = GET_CODE (operands[1]);
4236 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4237 rtx tem;
4239 if ((code != NE && code != EQ
4240 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
4241 && extended_count (operands[3], DImode, unsignedp) >= 1)))
4242 FAIL;
4244 if (GET_CODE (operands[3]) == CONST_INT)
4245 tem = gen_rtx_PLUS (SImode, operands[2],
4246 GEN_INT (- INTVAL (operands[3])));
4247 else
4248 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
4250 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
4251 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
4252 operands[6], const0_rtx);
4253 })
4255 ;; Prefer to use cmp and arithmetic when possible instead of a cmove.
4257 (define_split
4258 [(set (match_operand 0 "register_operand" "")
4259 (if_then_else (match_operator 1 "signed_comparison_operator"
4260 [(match_operand:DI 2 "reg_or_0_operand" "")
4261 (const_int 0)])
4262 (match_operand 3 "const_int_operand" "")
4263 (match_operand 4 "const_int_operand" "")))]
4264 ""
4265 [(const_int 0)]
4266 {
4267 if (alpha_split_conditional_move (GET_CODE (operands[1]), operands[0],
4268 operands[2], operands[3], operands[4]))
4269 DONE;
4270 else
4271 FAIL;
4272 })
4274 ;; ??? Why combine is allowed to create such non-canonical rtl, I don't know.
4275 ;; Oh well, we match it in movcc, so it must be partially our fault.
4276 (define_split
4277 [(set (match_operand 0 "register_operand" "")
4278 (if_then_else (match_operator 1 "signed_comparison_operator"
4279 [(const_int 0)
4280 (match_operand:DI 2 "reg_or_0_operand" "")])
4281 (match_operand 3 "const_int_operand" "")
4282 (match_operand 4 "const_int_operand" "")))]
4283 ""
4284 [(const_int 0)]
4285 {
4286 if (alpha_split_conditional_move (swap_condition (GET_CODE (operands[1])),
4287 operands[0], operands[2], operands[3],
4288 operands[4]))
4289 DONE;
4290 else
4291 FAIL;
4292 })
4294 (define_insn_and_split "*cmp_sadd_di"
4295 [(set (match_operand:DI 0 "register_operand" "=r")
4296 (plus:DI (if_then_else:DI
4297 (match_operator 1 "alpha_zero_comparison_operator"
4298 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4299 (const_int 0)])
4300 (match_operand:DI 3 "const48_operand" "I")
4301 (const_int 0))
4302 (match_operand:DI 4 "sext_add_operand" "rIO")))
4303 (clobber (match_scratch:DI 5 "=r"))]
4304 ""
4305 "#"
4306 "! no_new_pseudos || reload_completed"
4307 [(set (match_dup 5)
4308 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4309 (set (match_dup 0)
4310 (plus:DI (mult:DI (match_dup 5) (match_dup 3))
4311 (match_dup 4)))]
4312 {
4313 if (! no_new_pseudos)
4314 operands[5] = gen_reg_rtx (DImode);
4315 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4316 operands[5] = operands[0];
4317 })
4319 (define_insn_and_split "*cmp_sadd_si"
4320 [(set (match_operand:SI 0 "register_operand" "=r")
4321 (plus:SI (if_then_else:SI
4322 (match_operator 1 "alpha_zero_comparison_operator"
4323 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4324 (const_int 0)])
4325 (match_operand:SI 3 "const48_operand" "I")
4326 (const_int 0))
4327 (match_operand:SI 4 "sext_add_operand" "rIO")))
4328 (clobber (match_scratch:SI 5 "=r"))]
4329 ""
4330 "#"
4331 "! no_new_pseudos || reload_completed"
4332 [(set (match_dup 5)
4333 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4334 (set (match_dup 0)
4335 (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4336 (match_dup 4)))]
4337 {
4338 if (! no_new_pseudos)
4339 operands[5] = gen_reg_rtx (DImode);
4340 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4341 operands[5] = operands[0];
4342 })
4344 (define_insn_and_split "*cmp_sadd_sidi"
4345 [(set (match_operand:DI 0 "register_operand" "=r")
4346 (sign_extend:DI
4347 (plus:SI (if_then_else:SI
4348 (match_operator 1 "alpha_zero_comparison_operator"
4349 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4350 (const_int 0)])
4351 (match_operand:SI 3 "const48_operand" "I")
4352 (const_int 0))
4353 (match_operand:SI 4 "sext_add_operand" "rIO"))))
4354 (clobber (match_scratch:SI 5 "=r"))]
4355 ""
4356 "#"
4357 "! no_new_pseudos || reload_completed"
4358 [(set (match_dup 5)
4359 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4360 (set (match_dup 0)
4361 (sign_extend:DI (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4362 (match_dup 4))))]
4363 {
4364 if (! no_new_pseudos)
4365 operands[5] = gen_reg_rtx (DImode);
4366 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4367 operands[5] = operands[0];
4368 })
4370 (define_insn_and_split "*cmp_ssub_di"
4371 [(set (match_operand:DI 0 "register_operand" "=r")
4372 (minus:DI (if_then_else:DI
4373 (match_operator 1 "alpha_zero_comparison_operator"
4374 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4375 (const_int 0)])
4376 (match_operand:DI 3 "const48_operand" "I")
4377 (const_int 0))
4378 (match_operand:DI 4 "reg_or_8bit_operand" "rI")))
4379 (clobber (match_scratch:DI 5 "=r"))]
4380 ""
4381 "#"
4382 "! no_new_pseudos || reload_completed"
4383 [(set (match_dup 5)
4384 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4385 (set (match_dup 0)
4386 (minus:DI (mult:DI (match_dup 5) (match_dup 3))
4387 (match_dup 4)))]
4388 {
4389 if (! no_new_pseudos)
4390 operands[5] = gen_reg_rtx (DImode);
4391 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4392 operands[5] = operands[0];
4393 })
4395 (define_insn_and_split "*cmp_ssub_si"
4396 [(set (match_operand:SI 0 "register_operand" "=r")
4397 (minus:SI (if_then_else:SI
4398 (match_operator 1 "alpha_zero_comparison_operator"
4399 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4400 (const_int 0)])
4401 (match_operand:SI 3 "const48_operand" "I")
4402 (const_int 0))
4403 (match_operand:SI 4 "reg_or_8bit_operand" "rI")))
4404 (clobber (match_scratch:SI 5 "=r"))]
4405 ""
4406 "#"
4407 "! no_new_pseudos || reload_completed"
4408 [(set (match_dup 5)
4409 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4410 (set (match_dup 0)
4411 (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4412 (match_dup 4)))]
4413 {
4414 if (! no_new_pseudos)
4415 operands[5] = gen_reg_rtx (DImode);
4416 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4417 operands[5] = operands[0];
4418 })
4420 (define_insn_and_split "*cmp_ssub_sidi"
4421 [(set (match_operand:DI 0 "register_operand" "=r")
4422 (sign_extend:DI
4423 (minus:SI (if_then_else:SI
4424 (match_operator 1 "alpha_zero_comparison_operator"
4425 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4426 (const_int 0)])
4427 (match_operand:SI 3 "const48_operand" "I")
4428 (const_int 0))
4429 (match_operand:SI 4 "reg_or_8bit_operand" "rI"))))
4430 (clobber (match_scratch:SI 5 "=r"))]
4431 ""
4432 "#"
4433 "! no_new_pseudos || reload_completed"
4434 [(set (match_dup 5)
4435 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4436 (set (match_dup 0)
4437 (sign_extend:DI (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4438 (match_dup 4))))]
4439 {
4440 if (! no_new_pseudos)
4441 operands[5] = gen_reg_rtx (DImode);
4442 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4443 operands[5] = operands[0];
4444 })
4445 \f
4446 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
4447 ;; work differently, so we have different patterns for each.
4449 ;; On Unicos/Mk a call information word (CIW) must be generated for each
4450 ;; call. The CIW contains information about arguments passed in registers
4451 ;; and is stored in the caller's SSIB. Its offset relative to the beginning
4452 ;; of the SSIB is passed in $25. Handling this properly is quite complicated
4453 ;; in the presence of inlining since the CIWs for calls performed by the
4454 ;; inlined function must be stored in the SSIB of the function it is inlined
4455 ;; into as well. We encode the CIW in an unspec and append it to the list
4456 ;; of the CIWs for the current function only when the instruction for loading
4457 ;; $25 is generated.
4459 (define_expand "call"
4460 [(use (match_operand:DI 0 "" ""))
4461 (use (match_operand 1 "" ""))
4462 (use (match_operand 2 "" ""))
4463 (use (match_operand 3 "" ""))]
4464 ""
4465 {
4466 if (TARGET_ABI_WINDOWS_NT)
4467 emit_call_insn (gen_call_nt (operands[0], operands[1]));
4468 else if (TARGET_ABI_OPEN_VMS)
4469 emit_call_insn (gen_call_vms (operands[0], operands[2]));
4470 else if (TARGET_ABI_UNICOSMK)
4471 emit_call_insn (gen_call_umk (operands[0], operands[2]));
4472 else
4473 emit_call_insn (gen_call_osf (operands[0], operands[1]));
4474 DONE;
4475 })
4477 (define_expand "sibcall"
4478 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4479 (match_operand 1 "" ""))
4480 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4481 "TARGET_ABI_OSF"
4482 {
4483 gcc_assert (GET_CODE (operands[0]) == MEM);
4484 operands[0] = XEXP (operands[0], 0);
4485 })
4487 (define_expand "call_osf"
4488 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4489 (match_operand 1 "" ""))
4490 (use (reg:DI 29))
4491 (clobber (reg:DI 26))])]
4492 ""
4493 {
4494 gcc_assert (GET_CODE (operands[0]) == MEM);
4496 operands[0] = XEXP (operands[0], 0);
4497 if (! call_operand (operands[0], Pmode))
4498 operands[0] = copy_to_mode_reg (Pmode, operands[0]);
4499 })
4501 (define_expand "call_nt"
4502 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4503 (match_operand 1 "" ""))
4504 (clobber (reg:DI 26))])]
4505 ""
4506 {
4507 gcc_assert (GET_CODE (operands[0]) == MEM);
4509 operands[0] = XEXP (operands[0], 0);
4510 if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
4511 operands[0] = force_reg (DImode, operands[0]);
4512 })
4514 ;; Calls on Unicos/Mk are always indirect.
4515 ;; op 0: symbol ref for called function
4516 ;; op 1: CIW for $25 represented by an unspec
4518 (define_expand "call_umk"
4519 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4520 (match_operand 1 "" ""))
4521 (use (reg:DI 25))
4522 (clobber (reg:DI 26))])]
4523 ""
4524 {
4525 gcc_assert (GET_CODE (operands[0]) == MEM);
4527 /* Always load the address of the called function into a register;
4528 load the CIW in $25. */
4530 operands[0] = XEXP (operands[0], 0);
4531 if (GET_CODE (operands[0]) != REG)
4532 operands[0] = force_reg (DImode, operands[0]);
4534 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4535 })
4537 ;;
4538 ;; call openvms/alpha
4539 ;; op 0: symbol ref for called function
4540 ;; op 1: next_arg_reg (argument information value for R25)
4541 ;;
4542 (define_expand "call_vms"
4543 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4544 (match_operand 1 "" ""))
4545 (use (match_dup 2))
4546 (use (reg:DI 25))
4547 (use (reg:DI 26))
4548 (clobber (reg:DI 27))])]
4549 ""
4550 {
4551 gcc_assert (GET_CODE (operands[0]) == MEM);
4553 operands[0] = XEXP (operands[0], 0);
4555 /* Always load AI with argument information, then handle symbolic and
4556 indirect call differently. Load RA and set operands[2] to PV in
4557 both cases. */
4559 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4560 if (GET_CODE (operands[0]) == SYMBOL_REF)
4561 {
4562 alpha_need_linkage (XSTR (operands[0], 0), 0);
4564 operands[2] = const0_rtx;
4565 }
4566 else
4567 {
4568 emit_move_insn (gen_rtx_REG (Pmode, 26),
4569 gen_rtx_MEM (Pmode, plus_constant (operands[0], 8)));
4570 operands[2] = operands[0];
4571 }
4573 })
4575 (define_expand "call_value"
4576 [(use (match_operand 0 "" ""))
4577 (use (match_operand:DI 1 "" ""))
4578 (use (match_operand 2 "" ""))
4579 (use (match_operand 3 "" ""))
4580 (use (match_operand 4 "" ""))]
4581 ""
4582 {
4583 if (TARGET_ABI_WINDOWS_NT)
4584 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
4585 else if (TARGET_ABI_OPEN_VMS)
4586 emit_call_insn (gen_call_value_vms (operands[0], operands[1],
4587 operands[3]));
4588 else if (TARGET_ABI_UNICOSMK)
4589 emit_call_insn (gen_call_value_umk (operands[0], operands[1],
4590 operands[3]));
4591 else
4592 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
4593 operands[2]));
4594 DONE;
4595 })
4597 (define_expand "sibcall_value"
4598 [(parallel [(set (match_operand 0 "" "")
4599 (call (mem:DI (match_operand 1 "" ""))
4600 (match_operand 2 "" "")))
4601 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4602 "TARGET_ABI_OSF"
4603 {
4604 gcc_assert (GET_CODE (operands[1]) == MEM);
4605 operands[1] = XEXP (operands[1], 0);
4606 })
4608 (define_expand "call_value_osf"
4609 [(parallel [(set (match_operand 0 "" "")
4610 (call (mem:DI (match_operand 1 "" ""))
4611 (match_operand 2 "" "")))
4612 (use (reg:DI 29))
4613 (clobber (reg:DI 26))])]
4614 ""
4615 {
4616 gcc_assert (GET_CODE (operands[1]) == MEM);
4618 operands[1] = XEXP (operands[1], 0);
4619 if (! call_operand (operands[1], Pmode))
4620 operands[1] = copy_to_mode_reg (Pmode, operands[1]);
4621 })
4623 (define_expand "call_value_nt"
4624 [(parallel [(set (match_operand 0 "" "")
4625 (call (mem:DI (match_operand 1 "" ""))
4626 (match_operand 2 "" "")))
4627 (clobber (reg:DI 26))])]
4628 ""
4629 {
4630 gcc_assert (GET_CODE (operands[1]) == MEM);
4632 operands[1] = XEXP (operands[1], 0);
4633 if (GET_CODE (operands[1]) != SYMBOL_REF && GET_CODE (operands[1]) != REG)
4634 operands[1] = force_reg (DImode, operands[1]);
4635 })
4637 (define_expand "call_value_vms"
4638 [(parallel [(set (match_operand 0 "" "")
4639 (call (mem:DI (match_operand:DI 1 "" ""))
4640 (match_operand 2 "" "")))
4641 (use (match_dup 3))
4642 (use (reg:DI 25))
4643 (use (reg:DI 26))
4644 (clobber (reg:DI 27))])]
4645 ""
4646 {
4647 gcc_assert (GET_CODE (operands[1]) == MEM);
4649 operands[1] = XEXP (operands[1], 0);
4651 /* Always load AI with argument information, then handle symbolic and
4652 indirect call differently. Load RA and set operands[3] to PV in
4653 both cases. */
4655 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4656 if (GET_CODE (operands[1]) == SYMBOL_REF)
4657 {
4658 alpha_need_linkage (XSTR (operands[1], 0), 0);
4660 operands[3] = const0_rtx;
4661 }
4662 else
4663 {
4664 emit_move_insn (gen_rtx_REG (Pmode, 26),
4665 gen_rtx_MEM (Pmode, plus_constant (operands[1], 8)));
4666 operands[3] = operands[1];
4667 }
4668 })
4670 (define_expand "call_value_umk"
4671 [(parallel [(set (match_operand 0 "" "")
4672 (call (mem:DI (match_operand 1 "" ""))
4673 (match_operand 2 "" "")))
4674 (use (reg:DI 25))
4675 (clobber (reg:DI 26))])]
4676 ""
4677 {
4678 gcc_assert (GET_CODE (operands[1]) == MEM);
4680 operands[1] = XEXP (operands[1], 0);
4681 if (GET_CODE (operands[1]) != REG)
4682 operands[1] = force_reg (DImode, operands[1]);
4684 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4685 })
4687 (define_insn "*call_osf_1_er"
4688 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4689 (match_operand 1 "" ""))
4690 (use (reg:DI 29))
4691 (clobber (reg:DI 26))]
4692 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4693 "@
4694 jsr $26,(%0),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
4695 bsr $26,%0\t\t!samegp
4696 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
4697 [(set_attr "type" "jsr")
4698 (set_attr "length" "12,*,16")])
4700 ;; We must use peep2 instead of a split because we need accurate life
4701 ;; information for $gp. Consider the case of { bar(); while (1); }.
4702 (define_peephole2
4703 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4704 (match_operand 1 "" ""))
4705 (use (reg:DI 29))
4706 (clobber (reg:DI 26))])]
4707 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4708 && ! samegp_function_operand (operands[0], Pmode)
4709 && (peep2_regno_dead_p (1, 29)
4710 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
4711 [(parallel [(call (mem:DI (match_dup 2))
4712 (match_dup 1))
4713 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4714 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4715 (use (match_dup 0))
4716 (use (match_dup 3))])]
4717 {
4718 if (CONSTANT_P (operands[0]))
4719 {
4720 operands[2] = gen_rtx_REG (Pmode, 27);
4721 operands[3] = GEN_INT (alpha_next_sequence_number++);
4722 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4723 operands[0], operands[3]));
4724 }
4725 else
4726 {
4727 operands[2] = operands[0];
4728 operands[0] = const0_rtx;
4729 operands[3] = const0_rtx;
4730 }
4731 })
4733 (define_peephole2
4734 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4735 (match_operand 1 "" ""))
4736 (use (reg:DI 29))
4737 (clobber (reg:DI 26))])]
4738 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4739 && ! samegp_function_operand (operands[0], Pmode)
4740 && ! (peep2_regno_dead_p (1, 29)
4741 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
4742 [(parallel [(call (mem:DI (match_dup 2))
4743 (match_dup 1))
4744 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4745 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4746 (use (match_dup 0))
4747 (use (match_dup 4))])
4748 (set (reg:DI 29)
4749 (unspec_volatile:DI [(reg:DI 26) (match_dup 3)] UNSPECV_LDGP1))
4750 (set (reg:DI 29)
4751 (unspec:DI [(reg:DI 29) (match_dup 3)] UNSPEC_LDGP2))]
4752 {
4753 if (CONSTANT_P (operands[0]))
4754 {
4755 operands[2] = gen_rtx_REG (Pmode, 27);
4756 operands[4] = GEN_INT (alpha_next_sequence_number++);
4757 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4758 operands[0], operands[4]));
4759 }
4760 else
4761 {
4762 operands[2] = operands[0];
4763 operands[0] = const0_rtx;
4764 operands[4] = const0_rtx;
4765 }
4766 operands[3] = GEN_INT (alpha_next_sequence_number++);
4767 })
4769 ;; We add a blockage unspec_volatile to prevent insns from moving down
4770 ;; from above the call to in between the call and the ldah gpdisp.
4772 (define_insn "*call_osf_2_er"
4773 [(call (mem:DI (match_operand:DI 0 "register_operand" "c"))
4774 (match_operand 1 "" ""))
4775 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4776 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4777 (use (match_operand 2 "" ""))
4778 (use (match_operand 3 "const_int_operand" ""))]
4779 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4780 "jsr $26,(%0),%2%J3"
4781 [(set_attr "type" "jsr")
4782 (set_attr "cannot_copy" "true")])
4784 ;; We output a nop after noreturn calls at the very end of the function to
4785 ;; ensure that the return address always remains in the caller's code range,
4786 ;; as not doing so might confuse unwinding engines.
4787 ;;
4788 ;; The potential change in insn length is not reflected in the length
4789 ;; attributes at this stage. Since the extra space is only actually added at
4790 ;; the very end of the compilation process (via final/print_operand), it
4791 ;; really seems harmless and not worth the trouble of some extra computation
4792 ;; cost and complexity.
4794 (define_insn "*call_osf_1_noreturn"
4795 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4796 (match_operand 1 "" ""))
4797 (use (reg:DI 29))
4798 (clobber (reg:DI 26))]
4799 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
4800 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
4801 "@
4802 jsr $26,($27),0%+
4803 bsr $26,$%0..ng%+
4804 jsr $26,%0%+"
4805 [(set_attr "type" "jsr")
4806 (set_attr "length" "*,*,8")])
4808 (define_insn "*call_osf_1"
4809 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4810 (match_operand 1 "" ""))
4811 (use (reg:DI 29))
4812 (clobber (reg:DI 26))]
4813 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4814 "@
4815 jsr $26,($27),0\;ldgp $29,0($26)
4816 bsr $26,$%0..ng
4817 jsr $26,%0\;ldgp $29,0($26)"
4818 [(set_attr "type" "jsr")
4819 (set_attr "length" "12,*,16")])
4821 ;; Note that the DEC assembler expands "jmp foo" with $at, which
4822 ;; doesn't do what we want.
4823 (define_insn "*sibcall_osf_1_er"
4824 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4825 (match_operand 1 "" ""))
4826 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4827 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4828 "@
4829 br $31,%0\t\t!samegp
4830 ldq $27,%0($29)\t\t!literal!%#\;jmp $31,($27),%0\t\t!lituse_jsr!%#"
4831 [(set_attr "type" "jsr")
4832 (set_attr "length" "*,8")])
4834 (define_insn "*sibcall_osf_1"
4835 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4836 (match_operand 1 "" ""))
4837 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4838 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4839 "@
4840 br $31,$%0..ng
4841 lda $27,%0\;jmp $31,($27),%0"
4842 [(set_attr "type" "jsr")
4843 (set_attr "length" "*,8")])
4845 (define_insn "*call_nt_1"
4846 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,s"))
4847 (match_operand 1 "" ""))
4848 (clobber (reg:DI 26))]
4849 "TARGET_ABI_WINDOWS_NT"
4850 "@
4851 jsr $26,(%0)
4852 bsr $26,%0
4853 jsr $26,%0"
4854 [(set_attr "type" "jsr")
4855 (set_attr "length" "*,*,12")])
4857 ; GAS relies on the order and position of instructions output below in order
4858 ; to generate relocs for VMS link to potentially optimize the call.
4859 ; Please do not molest.
4860 (define_insn "*call_vms_1"
4861 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,s"))
4862 (match_operand 1 "" ""))
4863 (use (match_operand:DI 2 "nonmemory_operand" "r,n"))
4864 (use (reg:DI 25))
4865 (use (reg:DI 26))
4866 (clobber (reg:DI 27))]
4867 "TARGET_ABI_OPEN_VMS"
4868 {
4869 switch (which_alternative)
4870 {
4871 case 0:
4872 return "mov %2,$27\;jsr $26,0\;ldq $27,0($29)";
4873 case 1:
4874 operands [2] = alpha_use_linkage (operands [0], cfun->decl, 1, 0);
4875 operands [3] = alpha_use_linkage (operands [0], cfun->decl, 0, 0);
4876 return "ldq $26,%3\;ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)";
4877 default:
4878 gcc_unreachable ();
4879 }
4880 }
4881 [(set_attr "type" "jsr")
4882 (set_attr "length" "12,16")])
4884 (define_insn "*call_umk_1"
4885 [(call (mem:DI (match_operand:DI 0 "call_operand" "r"))
4886 (match_operand 1 "" ""))
4887 (use (reg:DI 25))
4888 (clobber (reg:DI 26))]
4889 "TARGET_ABI_UNICOSMK"
4890 "jsr $26,(%0)"
4891 [(set_attr "type" "jsr")])
4893 ;; Call subroutine returning any type.
4895 (define_expand "untyped_call"
4896 [(parallel [(call (match_operand 0 "" "")
4897 (const_int 0))
4898 (match_operand 1 "" "")
4899 (match_operand 2 "" "")])]
4900 ""
4901 {
4902 int i;
4904 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
4906 for (i = 0; i < XVECLEN (operands[2], 0); i++)
4907 {
4908 rtx set = XVECEXP (operands[2], 0, i);
4909 emit_move_insn (SET_DEST (set), SET_SRC (set));
4910 }
4912 /* The optimizer does not know that the call sets the function value
4913 registers we stored in the result block. We avoid problems by
4914 claiming that all hard registers are used and clobbered at this
4915 point. */
4916 emit_insn (gen_blockage ());
4918 DONE;
4919 })
4921 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
4922 ;; all of memory. This blocks insns from being moved across this point.
4924 (define_insn "blockage"
4925 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
4926 ""
4927 ""
4928 [(set_attr "length" "0")
4929 (set_attr "type" "none")])
4931 (define_insn "jump"
4932 [(set (pc)
4933 (label_ref (match_operand 0 "" "")))]
4934 ""
4935 "br $31,%l0"
4936 [(set_attr "type" "ibr")])
4938 (define_expand "return"
4939 [(return)]
4940 "direct_return ()"
4941 "")
4943 (define_insn "*return_internal"
4944 [(return)]
4945 "reload_completed"
4946 "ret $31,($26),1"
4947 [(set_attr "type" "ibr")])
4949 (define_insn "indirect_jump"
4950 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
4951 ""
4952 "jmp $31,(%0),0"
4953 [(set_attr "type" "ibr")])
4955 (define_expand "tablejump"
4956 [(parallel [(set (pc)
4957 (match_operand 0 "register_operand" ""))
4958 (use (label_ref:DI (match_operand 1 "" "")))])]
4959 ""
4960 {
4961 if (TARGET_ABI_WINDOWS_NT)
4962 {
4963 rtx dest = gen_reg_rtx (DImode);
4964 emit_insn (gen_extendsidi2 (dest, operands[0]));
4965 operands[0] = dest;
4966 }
4967 else if (TARGET_ABI_OSF)
4968 {
4969 rtx dest = gen_reg_rtx (DImode);
4970 emit_insn (gen_extendsidi2 (dest, operands[0]));
4971 emit_insn (gen_adddi3 (dest, pic_offset_table_rtx, dest));
4972 operands[0] = dest;
4973 }
4974 })
4976 (define_insn "*tablejump_osf_nt_internal"
4977 [(set (pc)
4978 (match_operand:DI 0 "register_operand" "r"))
4979 (use (label_ref:DI (match_operand 1 "" "")))]
4980 "(TARGET_ABI_OSF || TARGET_ABI_WINDOWS_NT)
4981 && alpha_tablejump_addr_vec (insn)"
4982 {
4983 operands[2] = alpha_tablejump_best_label (insn);
4984 return "jmp $31,(%0),%2";
4985 }
4986 [(set_attr "type" "ibr")])
4988 (define_insn "*tablejump_internal"
4989 [(set (pc)
4990 (match_operand:DI 0 "register_operand" "r"))
4991 (use (label_ref (match_operand 1 "" "")))]
4992 ""
4993 "jmp $31,(%0),0"
4994 [(set_attr "type" "ibr")])
4996 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
4997 ;; want to have to include pal.h in our .s file.
4998 ;;
4999 ;; Technically the type for call_pal is jsr, but we use that for determining
5000 ;; if we need a GP. Use ibr instead since it has the same EV5 scheduling
5001 ;; characteristics.
5002 (define_insn "imb"
5003 [(unspec_volatile [(const_int 0)] UNSPECV_IMB)]
5004 ""
5005 "call_pal 0x86"
5006 [(set_attr "type" "callpal")])
5008 ;; BUGCHK is documented common to OSF/1 and VMS PALcode.
5009 ;; NT does not document anything at 0x81 -- presumably it would generate
5010 ;; the equivalent of SIGILL, but this isn't that important.
5011 ;; ??? Presuming unicosmk uses either OSF/1 or VMS PALcode.
5012 (define_insn "trap"
5013 [(trap_if (const_int 1) (const_int 0))]
5014 "!TARGET_ABI_WINDOWS_NT"
5015 "call_pal 0x81"
5016 [(set_attr "type" "callpal")])
5018 ;; For userland, we load the thread pointer from the TCB.
5019 ;; For the kernel, we load the per-cpu private value.
5021 (define_insn "load_tp"
5022 [(set (match_operand:DI 0 "register_operand" "=v")
5023 (unspec:DI [(const_int 0)] UNSPEC_TP))]
5024 "TARGET_ABI_OSF"
5025 {
5026 if (TARGET_TLS_KERNEL)
5027 return "call_pal 0x32";
5028 else
5029 return "call_pal 0x9e";
5030 }
5031 [(set_attr "type" "callpal")])
5033 ;; For completeness, and possibly a __builtin function, here's how to
5034 ;; set the thread pointer. Since we don't describe enough of this
5035 ;; quantity for CSE, we have to use a volatile unspec, and then there's
5036 ;; not much point in creating an R16_REG register class.
5038 (define_expand "set_tp"
5039 [(set (reg:DI 16) (match_operand:DI 0 "input_operand" ""))
5040 (unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
5041 "TARGET_ABI_OSF"
5042 "")
5044 (define_insn "*set_tp"
5045 [(unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
5046 "TARGET_ABI_OSF"
5047 {
5048 if (TARGET_TLS_KERNEL)
5049 return "call_pal 0x31";
5050 else
5051 return "call_pal 0x9f";
5052 }
5053 [(set_attr "type" "callpal")])
5054 \f
5055 ;; Finally, we have the basic data motion insns. The byte and word insns
5056 ;; are done via define_expand. Start with the floating-point insns, since
5057 ;; they are simpler.
5059 (define_insn "*movsf_nofix"
5060 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
5061 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
5062 "TARGET_FPREGS && ! TARGET_FIX
5063 && (register_operand (operands[0], SFmode)
5064 || reg_or_0_operand (operands[1], SFmode))"
5065 "@
5066 cpys %R1,%R1,%0
5067 ld%, %0,%1
5068 bis $31,%r1,%0
5069 ldl %0,%1
5070 st%, %R1,%0
5071 stl %r1,%0"
5072 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
5074 (define_insn "*movsf_fix"
5075 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
5076 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
5077 "TARGET_FPREGS && TARGET_FIX
5078 && (register_operand (operands[0], SFmode)
5079 || reg_or_0_operand (operands[1], SFmode))"
5080 "@
5081 cpys %R1,%R1,%0
5082 ld%, %0,%1
5083 bis $31,%r1,%0
5084 ldl %0,%1
5085 st%, %R1,%0
5086 stl %r1,%0
5087 itofs %1,%0
5088 ftois %1,%0"
5089 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
5091 (define_insn "*movsf_nofp"
5092 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
5093 (match_operand:SF 1 "input_operand" "rG,m,r"))]
5094 "! TARGET_FPREGS
5095 && (register_operand (operands[0], SFmode)
5096 || reg_or_0_operand (operands[1], SFmode))"
5097 "@
5098 bis $31,%r1,%0
5099 ldl %0,%1
5100 stl %r1,%0"
5101 [(set_attr "type" "ilog,ild,ist")])
5103 (define_insn "*movdf_nofix"
5104 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
5105 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
5106 "TARGET_FPREGS && ! TARGET_FIX
5107 && (register_operand (operands[0], DFmode)
5108 || reg_or_0_operand (operands[1], DFmode))"
5109 "@
5110 cpys %R1,%R1,%0
5111 ld%- %0,%1
5112 bis $31,%r1,%0
5113 ldq %0,%1
5114 st%- %R1,%0
5115 stq %r1,%0"
5116 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
5118 (define_insn "*movdf_fix"
5119 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
5120 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
5121 "TARGET_FPREGS && TARGET_FIX
5122 && (register_operand (operands[0], DFmode)
5123 || reg_or_0_operand (operands[1], DFmode))"
5124 "@
5125 cpys %R1,%R1,%0
5126 ld%- %0,%1
5127 bis $31,%r1,%0
5128 ldq %0,%1
5129 st%- %R1,%0
5130 stq %r1,%0
5131 itoft %1,%0
5132 ftoit %1,%0"
5133 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
5135 (define_insn "*movdf_nofp"
5136 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
5137 (match_operand:DF 1 "input_operand" "rG,m,r"))]
5138 "! TARGET_FPREGS
5139 && (register_operand (operands[0], DFmode)
5140 || reg_or_0_operand (operands[1], DFmode))"
5141 "@
5142 bis $31,%r1,%0
5143 ldq %0,%1
5144 stq %r1,%0"
5145 [(set_attr "type" "ilog,ild,ist")])
5147 ;; Subregs suck for register allocation. Pretend we can move TFmode
5148 ;; data between general registers until after reload.
5150 (define_insn_and_split "*movtf_internal"
5151 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
5152 (match_operand:TF 1 "input_operand" "roG,rG"))]
5153 "register_operand (operands[0], TFmode)
5154 || reg_or_0_operand (operands[1], TFmode)"
5155 "#"
5156 "reload_completed"
5157 [(set (match_dup 0) (match_dup 2))
5158 (set (match_dup 1) (match_dup 3))]
5159 {
5160 alpha_split_tfmode_pair (operands);
5161 if (reg_overlap_mentioned_p (operands[0], operands[3]))
5162 {
5163 rtx tmp;
5164 tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
5165 tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
5166 }
5167 })
5169 (define_expand "movsf"
5170 [(set (match_operand:SF 0 "nonimmediate_operand" "")
5171 (match_operand:SF 1 "general_operand" ""))]
5172 ""
5173 {
5174 if (GET_CODE (operands[0]) == MEM
5175 && ! reg_or_0_operand (operands[1], SFmode))
5176 operands[1] = force_reg (SFmode, operands[1]);
5177 })
5179 (define_expand "movdf"
5180 [(set (match_operand:DF 0 "nonimmediate_operand" "")
5181 (match_operand:DF 1 "general_operand" ""))]
5182 ""
5183 {
5184 if (GET_CODE (operands[0]) == MEM
5185 && ! reg_or_0_operand (operands[1], DFmode))
5186 operands[1] = force_reg (DFmode, operands[1]);
5187 })
5189 (define_expand "movtf"
5190 [(set (match_operand:TF 0 "nonimmediate_operand" "")
5191 (match_operand:TF 1 "general_operand" ""))]
5192 ""
5193 {
5194 if (GET_CODE (operands[0]) == MEM
5195 && ! reg_or_0_operand (operands[1], TFmode))
5196 operands[1] = force_reg (TFmode, operands[1]);
5197 })
5199 (define_insn "*movsi"
5200 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m")
5201 (match_operand:SI 1 "input_operand" "rJ,K,L,n,m,rJ"))]
5202 "(TARGET_ABI_OSF || TARGET_ABI_UNICOSMK)
5203 && (register_operand (operands[0], SImode)
5204 || reg_or_0_operand (operands[1], SImode))"
5205 "@
5206 bis $31,%r1,%0
5207 lda %0,%1($31)
5208 ldah %0,%h1($31)
5209 #
5210 ldl %0,%1
5211 stl %r1,%0"
5212 [(set_attr "type" "ilog,iadd,iadd,multi,ild,ist")])
5214 (define_insn "*movsi_nt_vms"
5215 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m")
5216 (match_operand:SI 1 "input_operand" "rJ,K,L,s,n,m,rJ"))]
5217 "(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS)
5218 && (register_operand (operands[0], SImode)
5219 || reg_or_0_operand (operands[1], SImode))"
5220 "@
5221 bis $31,%1,%0
5222 lda %0,%1
5223 ldah %0,%h1
5224 lda %0,%1
5225 #
5226 ldl %0,%1
5227 stl %r1,%0"
5228 [(set_attr "type" "ilog,iadd,iadd,ldsym,multi,ild,ist")])
5230 (define_insn "*movhi_nobwx"
5231 [(set (match_operand:HI 0 "register_operand" "=r,r")
5232 (match_operand:HI 1 "input_operand" "rJ,n"))]
5233 "! TARGET_BWX
5234 && (register_operand (operands[0], HImode)
5235 || register_operand (operands[1], HImode))"
5236 "@
5237 bis $31,%r1,%0
5238 lda %0,%L1($31)"
5239 [(set_attr "type" "ilog,iadd")])
5241 (define_insn "*movhi_bwx"
5242 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
5243 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
5244 "TARGET_BWX
5245 && (register_operand (operands[0], HImode)
5246 || reg_or_0_operand (operands[1], HImode))"
5247 "@
5248 bis $31,%r1,%0
5249 lda %0,%L1($31)
5250 ldwu %0,%1
5251 stw %r1,%0"
5252 [(set_attr "type" "ilog,iadd,ild,ist")])
5254 (define_insn "*movqi_nobwx"
5255 [(set (match_operand:QI 0 "register_operand" "=r,r")
5256 (match_operand:QI 1 "input_operand" "rJ,n"))]
5257 "! TARGET_BWX
5258 && (register_operand (operands[0], QImode)
5259 || register_operand (operands[1], QImode))"
5260 "@
5261 bis $31,%r1,%0
5262 lda %0,%L1($31)"
5263 [(set_attr "type" "ilog,iadd")])
5265 (define_insn "*movqi_bwx"
5266 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
5267 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
5268 "TARGET_BWX
5269 && (register_operand (operands[0], QImode)
5270 || reg_or_0_operand (operands[1], QImode))"
5271 "@
5272 bis $31,%r1,%0
5273 lda %0,%L1($31)
5274 ldbu %0,%1
5275 stb %r1,%0"
5276 [(set_attr "type" "ilog,iadd,ild,ist")])
5278 ;; We do two major things here: handle mem->mem and construct long
5279 ;; constants.
5281 (define_expand "movsi"
5282 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5283 (match_operand:SI 1 "general_operand" ""))]
5284 ""
5285 {
5286 if (alpha_expand_mov (SImode, operands))
5287 DONE;
5288 })
5290 ;; Split a load of a large constant into the appropriate two-insn
5291 ;; sequence.
5293 (define_split
5294 [(set (match_operand:SI 0 "register_operand" "")
5295 (match_operand:SI 1 "non_add_const_operand" ""))]
5296 ""
5297 [(const_int 0)]
5298 {
5299 if (alpha_split_const_mov (SImode, operands))
5300 DONE;
5301 else
5302 FAIL;
5303 })
5305 ;; Split the load of an address into a four-insn sequence on Unicos/Mk.
5306 ;; Always generate a REG_EQUAL note for the last instruction to facilitate
5307 ;; optimizations. If the symbolic operand is a label_ref, generate REG_LABEL
5308 ;; notes and update LABEL_NUSES because this is not done automatically.
5309 ;; Labels may be incorrectly deleted if we don't do this.
5310 ;;
5311 ;; Describing what the individual instructions do correctly is too complicated
5312 ;; so use UNSPECs for each of the three parts of an address.
5314 (define_split
5315 [(set (match_operand:DI 0 "register_operand" "")
5316 (match_operand:DI 1 "symbolic_operand" ""))]
5317 "TARGET_ABI_UNICOSMK && reload_completed"
5318 [(const_int 0)]
5319 {
5320 rtx insn1, insn2, insn3;
5322 insn1 = emit_insn (gen_umk_laum (operands[0], operands[1]));
5323 emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
5324 insn2 = emit_insn (gen_umk_lalm (operands[0], operands[0], operands[1]));
5325 insn3 = emit_insn (gen_umk_lal (operands[0], operands[0], operands[1]));
5326 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1],
5327 REG_NOTES (insn3));
5328 if (GET_CODE (operands[1]) == LABEL_REF)
5329 {
5330 rtx label;
5332 label = XEXP (operands[1], 0);
5333 REG_NOTES (insn1) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5334 REG_NOTES (insn1));
5335 REG_NOTES (insn2) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5336 REG_NOTES (insn2));
5337 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5338 REG_NOTES (insn3));
5339 LABEL_NUSES (label) += 3;
5340 }
5341 DONE;
5342 })
5344 ;; Instructions for loading the three parts of an address on Unicos/Mk.
5346 (define_insn "umk_laum"
5347 [(set (match_operand:DI 0 "register_operand" "=r")
5348 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
5349 UNSPEC_UMK_LAUM))]
5350 "TARGET_ABI_UNICOSMK"
5351 "laum %r0,%t1($31)"
5352 [(set_attr "type" "iadd")])
5354 (define_insn "umk_lalm"
5355 [(set (match_operand:DI 0 "register_operand" "=r")
5356 (plus:DI (match_operand:DI 1 "register_operand" "r")
5357 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5358 UNSPEC_UMK_LALM)))]
5359 "TARGET_ABI_UNICOSMK"
5360 "lalm %r0,%t2(%r1)"
5361 [(set_attr "type" "iadd")])
5363 (define_insn "umk_lal"
5364 [(set (match_operand:DI 0 "register_operand" "=r")
5365 (plus:DI (match_operand:DI 1 "register_operand" "r")
5366 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5367 UNSPEC_UMK_LAL)))]
5368 "TARGET_ABI_UNICOSMK"
5369 "lal %r0,%t2(%r1)"
5370 [(set_attr "type" "iadd")])
5372 ;; Add a new call information word to the current function's list of CIWs
5373 ;; and load its index into $25. Doing it here ensures that the CIW will be
5374 ;; associated with the correct function even in the presence of inlining.
5376 (define_insn "*umk_load_ciw"
5377 [(set (reg:DI 25)
5378 (unspec:DI [(match_operand 0 "" "")] UNSPEC_UMK_LOAD_CIW))]
5379 "TARGET_ABI_UNICOSMK"
5380 {
5381 operands[0] = unicosmk_add_call_info_word (operands[0]);
5382 return "lda $25,%0";
5383 }
5384 [(set_attr "type" "iadd")])
5386 (define_insn "*movdi_er_low_l"
5387 [(set (match_operand:DI 0 "register_operand" "=r")
5388 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
5389 (match_operand:DI 2 "local_symbolic_operand" "")))]
5390 "TARGET_EXPLICIT_RELOCS"
5391 {
5392 if (true_regnum (operands[1]) == 29)
5393 return "lda %0,%2(%1)\t\t!gprel";
5394 else
5395 return "lda %0,%2(%1)\t\t!gprellow";
5396 }
5397 [(set_attr "usegp" "yes")])
5399 (define_split
5400 [(set (match_operand:DI 0 "register_operand" "")
5401 (match_operand:DI 1 "small_symbolic_operand" ""))]
5402 "TARGET_EXPLICIT_RELOCS && reload_completed"
5403 [(set (match_dup 0)
5404 (lo_sum:DI (match_dup 2) (match_dup 1)))]
5405 "operands[2] = pic_offset_table_rtx;")
5407 (define_split
5408 [(set (match_operand:DI 0 "register_operand" "")
5409 (match_operand:DI 1 "local_symbolic_operand" ""))]
5410 "TARGET_EXPLICIT_RELOCS && reload_completed"
5411 [(set (match_dup 0)
5412 (plus:DI (match_dup 2) (high:DI (match_dup 1))))
5413 (set (match_dup 0)
5414 (lo_sum:DI (match_dup 0) (match_dup 1)))]
5415 "operands[2] = pic_offset_table_rtx;")
5417 (define_split
5418 [(match_operand 0 "some_small_symbolic_operand" "")]
5419 ""
5420 [(match_dup 0)]
5421 "operands[0] = split_small_symbolic_operand (operands[0]);")
5423 ;; Accepts any symbolic, not just global, since function calls that
5424 ;; don't go via bsr still use !literal in hopes of linker relaxation.
5425 (define_insn "movdi_er_high_g"
5426 [(set (match_operand:DI 0 "register_operand" "=r")
5427 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5428 (match_operand:DI 2 "symbolic_operand" "")
5429 (match_operand 3 "const_int_operand" "")]
5430 UNSPEC_LITERAL))]
5431 "TARGET_EXPLICIT_RELOCS"
5432 {
5433 if (INTVAL (operands[3]) == 0)
5434 return "ldq %0,%2(%1)\t\t!literal";
5435 else
5436 return "ldq %0,%2(%1)\t\t!literal!%3";
5437 }
5438 [(set_attr "type" "ldsym")])
5440 (define_split
5441 [(set (match_operand:DI 0 "register_operand" "")
5442 (match_operand:DI 1 "global_symbolic_operand" ""))]
5443 "TARGET_EXPLICIT_RELOCS && reload_completed"
5444 [(set (match_dup 0)
5445 (unspec:DI [(match_dup 2)
5446 (match_dup 1)
5447 (const_int 0)] UNSPEC_LITERAL))]
5448 "operands[2] = pic_offset_table_rtx;")
5450 (define_insn "movdi_er_tlsgd"
5451 [(set (match_operand:DI 0 "register_operand" "=r")
5452 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5453 (match_operand:DI 2 "symbolic_operand" "")
5454 (match_operand 3 "const_int_operand" "")]
5455 UNSPEC_TLSGD))]
5456 "HAVE_AS_TLS"
5457 {
5458 if (INTVAL (operands[3]) == 0)
5459 return "lda %0,%2(%1)\t\t!tlsgd";
5460 else
5461 return "lda %0,%2(%1)\t\t!tlsgd!%3";
5462 })
5464 (define_insn "movdi_er_tlsldm"
5465 [(set (match_operand:DI 0 "register_operand" "=r")
5466 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5467 (match_operand 2 "const_int_operand" "")]
5468 UNSPEC_TLSLDM))]
5469 "HAVE_AS_TLS"
5470 {
5471 if (INTVAL (operands[2]) == 0)
5472 return "lda %0,%&(%1)\t\t!tlsldm";
5473 else
5474 return "lda %0,%&(%1)\t\t!tlsldm!%2";
5475 })
5477 (define_insn "*movdi_er_gotdtp"
5478 [(set (match_operand:DI 0 "register_operand" "=r")
5479 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5480 (match_operand:DI 2 "symbolic_operand" "")]
5481 UNSPEC_DTPREL))]
5482 "HAVE_AS_TLS"
5483 "ldq %0,%2(%1)\t\t!gotdtprel"
5484 [(set_attr "type" "ild")
5485 (set_attr "usegp" "yes")])
5487 (define_split
5488 [(set (match_operand:DI 0 "register_operand" "")
5489 (match_operand:DI 1 "gotdtp_symbolic_operand" ""))]
5490 "HAVE_AS_TLS && reload_completed"
5491 [(set (match_dup 0)
5492 (unspec:DI [(match_dup 2)
5493 (match_dup 1)] UNSPEC_DTPREL))]
5494 {
5495 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0);
5496 operands[2] = pic_offset_table_rtx;
5497 })
5499 (define_insn "*movdi_er_gottp"
5500 [(set (match_operand:DI 0 "register_operand" "=r")
5501 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5502 (match_operand:DI 2 "symbolic_operand" "")]
5503 UNSPEC_TPREL))]
5504 "HAVE_AS_TLS"
5505 "ldq %0,%2(%1)\t\t!gottprel"
5506 [(set_attr "type" "ild")
5507 (set_attr "usegp" "yes")])
5509 (define_split
5510 [(set (match_operand:DI 0 "register_operand" "")
5511 (match_operand:DI 1 "gottp_symbolic_operand" ""))]
5512 "HAVE_AS_TLS && reload_completed"
5513 [(set (match_dup 0)
5514 (unspec:DI [(match_dup 2)
5515 (match_dup 1)] UNSPEC_TPREL))]
5516 {
5517 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0);
5518 operands[2] = pic_offset_table_rtx;
5519 })
5521 (define_insn "*movdi_er_nofix"
5522 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,r,m,*f,*f,Q")
5523 (match_operand:DI 1 "input_operand" "rJ,K,L,T,s,n,m,rJ,*fJ,Q,*f"))]
5524 "TARGET_EXPLICIT_RELOCS && ! TARGET_FIX
5525 && (register_operand (operands[0], DImode)
5526 || reg_or_0_operand (operands[1], DImode))"
5527 "@
5528 mov %r1,%0
5529 lda %0,%1($31)
5530 ldah %0,%h1($31)
5531 #
5532 #
5533 #
5534 ldq%A1 %0,%1
5535 stq%A0 %r1,%0
5536 fmov %R1,%0
5537 ldt %0,%1
5538 stt %R1,%0"
5539 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,multi,ild,ist,fcpys,fld,fst")
5540 (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*,*")])
5542 ;; The 'U' constraint matches symbolic operands on Unicos/Mk. Those should
5543 ;; have been split up by the rules above but we shouldn't reject the
5544 ;; possibility of them getting through.
5546 (define_insn "*movdi_nofix"
5547 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,r,m,*f,*f,Q")
5548 (match_operand:DI 1 "input_operand" "rJ,K,L,U,s,n,m,rJ,*fJ,Q,*f"))]
5549 "! TARGET_FIX
5550 && (register_operand (operands[0], DImode)
5551 || reg_or_0_operand (operands[1], DImode))"
5552 "@
5553 bis $31,%r1,%0
5554 lda %0,%1($31)
5555 ldah %0,%h1($31)
5556 laum %0,%t1($31)\;sll %0,32,%0\;lalm %0,%t1(%0)\;lal %0,%t1(%0)
5557 lda %0,%1
5558 #
5559 ldq%A1 %0,%1
5560 stq%A0 %r1,%0
5561 cpys %R1,%R1,%0
5562 ldt %0,%1
5563 stt %R1,%0"
5564 [(set_attr "type" "ilog,iadd,iadd,ldsym,ldsym,multi,ild,ist,fcpys,fld,fst")
5565 (set_attr "length" "*,*,*,16,*,*,*,*,*,*,*")])
5567 (define_insn "*movdi_er_fix"
5568 [(set (match_operand:DI 0 "nonimmediate_operand"
5569 "=r,r,r,r,r,r,r, m, *f,*f, Q, r,*f")
5570 (match_operand:DI 1 "input_operand"
5571 "rJ,K,L,T,s,n,m,rJ,*fJ, Q,*f,*f, r"))]
5572 "TARGET_EXPLICIT_RELOCS && TARGET_FIX
5573 && (register_operand (operands[0], DImode)
5574 || reg_or_0_operand (operands[1], DImode))"
5575 "@
5576 mov %r1,%0
5577 lda %0,%1($31)
5578 ldah %0,%h1($31)
5579 #
5580 #
5581 #
5582 ldq%A1 %0,%1
5583 stq%A0 %r1,%0
5584 fmov %R1,%0
5585 ldt %0,%1
5586 stt %R1,%0
5587 ftoit %1,%0
5588 itoft %1,%0"
5589 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,multi,ild,ist,fcpys,fld,fst,ftoi,itof")
5590 (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*,*,*,*")])
5592 (define_insn "*movdi_fix"
5593 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q,r,*f")
5594 (match_operand:DI 1 "input_operand" "rJ,K,L,s,n,m,rJ,*fJ,Q,*f,*f,r"))]
5595 "! TARGET_EXPLICIT_RELOCS && TARGET_FIX
5596 && (register_operand (operands[0], DImode)
5597 || reg_or_0_operand (operands[1], DImode))"
5598 "@
5599 bis $31,%r1,%0
5600 lda %0,%1($31)
5601 ldah %0,%h1($31)
5602 lda %0,%1
5603 #
5604 ldq%A1 %0,%1
5605 stq%A0 %r1,%0
5606 cpys %R1,%R1,%0
5607 ldt %0,%1
5608 stt %R1,%0
5609 ftoit %1,%0
5610 itoft %1,%0"
5611 [(set_attr "type" "ilog,iadd,iadd,ldsym,multi,ild,ist,fcpys,fld,fst,ftoi,itof")])
5613 ;; VMS needs to set up "vms_base_regno" for unwinding. This move
5614 ;; often appears dead to the life analysis code, at which point we
5615 ;; die for emitting dead prologue instructions. Force this live.
5617 (define_insn "force_movdi"
5618 [(set (match_operand:DI 0 "register_operand" "=r")
5619 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")]
5620 UNSPECV_FORCE_MOV))]
5621 ""
5622 "mov %1,%0"
5623 [(set_attr "type" "ilog")])
5625 ;; We do three major things here: handle mem->mem, put 64-bit constants in
5626 ;; memory, and construct long 32-bit constants.
5628 (define_expand "movdi"
5629 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5630 (match_operand:DI 1 "general_operand" ""))]
5631 ""
5632 {
5633 if (alpha_expand_mov (DImode, operands))
5634 DONE;
5635 })
5637 ;; Split a load of a large constant into the appropriate two-insn
5638 ;; sequence.
5640 (define_split
5641 [(set (match_operand:DI 0 "register_operand" "")
5642 (match_operand:DI 1 "non_add_const_operand" ""))]
5643 ""
5644 [(const_int 0)]
5645 {
5646 if (alpha_split_const_mov (DImode, operands))
5647 DONE;
5648 else
5649 FAIL;
5650 })
5652 ;; These are the partial-word cases.
5653 ;;
5654 ;; First we have the code to load an aligned word. Operand 0 is the register
5655 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
5656 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
5657 ;; number of bits within the word that the value is. Operand 3 is an SImode
5658 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
5659 ;; same register. It is allowed to conflict with operand 1 as well.
5661 (define_expand "aligned_loadqi"
5662 [(set (match_operand:SI 3 "register_operand" "")
5663 (match_operand:SI 1 "memory_operand" ""))
5664 (set (match_operand:DI 0 "register_operand" "")
5665 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5666 (const_int 8)
5667 (match_operand:DI 2 "const_int_operand" "")))]
5669 ""
5670 "")
5672 (define_expand "aligned_loadhi"
5673 [(set (match_operand:SI 3 "register_operand" "")
5674 (match_operand:SI 1 "memory_operand" ""))
5675 (set (match_operand:DI 0 "register_operand" "")
5676 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5677 (const_int 16)
5678 (match_operand:DI 2 "const_int_operand" "")))]
5680 ""
5681 "")
5683 ;; Similar for unaligned loads, where we use the sequence from the
5684 ;; Alpha Architecture manual. We have to distinguish between little-endian
5685 ;; and big-endian systems as the sequences are different.
5686 ;;
5687 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where
5688 ;; operand 3 can overlap the input and output registers.
5690 (define_expand "unaligned_loadqi"
5691 [(use (match_operand:DI 0 "register_operand" ""))
5692 (use (match_operand:DI 1 "address_operand" ""))
5693 (use (match_operand:DI 2 "register_operand" ""))
5694 (use (match_operand:DI 3 "register_operand" ""))]
5695 ""
5696 {
5697 if (WORDS_BIG_ENDIAN)
5698 emit_insn (gen_unaligned_loadqi_be (operands[0], operands[1],
5699 operands[2], operands[3]));
5700 else
5701 emit_insn (gen_unaligned_loadqi_le (operands[0], operands[1],
5702 operands[2], operands[3]));
5703 DONE;
5704 })
5706 (define_expand "unaligned_loadqi_le"
5707 [(set (match_operand:DI 2 "register_operand" "")
5708 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5709 (const_int -8))))
5710 (set (match_operand:DI 3 "register_operand" "")
5711 (match_dup 1))
5712 (set (match_operand:DI 0 "register_operand" "")
5713 (zero_extract:DI (match_dup 2)
5714 (const_int 8)
5715 (ashift:DI (match_dup 3) (const_int 3))))]
5716 "! WORDS_BIG_ENDIAN"
5717 "")
5719 (define_expand "unaligned_loadqi_be"
5720 [(set (match_operand:DI 2 "register_operand" "")
5721 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5722 (const_int -8))))
5723 (set (match_operand:DI 3 "register_operand" "")
5724 (match_dup 1))
5725 (set (match_operand:DI 0 "register_operand" "")
5726 (zero_extract:DI (match_dup 2)
5727 (const_int 8)
5728 (minus:DI
5729 (const_int 56)
5730 (ashift:DI (match_dup 3) (const_int 3)))))]
5731 "WORDS_BIG_ENDIAN"
5732 "")
5734 (define_expand "unaligned_loadhi"
5735 [(use (match_operand:DI 0 "register_operand" ""))
5736 (use (match_operand:DI 1 "address_operand" ""))
5737 (use (match_operand:DI 2 "register_operand" ""))
5738 (use (match_operand:DI 3 "register_operand" ""))]
5739 ""
5740 {
5741 if (WORDS_BIG_ENDIAN)
5742 emit_insn (gen_unaligned_loadhi_be (operands[0], operands[1],
5743 operands[2], operands[3]));
5744 else
5745 emit_insn (gen_unaligned_loadhi_le (operands[0], operands[1],
5746 operands[2], operands[3]));
5747 DONE;
5748 })
5750 (define_expand "unaligned_loadhi_le"
5751 [(set (match_operand:DI 2 "register_operand" "")
5752 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5753 (const_int -8))))
5754 (set (match_operand:DI 3 "register_operand" "")
5755 (match_dup 1))
5756 (set (match_operand:DI 0 "register_operand" "")
5757 (zero_extract:DI (match_dup 2)
5758 (const_int 16)
5759 (ashift:DI (match_dup 3) (const_int 3))))]
5760 "! WORDS_BIG_ENDIAN"
5761 "")
5763 (define_expand "unaligned_loadhi_be"
5764 [(set (match_operand:DI 2 "register_operand" "")
5765 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5766 (const_int -8))))
5767 (set (match_operand:DI 3 "register_operand" "")
5768 (plus:DI (match_dup 1) (const_int 1)))
5769 (set (match_operand:DI 0 "register_operand" "")
5770 (zero_extract:DI (match_dup 2)
5771 (const_int 16)
5772 (minus:DI
5773 (const_int 56)
5774 (ashift:DI (match_dup 3) (const_int 3)))))]
5775 "WORDS_BIG_ENDIAN"
5776 "")
5778 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
5779 ;; aligned SImode MEM. Operand 1 is the register containing the
5780 ;; byte or word to store. Operand 2 is the number of bits within the word that
5781 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
5783 (define_expand "aligned_store"
5784 [(set (match_operand:SI 3 "register_operand" "")
5785 (match_operand:SI 0 "memory_operand" ""))
5786 (set (subreg:DI (match_dup 3) 0)
5787 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
5788 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
5789 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
5790 (match_operand:DI 2 "const_int_operand" "")))
5791 (set (subreg:DI (match_dup 4) 0)
5792 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
5793 (set (match_dup 0) (match_dup 4))]
5794 ""
5795 {
5796 operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
5797 << INTVAL (operands[2])));
5798 })
5800 ;; For the unaligned byte and halfword cases, we use code similar to that
5801 ;; in the ;; Architecture book, but reordered to lower the number of registers
5802 ;; required. Operand 0 is the address. Operand 1 is the data to store.
5803 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
5804 ;; be the same temporary, if desired. If the address is in a register,
5805 ;; operand 2 can be that register.
5807 (define_expand "unaligned_storeqi"
5808 [(use (match_operand:DI 0 "address_operand" ""))
5809 (use (match_operand:QI 1 "register_operand" ""))
5810 (use (match_operand:DI 2 "register_operand" ""))
5811 (use (match_operand:DI 3 "register_operand" ""))
5812 (use (match_operand:DI 4 "register_operand" ""))]
5813 ""
5814 {
5815 if (WORDS_BIG_ENDIAN)
5816 emit_insn (gen_unaligned_storeqi_be (operands[0], operands[1],
5817 operands[2], operands[3],
5818 operands[4]));
5819 else
5820 emit_insn (gen_unaligned_storeqi_le (operands[0], operands[1],
5821 operands[2], operands[3],
5822 operands[4]));
5823 DONE;
5824 })
5826 (define_expand "unaligned_storeqi_le"
5827 [(set (match_operand:DI 3 "register_operand" "")
5828 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5829 (const_int -8))))
5830 (set (match_operand:DI 2 "register_operand" "")
5831 (match_dup 0))
5832 (set (match_dup 3)
5833 (and:DI (not:DI (ashift:DI (const_int 255)
5834 (ashift:DI (match_dup 2) (const_int 3))))
5835 (match_dup 3)))
5836 (set (match_operand:DI 4 "register_operand" "")
5837 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5838 (ashift:DI (match_dup 2) (const_int 3))))
5839 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5840 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5841 (match_dup 4))]
5842 "! WORDS_BIG_ENDIAN"
5843 "")
5845 (define_expand "unaligned_storeqi_be"
5846 [(set (match_operand:DI 3 "register_operand" "")
5847 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5848 (const_int -8))))
5849 (set (match_operand:DI 2 "register_operand" "")
5850 (match_dup 0))
5851 (set (match_dup 3)
5852 (and:DI (not:DI (ashift:DI (const_int 255)
5853 (minus:DI (const_int 56)
5854 (ashift:DI (match_dup 2) (const_int 3)))))
5855 (match_dup 3)))
5856 (set (match_operand:DI 4 "register_operand" "")
5857 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5858 (minus:DI (const_int 56)
5859 (ashift:DI (match_dup 2) (const_int 3)))))
5860 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5861 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5862 (match_dup 4))]
5863 "WORDS_BIG_ENDIAN"
5864 "")
5866 (define_expand "unaligned_storehi"
5867 [(use (match_operand:DI 0 "address_operand" ""))
5868 (use (match_operand:HI 1 "register_operand" ""))
5869 (use (match_operand:DI 2 "register_operand" ""))
5870 (use (match_operand:DI 3 "register_operand" ""))
5871 (use (match_operand:DI 4 "register_operand" ""))]
5872 ""
5873 {
5874 if (WORDS_BIG_ENDIAN)
5875 emit_insn (gen_unaligned_storehi_be (operands[0], operands[1],
5876 operands[2], operands[3],
5877 operands[4]));
5878 else
5879 emit_insn (gen_unaligned_storehi_le (operands[0], operands[1],
5880 operands[2], operands[3],
5881 operands[4]));
5882 DONE;
5883 })
5885 (define_expand "unaligned_storehi_le"
5886 [(set (match_operand:DI 3 "register_operand" "")
5887 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5888 (const_int -8))))
5889 (set (match_operand:DI 2 "register_operand" "")
5890 (match_dup 0))
5891 (set (match_dup 3)
5892 (and:DI (not:DI (ashift:DI (const_int 65535)
5893 (ashift:DI (match_dup 2) (const_int 3))))
5894 (match_dup 3)))
5895 (set (match_operand:DI 4 "register_operand" "")
5896 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5897 (ashift:DI (match_dup 2) (const_int 3))))
5898 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5899 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5900 (match_dup 4))]
5901 "! WORDS_BIG_ENDIAN"
5902 "")
5904 (define_expand "unaligned_storehi_be"
5905 [(set (match_operand:DI 3 "register_operand" "")
5906 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5907 (const_int -8))))
5908 (set (match_operand:DI 2 "register_operand" "")
5909 (plus:DI (match_dup 0) (const_int 1)))
5910 (set (match_dup 3)
5911 (and:DI (not:DI (ashift:DI
5912 (const_int 65535)
5913 (minus:DI (const_int 56)
5914 (ashift:DI (match_dup 2) (const_int 3)))))
5915 (match_dup 3)))
5916 (set (match_operand:DI 4 "register_operand" "")
5917 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5918 (minus:DI (const_int 56)
5919 (ashift:DI (match_dup 2) (const_int 3)))))
5920 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5921 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5922 (match_dup 4))]
5923 "WORDS_BIG_ENDIAN"
5924 "")
5925 \f
5926 ;; Here are the define_expand's for QI and HI moves that use the above
5927 ;; patterns. We have the normal sets, plus the ones that need scratch
5928 ;; registers for reload.
5930 (define_expand "movqi"
5931 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5932 (match_operand:QI 1 "general_operand" ""))]
5933 ""
5934 {
5935 if (TARGET_BWX
5936 ? alpha_expand_mov (QImode, operands)
5937 : alpha_expand_mov_nobwx (QImode, operands))
5938 DONE;
5939 })
5941 (define_expand "movhi"
5942 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5943 (match_operand:HI 1 "general_operand" ""))]
5944 ""
5945 {
5946 if (TARGET_BWX
5947 ? alpha_expand_mov (HImode, operands)
5948 : alpha_expand_mov_nobwx (HImode, operands))
5949 DONE;
5950 })
5952 ;; Here are the versions for reload. Note that in the unaligned cases
5953 ;; we know that the operand must not be a pseudo-register because stack
5954 ;; slots are always aligned references.
5956 (define_expand "reload_inqi"
5957 [(parallel [(match_operand:QI 0 "register_operand" "=r")
5958 (match_operand:QI 1 "any_memory_operand" "m")
5959 (match_operand:TI 2 "register_operand" "=&r")])]
5960 "! TARGET_BWX"
5961 {
5962 rtx scratch, seq;
5964 if (aligned_memory_operand (operands[1], QImode))
5965 {
5966 seq = gen_reload_inqi_help (operands[0], operands[1],
5967 gen_rtx_REG (SImode, REGNO (operands[2])));
5968 }
5969 else
5970 {
5971 rtx addr;
5973 /* It is possible that one of the registers we got for operands[2]
5974 might coincide with that of operands[0] (which is why we made
5975 it TImode). Pick the other one to use as our scratch. */
5976 if (REGNO (operands[0]) == REGNO (operands[2]))
5977 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5978 else
5979 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5981 addr = get_unaligned_address (operands[1]);
5982 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
5983 seq = gen_unaligned_loadqi (operands[0], addr, scratch, operands[0]);
5984 alpha_set_memflags (seq, operands[1]);
5985 }
5986 emit_insn (seq);
5987 DONE;
5988 })
5990 (define_expand "reload_inhi"
5991 [(parallel [(match_operand:HI 0 "register_operand" "=r")
5992 (match_operand:HI 1 "any_memory_operand" "m")
5993 (match_operand:TI 2 "register_operand" "=&r")])]
5994 "! TARGET_BWX"
5995 {
5996 rtx scratch, seq;
5998 if (aligned_memory_operand (operands[1], HImode))
5999 {
6000 seq = gen_reload_inhi_help (operands[0], operands[1],
6001 gen_rtx_REG (SImode, REGNO (operands[2])));
6002 }
6003 else
6004 {
6005 rtx addr;
6007 /* It is possible that one of the registers we got for operands[2]
6008 might coincide with that of operands[0] (which is why we made
6009 it TImode). Pick the other one to use as our scratch. */
6010 if (REGNO (operands[0]) == REGNO (operands[2]))
6011 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6012 else
6013 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
6015 addr = get_unaligned_address (operands[1]);
6016 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
6017 seq = gen_unaligned_loadhi (operands[0], addr, scratch, operands[0]);
6018 alpha_set_memflags (seq, operands[1]);
6019 }
6020 emit_insn (seq);
6021 DONE;
6022 })
6024 (define_expand "reload_outqi"
6025 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
6026 (match_operand:QI 1 "register_operand" "r")
6027 (match_operand:TI 2 "register_operand" "=&r")])]
6028 "! TARGET_BWX"
6029 {
6030 if (aligned_memory_operand (operands[0], QImode))
6031 {
6032 emit_insn (gen_reload_outqi_help
6033 (operands[0], operands[1],
6034 gen_rtx_REG (SImode, REGNO (operands[2])),
6035 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
6036 }
6037 else
6038 {
6039 rtx addr = get_unaligned_address (operands[0]);
6040 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
6041 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6042 rtx scratch3 = scratch1;
6043 rtx seq;
6045 if (GET_CODE (addr) == REG)
6046 scratch1 = addr;
6048 seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
6049 scratch2, scratch3);
6050 alpha_set_memflags (seq, operands[0]);
6051 emit_insn (seq);
6052 }
6053 DONE;
6054 })
6056 (define_expand "reload_outhi"
6057 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
6058 (match_operand:HI 1 "register_operand" "r")
6059 (match_operand:TI 2 "register_operand" "=&r")])]
6060 "! TARGET_BWX"
6061 {
6062 if (aligned_memory_operand (operands[0], HImode))
6063 {
6064 emit_insn (gen_reload_outhi_help
6065 (operands[0], operands[1],
6066 gen_rtx_REG (SImode, REGNO (operands[2])),
6067 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
6068 }
6069 else
6070 {
6071 rtx addr = get_unaligned_address (operands[0]);
6072 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
6073 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6074 rtx scratch3 = scratch1;
6075 rtx seq;
6077 if (GET_CODE (addr) == REG)
6078 scratch1 = addr;
6080 seq = gen_unaligned_storehi (addr, operands[1], scratch1,
6081 scratch2, scratch3);
6082 alpha_set_memflags (seq, operands[0]);
6083 emit_insn (seq);
6084 }
6085 DONE;
6086 })
6088 ;; Helpers for the above. The way reload is structured, we can't
6089 ;; always get a proper address for a stack slot during reload_foo
6090 ;; expansion, so we must delay our address manipulations until after.
6092 (define_insn_and_split "reload_inqi_help"
6093 [(set (match_operand:QI 0 "register_operand" "=r")
6094 (match_operand:QI 1 "memory_operand" "m"))
6095 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6096 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6097 "#"
6098 "! TARGET_BWX && reload_completed"
6099 [(const_int 0)]
6100 {
6101 rtx aligned_mem, bitnum;
6102 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6103 operands[0] = gen_lowpart (DImode, operands[0]);
6104 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
6105 operands[2]));
6106 DONE;
6107 })
6109 (define_insn_and_split "reload_inhi_help"
6110 [(set (match_operand:HI 0 "register_operand" "=r")
6111 (match_operand:HI 1 "memory_operand" "m"))
6112 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6113 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6114 "#"
6115 "! TARGET_BWX && reload_completed"
6116 [(const_int 0)]
6117 {
6118 rtx aligned_mem, bitnum;
6119 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6120 operands[0] = gen_lowpart (DImode, operands[0]);
6121 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
6122 operands[2]));
6123 DONE;
6124 })
6126 (define_insn_and_split "reload_outqi_help"
6127 [(set (match_operand:QI 0 "memory_operand" "=m")
6128 (match_operand:QI 1 "register_operand" "r"))
6129 (clobber (match_operand:SI 2 "register_operand" "=r"))
6130 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6131 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6132 "#"
6133 "! TARGET_BWX && reload_completed"
6134 [(const_int 0)]
6135 {
6136 rtx aligned_mem, bitnum;
6137 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6138 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6139 operands[2], operands[3]));
6140 DONE;
6141 })
6143 (define_insn_and_split "reload_outhi_help"
6144 [(set (match_operand:HI 0 "memory_operand" "=m")
6145 (match_operand:HI 1 "register_operand" "r"))
6146 (clobber (match_operand:SI 2 "register_operand" "=r"))
6147 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6148 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6149 "#"
6150 "! TARGET_BWX && reload_completed"
6151 [(const_int 0)]
6152 {
6153 rtx aligned_mem, bitnum;
6154 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6155 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6156 operands[2], operands[3]));
6157 DONE;
6158 })
6159 \f
6160 ;; Vector operations
6162 (define_mode_macro VEC [V8QI V4HI V2SI])
6164 (define_expand "mov<mode>"
6165 [(set (match_operand:VEC 0 "nonimmediate_operand" "")
6166 (match_operand:VEC 1 "general_operand" ""))]
6167 ""
6168 {
6169 if (alpha_expand_mov (<MODE>mode, operands))
6170 DONE;
6171 })
6173 (define_split
6174 [(set (match_operand:VEC 0 "register_operand" "")
6175 (match_operand:VEC 1 "non_zero_const_operand" ""))]
6176 ""
6177 [(const_int 0)]
6178 {
6179 if (alpha_split_const_mov (<MODE>mode, operands))
6180 DONE;
6181 else
6182 FAIL;
6183 })
6186 (define_expand "movmisalign<mode>"
6187 [(set (match_operand:VEC 0 "nonimmediate_operand" "")
6188 (match_operand:VEC 1 "general_operand" ""))]
6189 ""
6190 {
6191 alpha_expand_movmisalign (<MODE>mode, operands);
6192 DONE;
6193 })
6195 (define_insn "*mov<mode>_fix"
6196 [(set (match_operand:VEC 0 "nonimmediate_operand" "=r,r,r,m,*f,*f,m,r,*f")
6197 (match_operand:VEC 1 "input_operand" "rW,i,m,rW,*fW,m,*f,*f,r"))]
6198 "TARGET_FIX
6199 && (register_operand (operands[0], <MODE>mode)
6200 || reg_or_0_operand (operands[1], <MODE>mode))"
6201 "@
6202 bis $31,%r1,%0
6203 #
6204 ldq %0,%1
6205 stq %r1,%0
6206 cpys %R1,%R1,%0
6207 ldt %0,%1
6208 stt %R1,%0
6209 ftoit %1,%0
6210 itoft %1,%0"
6211 [(set_attr "type" "ilog,multi,ild,ist,fcpys,fld,fst,ftoi,itof")])
6213 (define_insn "*mov<mode>_nofix"
6214 [(set (match_operand:VEC 0 "nonimmediate_operand" "=r,r,r,m,*f,*f,m")
6215 (match_operand:VEC 1 "input_operand" "rW,i,m,rW,*fW,m,*f"))]
6216 "! TARGET_FIX
6217 && (register_operand (operands[0], <MODE>mode)
6218 || reg_or_0_operand (operands[1], <MODE>mode))"
6219 "@
6220 bis $31,%r1,%0
6221 #
6222 ldq %0,%1
6223 stq %r1,%0
6224 cpys %R1,%R1,%0
6225 ldt %0,%1
6226 stt %R1,%0"
6227 [(set_attr "type" "ilog,multi,ild,ist,fcpys,fld,fst")])
6229 (define_insn "uminv8qi3"
6230 [(set (match_operand:V8QI 0 "register_operand" "=r")
6231 (umin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6232 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6233 "TARGET_MAX"
6234 "minub8 %r1,%r2,%0"
6235 [(set_attr "type" "mvi")])
6237 (define_insn "sminv8qi3"
6238 [(set (match_operand:V8QI 0 "register_operand" "=r")
6239 (smin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6240 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6241 "TARGET_MAX"
6242 "minsb8 %r1,%r2,%0"
6243 [(set_attr "type" "mvi")])
6245 (define_insn "uminv4hi3"
6246 [(set (match_operand:V4HI 0 "register_operand" "=r")
6247 (umin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6248 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6249 "TARGET_MAX"
6250 "minuw4 %r1,%r2,%0"
6251 [(set_attr "type" "mvi")])
6253 (define_insn "sminv4hi3"
6254 [(set (match_operand:V4HI 0 "register_operand" "=r")
6255 (smin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6256 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6257 "TARGET_MAX"
6258 "minsw4 %r1,%r2,%0"
6259 [(set_attr "type" "mvi")])
6261 (define_insn "umaxv8qi3"
6262 [(set (match_operand:V8QI 0 "register_operand" "=r")
6263 (umax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6264 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6265 "TARGET_MAX"
6266 "maxub8 %r1,%r2,%0"
6267 [(set_attr "type" "mvi")])
6269 (define_insn "smaxv8qi3"
6270 [(set (match_operand:V8QI 0 "register_operand" "=r")
6271 (smax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6272 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6273 "TARGET_MAX"
6274 "maxsb8 %r1,%r2,%0"
6275 [(set_attr "type" "mvi")])
6277 (define_insn "umaxv4hi3"
6278 [(set (match_operand:V4HI 0 "register_operand" "=r")
6279 (umax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6280 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6281 "TARGET_MAX"
6282 "maxuw4 %r1,%r2,%0"
6283 [(set_attr "type" "mvi")])
6285 (define_insn "smaxv4hi3"
6286 [(set (match_operand:V4HI 0 "register_operand" "=r")
6287 (smax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6288 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6289 "TARGET_MAX"
6290 "maxsw4 %r1,%r2,%0"
6291 [(set_attr "type" "mvi")])
6293 (define_insn "one_cmpl<mode>2"
6294 [(set (match_operand:VEC 0 "register_operand" "=r")
6295 (not:VEC (match_operand:VEC 1 "register_operand" "r")))]
6296 ""
6297 "ornot $31,%1,%0"
6298 [(set_attr "type" "ilog")])
6300 (define_insn "and<mode>3"
6301 [(set (match_operand:VEC 0 "register_operand" "=r")
6302 (and:VEC (match_operand:VEC 1 "register_operand" "r")
6303 (match_operand:VEC 2 "register_operand" "r")))]
6304 ""
6305 "and %1,%2,%0"
6306 [(set_attr "type" "ilog")])
6308 (define_insn "*andnot<mode>3"
6309 [(set (match_operand:VEC 0 "register_operand" "=r")
6310 (and:VEC (not:VEC (match_operand:VEC 1 "register_operand" "r"))
6311 (match_operand:VEC 2 "register_operand" "r")))]
6312 ""
6313 "bic %2,%1,%0"
6314 [(set_attr "type" "ilog")])
6316 (define_insn "ior<mode>3"
6317 [(set (match_operand:VEC 0 "register_operand" "=r")
6318 (ior:VEC (match_operand:VEC 1 "register_operand" "r")
6319 (match_operand:VEC 2 "register_operand" "r")))]
6320 ""
6321 "bis %1,%2,%0"
6322 [(set_attr "type" "ilog")])
6324 (define_insn "*iornot<mode>3"
6325 [(set (match_operand:VEC 0 "register_operand" "=r")
6326 (ior:VEC (not:DI (match_operand:VEC 1 "register_operand" "r"))
6327 (match_operand:VEC 2 "register_operand" "r")))]
6328 ""
6329 "ornot %2,%1,%0"
6330 [(set_attr "type" "ilog")])
6332 (define_insn "xor<mode>3"
6333 [(set (match_operand:VEC 0 "register_operand" "=r")
6334 (xor:VEC (match_operand:VEC 1 "register_operand" "r")
6335 (match_operand:VEC 2 "register_operand" "r")))]
6336 ""
6337 "xor %1,%2,%0"
6338 [(set_attr "type" "ilog")])
6340 (define_insn "*xornot<mode>3"
6341 [(set (match_operand:VEC 0 "register_operand" "=r")
6342 (not:VEC (xor:VEC (match_operand:VEC 1 "register_operand" "r")
6343 (match_operand:VEC 2 "register_operand" "r"))))]
6344 ""
6345 "eqv %1,%2,%0"
6346 [(set_attr "type" "ilog")])
6348 (define_expand "vec_shl_<mode>"
6349 [(set (match_operand:VEC 0 "register_operand" "")
6350 (ashift:DI (match_operand:VEC 1 "register_operand" "")
6351 (match_operand:DI 2 "reg_or_6bit_operand" "")))]
6352 ""
6353 {
6354 operands[0] = gen_lowpart (DImode, operands[0]);
6355 operands[1] = gen_lowpart (DImode, operands[1]);
6356 })
6358 (define_expand "vec_shr_<mode>"
6359 [(set (match_operand:VEC 0 "register_operand" "")
6360 (lshiftrt:DI (match_operand:VEC 1 "register_operand" "")
6361 (match_operand:DI 2 "reg_or_6bit_operand" "")))]
6362 ""
6363 {
6364 operands[0] = gen_lowpart (DImode, operands[0]);
6365 operands[1] = gen_lowpart (DImode, operands[1]);
6366 })
6367 \f
6368 ;; Bit field extract patterns which use ext[wlq][lh]
6370 (define_expand "extv"
6371 [(set (match_operand:DI 0 "register_operand" "")
6372 (sign_extract:DI (match_operand:QI 1 "memory_operand" "")
6373 (match_operand:DI 2 "immediate_operand" "")
6374 (match_operand:DI 3 "immediate_operand" "")))]
6375 ""
6376 {
6377 int ofs;
6379 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6380 if (INTVAL (operands[3]) % 8 != 0
6381 || (INTVAL (operands[2]) != 16
6382 && INTVAL (operands[2]) != 32
6383 && INTVAL (operands[2]) != 64))
6384 FAIL;
6386 /* From mips.md: extract_bit_field doesn't verify that our source
6387 matches the predicate, so we force it to be a MEM here. */
6388 if (GET_CODE (operands[1]) != MEM)
6389 FAIL;
6391 /* The bit number is relative to the mode of operand 1 which is
6392 usually QImode (this might actually be a bug in expmed.c). Note
6393 that the bit number is negative in big-endian mode in this case.
6394 We have to convert that to the offset. */
6395 if (WORDS_BIG_ENDIAN)
6396 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6397 - INTVAL (operands[2]) - INTVAL (operands[3]);
6398 else
6399 ofs = INTVAL (operands[3]);
6401 ofs = ofs / 8;
6403 alpha_expand_unaligned_load (operands[0], operands[1],
6404 INTVAL (operands[2]) / 8,
6405 ofs, 1);
6406 DONE;
6407 })
6409 (define_expand "extzv"
6410 [(set (match_operand:DI 0 "register_operand" "")
6411 (zero_extract:DI (match_operand:DI 1 "nonimmediate_operand" "")
6412 (match_operand:DI 2 "immediate_operand" "")
6413 (match_operand:DI 3 "immediate_operand" "")))]
6414 ""
6415 {
6416 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6417 if (INTVAL (operands[3]) % 8 != 0
6418 || (INTVAL (operands[2]) != 8
6419 && INTVAL (operands[2]) != 16
6420 && INTVAL (operands[2]) != 32
6421 && INTVAL (operands[2]) != 64))
6422 FAIL;
6424 if (GET_CODE (operands[1]) == MEM)
6425 {
6426 int ofs;
6428 /* Fail 8 bit fields, falling back on a simple byte load. */
6429 if (INTVAL (operands[2]) == 8)
6430 FAIL;
6432 /* The bit number is relative to the mode of operand 1 which is
6433 usually QImode (this might actually be a bug in expmed.c). Note
6434 that the bit number is negative in big-endian mode in this case.
6435 We have to convert that to the offset. */
6436 if (WORDS_BIG_ENDIAN)
6437 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6438 - INTVAL (operands[2]) - INTVAL (operands[3]);
6439 else
6440 ofs = INTVAL (operands[3]);
6442 ofs = ofs / 8;
6444 alpha_expand_unaligned_load (operands[0], operands[1],
6445 INTVAL (operands[2]) / 8,
6446 ofs, 0);
6447 DONE;
6448 }
6449 })
6451 (define_expand "insv"
6452 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
6453 (match_operand:DI 1 "immediate_operand" "")
6454 (match_operand:DI 2 "immediate_operand" ""))
6455 (match_operand:DI 3 "register_operand" ""))]
6456 ""
6457 {
6458 int ofs;
6460 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6461 if (INTVAL (operands[2]) % 8 != 0
6462 || (INTVAL (operands[1]) != 16
6463 && INTVAL (operands[1]) != 32
6464 && INTVAL (operands[1]) != 64))
6465 FAIL;
6467 /* From mips.md: store_bit_field doesn't verify that our source
6468 matches the predicate, so we force it to be a MEM here. */
6469 if (GET_CODE (operands[0]) != MEM)
6470 FAIL;
6472 /* The bit number is relative to the mode of operand 1 which is
6473 usually QImode (this might actually be a bug in expmed.c). Note
6474 that the bit number is negative in big-endian mode in this case.
6475 We have to convert that to the offset. */
6476 if (WORDS_BIG_ENDIAN)
6477 ofs = GET_MODE_BITSIZE (GET_MODE (operands[0]))
6478 - INTVAL (operands[1]) - INTVAL (operands[2]);
6479 else
6480 ofs = INTVAL (operands[2]);
6482 ofs = ofs / 8;
6484 alpha_expand_unaligned_store (operands[0], operands[3],
6485 INTVAL (operands[1]) / 8, ofs);
6486 DONE;
6487 })
6489 ;; Block move/clear, see alpha.c for more details.
6490 ;; Argument 0 is the destination
6491 ;; Argument 1 is the source
6492 ;; Argument 2 is the length
6493 ;; Argument 3 is the alignment
6495 (define_expand "movmemqi"
6496 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6497 (match_operand:BLK 1 "memory_operand" ""))
6498 (use (match_operand:DI 2 "immediate_operand" ""))
6499 (use (match_operand:DI 3 "immediate_operand" ""))])]
6500 ""
6501 {
6502 if (alpha_expand_block_move (operands))
6503 DONE;
6504 else
6505 FAIL;
6506 })
6508 (define_expand "movmemdi"
6509 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6510 (match_operand:BLK 1 "memory_operand" ""))
6511 (use (match_operand:DI 2 "immediate_operand" ""))
6512 (use (match_operand:DI 3 "immediate_operand" ""))
6513 (use (match_dup 4))
6514 (clobber (reg:DI 25))
6515 (clobber (reg:DI 16))
6516 (clobber (reg:DI 17))
6517 (clobber (reg:DI 18))
6518 (clobber (reg:DI 19))
6519 (clobber (reg:DI 20))
6520 (clobber (reg:DI 26))
6521 (clobber (reg:DI 27))])]
6522 "TARGET_ABI_OPEN_VMS"
6523 {
6524 operands[4] = gen_rtx_SYMBOL_REF (Pmode, "OTS$MOVE");
6525 alpha_need_linkage (XSTR (operands[4], 0), 0);
6526 })
6528 (define_insn "*movmemdi_1"
6529 [(set (match_operand:BLK 0 "memory_operand" "=m,=m")
6530 (match_operand:BLK 1 "memory_operand" "m,m"))
6531 (use (match_operand:DI 2 "nonmemory_operand" "r,i"))
6532 (use (match_operand:DI 3 "immediate_operand" ""))
6533 (use (match_operand:DI 4 "call_operand" "i,i"))
6534 (clobber (reg:DI 25))
6535 (clobber (reg:DI 16))
6536 (clobber (reg:DI 17))
6537 (clobber (reg:DI 18))
6538 (clobber (reg:DI 19))
6539 (clobber (reg:DI 20))
6540 (clobber (reg:DI 26))
6541 (clobber (reg:DI 27))]
6542 "TARGET_ABI_OPEN_VMS"
6543 {
6544 operands [5] = alpha_use_linkage (operands [4], cfun->decl, 0, 1);
6545 switch (which_alternative)
6546 {
6547 case 0:
6548 return "lda $16,%0\;bis $31,%2,$17\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)";
6549 case 1:
6550 return "lda $16,%0\;lda $17,%2($31)\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)";
6551 default:
6552 gcc_unreachable ();
6553 }
6554 }
6555 [(set_attr "type" "multi")
6556 (set_attr "length" "28")])
6558 (define_expand "setmemqi"
6559 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6560 (match_operand 2 "const_int_operand" ""))
6561 (use (match_operand:DI 1 "immediate_operand" ""))
6562 (use (match_operand:DI 3 "immediate_operand" ""))])]
6563 ""
6564 {
6565 /* If value to set is not zero, use the library routine. */
6566 if (operands[2] != const0_rtx)
6567 FAIL;
6569 if (alpha_expand_block_clear (operands))
6570 DONE;
6571 else
6572 FAIL;
6573 })
6575 (define_expand "setmemdi"
6576 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6577 (match_operand 2 "const_int_operand" ""))
6578 (use (match_operand:DI 1 "immediate_operand" ""))
6579 (use (match_operand:DI 3 "immediate_operand" ""))
6580 (use (match_dup 4))
6581 (clobber (reg:DI 25))
6582 (clobber (reg:DI 16))
6583 (clobber (reg:DI 17))
6584 (clobber (reg:DI 26))
6585 (clobber (reg:DI 27))])]
6586 "TARGET_ABI_OPEN_VMS"
6587 {
6588 /* If value to set is not zero, use the library routine. */
6589 if (operands[2] != const0_rtx)
6590 FAIL;
6592 operands[4] = gen_rtx_SYMBOL_REF (Pmode, "OTS$ZERO");
6593 alpha_need_linkage (XSTR (operands[4], 0), 0);
6594 })
6596 (define_insn "*clrmemdi_1"
6597 [(set (match_operand:BLK 0 "memory_operand" "=m,=m")
6598 (const_int 0))
6599 (use (match_operand:DI 1 "nonmemory_operand" "r,i"))
6600 (use (match_operand:DI 2 "immediate_operand" ""))
6601 (use (match_operand:DI 3 "call_operand" "i,i"))
6602 (clobber (reg:DI 25))
6603 (clobber (reg:DI 16))
6604 (clobber (reg:DI 17))
6605 (clobber (reg:DI 26))
6606 (clobber (reg:DI 27))]
6607 "TARGET_ABI_OPEN_VMS"
6608 {
6609 operands [4] = alpha_use_linkage (operands [3], cfun->decl, 0, 1);
6610 switch (which_alternative)
6611 {
6612 case 0:
6613 return "lda $16,%0\;bis $31,%1,$17\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)";
6614 case 1:
6615 return "lda $16,%0\;lda $17,%1($31)\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)";
6616 default:
6617 gcc_unreachable ();
6618 }
6619 }
6620 [(set_attr "type" "multi")
6621 (set_attr "length" "24")])
6623 \f
6624 ;; Subroutine of stack space allocation. Perform a stack probe.
6625 (define_expand "probe_stack"
6626 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
6627 ""
6628 {
6629 operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx,
6630 INTVAL (operands[0])));
6631 MEM_VOLATILE_P (operands[1]) = 1;
6633 operands[0] = const0_rtx;
6634 })
6636 ;; This is how we allocate stack space. If we are allocating a
6637 ;; constant amount of space and we know it is less than 4096
6638 ;; bytes, we need do nothing.
6639 ;;
6640 ;; If it is more than 4096 bytes, we need to probe the stack
6641 ;; periodically.
6642 (define_expand "allocate_stack"
6643 [(set (reg:DI 30)
6644 (plus:DI (reg:DI 30)
6645 (match_operand:DI 1 "reg_or_cint_operand" "")))
6646 (set (match_operand:DI 0 "register_operand" "=r")
6647 (match_dup 2))]
6648 ""
6649 {
6650 if (GET_CODE (operands[1]) == CONST_INT
6651 && INTVAL (operands[1]) < 32768)
6652 {
6653 if (INTVAL (operands[1]) >= 4096)
6654 {
6655 /* We do this the same way as in the prologue and generate explicit
6656 probes. Then we update the stack by the constant. */
6658 int probed = 4096;
6660 emit_insn (gen_probe_stack (GEN_INT (- probed)));
6661 while (probed + 8192 < INTVAL (operands[1]))
6662 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
6664 if (probed + 4096 < INTVAL (operands[1]))
6665 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1]))));
6666 }
6668 operands[1] = GEN_INT (- INTVAL (operands[1]));
6669 operands[2] = virtual_stack_dynamic_rtx;
6670 }
6671 else
6672 {
6673 rtx out_label = 0;
6674 rtx loop_label = gen_label_rtx ();
6675 rtx want = gen_reg_rtx (Pmode);
6676 rtx tmp = gen_reg_rtx (Pmode);
6677 rtx memref;
6679 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
6680 force_reg (Pmode, operands[1])));
6681 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
6683 if (GET_CODE (operands[1]) != CONST_INT)
6684 {
6685 out_label = gen_label_rtx ();
6686 emit_insn (gen_cmpdi (want, tmp));
6687 emit_jump_insn (gen_bgeu (out_label));
6688 }
6690 emit_label (loop_label);
6691 memref = gen_rtx_MEM (DImode, tmp);
6692 MEM_VOLATILE_P (memref) = 1;
6693 emit_move_insn (memref, const0_rtx);
6694 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
6695 emit_insn (gen_cmpdi (tmp, want));
6696 emit_jump_insn (gen_bgtu (loop_label));
6698 memref = gen_rtx_MEM (DImode, want);
6699 MEM_VOLATILE_P (memref) = 1;
6700 emit_move_insn (memref, const0_rtx);
6702 if (out_label)
6703 emit_label (out_label);
6705 emit_move_insn (stack_pointer_rtx, want);
6706 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6707 DONE;
6708 }
6709 })
6711 ;; This is used by alpha_expand_prolog to do the same thing as above,
6712 ;; except we cannot at that time generate new basic blocks, so we hide
6713 ;; the loop in this one insn.
6715 (define_insn "prologue_stack_probe_loop"
6716 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
6717 (match_operand:DI 1 "register_operand" "r")]
6718 UNSPECV_PSPL)]
6719 ""
6720 {
6721 operands[2] = gen_label_rtx ();
6722 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6723 CODE_LABEL_NUMBER (operands[2]));
6725 return "stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2";
6726 }
6727 [(set_attr "length" "16")
6728 (set_attr "type" "multi")])
6730 (define_expand "prologue"
6731 [(clobber (const_int 0))]
6732 ""
6733 {
6734 alpha_expand_prologue ();
6735 DONE;
6736 })
6738 ;; These take care of emitting the ldgp insn in the prologue. This will be
6739 ;; an lda/ldah pair and we want to align them properly. So we have two
6740 ;; unspec_volatile insns, the first of which emits the ldgp assembler macro
6741 ;; and the second of which emits nothing. However, both are marked as type
6742 ;; IADD (the default) so the alignment code in alpha.c does the right thing
6743 ;; with them.
6745 (define_expand "prologue_ldgp"
6746 [(set (match_dup 0)
6747 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6748 (set (match_dup 0)
6749 (unspec_volatile:DI [(match_dup 0) (match_dup 2)] UNSPECV_PLDGP2))]
6750 ""
6751 {
6752 operands[0] = pic_offset_table_rtx;
6753 operands[1] = gen_rtx_REG (Pmode, 27);
6754 operands[2] = (TARGET_EXPLICIT_RELOCS
6755 ? GEN_INT (alpha_next_sequence_number++)
6756 : const0_rtx);
6757 })
6759 (define_insn "*ldgp_er_1"
6760 [(set (match_operand:DI 0 "register_operand" "=r")
6761 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6762 (match_operand 2 "const_int_operand" "")]
6763 UNSPECV_LDGP1))]
6764 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6765 "ldah %0,0(%1)\t\t!gpdisp!%2"
6766 [(set_attr "cannot_copy" "true")])
6768 (define_insn "*ldgp_er_2"
6769 [(set (match_operand:DI 0 "register_operand" "=r")
6770 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
6771 (match_operand 2 "const_int_operand" "")]
6772 UNSPEC_LDGP2))]
6773 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6774 "lda %0,0(%1)\t\t!gpdisp!%2"
6775 [(set_attr "cannot_copy" "true")])
6777 (define_insn "*prologue_ldgp_er_2"
6778 [(set (match_operand:DI 0 "register_operand" "=r")
6779 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6780 (match_operand 2 "const_int_operand" "")]
6781 UNSPECV_PLDGP2))]
6782 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6783 "lda %0,0(%1)\t\t!gpdisp!%2\n$%~..ng:"
6784 [(set_attr "cannot_copy" "true")])
6786 (define_insn "*prologue_ldgp_1"
6787 [(set (match_operand:DI 0 "register_operand" "=r")
6788 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6789 (match_operand 2 "const_int_operand" "")]
6790 UNSPECV_LDGP1))]
6791 ""
6792 "ldgp %0,0(%1)\n$%~..ng:"
6793 [(set_attr "cannot_copy" "true")])
6795 (define_insn "*prologue_ldgp_2"
6796 [(set (match_operand:DI 0 "register_operand" "=r")
6797 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6798 (match_operand 2 "const_int_operand" "")]
6799 UNSPECV_PLDGP2))]
6800 ""
6801 "")
6803 ;; The _mcount profiling hook has special calling conventions, and
6804 ;; does not clobber all the registers that a normal call would. So
6805 ;; hide the fact this is a call at all.
6807 (define_insn "prologue_mcount"
6808 [(unspec_volatile [(const_int 0)] UNSPECV_MCOUNT)]
6809 ""
6810 {
6811 if (TARGET_EXPLICIT_RELOCS)
6812 /* Note that we cannot use a lituse_jsr reloc, since _mcount
6813 cannot be called via the PLT. */
6814 return "ldq $28,_mcount($29)\t\t!literal\;jsr $28,($28),_mcount";
6815 else
6816 return "lda $28,_mcount\;jsr $28,($28),_mcount";
6817 }
6818 [(set_attr "type" "multi")
6819 (set_attr "length" "8")])
6821 (define_insn "init_fp"
6822 [(set (match_operand:DI 0 "register_operand" "=r")
6823 (match_operand:DI 1 "register_operand" "r"))
6824 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))]
6825 ""
6826 "bis $31,%1,%0")
6828 (define_expand "epilogue"
6829 [(return)]
6830 ""
6831 {
6832 alpha_expand_epilogue ();
6833 })
6835 (define_expand "sibcall_epilogue"
6836 [(return)]
6837 "TARGET_ABI_OSF"
6838 {
6839 alpha_expand_epilogue ();
6840 DONE;
6841 })
6843 (define_expand "builtin_longjmp"
6844 [(use (match_operand:DI 0 "register_operand" "r"))]
6845 "TARGET_ABI_OSF"
6846 {
6847 /* The elements of the buffer are, in order: */
6848 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6849 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
6850 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 16));
6851 rtx pv = gen_rtx_REG (Pmode, 27);
6853 /* This bit is the same as expand_builtin_longjmp. */
6854 emit_move_insn (hard_frame_pointer_rtx, fp);
6855 emit_move_insn (pv, lab);
6856 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6857 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6858 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6860 /* Load the label we are jumping through into $27 so that we know
6861 where to look for it when we get back to setjmp's function for
6862 restoring the gp. */
6863 emit_jump_insn (gen_builtin_longjmp_internal (pv));
6864 emit_barrier ();
6865 DONE;
6866 })
6868 ;; This is effectively a copy of indirect_jump, but constrained such
6869 ;; that register renaming cannot foil our cunning plan with $27.
6870 (define_insn "builtin_longjmp_internal"
6871 [(set (pc)
6872 (unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
6873 UNSPECV_LONGJMP))]
6874 ""
6875 "jmp $31,(%0),0"
6876 [(set_attr "type" "ibr")])
6878 (define_expand "builtin_setjmp_receiver"
6879 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6880 "TARGET_ABI_OSF"
6881 "")
6883 (define_insn_and_split "*builtin_setjmp_receiver_1"
6884 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_SETJMPR)]
6885 "TARGET_ABI_OSF"
6886 {
6887 if (TARGET_EXPLICIT_RELOCS)
6888 return "#";
6889 else
6890 return "br $27,$LSJ%=\n$LSJ%=:\;ldgp $29,0($27)";
6891 }
6892 "&& TARGET_EXPLICIT_RELOCS && reload_completed"
6893 [(set (match_dup 1)
6894 (unspec_volatile:DI [(match_dup 2) (match_dup 3)] UNSPECV_LDGP1))
6895 (set (match_dup 1)
6896 (unspec:DI [(match_dup 1) (match_dup 3)] UNSPEC_LDGP2))]
6897 {
6898 if (prev_nonnote_insn (curr_insn) != XEXP (operands[0], 0))
6899 emit_insn (gen_rtx_UNSPEC_VOLATILE (VOIDmode, gen_rtvec (1, operands[0]),
6900 UNSPECV_SETJMPR_ER));
6901 operands[1] = pic_offset_table_rtx;
6902 operands[2] = gen_rtx_REG (Pmode, 27);
6903 operands[3] = GEN_INT (alpha_next_sequence_number++);
6904 }
6905 [(set_attr "length" "12")
6906 (set_attr "type" "multi")])
6908 (define_insn "*builtin_setjmp_receiver_er_sl_1"
6909 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_SETJMPR_ER)]
6910 "TARGET_ABI_OSF && TARGET_EXPLICIT_RELOCS && TARGET_AS_CAN_SUBTRACT_LABELS"
6911 "lda $27,$LSJ%=-%l0($27)\n$LSJ%=:")
6913 (define_insn "*builtin_setjmp_receiver_er_1"
6914 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_SETJMPR_ER)]
6915 "TARGET_ABI_OSF && TARGET_EXPLICIT_RELOCS"
6916 "br $27,$LSJ%=\n$LSJ%=:"
6917 [(set_attr "type" "ibr")])
6919 (define_expand "exception_receiver"
6920 [(unspec_volatile [(match_dup 0)] UNSPECV_EHR)]
6921 "TARGET_ABI_OSF"
6922 {
6923 if (TARGET_LD_BUGGY_LDGP)
6924 operands[0] = alpha_gp_save_rtx ();
6925 else
6926 operands[0] = const0_rtx;
6927 })
6929 (define_insn "*exception_receiver_2"
6930 [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] UNSPECV_EHR)]
6931 "TARGET_ABI_OSF && TARGET_LD_BUGGY_LDGP"
6932 "ldq $29,%0"
6933 [(set_attr "type" "ild")])
6935 (define_insn_and_split "*exception_receiver_1"
6936 [(unspec_volatile [(const_int 0)] UNSPECV_EHR)]
6937 "TARGET_ABI_OSF"
6938 {
6939 if (TARGET_EXPLICIT_RELOCS)
6940 return "ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*";
6941 else
6942 return "ldgp $29,0($26)";
6943 }
6944 "&& TARGET_EXPLICIT_RELOCS && reload_completed"
6945 [(set (match_dup 0)
6946 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6947 (set (match_dup 0)
6948 (unspec:DI [(match_dup 0) (match_dup 2)] UNSPEC_LDGP2))]
6949 {
6950 operands[0] = pic_offset_table_rtx;
6951 operands[1] = gen_rtx_REG (Pmode, 26);
6952 operands[2] = GEN_INT (alpha_next_sequence_number++);
6953 }
6954 [(set_attr "length" "8")
6955 (set_attr "type" "multi")])
6957 (define_expand "nonlocal_goto_receiver"
6958 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6959 (set (reg:DI 27) (mem:DI (reg:DI 29)))
6960 (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6961 (use (reg:DI 27))]
6962 "TARGET_ABI_OPEN_VMS"
6963 "")
6965 (define_insn "arg_home"
6966 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
6967 (use (reg:DI 1))
6968 (use (reg:DI 25))
6969 (use (reg:DI 16))
6970 (use (reg:DI 17))
6971 (use (reg:DI 18))
6972 (use (reg:DI 19))
6973 (use (reg:DI 20))
6974 (use (reg:DI 21))
6975 (use (reg:DI 48))
6976 (use (reg:DI 49))
6977 (use (reg:DI 50))
6978 (use (reg:DI 51))
6979 (use (reg:DI 52))
6980 (use (reg:DI 53))
6981 (clobber (mem:BLK (const_int 0)))
6982 (clobber (reg:DI 24))
6983 (clobber (reg:DI 25))
6984 (clobber (reg:DI 0))]
6985 "TARGET_ABI_OPEN_VMS"
6986 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
6987 [(set_attr "length" "16")
6988 (set_attr "type" "multi")])
6990 ;; Load the CIW into r2 for calling __T3E_MISMATCH
6992 (define_expand "umk_mismatch_args"
6993 [(set:DI (match_dup 1) (mem:DI (plus:DI (reg:DI 15) (const_int -16))))
6994 (set:DI (match_dup 2) (mem:DI (plus:DI (match_dup 1) (const_int -32))))
6995 (set:DI (reg:DI 1) (match_operand:DI 0 "const_int_operand" ""))
6996 (set:DI (match_dup 3) (plus:DI (mult:DI (reg:DI 25)
6997 (const_int 8))
6998 (match_dup 2)))
6999 (set:DI (reg:DI 2) (mem:DI (match_dup 3)))]
7000 "TARGET_ABI_UNICOSMK"
7001 {
7002 operands[1] = gen_reg_rtx (DImode);
7003 operands[2] = gen_reg_rtx (DImode);
7004 operands[3] = gen_reg_rtx (DImode);
7005 })
7007 (define_insn "arg_home_umk"
7008 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
7009 (use (reg:DI 1))
7010 (use (reg:DI 2))
7011 (use (reg:DI 16))
7012 (use (reg:DI 17))
7013 (use (reg:DI 18))
7014 (use (reg:DI 19))
7015 (use (reg:DI 20))
7016 (use (reg:DI 21))
7017 (use (reg:DI 48))
7018 (use (reg:DI 49))
7019 (use (reg:DI 50))
7020 (use (reg:DI 51))
7021 (use (reg:DI 52))
7022 (use (reg:DI 53))
7023 (clobber (mem:BLK (const_int 0)))
7024 (parallel [
7025 (clobber (reg:DI 22))
7026 (clobber (reg:DI 23))
7027 (clobber (reg:DI 24))
7028 (clobber (reg:DI 0))
7029 (clobber (reg:DI 1))
7030 (clobber (reg:DI 2))
7031 (clobber (reg:DI 3))
7032 (clobber (reg:DI 4))
7033 (clobber (reg:DI 5))
7034 (clobber (reg:DI 6))
7035 (clobber (reg:DI 7))
7036 (clobber (reg:DI 8))])]
7037 "TARGET_ABI_UNICOSMK"
7038 "laum $4,__T3E_MISMATCH($31)\;sll $4,32,$4\;lalm $4,__T3E_MISMATCH($4)\;lal $4,__T3E_MISMATCH($4)\;jsr $3,($4)"
7039 [(set_attr "length" "16")
7040 (set_attr "type" "multi")])
7042 ;; Prefetch data.
7043 ;;
7044 ;; On EV4, these instructions are nops -- no load occurs.
7045 ;;
7046 ;; On EV5, these instructions act as a normal load, and thus can trap
7047 ;; if the address is invalid. The OS may (or may not) handle this in
7048 ;; the entMM fault handler and suppress the fault. If so, then this
7049 ;; has the effect of a read prefetch instruction.
7050 ;;
7051 ;; On EV6, these become official prefetch instructions.
7053 (define_insn "prefetch"
7054 [(prefetch (match_operand:DI 0 "address_operand" "p")
7055 (match_operand:DI 1 "const_int_operand" "n")
7056 (match_operand:DI 2 "const_int_operand" "n"))]
7057 "TARGET_FIXUP_EV5_PREFETCH || alpha_cpu == PROCESSOR_EV6"
7058 {
7059 /* Interpret "no temporal locality" as this data should be evicted once
7060 it is used. The "evict next" alternatives load the data into the cache
7061 and leave the LRU eviction counter pointing to that block. */
7062 static const char * const alt[2][2] = {
7063 {
7064 "ldq $31,%a0", /* read, evict next */
7065 "ldl $31,%a0", /* read, evict last */
7066 },
7067 {
7068 "ldt $f31,%a0", /* write, evict next */
7069 "lds $f31,%a0", /* write, evict last */
7070 }
7071 };
7073 bool write = INTVAL (operands[1]) != 0;
7074 bool lru = INTVAL (operands[2]) != 0;
7076 return alt[write][lru];
7077 }
7078 [(set_attr "type" "ild")])
7080 ;; Close the trap shadow of preceding instructions. This is generated
7081 ;; by alpha_reorg.
7083 (define_insn "trapb"
7084 [(unspec_volatile [(const_int 0)] UNSPECV_TRAPB)]
7085 ""
7086 "trapb"
7087 [(set_attr "type" "misc")])
7089 ;; No-op instructions used by machine-dependent reorg to preserve
7090 ;; alignment for instruction issue.
7091 ;; The Unicos/Mk assembler does not support these opcodes.
7093 (define_insn "nop"
7094 [(const_int 0)]
7095 ""
7096 "bis $31,$31,$31"
7097 [(set_attr "type" "ilog")])
7099 (define_insn "fnop"
7100 [(const_int 1)]
7101 "TARGET_FP"
7102 "cpys $f31,$f31,$f31"
7103 [(set_attr "type" "fcpys")])
7105 (define_insn "unop"
7106 [(const_int 2)]
7107 ""
7108 "ldq_u $31,0($30)")
7110 ;; On Unicos/Mk we use a macro for aligning code.
7112 (define_insn "realign"
7113 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")]
7114 UNSPECV_REALIGN)]
7115 ""
7116 {
7117 if (TARGET_ABI_UNICOSMK)
7118 return "gcc@code@align %0";
7119 else
7120 return ".align %0 #realign";
7121 })
7122 \f
7123 ;; Instructions to be emitted from __builtins.
7125 (define_insn "builtin_cmpbge"
7126 [(set (match_operand:DI 0 "register_operand" "=r")
7127 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rJ")
7128 (match_operand:DI 2 "reg_or_8bit_operand" "rI")]
7129 UNSPEC_CMPBGE))]
7130 ""
7131 "cmpbge %r1,%2,%0"
7132 ;; The EV6 data sheets list this as ILOG. OTOH, EV6 doesn't
7133 ;; actually differentiate between ILOG and ICMP in the schedule.
7134 [(set_attr "type" "icmp")])
7136 (define_expand "builtin_extbl"
7137 [(match_operand:DI 0 "register_operand" "")
7138 (match_operand:DI 1 "reg_or_0_operand" "")
7139 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7140 ""
7141 {
7142 rtx (*gen) (rtx, rtx, rtx, rtx);
7143 if (WORDS_BIG_ENDIAN)
7144 gen = gen_extxl_be;
7145 else
7146 gen = gen_extxl_le;
7147 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (8), operands[2]));
7148 DONE;
7149 })
7151 (define_expand "builtin_extwl"
7152 [(match_operand:DI 0 "register_operand" "")
7153 (match_operand:DI 1 "reg_or_0_operand" "")
7154 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7155 ""
7156 {
7157 rtx (*gen) (rtx, rtx, rtx, rtx);
7158 if (WORDS_BIG_ENDIAN)
7159 gen = gen_extxl_be;
7160 else
7161 gen = gen_extxl_le;
7162 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (16), operands[2]));
7163 DONE;
7164 })
7166 (define_expand "builtin_extll"
7167 [(match_operand:DI 0 "register_operand" "")
7168 (match_operand:DI 1 "reg_or_0_operand" "")
7169 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7170 ""
7171 {
7172 rtx (*gen) (rtx, rtx, rtx, rtx);
7173 if (WORDS_BIG_ENDIAN)
7174 gen = gen_extxl_be;
7175 else
7176 gen = gen_extxl_le;
7177 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (32), operands[2]));
7178 DONE;
7179 })
7181 (define_expand "builtin_extql"
7182 [(match_operand:DI 0 "register_operand" "")
7183 (match_operand:DI 1 "reg_or_0_operand" "")
7184 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7185 ""
7186 {
7187 rtx (*gen) (rtx, rtx, rtx, rtx);
7188 if (WORDS_BIG_ENDIAN)
7189 gen = gen_extxl_be;
7190 else
7191 gen = gen_extxl_le;
7192 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (64), operands[2]));
7193 DONE;
7194 })
7196 (define_expand "builtin_extwh"
7197 [(match_operand:DI 0 "register_operand" "")
7198 (match_operand:DI 1 "reg_or_0_operand" "")
7199 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7200 ""
7201 {
7202 rtx (*gen) (rtx, rtx, rtx);
7203 if (WORDS_BIG_ENDIAN)
7204 gen = gen_extwh_be;
7205 else
7206 gen = gen_extwh_le;
7207 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7208 DONE;
7209 })
7211 (define_expand "builtin_extlh"
7212 [(match_operand:DI 0 "register_operand" "")
7213 (match_operand:DI 1 "reg_or_0_operand" "")
7214 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7215 ""
7216 {
7217 rtx (*gen) (rtx, rtx, rtx);
7218 if (WORDS_BIG_ENDIAN)
7219 gen = gen_extlh_be;
7220 else
7221 gen = gen_extlh_le;
7222 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7223 DONE;
7224 })
7226 (define_expand "builtin_extqh"
7227 [(match_operand:DI 0 "register_operand" "")
7228 (match_operand:DI 1 "reg_or_0_operand" "")
7229 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7230 ""
7231 {
7232 rtx (*gen) (rtx, rtx, rtx);
7233 if (WORDS_BIG_ENDIAN)
7234 gen = gen_extqh_be;
7235 else
7236 gen = gen_extqh_le;
7237 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7238 DONE;
7239 })
7241 (define_expand "builtin_insbl"
7242 [(match_operand:DI 0 "register_operand" "")
7243 (match_operand:DI 1 "register_operand" "")
7244 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7245 ""
7246 {
7247 rtx (*gen) (rtx, rtx, rtx);
7248 if (WORDS_BIG_ENDIAN)
7249 gen = gen_insbl_be;
7250 else
7251 gen = gen_insbl_le;
7252 operands[1] = gen_lowpart (QImode, operands[1]);
7253 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7254 DONE;
7255 })
7257 (define_expand "builtin_inswl"
7258 [(match_operand:DI 0 "register_operand" "")
7259 (match_operand:DI 1 "register_operand" "")
7260 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7261 ""
7262 {
7263 rtx (*gen) (rtx, rtx, rtx);
7264 if (WORDS_BIG_ENDIAN)
7265 gen = gen_inswl_be;
7266 else
7267 gen = gen_inswl_le;
7268 operands[1] = gen_lowpart (HImode, operands[1]);
7269 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7270 DONE;
7271 })
7273 (define_expand "builtin_insll"
7274 [(match_operand:DI 0 "register_operand" "")
7275 (match_operand:DI 1 "register_operand" "")
7276 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7277 ""
7278 {
7279 rtx (*gen) (rtx, rtx, rtx);
7280 if (WORDS_BIG_ENDIAN)
7281 gen = gen_insll_be;
7282 else
7283 gen = gen_insll_le;
7284 operands[1] = gen_lowpart (SImode, operands[1]);
7285 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7286 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7287 DONE;
7288 })
7290 (define_expand "builtin_insql"
7291 [(match_operand:DI 0 "register_operand" "")
7292 (match_operand:DI 1 "reg_or_0_operand" "")
7293 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7294 ""
7295 {
7296 rtx (*gen) (rtx, rtx, rtx);
7297 if (WORDS_BIG_ENDIAN)
7298 gen = gen_insql_be;
7299 else
7300 gen = gen_insql_le;
7301 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7302 DONE;
7303 })
7305 (define_expand "builtin_inswh"
7306 [(match_operand:DI 0 "register_operand" "")
7307 (match_operand:DI 1 "register_operand" "")
7308 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7309 ""
7310 {
7311 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (16), operands[2]));
7312 DONE;
7313 })
7315 (define_expand "builtin_inslh"
7316 [(match_operand:DI 0 "register_operand" "")
7317 (match_operand:DI 1 "register_operand" "")
7318 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7319 ""
7320 {
7321 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (32), operands[2]));
7322 DONE;
7323 })
7325 (define_expand "builtin_insqh"
7326 [(match_operand:DI 0 "register_operand" "")
7327 (match_operand:DI 1 "register_operand" "")
7328 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7329 ""
7330 {
7331 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (64), operands[2]));
7332 DONE;
7333 })
7335 (define_expand "builtin_mskbl"
7336 [(match_operand:DI 0 "register_operand" "")
7337 (match_operand:DI 1 "reg_or_0_operand" "")
7338 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7339 ""
7340 {
7341 rtx (*gen) (rtx, rtx, rtx, rtx);
7342 rtx mask;
7343 if (WORDS_BIG_ENDIAN)
7344 gen = gen_mskxl_be;
7345 else
7346 gen = gen_mskxl_le;
7347 mask = GEN_INT (0xff);
7348 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7349 DONE;
7350 })
7352 (define_expand "builtin_mskwl"
7353 [(match_operand:DI 0 "register_operand" "")
7354 (match_operand:DI 1 "reg_or_0_operand" "")
7355 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7356 ""
7357 {
7358 rtx (*gen) (rtx, rtx, rtx, rtx);
7359 rtx mask;
7360 if (WORDS_BIG_ENDIAN)
7361 gen = gen_mskxl_be;
7362 else
7363 gen = gen_mskxl_le;
7364 mask = GEN_INT (0xffff);
7365 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7366 DONE;
7367 })
7369 (define_expand "builtin_mskll"
7370 [(match_operand:DI 0 "register_operand" "")
7371 (match_operand:DI 1 "reg_or_0_operand" "")
7372 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7373 ""
7374 {
7375 rtx (*gen) (rtx, rtx, rtx, rtx);
7376 rtx mask;
7377 if (WORDS_BIG_ENDIAN)
7378 gen = gen_mskxl_be;
7379 else
7380 gen = gen_mskxl_le;
7381 mask = immed_double_const (0xffffffff, 0, DImode);
7382 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7383 DONE;
7384 })
7386 (define_expand "builtin_mskql"
7387 [(match_operand:DI 0 "register_operand" "")
7388 (match_operand:DI 1 "reg_or_0_operand" "")
7389 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7390 ""
7391 {
7392 rtx (*gen) (rtx, rtx, rtx, rtx);
7393 rtx mask;
7394 if (WORDS_BIG_ENDIAN)
7395 gen = gen_mskxl_be;
7396 else
7397 gen = gen_mskxl_le;
7398 mask = constm1_rtx;
7399 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7400 DONE;
7401 })
7403 (define_expand "builtin_mskwh"
7404 [(match_operand:DI 0 "register_operand" "")
7405 (match_operand:DI 1 "register_operand" "")
7406 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7407 ""
7408 {
7409 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (16), operands[2]));
7410 DONE;
7411 })
7413 (define_expand "builtin_msklh"
7414 [(match_operand:DI 0 "register_operand" "")
7415 (match_operand:DI 1 "register_operand" "")
7416 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7417 ""
7418 {
7419 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (32), operands[2]));
7420 DONE;
7421 })
7423 (define_expand "builtin_mskqh"
7424 [(match_operand:DI 0 "register_operand" "")
7425 (match_operand:DI 1 "register_operand" "")
7426 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7427 ""
7428 {
7429 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (64), operands[2]));
7430 DONE;
7431 })
7433 (define_expand "builtin_zap"
7434 [(set (match_operand:DI 0 "register_operand" "")
7435 (and:DI (unspec:DI
7436 [(match_operand:DI 2 "reg_or_cint_operand" "")]
7437 UNSPEC_ZAP)
7438 (match_operand:DI 1 "reg_or_cint_operand" "")))]
7439 ""
7440 {
7441 if (GET_CODE (operands[2]) == CONST_INT)
7442 {
7443 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
7445 if (mask == const0_rtx)
7446 {
7447 emit_move_insn (operands[0], const0_rtx);
7448 DONE;
7449 }
7450 if (mask == constm1_rtx)
7451 {
7452 emit_move_insn (operands[0], operands[1]);
7453 DONE;
7454 }
7456 operands[1] = force_reg (DImode, operands[1]);
7457 emit_insn (gen_anddi3 (operands[0], operands[1], mask));
7458 DONE;
7459 }
7461 operands[1] = force_reg (DImode, operands[1]);
7462 operands[2] = gen_lowpart (QImode, operands[2]);
7463 })
7465 (define_insn "*builtin_zap_1"
7466 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
7467 (and:DI (unspec:DI
7468 [(match_operand:QI 2 "reg_or_cint_operand" "n,n,r,r")]
7469 UNSPEC_ZAP)
7470 (match_operand:DI 1 "reg_or_cint_operand" "n,r,J,r")))]
7471 ""
7472 "@
7473 #
7474 #
7475 bis $31,$31,%0
7476 zap %r1,%2,%0"
7477 [(set_attr "type" "shift,shift,ilog,shift")])
7479 (define_split
7480 [(set (match_operand:DI 0 "register_operand" "")
7481 (and:DI (unspec:DI
7482 [(match_operand:QI 2 "const_int_operand" "")]
7483 UNSPEC_ZAP)
7484 (match_operand:DI 1 "const_int_operand" "")))]
7485 ""
7486 [(const_int 0)]
7487 {
7488 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
7489 if (HOST_BITS_PER_WIDE_INT >= 64 || GET_CODE (mask) == CONST_INT)
7490 operands[1] = gen_int_mode (INTVAL (operands[1]) & INTVAL (mask), DImode);
7491 else
7492 {
7493 HOST_WIDE_INT c_lo = INTVAL (operands[1]);
7494 HOST_WIDE_INT c_hi = (c_lo < 0 ? -1 : 0);
7495 operands[1] = immed_double_const (c_lo & CONST_DOUBLE_LOW (mask),
7496 c_hi & CONST_DOUBLE_HIGH (mask),
7497 DImode);
7498 }
7499 emit_move_insn (operands[0], operands[1]);
7500 DONE;
7501 })
7503 (define_split
7504 [(set (match_operand:DI 0 "register_operand" "")
7505 (and:DI (unspec:DI
7506 [(match_operand:QI 2 "const_int_operand" "")]
7507 UNSPEC_ZAP)
7508 (match_operand:DI 1 "register_operand" "")))]
7509 ""
7510 [(set (match_dup 0)
7511 (and:DI (match_dup 1) (match_dup 2)))]
7512 {
7513 operands[2] = alpha_expand_zap_mask (INTVAL (operands[2]));
7514 if (operands[2] == const0_rtx)
7515 {
7516 emit_move_insn (operands[0], const0_rtx);
7517 DONE;
7518 }
7519 if (operands[2] == constm1_rtx)
7520 {
7521 emit_move_insn (operands[0], operands[1]);
7522 DONE;
7523 }
7524 })
7526 (define_expand "builtin_zapnot"
7527 [(set (match_operand:DI 0 "register_operand" "")
7528 (and:DI (unspec:DI
7529 [(not:QI (match_operand:DI 2 "reg_or_cint_operand" ""))]
7530 UNSPEC_ZAP)
7531 (match_operand:DI 1 "reg_or_cint_operand" "")))]
7532 ""
7533 {
7534 if (GET_CODE (operands[2]) == CONST_INT)
7535 {
7536 rtx mask = alpha_expand_zap_mask (~ INTVAL (operands[2]));
7538 if (mask == const0_rtx)
7539 {
7540 emit_move_insn (operands[0], const0_rtx);
7541 DONE;
7542 }
7543 if (mask == constm1_rtx)
7544 {
7545 emit_move_insn (operands[0], operands[1]);
7546 DONE;
7547 }
7549 operands[1] = force_reg (DImode, operands[1]);
7550 emit_insn (gen_anddi3 (operands[0], operands[1], mask));
7551 DONE;
7552 }
7554 operands[1] = force_reg (DImode, operands[1]);
7555 operands[2] = gen_lowpart (QImode, operands[2]);
7556 })
7558 (define_insn "*builtin_zapnot_1"
7559 [(set (match_operand:DI 0 "register_operand" "=r")
7560 (and:DI (unspec:DI
7561 [(not:QI (match_operand:QI 2 "register_operand" "r"))]
7562 UNSPEC_ZAP)
7563 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
7564 ""
7565 "zapnot %r1,%2,%0"
7566 [(set_attr "type" "shift")])
7568 (define_insn "builtin_amask"
7569 [(set (match_operand:DI 0 "register_operand" "=r")
7570 (unspec:DI [(match_operand:DI 1 "reg_or_8bit_operand" "rI")]
7571 UNSPEC_AMASK))]
7572 ""
7573 "amask %1,%0"
7574 [(set_attr "type" "ilog")])
7576 (define_insn "builtin_implver"
7577 [(set (match_operand:DI 0 "register_operand" "=r")
7578 (unspec:DI [(const_int 0)] UNSPEC_IMPLVER))]
7579 ""
7580 "implver %0"
7581 [(set_attr "type" "ilog")])
7583 (define_insn "builtin_rpcc"
7584 [(set (match_operand:DI 0 "register_operand" "=r")
7585 (unspec_volatile:DI [(const_int 0)] UNSPECV_RPCC))]
7586 ""
7587 "rpcc %0"
7588 [(set_attr "type" "ilog")])
7590 (define_expand "builtin_minub8"
7591 [(match_operand:DI 0 "register_operand" "")
7592 (match_operand:DI 1 "reg_or_0_operand" "")
7593 (match_operand:DI 2 "reg_or_0_operand" "")]
7594 "TARGET_MAX"
7595 {
7596 alpha_expand_builtin_vector_binop (gen_uminv8qi3, V8QImode, operands[0],
7597 operands[1], operands[2]);
7598 DONE;
7599 })
7601 (define_expand "builtin_minsb8"
7602 [(match_operand:DI 0 "register_operand" "")
7603 (match_operand:DI 1 "reg_or_0_operand" "")
7604 (match_operand:DI 2 "reg_or_0_operand" "")]
7605 "TARGET_MAX"
7606 {
7607 alpha_expand_builtin_vector_binop (gen_sminv8qi3, V8QImode, operands[0],
7608 operands[1], operands[2]);
7609 DONE;
7610 })
7612 (define_expand "builtin_minuw4"
7613 [(match_operand:DI 0 "register_operand" "")
7614 (match_operand:DI 1 "reg_or_0_operand" "")
7615 (match_operand:DI 2 "reg_or_0_operand" "")]
7616 "TARGET_MAX"
7617 {
7618 alpha_expand_builtin_vector_binop (gen_uminv4hi3, V4HImode, operands[0],
7619 operands[1], operands[2]);
7620 DONE;
7621 })
7623 (define_expand "builtin_minsw4"
7624 [(match_operand:DI 0 "register_operand" "")
7625 (match_operand:DI 1 "reg_or_0_operand" "")
7626 (match_operand:DI 2 "reg_or_0_operand" "")]
7627 "TARGET_MAX"
7628 {
7629 alpha_expand_builtin_vector_binop (gen_sminv4hi3, V4HImode, operands[0],
7630 operands[1], operands[2]);
7631 DONE;
7632 })
7634 (define_expand "builtin_maxub8"
7635 [(match_operand:DI 0 "register_operand" "")
7636 (match_operand:DI 1 "reg_or_0_operand" "")
7637 (match_operand:DI 2 "reg_or_0_operand" "")]
7638 "TARGET_MAX"
7639 {
7640 alpha_expand_builtin_vector_binop (gen_umaxv8qi3, V8QImode, operands[0],
7641 operands[1], operands[2]);
7642 DONE;
7643 })
7645 (define_expand "builtin_maxsb8"
7646 [(match_operand:DI 0 "register_operand" "")
7647 (match_operand:DI 1 "reg_or_0_operand" "")
7648 (match_operand:DI 2 "reg_or_0_operand" "")]
7649 "TARGET_MAX"
7650 {
7651 alpha_expand_builtin_vector_binop (gen_smaxv8qi3, V8QImode, operands[0],
7652 operands[1], operands[2]);
7653 DONE;
7654 })
7656 (define_expand "builtin_maxuw4"
7657 [(match_operand:DI 0 "register_operand" "")
7658 (match_operand:DI 1 "reg_or_0_operand" "")
7659 (match_operand:DI 2 "reg_or_0_operand" "")]
7660 "TARGET_MAX"
7661 {
7662 alpha_expand_builtin_vector_binop (gen_umaxv4hi3, V4HImode, operands[0],
7663 operands[1], operands[2]);
7664 DONE;
7665 })
7667 (define_expand "builtin_maxsw4"
7668 [(match_operand:DI 0 "register_operand" "")
7669 (match_operand:DI 1 "reg_or_0_operand" "")
7670 (match_operand:DI 2 "reg_or_0_operand" "")]
7671 "TARGET_MAX"
7672 {
7673 alpha_expand_builtin_vector_binop (gen_smaxv4hi3, V4HImode, operands[0],
7674 operands[1], operands[2]);
7675 DONE;
7676 })
7678 (define_insn "builtin_perr"
7679 [(set (match_operand:DI 0 "register_operand" "=r")
7680 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "%rJ")
7681 (match_operand:DI 2 "reg_or_8bit_operand" "rJ")]
7682 UNSPEC_PERR))]
7683 "TARGET_MAX"
7684 "perr %r1,%r2,%0"
7685 [(set_attr "type" "mvi")])
7687 (define_expand "builtin_pklb"
7688 [(set (match_operand:DI 0 "register_operand" "")
7689 (vec_concat:V8QI
7690 (vec_concat:V4QI
7691 (truncate:V2QI (match_operand:DI 1 "register_operand" ""))
7692 (match_dup 2))
7693 (match_dup 3)))]
7694 "TARGET_MAX"
7695 {
7696 operands[0] = gen_lowpart (V8QImode, operands[0]);
7697 operands[1] = gen_lowpart (V2SImode, operands[1]);
7698 operands[2] = CONST0_RTX (V2QImode);
7699 operands[3] = CONST0_RTX (V4QImode);
7700 })
7702 (define_insn "*pklb"
7703 [(set (match_operand:V8QI 0 "register_operand" "=r")
7704 (vec_concat:V8QI
7705 (vec_concat:V4QI
7706 (truncate:V2QI (match_operand:V2SI 1 "register_operand" "r"))
7707 (match_operand:V2QI 2 "const0_operand" ""))
7708 (match_operand:V4QI 3 "const0_operand" "")))]
7709 "TARGET_MAX"
7710 "pklb %r1,%0"
7711 [(set_attr "type" "mvi")])
7713 (define_expand "builtin_pkwb"
7714 [(set (match_operand:DI 0 "register_operand" "")
7715 (vec_concat:V8QI
7716 (truncate:V4QI (match_operand:DI 1 "register_operand" ""))
7717 (match_dup 2)))]
7718 "TARGET_MAX"
7719 {
7720 operands[0] = gen_lowpart (V8QImode, operands[0]);
7721 operands[1] = gen_lowpart (V4HImode, operands[1]);
7722 operands[2] = CONST0_RTX (V4QImode);
7723 })
7725 (define_insn "*pkwb"
7726 [(set (match_operand:V8QI 0 "register_operand" "=r")
7727 (vec_concat:V8QI
7728 (truncate:V4QI (match_operand:V4HI 1 "register_operand" "r"))
7729 (match_operand:V4QI 2 "const0_operand" "")))]
7730 "TARGET_MAX"
7731 "pkwb %r1,%0"
7732 [(set_attr "type" "mvi")])
7734 (define_expand "builtin_unpkbl"
7735 [(set (match_operand:DI 0 "register_operand" "")
7736 (zero_extend:V2SI
7737 (vec_select:V2QI (match_operand:DI 1 "register_operand" "")
7738 (parallel [(const_int 0) (const_int 1)]))))]
7739 "TARGET_MAX"
7740 {
7741 operands[0] = gen_lowpart (V2SImode, operands[0]);
7742 operands[1] = gen_lowpart (V8QImode, operands[1]);
7743 })
7745 (define_insn "*unpkbl"
7746 [(set (match_operand:V2SI 0 "register_operand" "=r")
7747 (zero_extend:V2SI
7748 (vec_select:V2QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
7749 (parallel [(const_int 0) (const_int 1)]))))]
7750 "TARGET_MAX"
7751 "unpkbl %r1,%0"
7752 [(set_attr "type" "mvi")])
7754 (define_expand "builtin_unpkbw"
7755 [(set (match_operand:DI 0 "register_operand" "")
7756 (zero_extend:V4HI
7757 (vec_select:V4QI (match_operand:DI 1 "register_operand" "")
7758 (parallel [(const_int 0)
7759 (const_int 1)
7760 (const_int 2)
7761 (const_int 3)]))))]
7762 "TARGET_MAX"
7763 {
7764 operands[0] = gen_lowpart (V4HImode, operands[0]);
7765 operands[1] = gen_lowpart (V8QImode, operands[1]);
7766 })
7768 (define_insn "*unpkbw"
7769 [(set (match_operand:V4HI 0 "register_operand" "=r")
7770 (zero_extend:V4HI
7771 (vec_select:V4QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
7772 (parallel [(const_int 0)
7773 (const_int 1)
7774 (const_int 2)
7775 (const_int 3)]))))]
7776 "TARGET_MAX"
7777 "unpkbw %r1,%0"
7778 [(set_attr "type" "mvi")])
7779 \f
7780 (include "sync.md")
7781 \f
7782 ;; The call patterns are at the end of the file because their
7783 ;; wildcard operand0 interferes with nice recognition.
7785 (define_insn "*call_value_osf_1_er"
7786 [(set (match_operand 0 "" "")
7787 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7788 (match_operand 2 "" "")))
7789 (use (reg:DI 29))
7790 (clobber (reg:DI 26))]
7791 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7792 "@
7793 jsr $26,(%1),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
7794 bsr $26,%1\t\t!samegp
7795 ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
7796 [(set_attr "type" "jsr")
7797 (set_attr "length" "12,*,16")])
7799 ;; We must use peep2 instead of a split because we need accurate life
7800 ;; information for $gp. Consider the case of { bar(); while (1); }.
7801 (define_peephole2
7802 [(parallel [(set (match_operand 0 "" "")
7803 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
7804 (match_operand 2 "" "")))
7805 (use (reg:DI 29))
7806 (clobber (reg:DI 26))])]
7807 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
7808 && ! samegp_function_operand (operands[1], Pmode)
7809 && (peep2_regno_dead_p (1, 29)
7810 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
7811 [(parallel [(set (match_dup 0)
7812 (call (mem:DI (match_dup 3))
7813 (match_dup 2)))
7814 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7815 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
7816 (use (match_dup 1))
7817 (use (match_dup 4))])]
7818 {
7819 if (CONSTANT_P (operands[1]))
7820 {
7821 operands[3] = gen_rtx_REG (Pmode, 27);
7822 operands[4] = GEN_INT (alpha_next_sequence_number++);
7823 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
7824 operands[1], operands[4]));
7825 }
7826 else
7827 {
7828 operands[3] = operands[1];
7829 operands[1] = const0_rtx;
7830 operands[4] = const0_rtx;
7831 }
7832 })
7834 (define_peephole2
7835 [(parallel [(set (match_operand 0 "" "")
7836 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
7837 (match_operand 2 "" "")))
7838 (use (reg:DI 29))
7839 (clobber (reg:DI 26))])]
7840 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
7841 && ! samegp_function_operand (operands[1], Pmode)
7842 && ! (peep2_regno_dead_p (1, 29)
7843 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
7844 [(parallel [(set (match_dup 0)
7845 (call (mem:DI (match_dup 3))
7846 (match_dup 2)))
7847 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7848 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
7849 (use (match_dup 1))
7850 (use (match_dup 5))])
7851 (set (reg:DI 29)
7852 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
7853 (set (reg:DI 29)
7854 (unspec:DI [(reg:DI 29) (match_dup 4)] UNSPEC_LDGP2))]
7855 {
7856 if (CONSTANT_P (operands[1]))
7857 {
7858 operands[3] = gen_rtx_REG (Pmode, 27);
7859 operands[5] = GEN_INT (alpha_next_sequence_number++);
7860 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
7861 operands[1], operands[5]));
7862 }
7863 else
7864 {
7865 operands[3] = operands[1];
7866 operands[1] = const0_rtx;
7867 operands[5] = const0_rtx;
7868 }
7869 operands[4] = GEN_INT (alpha_next_sequence_number++);
7870 })
7872 ;; We add a blockage unspec_volatile to prevent insns from moving down
7873 ;; from above the call to in between the call and the ldah gpdisp.
7874 (define_insn "*call_value_osf_2_er"
7875 [(set (match_operand 0 "" "")
7876 (call (mem:DI (match_operand:DI 1 "register_operand" "c"))
7877 (match_operand 2 "" "")))
7878 (set (reg:DI 26)
7879 (plus:DI (pc) (const_int 4)))
7880 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
7881 (use (match_operand 3 "" ""))
7882 (use (match_operand 4 "" ""))]
7883 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7884 "jsr $26,(%1),%3%J4"
7885 [(set_attr "type" "jsr")
7886 (set_attr "cannot_copy" "true")])
7888 (define_insn "*call_value_osf_1_noreturn"
7889 [(set (match_operand 0 "" "")
7890 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7891 (match_operand 2 "" "")))
7892 (use (reg:DI 29))
7893 (clobber (reg:DI 26))]
7894 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
7895 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7896 "@
7897 jsr $26,($27),0%+
7898 bsr $26,$%1..ng%+
7899 jsr $26,%1%+"
7900 [(set_attr "type" "jsr")
7901 (set_attr "length" "*,*,8")])
7903 (define_insn_and_split "call_value_osf_tlsgd"
7904 [(set (match_operand 0 "" "")
7905 (call (mem:DI (match_operand:DI 1 "symbolic_operand" ""))
7906 (const_int 0)))
7907 (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSGD_CALL)
7908 (use (reg:DI 29))
7909 (clobber (reg:DI 26))]
7910 "HAVE_AS_TLS"
7911 "#"
7912 "&& reload_completed"
7913 [(set (match_dup 3)
7914 (unspec:DI [(match_dup 5)
7915 (match_dup 1)
7916 (match_dup 2)] UNSPEC_LITERAL))
7917 (parallel [(set (match_dup 0)
7918 (call (mem:DI (match_dup 3))
7919 (const_int 0)))
7920 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7921 (unspec_volatile [(match_dup 5)] UNSPECV_BLOCKAGE)
7922 (use (match_dup 1))
7923 (use (unspec [(match_dup 2)] UNSPEC_TLSGD_CALL))])
7924 (set (match_dup 5)
7925 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
7926 (set (match_dup 5)
7927 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))]
7928 {
7929 operands[3] = gen_rtx_REG (Pmode, 27);
7930 operands[4] = GEN_INT (alpha_next_sequence_number++);
7931 operands[5] = pic_offset_table_rtx;
7932 }
7933 [(set_attr "type" "multi")])
7935 (define_insn_and_split "call_value_osf_tlsldm"
7936 [(set (match_operand 0 "" "")
7937 (call (mem:DI (match_operand:DI 1 "symbolic_operand" ""))
7938 (const_int 0)))
7939 (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSLDM_CALL)
7940 (use (reg:DI 29))
7941 (clobber (reg:DI 26))]
7942 "HAVE_AS_TLS"
7943 "#"
7944 "&& reload_completed"
7945 [(set (match_dup 3)
7946 (unspec:DI [(match_dup 5)
7947 (match_dup 1)
7948 (match_dup 2)] UNSPEC_LITERAL))
7949 (parallel [(set (match_dup 0)
7950 (call (mem:DI (match_dup 3))
7951 (const_int 0)))
7952 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7953 (unspec_volatile [(match_dup 5)] UNSPECV_BLOCKAGE)
7954 (use (match_dup 1))
7955 (use (unspec [(match_dup 2)] UNSPEC_TLSLDM_CALL))])
7956 (set (reg:DI 29)
7957 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
7958 (set (reg:DI 29)
7959 (unspec:DI [(reg:DI 29) (match_dup 4)] UNSPEC_LDGP2))]
7960 {
7961 operands[3] = gen_rtx_REG (Pmode, 27);
7962 operands[4] = GEN_INT (alpha_next_sequence_number++);
7963 operands[5] = pic_offset_table_rtx;
7964 }
7965 [(set_attr "type" "multi")])
7967 (define_insn "*call_value_osf_1"
7968 [(set (match_operand 0 "" "")
7969 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7970 (match_operand 2 "" "")))
7971 (use (reg:DI 29))
7972 (clobber (reg:DI 26))]
7973 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7974 "@
7975 jsr $26,($27),0\;ldgp $29,0($26)
7976 bsr $26,$%1..ng
7977 jsr $26,%1\;ldgp $29,0($26)"
7978 [(set_attr "type" "jsr")
7979 (set_attr "length" "12,*,16")])
7981 (define_insn "*sibcall_value_osf_1_er"
7982 [(set (match_operand 0 "" "")
7983 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
7984 (match_operand 2 "" "")))
7985 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
7986 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7987 "@
7988 br $31,%1\t\t!samegp
7989 ldq $27,%1($29)\t\t!literal!%#\;jmp $31,($27),%1\t\t!lituse_jsr!%#"
7990 [(set_attr "type" "jsr")
7991 (set_attr "length" "*,8")])
7993 (define_insn "*sibcall_value_osf_1"
7994 [(set (match_operand 0 "" "")
7995 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
7996 (match_operand 2 "" "")))
7997 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
7998 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7999 "@
8000 br $31,$%1..ng
8001 lda $27,%1\;jmp $31,($27),%1"
8002 [(set_attr "type" "jsr")
8003 (set_attr "length" "*,8")])
8005 (define_insn "*call_value_nt_1"
8006 [(set (match_operand 0 "" "")
8007 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,s"))
8008 (match_operand 2 "" "")))
8009 (clobber (reg:DI 26))]
8010 "TARGET_ABI_WINDOWS_NT"
8011 "@
8012 jsr $26,(%1)
8013 bsr $26,%1
8014 jsr $26,%1"
8015 [(set_attr "type" "jsr")
8016 (set_attr "length" "*,*,12")])
8018 ; GAS relies on the order and position of instructions output below in order
8019 ; to generate relocs for VMS link to potentially optimize the call.
8020 ; Please do not molest.
8021 (define_insn "*call_value_vms_1"
8022 [(set (match_operand 0 "" "")
8023 (call (mem:DI (match_operand:DI 1 "call_operand" "r,s"))
8024 (match_operand 2 "" "")))
8025 (use (match_operand:DI 3 "nonmemory_operand" "r,n"))
8026 (use (reg:DI 25))
8027 (use (reg:DI 26))
8028 (clobber (reg:DI 27))]
8029 "TARGET_ABI_OPEN_VMS"
8030 {
8031 switch (which_alternative)
8032 {
8033 case 0:
8034 return "mov %3,$27\;jsr $26,0\;ldq $27,0($29)";
8035 case 1:
8036 operands [3] = alpha_use_linkage (operands [1], cfun->decl, 1, 0);
8037 operands [4] = alpha_use_linkage (operands [1], cfun->decl, 0, 0);
8038 return "ldq $26,%4\;ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)";
8039 default:
8040 gcc_unreachable ();
8041 }
8042 }
8043 [(set_attr "type" "jsr")
8044 (set_attr "length" "12,16")])
8046 (define_insn "*call_value_umk"
8047 [(set (match_operand 0 "" "")
8048 (call (mem:DI (match_operand:DI 1 "call_operand" "r"))
8049 (match_operand 2 "" "")))
8050 (use (reg:DI 25))
8051 (clobber (reg:DI 26))]
8052 "TARGET_ABI_UNICOSMK"
8053 "jsr $26,(%1)"
8054 [(set_attr "type" "jsr")])