| blob | 11964ddf3343a946c58274162e5d5b5cf25fb890 |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it
10 ;; under the terms of the GNU General Public License as published
11 ;; by the Free Software Foundation; either version 2, or (at your
12 ;; option) any later version.
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
15 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 ;; License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to the
21 ;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
22 ;; MA 02110-1301, USA.
24 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
26 ;;
27 ;; UNSPEC usage
28 ;;
30 (define_constants
31 [(UNSPEC_FRSP 0) ; frsp for POWER machines
32 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
33 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
34 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
35 (UNSPEC_MOVSI_GOT 8)
36 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
37 (UNSPEC_FCTIWZ 10)
38 (UNSPEC_FRIM 11)
39 (UNSPEC_FRIN 12)
40 (UNSPEC_FRIP 13)
41 (UNSPEC_FRIZ 14)
42 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
43 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
44 (UNSPEC_TLSGD 17)
45 (UNSPEC_TLSLD 18)
46 (UNSPEC_MOVESI_FROM_CR 19)
47 (UNSPEC_MOVESI_TO_CR 20)
48 (UNSPEC_TLSDTPREL 21)
49 (UNSPEC_TLSDTPRELHA 22)
50 (UNSPEC_TLSDTPRELLO 23)
51 (UNSPEC_TLSGOTDTPREL 24)
52 (UNSPEC_TLSTPREL 25)
53 (UNSPEC_TLSTPRELHA 26)
54 (UNSPEC_TLSTPRELLO 27)
55 (UNSPEC_TLSGOTTPREL 28)
56 (UNSPEC_TLSTLS 29)
57 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
58 (UNSPEC_MV_CR_GT 31) ; move_from_CR_eq_bit
59 (UNSPEC_STFIWX 32)
60 (UNSPEC_POPCNTB 33)
61 (UNSPEC_FRES 34)
62 (UNSPEC_SP_SET 35)
63 (UNSPEC_SP_TEST 36)
64 (UNSPEC_SYNC 37)
65 (UNSPEC_LWSYNC 38)
66 (UNSPEC_ISYNC 39)
67 (UNSPEC_SYNC_OP 40)
68 (UNSPEC_ATOMIC 41)
69 (UNSPEC_CMPXCHG 42)
70 (UNSPEC_XCHG 43)
71 (UNSPEC_AND 44)
72 ])
74 ;;
75 ;; UNSPEC_VOLATILE usage
76 ;;
78 (define_constants
79 [(UNSPECV_BLOCK 0)
80 (UNSPECV_LL 1) ; load-locked
81 (UNSPECV_SC 2) ; store-conditional
82 (UNSPECV_EH_RR 9) ; eh_reg_restore
83 ])
84 \f
85 ;; Define an insn type attribute. This is used in function unit delay
86 ;; computations.
87 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c"
88 (const_string "integer"))
90 ;; Length (in bytes).
91 ; '(pc)' in the following doesn't include the instruction itself; it is
92 ; calculated as if the instruction had zero size.
93 (define_attr "length" ""
94 (if_then_else (eq_attr "type" "branch")
95 (if_then_else (and (ge (minus (match_dup 0) (pc))
96 (const_int -32768))
97 (lt (minus (match_dup 0) (pc))
98 (const_int 32764)))
99 (const_int 4)
100 (const_int 8))
101 (const_int 4)))
103 ;; Processor type -- this attribute must exactly match the processor_type
104 ;; enumeration in rs6000.h.
106 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5"
107 (const (symbol_ref "rs6000_cpu_attr")))
109 (automata_option "ndfa")
111 (include "rios1.md")
112 (include "rios2.md")
113 (include "rs64.md")
114 (include "mpc.md")
115 (include "40x.md")
116 (include "440.md")
117 (include "603.md")
118 (include "6xx.md")
119 (include "7xx.md")
120 (include "7450.md")
121 (include "8540.md")
122 (include "power4.md")
123 (include "power5.md")
125 (include "predicates.md")
127 (include "darwin.md")
129 \f
130 ;; Mode macros
132 ; This mode macro allows :GPR to be used to indicate the allowable size
133 ; of whole values in GPRs.
134 (define_mode_macro GPR [SI (DI "TARGET_POWERPC64")])
136 ; Any supported integer mode.
137 (define_mode_macro INT [QI HI SI DI TI])
139 ; Any supported integer mode that fits in one register.
140 (define_mode_macro INT1 [QI HI SI (DI "TARGET_POWERPC64")])
142 ; extend modes for DImode
143 (define_mode_macro QHSI [QI HI SI])
145 ; SImode or DImode, even if DImode doesn't fit in GPRs.
146 (define_mode_macro SDI [SI DI])
148 ; The size of a pointer. Also, the size of the value that a record-condition
149 ; (one with a '.') will compare.
150 (define_mode_macro P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
152 ; Any hardware-supported floating-point mode
153 (define_mode_macro FP [(SF "TARGET_HARD_FLOAT")
154 (DF "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)")
155 (TF "!TARGET_IEEEQUAD
156 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128")])
158 ; Various instructions that come in SI and DI forms.
159 ; A generic w/d attribute, for things like cmpw/cmpd.
160 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
162 ; DImode bits
163 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
165 \f
166 ;; Start with fixed-point load and store insns. Here we put only the more
167 ;; complex forms. Basic data transfer is done later.
169 (define_expand "zero_extend<mode>di2"
170 [(set (match_operand:DI 0 "gpc_reg_operand" "")
171 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
172 "TARGET_POWERPC64"
173 "")
175 (define_insn "*zero_extend<mode>di2_internal1"
176 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
177 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
178 "TARGET_POWERPC64"
179 "@
180 l<wd>z%U1%X1 %0,%1
181 rldicl %0,%1,0,<dbits>"
182 [(set_attr "type" "load,*")])
184 (define_insn "*zero_extend<mode>di2_internal2"
185 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
186 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
187 (const_int 0)))
188 (clobber (match_scratch:DI 2 "=r,r"))]
189 "TARGET_64BIT"
190 "@
191 rldicl. %2,%1,0,<dbits>
192 #"
193 [(set_attr "type" "compare")
194 (set_attr "length" "4,8")])
196 (define_split
197 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
198 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
199 (const_int 0)))
200 (clobber (match_scratch:DI 2 ""))]
201 "TARGET_POWERPC64 && reload_completed"
202 [(set (match_dup 2)
203 (zero_extend:DI (match_dup 1)))
204 (set (match_dup 0)
205 (compare:CC (match_dup 2)
206 (const_int 0)))]
207 "")
209 (define_insn "*zero_extend<mode>di2_internal3"
210 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
211 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
212 (const_int 0)))
213 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
214 (zero_extend:DI (match_dup 1)))]
215 "TARGET_64BIT"
216 "@
217 rldicl. %0,%1,0,<dbits>
218 #"
219 [(set_attr "type" "compare")
220 (set_attr "length" "4,8")])
222 (define_split
223 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
224 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
225 (const_int 0)))
226 (set (match_operand:DI 0 "gpc_reg_operand" "")
227 (zero_extend:DI (match_dup 1)))]
228 "TARGET_POWERPC64 && reload_completed"
229 [(set (match_dup 0)
230 (zero_extend:DI (match_dup 1)))
231 (set (match_dup 2)
232 (compare:CC (match_dup 0)
233 (const_int 0)))]
234 "")
236 (define_insn "extendqidi2"
237 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
238 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
239 "TARGET_POWERPC64"
240 "extsb %0,%1")
242 (define_insn ""
243 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
244 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
245 (const_int 0)))
246 (clobber (match_scratch:DI 2 "=r,r"))]
247 "TARGET_64BIT"
248 "@
249 extsb. %2,%1
250 #"
251 [(set_attr "type" "compare")
252 (set_attr "length" "4,8")])
254 (define_split
255 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
256 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
257 (const_int 0)))
258 (clobber (match_scratch:DI 2 ""))]
259 "TARGET_POWERPC64 && reload_completed"
260 [(set (match_dup 2)
261 (sign_extend:DI (match_dup 1)))
262 (set (match_dup 0)
263 (compare:CC (match_dup 2)
264 (const_int 0)))]
265 "")
267 (define_insn ""
268 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
269 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
270 (const_int 0)))
271 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
272 (sign_extend:DI (match_dup 1)))]
273 "TARGET_64BIT"
274 "@
275 extsb. %0,%1
276 #"
277 [(set_attr "type" "compare")
278 (set_attr "length" "4,8")])
280 (define_split
281 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
282 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
283 (const_int 0)))
284 (set (match_operand:DI 0 "gpc_reg_operand" "")
285 (sign_extend:DI (match_dup 1)))]
286 "TARGET_POWERPC64 && reload_completed"
287 [(set (match_dup 0)
288 (sign_extend:DI (match_dup 1)))
289 (set (match_dup 2)
290 (compare:CC (match_dup 0)
291 (const_int 0)))]
292 "")
294 (define_expand "extendhidi2"
295 [(set (match_operand:DI 0 "gpc_reg_operand" "")
296 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
297 "TARGET_POWERPC64"
298 "")
300 (define_insn ""
301 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
302 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
303 "TARGET_POWERPC64"
304 "@
305 lha%U1%X1 %0,%1
306 extsh %0,%1"
307 [(set_attr "type" "load_ext,*")])
309 (define_insn ""
310 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
311 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
312 (const_int 0)))
313 (clobber (match_scratch:DI 2 "=r,r"))]
314 "TARGET_64BIT"
315 "@
316 extsh. %2,%1
317 #"
318 [(set_attr "type" "compare")
319 (set_attr "length" "4,8")])
321 (define_split
322 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
323 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
324 (const_int 0)))
325 (clobber (match_scratch:DI 2 ""))]
326 "TARGET_POWERPC64 && reload_completed"
327 [(set (match_dup 2)
328 (sign_extend:DI (match_dup 1)))
329 (set (match_dup 0)
330 (compare:CC (match_dup 2)
331 (const_int 0)))]
332 "")
334 (define_insn ""
335 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
336 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
337 (const_int 0)))
338 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
339 (sign_extend:DI (match_dup 1)))]
340 "TARGET_64BIT"
341 "@
342 extsh. %0,%1
343 #"
344 [(set_attr "type" "compare")
345 (set_attr "length" "4,8")])
347 (define_split
348 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
349 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
350 (const_int 0)))
351 (set (match_operand:DI 0 "gpc_reg_operand" "")
352 (sign_extend:DI (match_dup 1)))]
353 "TARGET_POWERPC64 && reload_completed"
354 [(set (match_dup 0)
355 (sign_extend:DI (match_dup 1)))
356 (set (match_dup 2)
357 (compare:CC (match_dup 0)
358 (const_int 0)))]
359 "")
361 (define_expand "extendsidi2"
362 [(set (match_operand:DI 0 "gpc_reg_operand" "")
363 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
364 "TARGET_POWERPC64"
365 "")
367 (define_insn ""
368 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
369 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
370 "TARGET_POWERPC64"
371 "@
372 lwa%U1%X1 %0,%1
373 extsw %0,%1"
374 [(set_attr "type" "load_ext,*")])
376 (define_insn ""
377 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
378 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
379 (const_int 0)))
380 (clobber (match_scratch:DI 2 "=r,r"))]
381 "TARGET_64BIT"
382 "@
383 extsw. %2,%1
384 #"
385 [(set_attr "type" "compare")
386 (set_attr "length" "4,8")])
388 (define_split
389 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
390 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
391 (const_int 0)))
392 (clobber (match_scratch:DI 2 ""))]
393 "TARGET_POWERPC64 && reload_completed"
394 [(set (match_dup 2)
395 (sign_extend:DI (match_dup 1)))
396 (set (match_dup 0)
397 (compare:CC (match_dup 2)
398 (const_int 0)))]
399 "")
401 (define_insn ""
402 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
403 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
404 (const_int 0)))
405 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
406 (sign_extend:DI (match_dup 1)))]
407 "TARGET_64BIT"
408 "@
409 extsw. %0,%1
410 #"
411 [(set_attr "type" "compare")
412 (set_attr "length" "4,8")])
414 (define_split
415 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
416 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
417 (const_int 0)))
418 (set (match_operand:DI 0 "gpc_reg_operand" "")
419 (sign_extend:DI (match_dup 1)))]
420 "TARGET_POWERPC64 && reload_completed"
421 [(set (match_dup 0)
422 (sign_extend:DI (match_dup 1)))
423 (set (match_dup 2)
424 (compare:CC (match_dup 0)
425 (const_int 0)))]
426 "")
428 (define_expand "zero_extendqisi2"
429 [(set (match_operand:SI 0 "gpc_reg_operand" "")
430 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
431 ""
432 "")
434 (define_insn ""
435 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
436 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
437 ""
438 "@
439 lbz%U1%X1 %0,%1
440 {rlinm|rlwinm} %0,%1,0,0xff"
441 [(set_attr "type" "load,*")])
443 (define_insn ""
444 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
445 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
446 (const_int 0)))
447 (clobber (match_scratch:SI 2 "=r,r"))]
448 ""
449 "@
450 {andil.|andi.} %2,%1,0xff
451 #"
452 [(set_attr "type" "compare")
453 (set_attr "length" "4,8")])
455 (define_split
456 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
457 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
458 (const_int 0)))
459 (clobber (match_scratch:SI 2 ""))]
460 "reload_completed"
461 [(set (match_dup 2)
462 (zero_extend:SI (match_dup 1)))
463 (set (match_dup 0)
464 (compare:CC (match_dup 2)
465 (const_int 0)))]
466 "")
468 (define_insn ""
469 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
470 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
471 (const_int 0)))
472 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
473 (zero_extend:SI (match_dup 1)))]
474 ""
475 "@
476 {andil.|andi.} %0,%1,0xff
477 #"
478 [(set_attr "type" "compare")
479 (set_attr "length" "4,8")])
481 (define_split
482 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
483 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
484 (const_int 0)))
485 (set (match_operand:SI 0 "gpc_reg_operand" "")
486 (zero_extend:SI (match_dup 1)))]
487 "reload_completed"
488 [(set (match_dup 0)
489 (zero_extend:SI (match_dup 1)))
490 (set (match_dup 2)
491 (compare:CC (match_dup 0)
492 (const_int 0)))]
493 "")
495 (define_expand "extendqisi2"
496 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
497 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
498 ""
499 "
500 {
501 if (TARGET_POWERPC)
502 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
503 else if (TARGET_POWER)
504 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
505 else
506 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
507 DONE;
508 }")
510 (define_insn "extendqisi2_ppc"
511 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
512 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
513 "TARGET_POWERPC"
514 "extsb %0,%1")
516 (define_insn ""
517 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
518 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
519 (const_int 0)))
520 (clobber (match_scratch:SI 2 "=r,r"))]
521 "TARGET_POWERPC"
522 "@
523 extsb. %2,%1
524 #"
525 [(set_attr "type" "compare")
526 (set_attr "length" "4,8")])
528 (define_split
529 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
530 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
531 (const_int 0)))
532 (clobber (match_scratch:SI 2 ""))]
533 "TARGET_POWERPC && reload_completed"
534 [(set (match_dup 2)
535 (sign_extend:SI (match_dup 1)))
536 (set (match_dup 0)
537 (compare:CC (match_dup 2)
538 (const_int 0)))]
539 "")
541 (define_insn ""
542 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
543 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
544 (const_int 0)))
545 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
546 (sign_extend:SI (match_dup 1)))]
547 "TARGET_POWERPC"
548 "@
549 extsb. %0,%1
550 #"
551 [(set_attr "type" "compare")
552 (set_attr "length" "4,8")])
554 (define_split
555 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
556 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
557 (const_int 0)))
558 (set (match_operand:SI 0 "gpc_reg_operand" "")
559 (sign_extend:SI (match_dup 1)))]
560 "TARGET_POWERPC && reload_completed"
561 [(set (match_dup 0)
562 (sign_extend:SI (match_dup 1)))
563 (set (match_dup 2)
564 (compare:CC (match_dup 0)
565 (const_int 0)))]
566 "")
568 (define_expand "extendqisi2_power"
569 [(parallel [(set (match_dup 2)
570 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
571 (const_int 24)))
572 (clobber (scratch:SI))])
573 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
574 (ashiftrt:SI (match_dup 2)
575 (const_int 24)))
576 (clobber (scratch:SI))])]
577 "TARGET_POWER"
578 "
579 { operands[1] = gen_lowpart (SImode, operands[1]);
580 operands[2] = gen_reg_rtx (SImode); }")
582 (define_expand "extendqisi2_no_power"
583 [(set (match_dup 2)
584 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
585 (const_int 24)))
586 (set (match_operand:SI 0 "gpc_reg_operand" "")
587 (ashiftrt:SI (match_dup 2)
588 (const_int 24)))]
589 "! TARGET_POWER && ! TARGET_POWERPC"
590 "
591 { operands[1] = gen_lowpart (SImode, operands[1]);
592 operands[2] = gen_reg_rtx (SImode); }")
594 (define_expand "zero_extendqihi2"
595 [(set (match_operand:HI 0 "gpc_reg_operand" "")
596 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
597 ""
598 "")
600 (define_insn ""
601 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
602 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
603 ""
604 "@
605 lbz%U1%X1 %0,%1
606 {rlinm|rlwinm} %0,%1,0,0xff"
607 [(set_attr "type" "load,*")])
609 (define_insn ""
610 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
611 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
612 (const_int 0)))
613 (clobber (match_scratch:HI 2 "=r,r"))]
614 ""
615 "@
616 {andil.|andi.} %2,%1,0xff
617 #"
618 [(set_attr "type" "compare")
619 (set_attr "length" "4,8")])
621 (define_split
622 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
623 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
624 (const_int 0)))
625 (clobber (match_scratch:HI 2 ""))]
626 "reload_completed"
627 [(set (match_dup 2)
628 (zero_extend:HI (match_dup 1)))
629 (set (match_dup 0)
630 (compare:CC (match_dup 2)
631 (const_int 0)))]
632 "")
634 (define_insn ""
635 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
636 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
637 (const_int 0)))
638 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
639 (zero_extend:HI (match_dup 1)))]
640 ""
641 "@
642 {andil.|andi.} %0,%1,0xff
643 #"
644 [(set_attr "type" "compare")
645 (set_attr "length" "4,8")])
647 (define_split
648 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
649 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
650 (const_int 0)))
651 (set (match_operand:HI 0 "gpc_reg_operand" "")
652 (zero_extend:HI (match_dup 1)))]
653 "reload_completed"
654 [(set (match_dup 0)
655 (zero_extend:HI (match_dup 1)))
656 (set (match_dup 2)
657 (compare:CC (match_dup 0)
658 (const_int 0)))]
659 "")
661 (define_expand "extendqihi2"
662 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
663 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
664 ""
665 "
666 {
667 if (TARGET_POWERPC)
668 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
669 else if (TARGET_POWER)
670 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
671 else
672 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
673 DONE;
674 }")
676 (define_insn "extendqihi2_ppc"
677 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
678 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
679 "TARGET_POWERPC"
680 "extsb %0,%1")
682 (define_insn ""
683 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
684 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
685 (const_int 0)))
686 (clobber (match_scratch:HI 2 "=r,r"))]
687 "TARGET_POWERPC"
688 "@
689 extsb. %2,%1
690 #"
691 [(set_attr "type" "compare")
692 (set_attr "length" "4,8")])
694 (define_split
695 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
696 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
697 (const_int 0)))
698 (clobber (match_scratch:HI 2 ""))]
699 "TARGET_POWERPC && reload_completed"
700 [(set (match_dup 2)
701 (sign_extend:HI (match_dup 1)))
702 (set (match_dup 0)
703 (compare:CC (match_dup 2)
704 (const_int 0)))]
705 "")
707 (define_insn ""
708 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
709 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
710 (const_int 0)))
711 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
712 (sign_extend:HI (match_dup 1)))]
713 "TARGET_POWERPC"
714 "@
715 extsb. %0,%1
716 #"
717 [(set_attr "type" "compare")
718 (set_attr "length" "4,8")])
720 (define_split
721 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
722 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
723 (const_int 0)))
724 (set (match_operand:HI 0 "gpc_reg_operand" "")
725 (sign_extend:HI (match_dup 1)))]
726 "TARGET_POWERPC && reload_completed"
727 [(set (match_dup 0)
728 (sign_extend:HI (match_dup 1)))
729 (set (match_dup 2)
730 (compare:CC (match_dup 0)
731 (const_int 0)))]
732 "")
734 (define_expand "extendqihi2_power"
735 [(parallel [(set (match_dup 2)
736 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
737 (const_int 24)))
738 (clobber (scratch:SI))])
739 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
740 (ashiftrt:SI (match_dup 2)
741 (const_int 24)))
742 (clobber (scratch:SI))])]
743 "TARGET_POWER"
744 "
745 { operands[0] = gen_lowpart (SImode, operands[0]);
746 operands[1] = gen_lowpart (SImode, operands[1]);
747 operands[2] = gen_reg_rtx (SImode); }")
749 (define_expand "extendqihi2_no_power"
750 [(set (match_dup 2)
751 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
752 (const_int 24)))
753 (set (match_operand:HI 0 "gpc_reg_operand" "")
754 (ashiftrt:SI (match_dup 2)
755 (const_int 24)))]
756 "! TARGET_POWER && ! TARGET_POWERPC"
757 "
758 { operands[0] = gen_lowpart (SImode, operands[0]);
759 operands[1] = gen_lowpart (SImode, operands[1]);
760 operands[2] = gen_reg_rtx (SImode); }")
762 (define_expand "zero_extendhisi2"
763 [(set (match_operand:SI 0 "gpc_reg_operand" "")
764 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
765 ""
766 "")
768 (define_insn ""
769 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
770 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
771 ""
772 "@
773 lhz%U1%X1 %0,%1
774 {rlinm|rlwinm} %0,%1,0,0xffff"
775 [(set_attr "type" "load,*")])
777 (define_insn ""
778 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
779 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
780 (const_int 0)))
781 (clobber (match_scratch:SI 2 "=r,r"))]
782 ""
783 "@
784 {andil.|andi.} %2,%1,0xffff
785 #"
786 [(set_attr "type" "compare")
787 (set_attr "length" "4,8")])
789 (define_split
790 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
791 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
792 (const_int 0)))
793 (clobber (match_scratch:SI 2 ""))]
794 "reload_completed"
795 [(set (match_dup 2)
796 (zero_extend:SI (match_dup 1)))
797 (set (match_dup 0)
798 (compare:CC (match_dup 2)
799 (const_int 0)))]
800 "")
802 (define_insn ""
803 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
804 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
805 (const_int 0)))
806 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
807 (zero_extend:SI (match_dup 1)))]
808 ""
809 "@
810 {andil.|andi.} %0,%1,0xffff
811 #"
812 [(set_attr "type" "compare")
813 (set_attr "length" "4,8")])
815 (define_split
816 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
817 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
818 (const_int 0)))
819 (set (match_operand:SI 0 "gpc_reg_operand" "")
820 (zero_extend:SI (match_dup 1)))]
821 "reload_completed"
822 [(set (match_dup 0)
823 (zero_extend:SI (match_dup 1)))
824 (set (match_dup 2)
825 (compare:CC (match_dup 0)
826 (const_int 0)))]
827 "")
829 (define_expand "extendhisi2"
830 [(set (match_operand:SI 0 "gpc_reg_operand" "")
831 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
832 ""
833 "")
835 (define_insn ""
836 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
837 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
838 ""
839 "@
840 lha%U1%X1 %0,%1
841 {exts|extsh} %0,%1"
842 [(set_attr "type" "load_ext,*")])
844 (define_insn ""
845 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
846 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
847 (const_int 0)))
848 (clobber (match_scratch:SI 2 "=r,r"))]
849 ""
850 "@
851 {exts.|extsh.} %2,%1
852 #"
853 [(set_attr "type" "compare")
854 (set_attr "length" "4,8")])
856 (define_split
857 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
858 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
859 (const_int 0)))
860 (clobber (match_scratch:SI 2 ""))]
861 "reload_completed"
862 [(set (match_dup 2)
863 (sign_extend:SI (match_dup 1)))
864 (set (match_dup 0)
865 (compare:CC (match_dup 2)
866 (const_int 0)))]
867 "")
869 (define_insn ""
870 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
871 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
872 (const_int 0)))
873 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
874 (sign_extend:SI (match_dup 1)))]
875 ""
876 "@
877 {exts.|extsh.} %0,%1
878 #"
879 [(set_attr "type" "compare")
880 (set_attr "length" "4,8")])
881 \f
882 (define_split
883 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
884 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
885 (const_int 0)))
886 (set (match_operand:SI 0 "gpc_reg_operand" "")
887 (sign_extend:SI (match_dup 1)))]
888 "reload_completed"
889 [(set (match_dup 0)
890 (sign_extend:SI (match_dup 1)))
891 (set (match_dup 2)
892 (compare:CC (match_dup 0)
893 (const_int 0)))]
894 "")
896 ;; Fixed-point arithmetic insns.
898 (define_expand "add<mode>3"
899 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
900 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
901 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
902 ""
903 "
904 {
905 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
906 {
907 if (non_short_cint_operand (operands[2], DImode))
908 FAIL;
909 }
910 else if (GET_CODE (operands[2]) == CONST_INT
911 && ! add_operand (operands[2], <MODE>mode))
912 {
913 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
914 ? operands[0] : gen_reg_rtx (<MODE>mode));
916 HOST_WIDE_INT val = INTVAL (operands[2]);
917 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
918 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
920 if (<MODE>mode == DImode && !CONST_OK_FOR_LETTER_P (rest, 'L'))
921 FAIL;
923 /* The ordering here is important for the prolog expander.
924 When space is allocated from the stack, adding 'low' first may
925 produce a temporary deallocation (which would be bad). */
926 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
927 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
928 DONE;
929 }
930 }")
932 ;; Discourage ai/addic because of carry but provide it in an alternative
933 ;; allowing register zero as source.
934 (define_insn "*add<mode>3_internal1"
935 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
936 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
937 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
938 ""
939 "@
940 {cax|add} %0,%1,%2
941 {cal %0,%2(%1)|addi %0,%1,%2}
942 {ai|addic} %0,%1,%2
943 {cau|addis} %0,%1,%v2"
944 [(set_attr "length" "4,4,4,4")])
946 (define_insn "addsi3_high"
947 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
948 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
949 (high:SI (match_operand 2 "" ""))))]
950 "TARGET_MACHO && !TARGET_64BIT"
951 "{cau|addis} %0,%1,ha16(%2)"
952 [(set_attr "length" "4")])
954 (define_insn "*add<mode>3_internal2"
955 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
956 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
957 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
958 (const_int 0)))
959 (clobber (match_scratch:P 3 "=r,r,r,r"))]
960 ""
961 "@
962 {cax.|add.} %3,%1,%2
963 {ai.|addic.} %3,%1,%2
964 #
965 #"
966 [(set_attr "type" "fast_compare,compare,compare,compare")
967 (set_attr "length" "4,4,8,8")])
969 (define_split
970 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
971 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
972 (match_operand:GPR 2 "reg_or_short_operand" ""))
973 (const_int 0)))
974 (clobber (match_scratch:GPR 3 ""))]
975 "reload_completed"
976 [(set (match_dup 3)
977 (plus:GPR (match_dup 1)
978 (match_dup 2)))
979 (set (match_dup 0)
980 (compare:CC (match_dup 3)
981 (const_int 0)))]
982 "")
984 (define_insn "*add<mode>3_internal3"
985 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
986 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
987 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
988 (const_int 0)))
989 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
990 (plus:P (match_dup 1)
991 (match_dup 2)))]
992 ""
993 "@
994 {cax.|add.} %0,%1,%2
995 {ai.|addic.} %0,%1,%2
996 #
997 #"
998 [(set_attr "type" "fast_compare,compare,compare,compare")
999 (set_attr "length" "4,4,8,8")])
1001 (define_split
1002 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1003 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1004 (match_operand:P 2 "reg_or_short_operand" ""))
1005 (const_int 0)))
1006 (set (match_operand:P 0 "gpc_reg_operand" "")
1007 (plus:P (match_dup 1) (match_dup 2)))]
1008 "reload_completed"
1009 [(set (match_dup 0)
1010 (plus:P (match_dup 1)
1011 (match_dup 2)))
1012 (set (match_dup 3)
1013 (compare:CC (match_dup 0)
1014 (const_int 0)))]
1015 "")
1017 ;; Split an add that we can't do in one insn into two insns, each of which
1018 ;; does one 16-bit part. This is used by combine. Note that the low-order
1019 ;; add should be last in case the result gets used in an address.
1021 (define_split
1022 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1023 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1024 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1025 ""
1026 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1027 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1028 "
1029 {
1030 HOST_WIDE_INT val = INTVAL (operands[2]);
1031 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1032 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1034 operands[4] = GEN_INT (low);
1035 if (<MODE>mode == SImode || CONST_OK_FOR_LETTER_P (rest, 'L'))
1036 operands[3] = GEN_INT (rest);
1037 else if (! no_new_pseudos)
1038 {
1039 operands[3] = gen_reg_rtx (DImode);
1040 emit_move_insn (operands[3], operands[2]);
1041 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1042 DONE;
1043 }
1044 else
1045 FAIL;
1046 }")
1048 (define_insn "one_cmpl<mode>2"
1049 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1050 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1051 ""
1052 "nor %0,%1,%1")
1054 (define_insn ""
1055 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1056 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1057 (const_int 0)))
1058 (clobber (match_scratch:P 2 "=r,r"))]
1059 ""
1060 "@
1061 nor. %2,%1,%1
1062 #"
1063 [(set_attr "type" "compare")
1064 (set_attr "length" "4,8")])
1066 (define_split
1067 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1068 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1069 (const_int 0)))
1070 (clobber (match_scratch:P 2 ""))]
1071 "reload_completed"
1072 [(set (match_dup 2)
1073 (not:P (match_dup 1)))
1074 (set (match_dup 0)
1075 (compare:CC (match_dup 2)
1076 (const_int 0)))]
1077 "")
1079 (define_insn ""
1080 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1081 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1082 (const_int 0)))
1083 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1084 (not:P (match_dup 1)))]
1085 ""
1086 "@
1087 nor. %0,%1,%1
1088 #"
1089 [(set_attr "type" "compare")
1090 (set_attr "length" "4,8")])
1092 (define_split
1093 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1094 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1095 (const_int 0)))
1096 (set (match_operand:P 0 "gpc_reg_operand" "")
1097 (not:P (match_dup 1)))]
1098 "reload_completed"
1099 [(set (match_dup 0)
1100 (not:P (match_dup 1)))
1101 (set (match_dup 2)
1102 (compare:CC (match_dup 0)
1103 (const_int 0)))]
1104 "")
1106 (define_insn ""
1107 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1108 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1109 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1110 "! TARGET_POWERPC"
1111 "{sf%I1|subf%I1c} %0,%2,%1")
1113 (define_insn ""
1114 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1115 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1116 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1117 "TARGET_POWERPC"
1118 "@
1119 subf %0,%2,%1
1120 subfic %0,%2,%1")
1122 (define_insn ""
1123 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1124 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1125 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1126 (const_int 0)))
1127 (clobber (match_scratch:SI 3 "=r,r"))]
1128 "! TARGET_POWERPC"
1129 "@
1130 {sf.|subfc.} %3,%2,%1
1131 #"
1132 [(set_attr "type" "compare")
1133 (set_attr "length" "4,8")])
1135 (define_insn ""
1136 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1137 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1138 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1139 (const_int 0)))
1140 (clobber (match_scratch:P 3 "=r,r"))]
1141 "TARGET_POWERPC"
1142 "@
1143 subf. %3,%2,%1
1144 #"
1145 [(set_attr "type" "fast_compare")
1146 (set_attr "length" "4,8")])
1148 (define_split
1149 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1150 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1151 (match_operand:P 2 "gpc_reg_operand" ""))
1152 (const_int 0)))
1153 (clobber (match_scratch:P 3 ""))]
1154 "reload_completed"
1155 [(set (match_dup 3)
1156 (minus:P (match_dup 1)
1157 (match_dup 2)))
1158 (set (match_dup 0)
1159 (compare:CC (match_dup 3)
1160 (const_int 0)))]
1161 "")
1163 (define_insn ""
1164 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1165 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1166 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1167 (const_int 0)))
1168 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1169 (minus:SI (match_dup 1) (match_dup 2)))]
1170 "! TARGET_POWERPC"
1171 "@
1172 {sf.|subfc.} %0,%2,%1
1173 #"
1174 [(set_attr "type" "compare")
1175 (set_attr "length" "4,8")])
1177 (define_insn ""
1178 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1179 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1180 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1181 (const_int 0)))
1182 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1183 (minus:P (match_dup 1)
1184 (match_dup 2)))]
1185 "TARGET_POWERPC"
1186 "@
1187 subf. %0,%2,%1
1188 #"
1189 [(set_attr "type" "fast_compare")
1190 (set_attr "length" "4,8")])
1192 (define_split
1193 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1194 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1195 (match_operand:P 2 "gpc_reg_operand" ""))
1196 (const_int 0)))
1197 (set (match_operand:P 0 "gpc_reg_operand" "")
1198 (minus:P (match_dup 1)
1199 (match_dup 2)))]
1200 "reload_completed"
1201 [(set (match_dup 0)
1202 (minus:P (match_dup 1)
1203 (match_dup 2)))
1204 (set (match_dup 3)
1205 (compare:CC (match_dup 0)
1206 (const_int 0)))]
1207 "")
1209 (define_expand "sub<mode>3"
1210 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1211 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1212 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1213 ""
1214 "
1215 {
1216 if (GET_CODE (operands[2]) == CONST_INT)
1217 {
1218 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1219 negate_rtx (<MODE>mode, operands[2])));
1220 DONE;
1221 }
1222 }")
1224 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1225 ;; instruction and some auxiliary computations. Then we just have a single
1226 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1227 ;; combine.
1229 (define_expand "sminsi3"
1230 [(set (match_dup 3)
1231 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1232 (match_operand:SI 2 "reg_or_short_operand" ""))
1233 (const_int 0)
1234 (minus:SI (match_dup 2) (match_dup 1))))
1235 (set (match_operand:SI 0 "gpc_reg_operand" "")
1236 (minus:SI (match_dup 2) (match_dup 3)))]
1237 "TARGET_POWER || TARGET_ISEL"
1238 "
1239 {
1240 if (TARGET_ISEL)
1241 {
1242 operands[2] = force_reg (SImode, operands[2]);
1243 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1244 DONE;
1245 }
1247 operands[3] = gen_reg_rtx (SImode);
1248 }")
1250 (define_split
1251 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1252 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1253 (match_operand:SI 2 "reg_or_short_operand" "")))
1254 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1255 "TARGET_POWER"
1256 [(set (match_dup 3)
1257 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1258 (const_int 0)
1259 (minus:SI (match_dup 2) (match_dup 1))))
1260 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1261 "")
1263 (define_expand "smaxsi3"
1264 [(set (match_dup 3)
1265 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1266 (match_operand:SI 2 "reg_or_short_operand" ""))
1267 (const_int 0)
1268 (minus:SI (match_dup 2) (match_dup 1))))
1269 (set (match_operand:SI 0 "gpc_reg_operand" "")
1270 (plus:SI (match_dup 3) (match_dup 1)))]
1271 "TARGET_POWER || TARGET_ISEL"
1272 "
1273 {
1274 if (TARGET_ISEL)
1275 {
1276 operands[2] = force_reg (SImode, operands[2]);
1277 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1278 DONE;
1279 }
1280 operands[3] = gen_reg_rtx (SImode);
1281 }")
1283 (define_split
1284 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1285 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1286 (match_operand:SI 2 "reg_or_short_operand" "")))
1287 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1288 "TARGET_POWER"
1289 [(set (match_dup 3)
1290 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1291 (const_int 0)
1292 (minus:SI (match_dup 2) (match_dup 1))))
1293 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1294 "")
1296 (define_expand "uminsi3"
1297 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1298 (match_dup 5)))
1299 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1300 (match_dup 5)))
1301 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1302 (const_int 0)
1303 (minus:SI (match_dup 4) (match_dup 3))))
1304 (set (match_operand:SI 0 "gpc_reg_operand" "")
1305 (minus:SI (match_dup 2) (match_dup 3)))]
1306 "TARGET_POWER || TARGET_ISEL"
1307 "
1308 {
1309 if (TARGET_ISEL)
1310 {
1311 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1312 DONE;
1313 }
1314 operands[3] = gen_reg_rtx (SImode);
1315 operands[4] = gen_reg_rtx (SImode);
1316 operands[5] = GEN_INT (-2147483647 - 1);
1317 }")
1319 (define_expand "umaxsi3"
1320 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1321 (match_dup 5)))
1322 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1323 (match_dup 5)))
1324 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1325 (const_int 0)
1326 (minus:SI (match_dup 4) (match_dup 3))))
1327 (set (match_operand:SI 0 "gpc_reg_operand" "")
1328 (plus:SI (match_dup 3) (match_dup 1)))]
1329 "TARGET_POWER || TARGET_ISEL"
1330 "
1331 {
1332 if (TARGET_ISEL)
1333 {
1334 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1335 DONE;
1336 }
1337 operands[3] = gen_reg_rtx (SImode);
1338 operands[4] = gen_reg_rtx (SImode);
1339 operands[5] = GEN_INT (-2147483647 - 1);
1340 }")
1342 (define_insn ""
1343 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1344 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1345 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1346 (const_int 0)
1347 (minus:SI (match_dup 2) (match_dup 1))))]
1348 "TARGET_POWER"
1349 "doz%I2 %0,%1,%2")
1351 (define_insn ""
1352 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1353 (compare:CC
1354 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1355 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1356 (const_int 0)
1357 (minus:SI (match_dup 2) (match_dup 1)))
1358 (const_int 0)))
1359 (clobber (match_scratch:SI 3 "=r,r"))]
1360 "TARGET_POWER"
1361 "@
1362 doz%I2. %3,%1,%2
1363 #"
1364 [(set_attr "type" "delayed_compare")
1365 (set_attr "length" "4,8")])
1367 (define_split
1368 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1369 (compare:CC
1370 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1371 (match_operand:SI 2 "reg_or_short_operand" ""))
1372 (const_int 0)
1373 (minus:SI (match_dup 2) (match_dup 1)))
1374 (const_int 0)))
1375 (clobber (match_scratch:SI 3 ""))]
1376 "TARGET_POWER && reload_completed"
1377 [(set (match_dup 3)
1378 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1379 (const_int 0)
1380 (minus:SI (match_dup 2) (match_dup 1))))
1381 (set (match_dup 0)
1382 (compare:CC (match_dup 3)
1383 (const_int 0)))]
1384 "")
1386 (define_insn ""
1387 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1388 (compare:CC
1389 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1390 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1391 (const_int 0)
1392 (minus:SI (match_dup 2) (match_dup 1)))
1393 (const_int 0)))
1394 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1395 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1396 (const_int 0)
1397 (minus:SI (match_dup 2) (match_dup 1))))]
1398 "TARGET_POWER"
1399 "@
1400 doz%I2. %0,%1,%2
1401 #"
1402 [(set_attr "type" "delayed_compare")
1403 (set_attr "length" "4,8")])
1405 (define_split
1406 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1407 (compare:CC
1408 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1409 (match_operand:SI 2 "reg_or_short_operand" ""))
1410 (const_int 0)
1411 (minus:SI (match_dup 2) (match_dup 1)))
1412 (const_int 0)))
1413 (set (match_operand:SI 0 "gpc_reg_operand" "")
1414 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1415 (const_int 0)
1416 (minus:SI (match_dup 2) (match_dup 1))))]
1417 "TARGET_POWER && reload_completed"
1418 [(set (match_dup 0)
1419 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1420 (const_int 0)
1421 (minus:SI (match_dup 2) (match_dup 1))))
1422 (set (match_dup 3)
1423 (compare:CC (match_dup 0)
1424 (const_int 0)))]
1425 "")
1427 ;; We don't need abs with condition code because such comparisons should
1428 ;; never be done.
1429 (define_expand "abssi2"
1430 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1431 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1432 ""
1433 "
1434 {
1435 if (TARGET_ISEL)
1436 {
1437 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
1438 DONE;
1439 }
1440 else if (! TARGET_POWER)
1441 {
1442 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1443 DONE;
1444 }
1445 }")
1447 (define_insn "*abssi2_power"
1448 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1449 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1450 "TARGET_POWER"
1451 "abs %0,%1")
1453 (define_insn_and_split "abssi2_isel"
1454 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1455 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
1456 (clobber (match_scratch:SI 2 "=&b"))
1457 (clobber (match_scratch:CC 3 "=y"))]
1458 "TARGET_ISEL"
1459 "#"
1460 "&& reload_completed"
1461 [(set (match_dup 2) (neg:SI (match_dup 1)))
1462 (set (match_dup 3)
1463 (compare:CC (match_dup 1)
1464 (const_int 0)))
1465 (set (match_dup 0)
1466 (if_then_else:SI (ge (match_dup 3)
1467 (const_int 0))
1468 (match_dup 1)
1469 (match_dup 2)))]
1470 "")
1472 (define_insn_and_split "abssi2_nopower"
1473 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1474 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1475 (clobber (match_scratch:SI 2 "=&r,&r"))]
1476 "! TARGET_POWER && ! TARGET_ISEL"
1477 "#"
1478 "&& reload_completed"
1479 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1480 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1481 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
1482 "")
1484 (define_insn "*nabs_power"
1485 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1486 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
1487 "TARGET_POWER"
1488 "nabs %0,%1")
1490 (define_insn_and_split "*nabs_nopower"
1491 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1492 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1493 (clobber (match_scratch:SI 2 "=&r,&r"))]
1494 "! TARGET_POWER"
1495 "#"
1496 "&& reload_completed"
1497 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1498 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1499 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
1500 "")
1502 (define_expand "neg<mode>2"
1503 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1504 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
1505 ""
1506 "")
1508 (define_insn "*neg<mode>2_internal"
1509 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1510 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1511 ""
1512 "neg %0,%1")
1514 (define_insn ""
1515 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1516 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1517 (const_int 0)))
1518 (clobber (match_scratch:P 2 "=r,r"))]
1519 ""
1520 "@
1521 neg. %2,%1
1522 #"
1523 [(set_attr "type" "fast_compare")
1524 (set_attr "length" "4,8")])
1526 (define_split
1527 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1528 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
1529 (const_int 0)))
1530 (clobber (match_scratch:P 2 ""))]
1531 "reload_completed"
1532 [(set (match_dup 2)
1533 (neg:P (match_dup 1)))
1534 (set (match_dup 0)
1535 (compare:CC (match_dup 2)
1536 (const_int 0)))]
1537 "")
1539 (define_insn ""
1540 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1541 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1542 (const_int 0)))
1543 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1544 (neg:P (match_dup 1)))]
1545 ""
1546 "@
1547 neg. %0,%1
1548 #"
1549 [(set_attr "type" "fast_compare")
1550 (set_attr "length" "4,8")])
1552 (define_split
1553 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1554 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
1555 (const_int 0)))
1556 (set (match_operand:P 0 "gpc_reg_operand" "")
1557 (neg:P (match_dup 1)))]
1558 "reload_completed"
1559 [(set (match_dup 0)
1560 (neg:P (match_dup 1)))
1561 (set (match_dup 2)
1562 (compare:CC (match_dup 0)
1563 (const_int 0)))]
1564 "")
1566 (define_insn "clz<mode>2"
1567 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1568 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1569 ""
1570 "{cntlz|cntlz<wd>} %0,%1")
1572 (define_expand "ctz<mode>2"
1573 [(set (match_dup 2)
1574 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
1575 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
1576 (match_dup 2)))
1577 (clobber (scratch:CC))])
1578 (set (match_dup 4) (clz:GPR (match_dup 3)))
1579 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1580 (minus:GPR (match_dup 5) (match_dup 4)))]
1581 ""
1582 {
1583 operands[2] = gen_reg_rtx (<MODE>mode);
1584 operands[3] = gen_reg_rtx (<MODE>mode);
1585 operands[4] = gen_reg_rtx (<MODE>mode);
1586 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
1587 })
1589 (define_expand "ffs<mode>2"
1590 [(set (match_dup 2)
1591 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
1592 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
1593 (match_dup 2)))
1594 (clobber (scratch:CC))])
1595 (set (match_dup 4) (clz:GPR (match_dup 3)))
1596 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1597 (minus:GPR (match_dup 5) (match_dup 4)))]
1598 ""
1599 {
1600 operands[2] = gen_reg_rtx (<MODE>mode);
1601 operands[3] = gen_reg_rtx (<MODE>mode);
1602 operands[4] = gen_reg_rtx (<MODE>mode);
1603 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
1604 })
1606 (define_expand "popcount<mode>2"
1607 [(set (match_dup 2)
1608 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
1609 UNSPEC_POPCNTB))
1610 (set (match_dup 3)
1611 (mult:GPR (match_dup 2) (match_dup 4)))
1612 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1613 (lshiftrt:GPR (match_dup 3) (match_dup 5)))]
1614 "TARGET_POPCNTB"
1615 {
1616 operands[2] = gen_reg_rtx (<MODE>mode);
1617 operands[3] = gen_reg_rtx (<MODE>mode);
1618 operands[4] = force_reg (<MODE>mode,
1619 <MODE>mode == SImode
1620 ? GEN_INT (0x01010101)
1621 : GEN_INT ((HOST_WIDE_INT)
1622 0x01010101 << 32 | 0x01010101));
1623 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 8);
1624 })
1626 (define_insn "popcntb<mode>2"
1627 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1628 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
1629 UNSPEC_POPCNTB))]
1630 "TARGET_POPCNTB"
1631 "popcntb %0,%1")
1633 (define_expand "mulsi3"
1634 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1635 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1636 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
1637 ""
1638 "
1639 {
1640 if (TARGET_POWER)
1641 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
1642 else
1643 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
1644 DONE;
1645 }")
1647 (define_insn "mulsi3_mq"
1648 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1649 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1650 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1651 (clobber (match_scratch:SI 3 "=q,q"))]
1652 "TARGET_POWER"
1653 "@
1654 {muls|mullw} %0,%1,%2
1655 {muli|mulli} %0,%1,%2"
1656 [(set (attr "type")
1657 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1658 (const_string "imul3")
1659 (match_operand:SI 2 "short_cint_operand" "")
1660 (const_string "imul2")]
1661 (const_string "imul")))])
1663 (define_insn "mulsi3_no_mq"
1664 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1665 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1666 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
1667 "! TARGET_POWER"
1668 "@
1669 {muls|mullw} %0,%1,%2
1670 {muli|mulli} %0,%1,%2"
1671 [(set (attr "type")
1672 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1673 (const_string "imul3")
1674 (match_operand:SI 2 "short_cint_operand" "")
1675 (const_string "imul2")]
1676 (const_string "imul")))])
1678 (define_insn "*mulsi3_mq_internal1"
1679 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1680 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1681 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1682 (const_int 0)))
1683 (clobber (match_scratch:SI 3 "=r,r"))
1684 (clobber (match_scratch:SI 4 "=q,q"))]
1685 "TARGET_POWER"
1686 "@
1687 {muls.|mullw.} %3,%1,%2
1688 #"
1689 [(set_attr "type" "imul_compare")
1690 (set_attr "length" "4,8")])
1692 (define_split
1693 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1694 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1695 (match_operand:SI 2 "gpc_reg_operand" ""))
1696 (const_int 0)))
1697 (clobber (match_scratch:SI 3 ""))
1698 (clobber (match_scratch:SI 4 ""))]
1699 "TARGET_POWER && reload_completed"
1700 [(parallel [(set (match_dup 3)
1701 (mult:SI (match_dup 1) (match_dup 2)))
1702 (clobber (match_dup 4))])
1703 (set (match_dup 0)
1704 (compare:CC (match_dup 3)
1705 (const_int 0)))]
1706 "")
1708 (define_insn "*mulsi3_no_mq_internal1"
1709 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1710 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1711 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1712 (const_int 0)))
1713 (clobber (match_scratch:SI 3 "=r,r"))]
1714 "! TARGET_POWER"
1715 "@
1716 {muls.|mullw.} %3,%1,%2
1717 #"
1718 [(set_attr "type" "imul_compare")
1719 (set_attr "length" "4,8")])
1721 (define_split
1722 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1723 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1724 (match_operand:SI 2 "gpc_reg_operand" ""))
1725 (const_int 0)))
1726 (clobber (match_scratch:SI 3 ""))]
1727 "! TARGET_POWER && reload_completed"
1728 [(set (match_dup 3)
1729 (mult:SI (match_dup 1) (match_dup 2)))
1730 (set (match_dup 0)
1731 (compare:CC (match_dup 3)
1732 (const_int 0)))]
1733 "")
1735 (define_insn "*mulsi3_mq_internal2"
1736 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1737 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1738 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1739 (const_int 0)))
1740 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1741 (mult:SI (match_dup 1) (match_dup 2)))
1742 (clobber (match_scratch:SI 4 "=q,q"))]
1743 "TARGET_POWER"
1744 "@
1745 {muls.|mullw.} %0,%1,%2
1746 #"
1747 [(set_attr "type" "imul_compare")
1748 (set_attr "length" "4,8")])
1750 (define_split
1751 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1752 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1753 (match_operand:SI 2 "gpc_reg_operand" ""))
1754 (const_int 0)))
1755 (set (match_operand:SI 0 "gpc_reg_operand" "")
1756 (mult:SI (match_dup 1) (match_dup 2)))
1757 (clobber (match_scratch:SI 4 ""))]
1758 "TARGET_POWER && reload_completed"
1759 [(parallel [(set (match_dup 0)
1760 (mult:SI (match_dup 1) (match_dup 2)))
1761 (clobber (match_dup 4))])
1762 (set (match_dup 3)
1763 (compare:CC (match_dup 0)
1764 (const_int 0)))]
1765 "")
1767 (define_insn "*mulsi3_no_mq_internal2"
1768 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1769 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1770 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1771 (const_int 0)))
1772 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1773 (mult:SI (match_dup 1) (match_dup 2)))]
1774 "! TARGET_POWER"
1775 "@
1776 {muls.|mullw.} %0,%1,%2
1777 #"
1778 [(set_attr "type" "imul_compare")
1779 (set_attr "length" "4,8")])
1781 (define_split
1782 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1783 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1784 (match_operand:SI 2 "gpc_reg_operand" ""))
1785 (const_int 0)))
1786 (set (match_operand:SI 0 "gpc_reg_operand" "")
1787 (mult:SI (match_dup 1) (match_dup 2)))]
1788 "! TARGET_POWER && reload_completed"
1789 [(set (match_dup 0)
1790 (mult:SI (match_dup 1) (match_dup 2)))
1791 (set (match_dup 3)
1792 (compare:CC (match_dup 0)
1793 (const_int 0)))]
1794 "")
1796 ;; Operand 1 is divided by operand 2; quotient goes to operand
1797 ;; 0 and remainder to operand 3.
1798 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
1800 (define_expand "divmodsi4"
1801 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1802 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1803 (match_operand:SI 2 "gpc_reg_operand" "")))
1804 (set (match_operand:SI 3 "register_operand" "")
1805 (mod:SI (match_dup 1) (match_dup 2)))])]
1806 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
1807 "
1808 {
1809 if (! TARGET_POWER && ! TARGET_POWERPC)
1810 {
1811 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1812 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1813 emit_insn (gen_divss_call ());
1814 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1815 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
1816 DONE;
1817 }
1818 }")
1820 (define_insn "*divmodsi4_internal"
1821 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1822 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1823 (match_operand:SI 2 "gpc_reg_operand" "r")))
1824 (set (match_operand:SI 3 "register_operand" "=q")
1825 (mod:SI (match_dup 1) (match_dup 2)))]
1826 "TARGET_POWER"
1827 "divs %0,%1,%2"
1828 [(set_attr "type" "idiv")])
1830 (define_expand "udiv<mode>3"
1831 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1832 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1833 (match_operand:GPR 2 "gpc_reg_operand" "")))]
1834 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
1835 "
1836 {
1837 if (! TARGET_POWER && ! TARGET_POWERPC)
1838 {
1839 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1840 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1841 emit_insn (gen_quous_call ());
1842 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1843 DONE;
1844 }
1845 else if (TARGET_POWER)
1846 {
1847 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
1848 DONE;
1849 }
1850 }")
1852 (define_insn "udivsi3_mq"
1853 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1854 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1855 (match_operand:SI 2 "gpc_reg_operand" "r")))
1856 (clobber (match_scratch:SI 3 "=q"))]
1857 "TARGET_POWERPC && TARGET_POWER"
1858 "divwu %0,%1,%2"
1859 [(set_attr "type" "idiv")])
1861 (define_insn "*udivsi3_no_mq"
1862 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1863 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
1864 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
1865 "TARGET_POWERPC && ! TARGET_POWER"
1866 "div<wd>u %0,%1,%2"
1867 [(set_attr "type" "idiv")])
1869 ;; For powers of two we can do srai/aze for divide and then adjust for
1870 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
1871 ;; used; for PowerPC, force operands into register and do a normal divide;
1872 ;; for AIX common-mode, use quoss call on register operands.
1873 (define_expand "div<mode>3"
1874 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1875 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1876 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
1877 ""
1878 "
1879 {
1880 if (GET_CODE (operands[2]) == CONST_INT
1881 && INTVAL (operands[2]) > 0
1882 && exact_log2 (INTVAL (operands[2])) >= 0)
1883 ;
1884 else if (TARGET_POWERPC)
1885 {
1886 operands[2] = force_reg (<MODE>mode, operands[2]);
1887 if (TARGET_POWER)
1888 {
1889 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
1890 DONE;
1891 }
1892 }
1893 else if (TARGET_POWER)
1894 FAIL;
1895 else
1896 {
1897 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1898 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1899 emit_insn (gen_quoss_call ());
1900 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1901 DONE;
1902 }
1903 }")
1905 (define_insn "divsi3_mq"
1906 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1907 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1908 (match_operand:SI 2 "gpc_reg_operand" "r")))
1909 (clobber (match_scratch:SI 3 "=q"))]
1910 "TARGET_POWERPC && TARGET_POWER"
1911 "divw %0,%1,%2"
1912 [(set_attr "type" "idiv")])
1914 (define_insn "*div<mode>3_no_mq"
1915 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1916 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
1917 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
1918 "TARGET_POWERPC && ! TARGET_POWER"
1919 "div<wd> %0,%1,%2"
1920 [(set_attr "type" "idiv")])
1922 (define_expand "mod<mode>3"
1923 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
1924 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
1925 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
1926 ""
1927 "
1928 {
1929 int i;
1930 rtx temp1;
1931 rtx temp2;
1933 if (GET_CODE (operands[2]) != CONST_INT
1934 || INTVAL (operands[2]) <= 0
1935 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
1936 FAIL;
1938 temp1 = gen_reg_rtx (<MODE>mode);
1939 temp2 = gen_reg_rtx (<MODE>mode);
1941 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
1942 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
1943 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
1944 DONE;
1945 }")
1947 (define_insn ""
1948 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1949 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
1950 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
1951 ""
1952 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
1953 [(set_attr "type" "two")
1954 (set_attr "length" "8")])
1956 (define_insn ""
1957 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1958 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1959 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
1960 (const_int 0)))
1961 (clobber (match_scratch:P 3 "=r,r"))]
1962 ""
1963 "@
1964 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
1965 #"
1966 [(set_attr "type" "compare")
1967 (set_attr "length" "8,12")])
1969 (define_split
1970 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1971 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1972 (match_operand:GPR 2 "exact_log2_cint_operand"
1973 ""))
1974 (const_int 0)))
1975 (clobber (match_scratch:GPR 3 ""))]
1976 "reload_completed"
1977 [(set (match_dup 3)
1978 (div:<MODE> (match_dup 1) (match_dup 2)))
1979 (set (match_dup 0)
1980 (compare:CC (match_dup 3)
1981 (const_int 0)))]
1982 "")
1984 (define_insn ""
1985 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1986 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1987 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
1988 (const_int 0)))
1989 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1990 (div:P (match_dup 1) (match_dup 2)))]
1991 ""
1992 "@
1993 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
1994 #"
1995 [(set_attr "type" "compare")
1996 (set_attr "length" "8,12")])
1998 (define_split
1999 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2000 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2001 (match_operand:GPR 2 "exact_log2_cint_operand"
2002 ""))
2003 (const_int 0)))
2004 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2005 (div:GPR (match_dup 1) (match_dup 2)))]
2006 "reload_completed"
2007 [(set (match_dup 0)
2008 (div:<MODE> (match_dup 1) (match_dup 2)))
2009 (set (match_dup 3)
2010 (compare:CC (match_dup 0)
2011 (const_int 0)))]
2012 "")
2014 (define_insn ""
2015 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2016 (udiv:SI
2017 (plus:DI (ashift:DI
2018 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2019 (const_int 32))
2020 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2021 (match_operand:SI 3 "gpc_reg_operand" "r")))
2022 (set (match_operand:SI 2 "register_operand" "=*q")
2023 (umod:SI
2024 (plus:DI (ashift:DI
2025 (zero_extend:DI (match_dup 1)) (const_int 32))
2026 (zero_extend:DI (match_dup 4)))
2027 (match_dup 3)))]
2028 "TARGET_POWER"
2029 "div %0,%1,%3"
2030 [(set_attr "type" "idiv")])
2032 ;; To do unsigned divide we handle the cases of the divisor looking like a
2033 ;; negative number. If it is a constant that is less than 2**31, we don't
2034 ;; have to worry about the branches. So make a few subroutines here.
2035 ;;
2036 ;; First comes the normal case.
2037 (define_expand "udivmodsi4_normal"
2038 [(set (match_dup 4) (const_int 0))
2039 (parallel [(set (match_operand:SI 0 "" "")
2040 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2041 (const_int 32))
2042 (zero_extend:DI (match_operand:SI 1 "" "")))
2043 (match_operand:SI 2 "" "")))
2044 (set (match_operand:SI 3 "" "")
2045 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2046 (const_int 32))
2047 (zero_extend:DI (match_dup 1)))
2048 (match_dup 2)))])]
2049 "TARGET_POWER"
2050 "
2051 { operands[4] = gen_reg_rtx (SImode); }")
2053 ;; This handles the branches.
2054 (define_expand "udivmodsi4_tests"
2055 [(set (match_operand:SI 0 "" "") (const_int 0))
2056 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2057 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2058 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2059 (label_ref (match_operand:SI 4 "" "")) (pc)))
2060 (set (match_dup 0) (const_int 1))
2061 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2062 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2063 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2064 (label_ref (match_dup 4)) (pc)))]
2065 "TARGET_POWER"
2066 "
2067 { operands[5] = gen_reg_rtx (CCUNSmode);
2068 operands[6] = gen_reg_rtx (CCmode);
2069 }")
2071 (define_expand "udivmodsi4"
2072 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2073 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2074 (match_operand:SI 2 "reg_or_cint_operand" "")))
2075 (set (match_operand:SI 3 "gpc_reg_operand" "")
2076 (umod:SI (match_dup 1) (match_dup 2)))])]
2077 ""
2078 "
2079 {
2080 rtx label = 0;
2082 if (! TARGET_POWER)
2083 {
2084 if (! TARGET_POWERPC)
2085 {
2086 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2087 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2088 emit_insn (gen_divus_call ());
2089 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2090 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2091 DONE;
2092 }
2093 else
2094 FAIL;
2095 }
2097 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2098 {
2099 operands[2] = force_reg (SImode, operands[2]);
2100 label = gen_label_rtx ();
2101 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2102 operands[3], label));
2103 }
2104 else
2105 operands[2] = force_reg (SImode, operands[2]);
2107 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2108 operands[3]));
2109 if (label)
2110 emit_label (label);
2112 DONE;
2113 }")
2115 ;; AIX architecture-independent common-mode multiply (DImode),
2116 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2117 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2118 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2119 ;; assumed unused if generating common-mode, so ignore.
2120 (define_insn "mulh_call"
2121 [(set (reg:SI 3)
2122 (truncate:SI
2123 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2124 (sign_extend:DI (reg:SI 4)))
2125 (const_int 32))))
2126 (clobber (match_scratch:SI 0 "=l"))]
2127 "! TARGET_POWER && ! TARGET_POWERPC"
2128 "bla __mulh"
2129 [(set_attr "type" "imul")])
2131 (define_insn "mull_call"
2132 [(set (reg:DI 3)
2133 (mult:DI (sign_extend:DI (reg:SI 3))
2134 (sign_extend:DI (reg:SI 4))))
2135 (clobber (match_scratch:SI 0 "=l"))
2136 (clobber (reg:SI 0))]
2137 "! TARGET_POWER && ! TARGET_POWERPC"
2138 "bla __mull"
2139 [(set_attr "type" "imul")])
2141 (define_insn "divss_call"
2142 [(set (reg:SI 3)
2143 (div:SI (reg:SI 3) (reg:SI 4)))
2144 (set (reg:SI 4)
2145 (mod:SI (reg:SI 3) (reg:SI 4)))
2146 (clobber (match_scratch:SI 0 "=l"))
2147 (clobber (reg:SI 0))]
2148 "! TARGET_POWER && ! TARGET_POWERPC"
2149 "bla __divss"
2150 [(set_attr "type" "idiv")])
2152 (define_insn "divus_call"
2153 [(set (reg:SI 3)
2154 (udiv:SI (reg:SI 3) (reg:SI 4)))
2155 (set (reg:SI 4)
2156 (umod:SI (reg:SI 3) (reg:SI 4)))
2157 (clobber (match_scratch:SI 0 "=l"))
2158 (clobber (reg:SI 0))
2159 (clobber (match_scratch:CC 1 "=x"))
2160 (clobber (reg:CC 69))]
2161 "! TARGET_POWER && ! TARGET_POWERPC"
2162 "bla __divus"
2163 [(set_attr "type" "idiv")])
2165 (define_insn "quoss_call"
2166 [(set (reg:SI 3)
2167 (div:SI (reg:SI 3) (reg:SI 4)))
2168 (clobber (match_scratch:SI 0 "=l"))]
2169 "! TARGET_POWER && ! TARGET_POWERPC"
2170 "bla __quoss"
2171 [(set_attr "type" "idiv")])
2173 (define_insn "quous_call"
2174 [(set (reg:SI 3)
2175 (udiv:SI (reg:SI 3) (reg:SI 4)))
2176 (clobber (match_scratch:SI 0 "=l"))
2177 (clobber (reg:SI 0))
2178 (clobber (match_scratch:CC 1 "=x"))
2179 (clobber (reg:CC 69))]
2180 "! TARGET_POWER && ! TARGET_POWERPC"
2181 "bla __quous"
2182 [(set_attr "type" "idiv")])
2183 \f
2184 ;; Logical instructions
2185 ;; The logical instructions are mostly combined by using match_operator,
2186 ;; but the plain AND insns are somewhat different because there is no
2187 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2188 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2190 (define_insn "andsi3"
2191 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2192 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2193 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2194 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2195 ""
2196 "@
2197 and %0,%1,%2
2198 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2199 {andil.|andi.} %0,%1,%b2
2200 {andiu.|andis.} %0,%1,%u2"
2201 [(set_attr "type" "*,*,compare,compare")])
2203 ;; Note to set cr's other than cr0 we do the and immediate and then
2204 ;; the test again -- this avoids a mfcr which on the higher end
2205 ;; machines causes an execution serialization
2207 (define_insn "*andsi3_internal2"
2208 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2209 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2210 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2211 (const_int 0)))
2212 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2213 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2214 "TARGET_32BIT"
2215 "@
2216 and. %3,%1,%2
2217 {andil.|andi.} %3,%1,%b2
2218 {andiu.|andis.} %3,%1,%u2
2219 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2220 #
2221 #
2222 #
2223 #"
2224 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2225 (set_attr "length" "4,4,4,4,8,8,8,8")])
2227 (define_insn "*andsi3_internal3"
2228 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2229 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2230 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2231 (const_int 0)))
2232 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2233 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2234 "TARGET_64BIT"
2235 "@
2236 #
2237 {andil.|andi.} %3,%1,%b2
2238 {andiu.|andis.} %3,%1,%u2
2239 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2240 #
2241 #
2242 #
2243 #"
2244 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2245 (set_attr "length" "8,4,4,4,8,8,8,8")])
2247 (define_split
2248 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2249 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2250 (match_operand:GPR 2 "and_operand" ""))
2251 (const_int 0)))
2252 (clobber (match_scratch:GPR 3 ""))
2253 (clobber (match_scratch:CC 4 ""))]
2254 "reload_completed"
2255 [(parallel [(set (match_dup 3)
2256 (and:<MODE> (match_dup 1)
2257 (match_dup 2)))
2258 (clobber (match_dup 4))])
2259 (set (match_dup 0)
2260 (compare:CC (match_dup 3)
2261 (const_int 0)))]
2262 "")
2264 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2265 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2267 (define_split
2268 [(set (match_operand:CC 0 "cc_reg_operand" "")
2269 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2270 (match_operand:SI 2 "gpc_reg_operand" ""))
2271 (const_int 0)))
2272 (clobber (match_scratch:SI 3 ""))
2273 (clobber (match_scratch:CC 4 ""))]
2274 "TARGET_POWERPC64 && reload_completed"
2275 [(parallel [(set (match_dup 3)
2276 (and:SI (match_dup 1)
2277 (match_dup 2)))
2278 (clobber (match_dup 4))])
2279 (set (match_dup 0)
2280 (compare:CC (match_dup 3)
2281 (const_int 0)))]
2282 "")
2284 (define_insn "*andsi3_internal4"
2285 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2286 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2287 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2288 (const_int 0)))
2289 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2290 (and:SI (match_dup 1)
2291 (match_dup 2)))
2292 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2293 "TARGET_32BIT"
2294 "@
2295 and. %0,%1,%2
2296 {andil.|andi.} %0,%1,%b2
2297 {andiu.|andis.} %0,%1,%u2
2298 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2299 #
2300 #
2301 #
2302 #"
2303 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2304 (set_attr "length" "4,4,4,4,8,8,8,8")])
2306 (define_insn "*andsi3_internal5"
2307 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2308 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2309 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2310 (const_int 0)))
2311 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2312 (and:SI (match_dup 1)
2313 (match_dup 2)))
2314 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2315 "TARGET_64BIT"
2316 "@
2317 #
2318 {andil.|andi.} %0,%1,%b2
2319 {andiu.|andis.} %0,%1,%u2
2320 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2321 #
2322 #
2323 #
2324 #"
2325 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2326 (set_attr "length" "8,4,4,4,8,8,8,8")])
2328 (define_split
2329 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2330 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2331 (match_operand:SI 2 "and_operand" ""))
2332 (const_int 0)))
2333 (set (match_operand:SI 0 "gpc_reg_operand" "")
2334 (and:SI (match_dup 1)
2335 (match_dup 2)))
2336 (clobber (match_scratch:CC 4 ""))]
2337 "reload_completed"
2338 [(parallel [(set (match_dup 0)
2339 (and:SI (match_dup 1)
2340 (match_dup 2)))
2341 (clobber (match_dup 4))])
2342 (set (match_dup 3)
2343 (compare:CC (match_dup 0)
2344 (const_int 0)))]
2345 "")
2347 (define_split
2348 [(set (match_operand:CC 3 "cc_reg_operand" "")
2349 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2350 (match_operand:SI 2 "gpc_reg_operand" ""))
2351 (const_int 0)))
2352 (set (match_operand:SI 0 "gpc_reg_operand" "")
2353 (and:SI (match_dup 1)
2354 (match_dup 2)))
2355 (clobber (match_scratch:CC 4 ""))]
2356 "TARGET_POWERPC64 && reload_completed"
2357 [(parallel [(set (match_dup 0)
2358 (and:SI (match_dup 1)
2359 (match_dup 2)))
2360 (clobber (match_dup 4))])
2361 (set (match_dup 3)
2362 (compare:CC (match_dup 0)
2363 (const_int 0)))]
2364 "")
2366 ;; Handle the PowerPC64 rlwinm corner case
2368 (define_insn_and_split "*andsi3_internal6"
2369 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2370 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2371 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2372 "TARGET_POWERPC64"
2373 "#"
2374 "TARGET_POWERPC64"
2375 [(set (match_dup 0)
2376 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2377 (match_dup 4)))
2378 (set (match_dup 0)
2379 (rotate:SI (match_dup 0) (match_dup 5)))]
2380 "
2381 {
2382 int mb = extract_MB (operands[2]);
2383 int me = extract_ME (operands[2]);
2384 operands[3] = GEN_INT (me + 1);
2385 operands[5] = GEN_INT (32 - (me + 1));
2386 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2387 }"
2388 [(set_attr "length" "8")])
2390 (define_expand "iorsi3"
2391 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2392 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2393 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2394 ""
2395 "
2396 {
2397 if (GET_CODE (operands[2]) == CONST_INT
2398 && ! logical_operand (operands[2], SImode))
2399 {
2400 HOST_WIDE_INT value = INTVAL (operands[2]);
2401 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2402 ? operands[0] : gen_reg_rtx (SImode));
2404 emit_insn (gen_iorsi3 (tmp, operands[1],
2405 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2406 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2407 DONE;
2408 }
2409 }")
2411 (define_expand "xorsi3"
2412 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2413 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2414 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2415 ""
2416 "
2417 {
2418 if (GET_CODE (operands[2]) == CONST_INT
2419 && ! logical_operand (operands[2], SImode))
2420 {
2421 HOST_WIDE_INT value = INTVAL (operands[2]);
2422 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2423 ? operands[0] : gen_reg_rtx (SImode));
2425 emit_insn (gen_xorsi3 (tmp, operands[1],
2426 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2427 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2428 DONE;
2429 }
2430 }")
2432 (define_insn "*boolsi3_internal1"
2433 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2434 (match_operator:SI 3 "boolean_or_operator"
2435 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2436 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
2437 ""
2438 "@
2439 %q3 %0,%1,%2
2440 {%q3il|%q3i} %0,%1,%b2
2441 {%q3iu|%q3is} %0,%1,%u2")
2443 (define_insn "*boolsi3_internal2"
2444 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2445 (compare:CC (match_operator:SI 4 "boolean_or_operator"
2446 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2447 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2448 (const_int 0)))
2449 (clobber (match_scratch:SI 3 "=r,r"))]
2450 "TARGET_32BIT"
2451 "@
2452 %q4. %3,%1,%2
2453 #"
2454 [(set_attr "type" "compare")
2455 (set_attr "length" "4,8")])
2457 (define_split
2458 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2459 (compare:CC (match_operator:SI 4 "boolean_operator"
2460 [(match_operand:SI 1 "gpc_reg_operand" "")
2461 (match_operand:SI 2 "gpc_reg_operand" "")])
2462 (const_int 0)))
2463 (clobber (match_scratch:SI 3 ""))]
2464 "TARGET_32BIT && reload_completed"
2465 [(set (match_dup 3) (match_dup 4))
2466 (set (match_dup 0)
2467 (compare:CC (match_dup 3)
2468 (const_int 0)))]
2469 "")
2471 (define_insn "*boolsi3_internal3"
2472 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2473 (compare:CC (match_operator:SI 4 "boolean_operator"
2474 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2475 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2476 (const_int 0)))
2477 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2478 (match_dup 4))]
2479 "TARGET_32BIT"
2480 "@
2481 %q4. %0,%1,%2
2482 #"
2483 [(set_attr "type" "compare")
2484 (set_attr "length" "4,8")])
2486 (define_split
2487 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2488 (compare:CC (match_operator:SI 4 "boolean_operator"
2489 [(match_operand:SI 1 "gpc_reg_operand" "")
2490 (match_operand:SI 2 "gpc_reg_operand" "")])
2491 (const_int 0)))
2492 (set (match_operand:SI 0 "gpc_reg_operand" "")
2493 (match_dup 4))]
2494 "TARGET_32BIT && reload_completed"
2495 [(set (match_dup 0) (match_dup 4))
2496 (set (match_dup 3)
2497 (compare:CC (match_dup 0)
2498 (const_int 0)))]
2499 "")
2501 ;; Split a logical operation that we can't do in one insn into two insns,
2502 ;; each of which does one 16-bit part. This is used by combine.
2504 (define_split
2505 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2506 (match_operator:SI 3 "boolean_or_operator"
2507 [(match_operand:SI 1 "gpc_reg_operand" "")
2508 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
2509 ""
2510 [(set (match_dup 0) (match_dup 4))
2511 (set (match_dup 0) (match_dup 5))]
2512 "
2513 {
2514 rtx i;
2515 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
2516 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2517 operands[1], i);
2518 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
2519 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2520 operands[0], i);
2521 }")
2523 (define_insn "*boolcsi3_internal1"
2524 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2525 (match_operator:SI 3 "boolean_operator"
2526 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2527 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
2528 ""
2529 "%q3 %0,%2,%1")
2531 (define_insn "*boolcsi3_internal2"
2532 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2533 (compare:CC (match_operator:SI 4 "boolean_operator"
2534 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2535 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2536 (const_int 0)))
2537 (clobber (match_scratch:SI 3 "=r,r"))]
2538 "TARGET_32BIT"
2539 "@
2540 %q4. %3,%2,%1
2541 #"
2542 [(set_attr "type" "compare")
2543 (set_attr "length" "4,8")])
2545 (define_split
2546 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2547 (compare:CC (match_operator:SI 4 "boolean_operator"
2548 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2549 (match_operand:SI 2 "gpc_reg_operand" "")])
2550 (const_int 0)))
2551 (clobber (match_scratch:SI 3 ""))]
2552 "TARGET_32BIT && reload_completed"
2553 [(set (match_dup 3) (match_dup 4))
2554 (set (match_dup 0)
2555 (compare:CC (match_dup 3)
2556 (const_int 0)))]
2557 "")
2559 (define_insn "*boolcsi3_internal3"
2560 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2561 (compare:CC (match_operator:SI 4 "boolean_operator"
2562 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2563 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2564 (const_int 0)))
2565 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2566 (match_dup 4))]
2567 "TARGET_32BIT"
2568 "@
2569 %q4. %0,%2,%1
2570 #"
2571 [(set_attr "type" "compare")
2572 (set_attr "length" "4,8")])
2574 (define_split
2575 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2576 (compare:CC (match_operator:SI 4 "boolean_operator"
2577 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2578 (match_operand:SI 2 "gpc_reg_operand" "")])
2579 (const_int 0)))
2580 (set (match_operand:SI 0 "gpc_reg_operand" "")
2581 (match_dup 4))]
2582 "TARGET_32BIT && reload_completed"
2583 [(set (match_dup 0) (match_dup 4))
2584 (set (match_dup 3)
2585 (compare:CC (match_dup 0)
2586 (const_int 0)))]
2587 "")
2589 (define_insn "*boolccsi3_internal1"
2590 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2591 (match_operator:SI 3 "boolean_operator"
2592 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2593 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
2594 ""
2595 "%q3 %0,%1,%2")
2597 (define_insn "*boolccsi3_internal2"
2598 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2599 (compare:CC (match_operator:SI 4 "boolean_operator"
2600 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2601 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2602 (const_int 0)))
2603 (clobber (match_scratch:SI 3 "=r,r"))]
2604 "TARGET_32BIT"
2605 "@
2606 %q4. %3,%1,%2
2607 #"
2608 [(set_attr "type" "compare")
2609 (set_attr "length" "4,8")])
2611 (define_split
2612 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2613 (compare:CC (match_operator:SI 4 "boolean_operator"
2614 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2615 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2616 (const_int 0)))
2617 (clobber (match_scratch:SI 3 ""))]
2618 "TARGET_32BIT && reload_completed"
2619 [(set (match_dup 3) (match_dup 4))
2620 (set (match_dup 0)
2621 (compare:CC (match_dup 3)
2622 (const_int 0)))]
2623 "")
2625 (define_insn "*boolccsi3_internal3"
2626 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2627 (compare:CC (match_operator:SI 4 "boolean_operator"
2628 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2629 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2630 (const_int 0)))
2631 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2632 (match_dup 4))]
2633 "TARGET_32BIT"
2634 "@
2635 %q4. %0,%1,%2
2636 #"
2637 [(set_attr "type" "compare")
2638 (set_attr "length" "4,8")])
2640 (define_split
2641 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2642 (compare:CC (match_operator:SI 4 "boolean_operator"
2643 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2644 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2645 (const_int 0)))
2646 (set (match_operand:SI 0 "gpc_reg_operand" "")
2647 (match_dup 4))]
2648 "TARGET_32BIT && reload_completed"
2649 [(set (match_dup 0) (match_dup 4))
2650 (set (match_dup 3)
2651 (compare:CC (match_dup 0)
2652 (const_int 0)))]
2653 "")
2655 ;; maskir insn. We need four forms because things might be in arbitrary
2656 ;; orders. Don't define forms that only set CR fields because these
2657 ;; would modify an input register.
2659 (define_insn "*maskir_internal1"
2660 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2661 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2662 (match_operand:SI 1 "gpc_reg_operand" "0"))
2663 (and:SI (match_dup 2)
2664 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
2665 "TARGET_POWER"
2666 "maskir %0,%3,%2")
2668 (define_insn "*maskir_internal2"
2669 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2670 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2671 (match_operand:SI 1 "gpc_reg_operand" "0"))
2672 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2673 (match_dup 2))))]
2674 "TARGET_POWER"
2675 "maskir %0,%3,%2")
2677 (define_insn "*maskir_internal3"
2678 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2679 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2680 (match_operand:SI 3 "gpc_reg_operand" "r"))
2681 (and:SI (not:SI (match_dup 2))
2682 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2683 "TARGET_POWER"
2684 "maskir %0,%3,%2")
2686 (define_insn "*maskir_internal4"
2687 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2688 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2689 (match_operand:SI 2 "gpc_reg_operand" "r"))
2690 (and:SI (not:SI (match_dup 2))
2691 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2692 "TARGET_POWER"
2693 "maskir %0,%3,%2")
2695 (define_insn "*maskir_internal5"
2696 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2697 (compare:CC
2698 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2699 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2700 (and:SI (match_dup 2)
2701 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
2702 (const_int 0)))
2703 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2704 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2705 (and:SI (match_dup 2) (match_dup 3))))]
2706 "TARGET_POWER"
2707 "@
2708 maskir. %0,%3,%2
2709 #"
2710 [(set_attr "type" "compare")
2711 (set_attr "length" "4,8")])
2713 (define_split
2714 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2715 (compare:CC
2716 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2717 (match_operand:SI 1 "gpc_reg_operand" ""))
2718 (and:SI (match_dup 2)
2719 (match_operand:SI 3 "gpc_reg_operand" "")))
2720 (const_int 0)))
2721 (set (match_operand:SI 0 "gpc_reg_operand" "")
2722 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2723 (and:SI (match_dup 2) (match_dup 3))))]
2724 "TARGET_POWER && reload_completed"
2725 [(set (match_dup 0)
2726 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2727 (and:SI (match_dup 2) (match_dup 3))))
2728 (set (match_dup 4)
2729 (compare:CC (match_dup 0)
2730 (const_int 0)))]
2731 "")
2733 (define_insn "*maskir_internal6"
2734 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2735 (compare:CC
2736 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2737 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2738 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2739 (match_dup 2)))
2740 (const_int 0)))
2741 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2742 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2743 (and:SI (match_dup 3) (match_dup 2))))]
2744 "TARGET_POWER"
2745 "@
2746 maskir. %0,%3,%2
2747 #"
2748 [(set_attr "type" "compare")
2749 (set_attr "length" "4,8")])
2751 (define_split
2752 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2753 (compare:CC
2754 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2755 (match_operand:SI 1 "gpc_reg_operand" ""))
2756 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2757 (match_dup 2)))
2758 (const_int 0)))
2759 (set (match_operand:SI 0 "gpc_reg_operand" "")
2760 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2761 (and:SI (match_dup 3) (match_dup 2))))]
2762 "TARGET_POWER && reload_completed"
2763 [(set (match_dup 0)
2764 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2765 (and:SI (match_dup 3) (match_dup 2))))
2766 (set (match_dup 4)
2767 (compare:CC (match_dup 0)
2768 (const_int 0)))]
2769 "")
2771 (define_insn "*maskir_internal7"
2772 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2773 (compare:CC
2774 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
2775 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
2776 (and:SI (not:SI (match_dup 2))
2777 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2778 (const_int 0)))
2779 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2780 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2781 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2782 "TARGET_POWER"
2783 "@
2784 maskir. %0,%3,%2
2785 #"
2786 [(set_attr "type" "compare")
2787 (set_attr "length" "4,8")])
2789 (define_split
2790 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2791 (compare:CC
2792 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
2793 (match_operand:SI 3 "gpc_reg_operand" ""))
2794 (and:SI (not:SI (match_dup 2))
2795 (match_operand:SI 1 "gpc_reg_operand" "")))
2796 (const_int 0)))
2797 (set (match_operand:SI 0 "gpc_reg_operand" "")
2798 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2799 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2800 "TARGET_POWER && reload_completed"
2801 [(set (match_dup 0)
2802 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2803 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2804 (set (match_dup 4)
2805 (compare:CC (match_dup 0)
2806 (const_int 0)))]
2807 "")
2809 (define_insn "*maskir_internal8"
2810 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2811 (compare:CC
2812 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2813 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2814 (and:SI (not:SI (match_dup 2))
2815 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2816 (const_int 0)))
2817 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2818 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2819 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2820 "TARGET_POWER"
2821 "@
2822 maskir. %0,%3,%2
2823 #"
2824 [(set_attr "type" "compare")
2825 (set_attr "length" "4,8")])
2827 (define_split
2828 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2829 (compare:CC
2830 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2831 (match_operand:SI 2 "gpc_reg_operand" ""))
2832 (and:SI (not:SI (match_dup 2))
2833 (match_operand:SI 1 "gpc_reg_operand" "")))
2834 (const_int 0)))
2835 (set (match_operand:SI 0 "gpc_reg_operand" "")
2836 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2837 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2838 "TARGET_POWER && reload_completed"
2839 [(set (match_dup 0)
2840 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2841 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2842 (set (match_dup 4)
2843 (compare:CC (match_dup 0)
2844 (const_int 0)))]
2845 "")
2846 \f
2847 ;; Rotate and shift insns, in all their variants. These support shifts,
2848 ;; field inserts and extracts, and various combinations thereof.
2849 (define_expand "insv"
2850 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
2851 (match_operand:SI 1 "const_int_operand" "")
2852 (match_operand:SI 2 "const_int_operand" ""))
2853 (match_operand 3 "gpc_reg_operand" ""))]
2854 ""
2855 "
2856 {
2857 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
2858 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2859 compiler if the address of the structure is taken later. Likewise, do
2860 not handle invalid E500 subregs. */
2861 if (GET_CODE (operands[0]) == SUBREG
2862 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
2863 || ((TARGET_E500_DOUBLE || TARGET_SPE)
2864 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
2865 FAIL;
2867 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
2868 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
2869 else
2870 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
2871 DONE;
2872 }")
2874 (define_insn "insvsi"
2875 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2876 (match_operand:SI 1 "const_int_operand" "i")
2877 (match_operand:SI 2 "const_int_operand" "i"))
2878 (match_operand:SI 3 "gpc_reg_operand" "r"))]
2879 ""
2880 "*
2881 {
2882 int start = INTVAL (operands[2]) & 31;
2883 int size = INTVAL (operands[1]) & 31;
2885 operands[4] = GEN_INT (32 - start - size);
2886 operands[1] = GEN_INT (start + size - 1);
2887 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2888 }"
2889 [(set_attr "type" "insert_word")])
2891 (define_insn "*insvsi_internal1"
2892 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2893 (match_operand:SI 1 "const_int_operand" "i")
2894 (match_operand:SI 2 "const_int_operand" "i"))
2895 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2896 (match_operand:SI 4 "const_int_operand" "i")))]
2897 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2898 "*
2899 {
2900 int shift = INTVAL (operands[4]) & 31;
2901 int start = INTVAL (operands[2]) & 31;
2902 int size = INTVAL (operands[1]) & 31;
2904 operands[4] = GEN_INT (shift - start - size);
2905 operands[1] = GEN_INT (start + size - 1);
2906 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2907 }"
2908 [(set_attr "type" "insert_word")])
2910 (define_insn "*insvsi_internal2"
2911 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2912 (match_operand:SI 1 "const_int_operand" "i")
2913 (match_operand:SI 2 "const_int_operand" "i"))
2914 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2915 (match_operand:SI 4 "const_int_operand" "i")))]
2916 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2917 "*
2918 {
2919 int shift = INTVAL (operands[4]) & 31;
2920 int start = INTVAL (operands[2]) & 31;
2921 int size = INTVAL (operands[1]) & 31;
2923 operands[4] = GEN_INT (32 - shift - start - size);
2924 operands[1] = GEN_INT (start + size - 1);
2925 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2926 }"
2927 [(set_attr "type" "insert_word")])
2929 (define_insn "*insvsi_internal3"
2930 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2931 (match_operand:SI 1 "const_int_operand" "i")
2932 (match_operand:SI 2 "const_int_operand" "i"))
2933 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2934 (match_operand:SI 4 "const_int_operand" "i")))]
2935 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2936 "*
2937 {
2938 int shift = INTVAL (operands[4]) & 31;
2939 int start = INTVAL (operands[2]) & 31;
2940 int size = INTVAL (operands[1]) & 31;
2942 operands[4] = GEN_INT (32 - shift - start - size);
2943 operands[1] = GEN_INT (start + size - 1);
2944 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2945 }"
2946 [(set_attr "type" "insert_word")])
2948 (define_insn "*insvsi_internal4"
2949 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2950 (match_operand:SI 1 "const_int_operand" "i")
2951 (match_operand:SI 2 "const_int_operand" "i"))
2952 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2953 (match_operand:SI 4 "const_int_operand" "i")
2954 (match_operand:SI 5 "const_int_operand" "i")))]
2955 "INTVAL (operands[4]) >= INTVAL (operands[1])"
2956 "*
2957 {
2958 int extract_start = INTVAL (operands[5]) & 31;
2959 int extract_size = INTVAL (operands[4]) & 31;
2960 int insert_start = INTVAL (operands[2]) & 31;
2961 int insert_size = INTVAL (operands[1]) & 31;
2963 /* Align extract field with insert field */
2964 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
2965 operands[1] = GEN_INT (insert_start + insert_size - 1);
2966 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
2967 }"
2968 [(set_attr "type" "insert_word")])
2970 ;; combine patterns for rlwimi
2971 (define_insn "*insvsi_internal5"
2972 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2973 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
2974 (match_operand:SI 1 "mask_operand" "i"))
2975 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2976 (match_operand:SI 2 "const_int_operand" "i"))
2977 (match_operand:SI 5 "mask_operand" "i"))))]
2978 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
2979 "*
2980 {
2981 int me = extract_ME(operands[5]);
2982 int mb = extract_MB(operands[5]);
2983 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
2984 operands[2] = GEN_INT(mb);
2985 operands[1] = GEN_INT(me);
2986 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2987 }"
2988 [(set_attr "type" "insert_word")])
2990 (define_insn "*insvsi_internal6"
2991 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2992 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2993 (match_operand:SI 2 "const_int_operand" "i"))
2994 (match_operand:SI 5 "mask_operand" "i"))
2995 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
2996 (match_operand:SI 1 "mask_operand" "i"))))]
2997 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
2998 "*
2999 {
3000 int me = extract_ME(operands[5]);
3001 int mb = extract_MB(operands[5]);
3002 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3003 operands[2] = GEN_INT(mb);
3004 operands[1] = GEN_INT(me);
3005 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3006 }"
3007 [(set_attr "type" "insert_word")])
3009 (define_insn "insvdi"
3010 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3011 (match_operand:SI 1 "const_int_operand" "i")
3012 (match_operand:SI 2 "const_int_operand" "i"))
3013 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3014 "TARGET_POWERPC64"
3015 "*
3016 {
3017 int start = INTVAL (operands[2]) & 63;
3018 int size = INTVAL (operands[1]) & 63;
3020 operands[1] = GEN_INT (64 - start - size);
3021 return \"rldimi %0,%3,%H1,%H2\";
3022 }")
3024 (define_insn "*insvdi_internal2"
3025 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3026 (match_operand:SI 1 "const_int_operand" "i")
3027 (match_operand:SI 2 "const_int_operand" "i"))
3028 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3029 (match_operand:SI 4 "const_int_operand" "i")))]
3030 "TARGET_POWERPC64
3031 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3032 "*
3033 {
3034 int shift = INTVAL (operands[4]) & 63;
3035 int start = (INTVAL (operands[2]) & 63) - 32;
3036 int size = INTVAL (operands[1]) & 63;
3038 operands[4] = GEN_INT (64 - shift - start - size);
3039 operands[2] = GEN_INT (start);
3040 operands[1] = GEN_INT (start + size - 1);
3041 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3042 }")
3044 (define_insn "*insvdi_internal3"
3045 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3046 (match_operand:SI 1 "const_int_operand" "i")
3047 (match_operand:SI 2 "const_int_operand" "i"))
3048 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3049 (match_operand:SI 4 "const_int_operand" "i")))]
3050 "TARGET_POWERPC64
3051 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3052 "*
3053 {
3054 int shift = INTVAL (operands[4]) & 63;
3055 int start = (INTVAL (operands[2]) & 63) - 32;
3056 int size = INTVAL (operands[1]) & 63;
3058 operands[4] = GEN_INT (64 - shift - start - size);
3059 operands[2] = GEN_INT (start);
3060 operands[1] = GEN_INT (start + size - 1);
3061 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3062 }")
3064 (define_expand "extzv"
3065 [(set (match_operand 0 "gpc_reg_operand" "")
3066 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3067 (match_operand:SI 2 "const_int_operand" "")
3068 (match_operand:SI 3 "const_int_operand" "")))]
3069 ""
3070 "
3071 {
3072 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3073 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3074 compiler if the address of the structure is taken later. */
3075 if (GET_CODE (operands[0]) == SUBREG
3076 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3077 FAIL;
3079 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3080 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3081 else
3082 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3083 DONE;
3084 }")
3086 (define_insn "extzvsi"
3087 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3088 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3089 (match_operand:SI 2 "const_int_operand" "i")
3090 (match_operand:SI 3 "const_int_operand" "i")))]
3091 ""
3092 "*
3093 {
3094 int start = INTVAL (operands[3]) & 31;
3095 int size = INTVAL (operands[2]) & 31;
3097 if (start + size >= 32)
3098 operands[3] = const0_rtx;
3099 else
3100 operands[3] = GEN_INT (start + size);
3101 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3102 }")
3104 (define_insn "*extzvsi_internal1"
3105 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3106 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3107 (match_operand:SI 2 "const_int_operand" "i,i")
3108 (match_operand:SI 3 "const_int_operand" "i,i"))
3109 (const_int 0)))
3110 (clobber (match_scratch:SI 4 "=r,r"))]
3111 ""
3112 "*
3113 {
3114 int start = INTVAL (operands[3]) & 31;
3115 int size = INTVAL (operands[2]) & 31;
3117 /* Force split for non-cc0 compare. */
3118 if (which_alternative == 1)
3119 return \"#\";
3121 /* If the bit-field being tested fits in the upper or lower half of a
3122 word, it is possible to use andiu. or andil. to test it. This is
3123 useful because the condition register set-use delay is smaller for
3124 andi[ul]. than for rlinm. This doesn't work when the starting bit
3125 position is 0 because the LT and GT bits may be set wrong. */
3127 if ((start > 0 && start + size <= 16) || start >= 16)
3128 {
3129 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3130 - (1 << (16 - (start & 15) - size))));
3131 if (start < 16)
3132 return \"{andiu.|andis.} %4,%1,%3\";
3133 else
3134 return \"{andil.|andi.} %4,%1,%3\";
3135 }
3137 if (start + size >= 32)
3138 operands[3] = const0_rtx;
3139 else
3140 operands[3] = GEN_INT (start + size);
3141 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3142 }"
3143 [(set_attr "type" "compare")
3144 (set_attr "length" "4,8")])
3146 (define_split
3147 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3148 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3149 (match_operand:SI 2 "const_int_operand" "")
3150 (match_operand:SI 3 "const_int_operand" ""))
3151 (const_int 0)))
3152 (clobber (match_scratch:SI 4 ""))]
3153 "reload_completed"
3154 [(set (match_dup 4)
3155 (zero_extract:SI (match_dup 1) (match_dup 2)
3156 (match_dup 3)))
3157 (set (match_dup 0)
3158 (compare:CC (match_dup 4)
3159 (const_int 0)))]
3160 "")
3162 (define_insn "*extzvsi_internal2"
3163 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3164 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3165 (match_operand:SI 2 "const_int_operand" "i,i")
3166 (match_operand:SI 3 "const_int_operand" "i,i"))
3167 (const_int 0)))
3168 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3169 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3170 ""
3171 "*
3172 {
3173 int start = INTVAL (operands[3]) & 31;
3174 int size = INTVAL (operands[2]) & 31;
3176 /* Force split for non-cc0 compare. */
3177 if (which_alternative == 1)
3178 return \"#\";
3180 /* Since we are using the output value, we can't ignore any need for
3181 a shift. The bit-field must end at the LSB. */
3182 if (start >= 16 && start + size == 32)
3183 {
3184 operands[3] = GEN_INT ((1 << size) - 1);
3185 return \"{andil.|andi.} %0,%1,%3\";
3186 }
3188 if (start + size >= 32)
3189 operands[3] = const0_rtx;
3190 else
3191 operands[3] = GEN_INT (start + size);
3192 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3193 }"
3194 [(set_attr "type" "compare")
3195 (set_attr "length" "4,8")])
3197 (define_split
3198 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3199 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3200 (match_operand:SI 2 "const_int_operand" "")
3201 (match_operand:SI 3 "const_int_operand" ""))
3202 (const_int 0)))
3203 (set (match_operand:SI 0 "gpc_reg_operand" "")
3204 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3205 "reload_completed"
3206 [(set (match_dup 0)
3207 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3208 (set (match_dup 4)
3209 (compare:CC (match_dup 0)
3210 (const_int 0)))]
3211 "")
3213 (define_insn "extzvdi"
3214 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3215 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3216 (match_operand:SI 2 "const_int_operand" "i")
3217 (match_operand:SI 3 "const_int_operand" "i")))]
3218 "TARGET_POWERPC64"
3219 "*
3220 {
3221 int start = INTVAL (operands[3]) & 63;
3222 int size = INTVAL (operands[2]) & 63;
3224 if (start + size >= 64)
3225 operands[3] = const0_rtx;
3226 else
3227 operands[3] = GEN_INT (start + size);
3228 operands[2] = GEN_INT (64 - size);
3229 return \"rldicl %0,%1,%3,%2\";
3230 }")
3232 (define_insn "*extzvdi_internal1"
3233 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3234 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3235 (match_operand:SI 2 "const_int_operand" "i")
3236 (match_operand:SI 3 "const_int_operand" "i"))
3237 (const_int 0)))
3238 (clobber (match_scratch:DI 4 "=r"))]
3239 "TARGET_64BIT"
3240 "*
3241 {
3242 int start = INTVAL (operands[3]) & 63;
3243 int size = INTVAL (operands[2]) & 63;
3245 if (start + size >= 64)
3246 operands[3] = const0_rtx;
3247 else
3248 operands[3] = GEN_INT (start + size);
3249 operands[2] = GEN_INT (64 - size);
3250 return \"rldicl. %4,%1,%3,%2\";
3251 }"
3252 [(set_attr "type" "compare")])
3254 (define_insn "*extzvdi_internal2"
3255 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3256 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3257 (match_operand:SI 2 "const_int_operand" "i")
3258 (match_operand:SI 3 "const_int_operand" "i"))
3259 (const_int 0)))
3260 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3261 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3262 "TARGET_64BIT"
3263 "*
3264 {
3265 int start = INTVAL (operands[3]) & 63;
3266 int size = INTVAL (operands[2]) & 63;
3268 if (start + size >= 64)
3269 operands[3] = const0_rtx;
3270 else
3271 operands[3] = GEN_INT (start + size);
3272 operands[2] = GEN_INT (64 - size);
3273 return \"rldicl. %0,%1,%3,%2\";
3274 }"
3275 [(set_attr "type" "compare")])
3277 (define_insn "rotlsi3"
3278 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3279 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3280 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3281 ""
3282 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
3284 (define_insn "*rotlsi3_internal2"
3285 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3286 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3287 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3288 (const_int 0)))
3289 (clobber (match_scratch:SI 3 "=r,r"))]
3290 ""
3291 "@
3292 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
3293 #"
3294 [(set_attr "type" "delayed_compare")
3295 (set_attr "length" "4,8")])
3297 (define_split
3298 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3299 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3300 (match_operand:SI 2 "reg_or_cint_operand" ""))
3301 (const_int 0)))
3302 (clobber (match_scratch:SI 3 ""))]
3303 "reload_completed"
3304 [(set (match_dup 3)
3305 (rotate:SI (match_dup 1) (match_dup 2)))
3306 (set (match_dup 0)
3307 (compare:CC (match_dup 3)
3308 (const_int 0)))]
3309 "")
3311 (define_insn "*rotlsi3_internal3"
3312 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3313 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3314 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3315 (const_int 0)))
3316 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3317 (rotate:SI (match_dup 1) (match_dup 2)))]
3318 ""
3319 "@
3320 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
3321 #"
3322 [(set_attr "type" "delayed_compare")
3323 (set_attr "length" "4,8")])
3325 (define_split
3326 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3327 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3328 (match_operand:SI 2 "reg_or_cint_operand" ""))
3329 (const_int 0)))
3330 (set (match_operand:SI 0 "gpc_reg_operand" "")
3331 (rotate:SI (match_dup 1) (match_dup 2)))]
3332 "reload_completed"
3333 [(set (match_dup 0)
3334 (rotate:SI (match_dup 1) (match_dup 2)))
3335 (set (match_dup 3)
3336 (compare:CC (match_dup 0)
3337 (const_int 0)))]
3338 "")
3340 (define_insn "*rotlsi3_internal4"
3341 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3342 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3343 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3344 (match_operand:SI 3 "mask_operand" "n")))]
3345 ""
3346 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
3348 (define_insn "*rotlsi3_internal5"
3349 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3350 (compare:CC (and:SI
3351 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3352 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3353 (match_operand:SI 3 "mask_operand" "n,n"))
3354 (const_int 0)))
3355 (clobber (match_scratch:SI 4 "=r,r"))]
3356 ""
3357 "@
3358 {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
3359 #"
3360 [(set_attr "type" "delayed_compare")
3361 (set_attr "length" "4,8")])
3363 (define_split
3364 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3365 (compare:CC (and:SI
3366 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3367 (match_operand:SI 2 "reg_or_cint_operand" ""))
3368 (match_operand:SI 3 "mask_operand" ""))
3369 (const_int 0)))
3370 (clobber (match_scratch:SI 4 ""))]
3371 "reload_completed"
3372 [(set (match_dup 4)
3373 (and:SI (rotate:SI (match_dup 1)
3374 (match_dup 2))
3375 (match_dup 3)))
3376 (set (match_dup 0)
3377 (compare:CC (match_dup 4)
3378 (const_int 0)))]
3379 "")
3381 (define_insn "*rotlsi3_internal6"
3382 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3383 (compare:CC (and:SI
3384 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3385 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3386 (match_operand:SI 3 "mask_operand" "n,n"))
3387 (const_int 0)))
3388 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3389 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3390 ""
3391 "@
3392 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
3393 #"
3394 [(set_attr "type" "delayed_compare")
3395 (set_attr "length" "4,8")])
3397 (define_split
3398 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3399 (compare:CC (and:SI
3400 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3401 (match_operand:SI 2 "reg_or_cint_operand" ""))
3402 (match_operand:SI 3 "mask_operand" ""))
3403 (const_int 0)))
3404 (set (match_operand:SI 0 "gpc_reg_operand" "")
3405 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3406 "reload_completed"
3407 [(set (match_dup 0)
3408 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3409 (set (match_dup 4)
3410 (compare:CC (match_dup 0)
3411 (const_int 0)))]
3412 "")
3414 (define_insn "*rotlsi3_internal7"
3415 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3416 (zero_extend:SI
3417 (subreg:QI
3418 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3419 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3420 ""
3421 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
3423 (define_insn "*rotlsi3_internal8"
3424 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3425 (compare:CC (zero_extend:SI
3426 (subreg:QI
3427 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3428 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3429 (const_int 0)))
3430 (clobber (match_scratch:SI 3 "=r,r"))]
3431 ""
3432 "@
3433 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff
3434 #"
3435 [(set_attr "type" "delayed_compare")
3436 (set_attr "length" "4,8")])
3438 (define_split
3439 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3440 (compare:CC (zero_extend:SI
3441 (subreg:QI
3442 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3443 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3444 (const_int 0)))
3445 (clobber (match_scratch:SI 3 ""))]
3446 "reload_completed"
3447 [(set (match_dup 3)
3448 (zero_extend:SI (subreg:QI
3449 (rotate:SI (match_dup 1)
3450 (match_dup 2)) 0)))
3451 (set (match_dup 0)
3452 (compare:CC (match_dup 3)
3453 (const_int 0)))]
3454 "")
3456 (define_insn "*rotlsi3_internal9"
3457 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3458 (compare:CC (zero_extend:SI
3459 (subreg:QI
3460 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3461 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3462 (const_int 0)))
3463 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3464 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3465 ""
3466 "@
3467 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff
3468 #"
3469 [(set_attr "type" "delayed_compare")
3470 (set_attr "length" "4,8")])
3472 (define_split
3473 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3474 (compare:CC (zero_extend:SI
3475 (subreg:QI
3476 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3477 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3478 (const_int 0)))
3479 (set (match_operand:SI 0 "gpc_reg_operand" "")
3480 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3481 "reload_completed"
3482 [(set (match_dup 0)
3483 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3484 (set (match_dup 3)
3485 (compare:CC (match_dup 0)
3486 (const_int 0)))]
3487 "")
3489 (define_insn "*rotlsi3_internal10"
3490 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3491 (zero_extend:SI
3492 (subreg:HI
3493 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3494 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3495 ""
3496 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
3498 (define_insn "*rotlsi3_internal11"
3499 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3500 (compare:CC (zero_extend:SI
3501 (subreg:HI
3502 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3503 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3504 (const_int 0)))
3505 (clobber (match_scratch:SI 3 "=r,r"))]
3506 ""
3507 "@
3508 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff
3509 #"
3510 [(set_attr "type" "delayed_compare")
3511 (set_attr "length" "4,8")])
3513 (define_split
3514 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3515 (compare:CC (zero_extend:SI
3516 (subreg:HI
3517 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3518 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3519 (const_int 0)))
3520 (clobber (match_scratch:SI 3 ""))]
3521 "reload_completed"
3522 [(set (match_dup 3)
3523 (zero_extend:SI (subreg:HI
3524 (rotate:SI (match_dup 1)
3525 (match_dup 2)) 0)))
3526 (set (match_dup 0)
3527 (compare:CC (match_dup 3)
3528 (const_int 0)))]
3529 "")
3531 (define_insn "*rotlsi3_internal12"
3532 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3533 (compare:CC (zero_extend:SI
3534 (subreg:HI
3535 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3536 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3537 (const_int 0)))
3538 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3539 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3540 ""
3541 "@
3542 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff
3543 #"
3544 [(set_attr "type" "delayed_compare")
3545 (set_attr "length" "4,8")])
3547 (define_split
3548 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3549 (compare:CC (zero_extend:SI
3550 (subreg:HI
3551 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3552 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3553 (const_int 0)))
3554 (set (match_operand:SI 0 "gpc_reg_operand" "")
3555 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3556 "reload_completed"
3557 [(set (match_dup 0)
3558 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3559 (set (match_dup 3)
3560 (compare:CC (match_dup 0)
3561 (const_int 0)))]
3562 "")
3564 ;; Note that we use "sle." instead of "sl." so that we can set
3565 ;; SHIFT_COUNT_TRUNCATED.
3567 (define_expand "ashlsi3"
3568 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3569 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3570 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3571 ""
3572 "
3573 {
3574 if (TARGET_POWER)
3575 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
3576 else
3577 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
3578 DONE;
3579 }")
3581 (define_insn "ashlsi3_power"
3582 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3583 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3584 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
3585 (clobber (match_scratch:SI 3 "=q,X"))]
3586 "TARGET_POWER"
3587 "@
3588 sle %0,%1,%2
3589 {sli|slwi} %0,%1,%h2")
3591 (define_insn "ashlsi3_no_power"
3592 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3593 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3594 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3595 "! TARGET_POWER"
3596 "{sl|slw}%I2 %0,%1,%h2")
3598 (define_insn ""
3599 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3600 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3601 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3602 (const_int 0)))
3603 (clobber (match_scratch:SI 3 "=r,r,r,r"))
3604 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3605 "TARGET_POWER"
3606 "@
3607 sle. %3,%1,%2
3608 {sli.|slwi.} %3,%1,%h2
3609 #
3610 #"
3611 [(set_attr "type" "delayed_compare")
3612 (set_attr "length" "4,4,8,8")])
3614 (define_split
3615 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3616 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3617 (match_operand:SI 2 "reg_or_cint_operand" ""))
3618 (const_int 0)))
3619 (clobber (match_scratch:SI 3 ""))
3620 (clobber (match_scratch:SI 4 ""))]
3621 "TARGET_POWER && reload_completed"
3622 [(parallel [(set (match_dup 3)
3623 (ashift:SI (match_dup 1) (match_dup 2)))
3624 (clobber (match_dup 4))])
3625 (set (match_dup 0)
3626 (compare:CC (match_dup 3)
3627 (const_int 0)))]
3628 "")
3630 (define_insn ""
3631 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3632 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3633 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3634 (const_int 0)))
3635 (clobber (match_scratch:SI 3 "=r,r"))]
3636 "! TARGET_POWER && TARGET_32BIT"
3637 "@
3638 {sl|slw}%I2. %3,%1,%h2
3639 #"
3640 [(set_attr "type" "delayed_compare")
3641 (set_attr "length" "4,8")])
3643 (define_split
3644 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3645 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3646 (match_operand:SI 2 "reg_or_cint_operand" ""))
3647 (const_int 0)))
3648 (clobber (match_scratch:SI 3 ""))]
3649 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3650 [(set (match_dup 3)
3651 (ashift:SI (match_dup 1) (match_dup 2)))
3652 (set (match_dup 0)
3653 (compare:CC (match_dup 3)
3654 (const_int 0)))]
3655 "")
3657 (define_insn ""
3658 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3659 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3660 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3661 (const_int 0)))
3662 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3663 (ashift:SI (match_dup 1) (match_dup 2)))
3664 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3665 "TARGET_POWER"
3666 "@
3667 sle. %0,%1,%2
3668 {sli.|slwi.} %0,%1,%h2
3669 #
3670 #"
3671 [(set_attr "type" "delayed_compare")
3672 (set_attr "length" "4,4,8,8")])
3674 (define_split
3675 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3676 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3677 (match_operand:SI 2 "reg_or_cint_operand" ""))
3678 (const_int 0)))
3679 (set (match_operand:SI 0 "gpc_reg_operand" "")
3680 (ashift:SI (match_dup 1) (match_dup 2)))
3681 (clobber (match_scratch:SI 4 ""))]
3682 "TARGET_POWER && reload_completed"
3683 [(parallel [(set (match_dup 0)
3684 (ashift:SI (match_dup 1) (match_dup 2)))
3685 (clobber (match_dup 4))])
3686 (set (match_dup 3)
3687 (compare:CC (match_dup 0)
3688 (const_int 0)))]
3689 "")
3691 (define_insn ""
3692 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3693 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3694 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3695 (const_int 0)))
3696 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3697 (ashift:SI (match_dup 1) (match_dup 2)))]
3698 "! TARGET_POWER && TARGET_32BIT"
3699 "@
3700 {sl|slw}%I2. %0,%1,%h2
3701 #"
3702 [(set_attr "type" "delayed_compare")
3703 (set_attr "length" "4,8")])
3705 (define_split
3706 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3707 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3708 (match_operand:SI 2 "reg_or_cint_operand" ""))
3709 (const_int 0)))
3710 (set (match_operand:SI 0 "gpc_reg_operand" "")
3711 (ashift:SI (match_dup 1) (match_dup 2)))]
3712 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3713 [(set (match_dup 0)
3714 (ashift:SI (match_dup 1) (match_dup 2)))
3715 (set (match_dup 3)
3716 (compare:CC (match_dup 0)
3717 (const_int 0)))]
3718 "")
3720 (define_insn "rlwinm"
3721 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3722 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3723 (match_operand:SI 2 "const_int_operand" "i"))
3724 (match_operand:SI 3 "mask_operand" "n")))]
3725 "includes_lshift_p (operands[2], operands[3])"
3726 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
3728 (define_insn ""
3729 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3730 (compare:CC
3731 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3732 (match_operand:SI 2 "const_int_operand" "i,i"))
3733 (match_operand:SI 3 "mask_operand" "n,n"))
3734 (const_int 0)))
3735 (clobber (match_scratch:SI 4 "=r,r"))]
3736 "includes_lshift_p (operands[2], operands[3])"
3737 "@
3738 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3739 #"
3740 [(set_attr "type" "delayed_compare")
3741 (set_attr "length" "4,8")])
3743 (define_split
3744 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3745 (compare:CC
3746 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3747 (match_operand:SI 2 "const_int_operand" ""))
3748 (match_operand:SI 3 "mask_operand" ""))
3749 (const_int 0)))
3750 (clobber (match_scratch:SI 4 ""))]
3751 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3752 [(set (match_dup 4)
3753 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
3754 (match_dup 3)))
3755 (set (match_dup 0)
3756 (compare:CC (match_dup 4)
3757 (const_int 0)))]
3758 "")
3760 (define_insn ""
3761 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3762 (compare:CC
3763 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3764 (match_operand:SI 2 "const_int_operand" "i,i"))
3765 (match_operand:SI 3 "mask_operand" "n,n"))
3766 (const_int 0)))
3767 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3768 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3769 "includes_lshift_p (operands[2], operands[3])"
3770 "@
3771 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
3772 #"
3773 [(set_attr "type" "delayed_compare")
3774 (set_attr "length" "4,8")])
3776 (define_split
3777 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3778 (compare:CC
3779 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3780 (match_operand:SI 2 "const_int_operand" ""))
3781 (match_operand:SI 3 "mask_operand" ""))
3782 (const_int 0)))
3783 (set (match_operand:SI 0 "gpc_reg_operand" "")
3784 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3785 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3786 [(set (match_dup 0)
3787 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3788 (set (match_dup 4)
3789 (compare:CC (match_dup 0)
3790 (const_int 0)))]
3791 "")
3793 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
3794 ;; "sli x,x,0".
3795 (define_expand "lshrsi3"
3796 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3797 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3798 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3799 ""
3800 "
3801 {
3802 if (TARGET_POWER)
3803 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
3804 else
3805 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
3806 DONE;
3807 }")
3809 (define_insn "lshrsi3_power"
3810 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3811 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
3812 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
3813 (clobber (match_scratch:SI 3 "=q,X,X"))]
3814 "TARGET_POWER"
3815 "@
3816 sre %0,%1,%2
3817 mr %0,%1
3818 {s%A2i|s%A2wi} %0,%1,%h2")
3820 (define_insn "lshrsi3_no_power"
3821 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3822 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3823 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
3824 "! TARGET_POWER"
3825 "@
3826 mr %0,%1
3827 {sr|srw}%I2 %0,%1,%h2")
3829 (define_insn ""
3830 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3831 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3832 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
3833 (const_int 0)))
3834 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
3835 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
3836 "TARGET_POWER"
3837 "@
3838 sre. %3,%1,%2
3839 mr. %1,%1
3840 {s%A2i.|s%A2wi.} %3,%1,%h2
3841 #
3842 #
3843 #"
3844 [(set_attr "type" "delayed_compare")
3845 (set_attr "length" "4,4,4,8,8,8")])
3847 (define_split
3848 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3849 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3850 (match_operand:SI 2 "reg_or_cint_operand" ""))
3851 (const_int 0)))
3852 (clobber (match_scratch:SI 3 ""))
3853 (clobber (match_scratch:SI 4 ""))]
3854 "TARGET_POWER && reload_completed"
3855 [(parallel [(set (match_dup 3)
3856 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3857 (clobber (match_dup 4))])
3858 (set (match_dup 0)
3859 (compare:CC (match_dup 3)
3860 (const_int 0)))]
3861 "")
3863 (define_insn ""
3864 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3865 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3866 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
3867 (const_int 0)))
3868 (clobber (match_scratch:SI 3 "=X,r,X,r"))]
3869 "! TARGET_POWER && TARGET_32BIT"
3870 "@
3871 mr. %1,%1
3872 {sr|srw}%I2. %3,%1,%h2
3873 #
3874 #"
3875 [(set_attr "type" "delayed_compare")
3876 (set_attr "length" "4,4,8,8")])
3878 (define_split
3879 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3880 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3881 (match_operand:SI 2 "reg_or_cint_operand" ""))
3882 (const_int 0)))
3883 (clobber (match_scratch:SI 3 ""))]
3884 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3885 [(set (match_dup 3)
3886 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3887 (set (match_dup 0)
3888 (compare:CC (match_dup 3)
3889 (const_int 0)))]
3890 "")
3892 (define_insn ""
3893 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3894 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3895 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
3896 (const_int 0)))
3897 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
3898 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3899 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
3900 "TARGET_POWER"
3901 "@
3902 sre. %0,%1,%2
3903 mr. %0,%1
3904 {s%A2i.|s%A2wi.} %0,%1,%h2
3905 #
3906 #
3907 #"
3908 [(set_attr "type" "delayed_compare")
3909 (set_attr "length" "4,4,4,8,8,8")])
3911 (define_split
3912 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3913 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3914 (match_operand:SI 2 "reg_or_cint_operand" ""))
3915 (const_int 0)))
3916 (set (match_operand:SI 0 "gpc_reg_operand" "")
3917 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3918 (clobber (match_scratch:SI 4 ""))]
3919 "TARGET_POWER && reload_completed"
3920 [(parallel [(set (match_dup 0)
3921 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3922 (clobber (match_dup 4))])
3923 (set (match_dup 3)
3924 (compare:CC (match_dup 0)
3925 (const_int 0)))]
3926 "")
3928 (define_insn ""
3929 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3930 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3931 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
3932 (const_int 0)))
3933 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3934 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
3935 "! TARGET_POWER && TARGET_32BIT"
3936 "@
3937 mr. %0,%1
3938 {sr|srw}%I2. %0,%1,%h2
3939 #
3940 #"
3941 [(set_attr "type" "delayed_compare")
3942 (set_attr "length" "4,4,8,8")])
3944 (define_split
3945 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3946 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3947 (match_operand:SI 2 "reg_or_cint_operand" ""))
3948 (const_int 0)))
3949 (set (match_operand:SI 0 "gpc_reg_operand" "")
3950 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
3951 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3952 [(set (match_dup 0)
3953 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3954 (set (match_dup 3)
3955 (compare:CC (match_dup 0)
3956 (const_int 0)))]
3957 "")
3959 (define_insn ""
3960 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3961 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3962 (match_operand:SI 2 "const_int_operand" "i"))
3963 (match_operand:SI 3 "mask_operand" "n")))]
3964 "includes_rshift_p (operands[2], operands[3])"
3965 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
3967 (define_insn ""
3968 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3969 (compare:CC
3970 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3971 (match_operand:SI 2 "const_int_operand" "i,i"))
3972 (match_operand:SI 3 "mask_operand" "n,n"))
3973 (const_int 0)))
3974 (clobber (match_scratch:SI 4 "=r,r"))]
3975 "includes_rshift_p (operands[2], operands[3])"
3976 "@
3977 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
3978 #"
3979 [(set_attr "type" "delayed_compare")
3980 (set_attr "length" "4,8")])
3982 (define_split
3983 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3984 (compare:CC
3985 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3986 (match_operand:SI 2 "const_int_operand" ""))
3987 (match_operand:SI 3 "mask_operand" ""))
3988 (const_int 0)))
3989 (clobber (match_scratch:SI 4 ""))]
3990 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
3991 [(set (match_dup 4)
3992 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
3993 (match_dup 3)))
3994 (set (match_dup 0)
3995 (compare:CC (match_dup 4)
3996 (const_int 0)))]
3997 "")
3999 (define_insn ""
4000 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4001 (compare:CC
4002 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4003 (match_operand:SI 2 "const_int_operand" "i,i"))
4004 (match_operand:SI 3 "mask_operand" "n,n"))
4005 (const_int 0)))
4006 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4007 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4008 "includes_rshift_p (operands[2], operands[3])"
4009 "@
4010 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4011 #"
4012 [(set_attr "type" "delayed_compare")
4013 (set_attr "length" "4,8")])
4015 (define_split
4016 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4017 (compare:CC
4018 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4019 (match_operand:SI 2 "const_int_operand" ""))
4020 (match_operand:SI 3 "mask_operand" ""))
4021 (const_int 0)))
4022 (set (match_operand:SI 0 "gpc_reg_operand" "")
4023 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4024 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4025 [(set (match_dup 0)
4026 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4027 (set (match_dup 4)
4028 (compare:CC (match_dup 0)
4029 (const_int 0)))]
4030 "")
4032 (define_insn ""
4033 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4034 (zero_extend:SI
4035 (subreg:QI
4036 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4037 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4038 "includes_rshift_p (operands[2], GEN_INT (255))"
4039 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4041 (define_insn ""
4042 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4043 (compare:CC
4044 (zero_extend:SI
4045 (subreg:QI
4046 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4047 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4048 (const_int 0)))
4049 (clobber (match_scratch:SI 3 "=r,r"))]
4050 "includes_rshift_p (operands[2], GEN_INT (255))"
4051 "@
4052 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4053 #"
4054 [(set_attr "type" "delayed_compare")
4055 (set_attr "length" "4,8")])
4057 (define_split
4058 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4059 (compare:CC
4060 (zero_extend:SI
4061 (subreg:QI
4062 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4063 (match_operand:SI 2 "const_int_operand" "")) 0))
4064 (const_int 0)))
4065 (clobber (match_scratch:SI 3 ""))]
4066 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4067 [(set (match_dup 3)
4068 (zero_extend:SI (subreg:QI
4069 (lshiftrt:SI (match_dup 1)
4070 (match_dup 2)) 0)))
4071 (set (match_dup 0)
4072 (compare:CC (match_dup 3)
4073 (const_int 0)))]
4074 "")
4076 (define_insn ""
4077 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4078 (compare:CC
4079 (zero_extend:SI
4080 (subreg:QI
4081 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4082 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4083 (const_int 0)))
4084 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4085 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4086 "includes_rshift_p (operands[2], GEN_INT (255))"
4087 "@
4088 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4089 #"
4090 [(set_attr "type" "delayed_compare")
4091 (set_attr "length" "4,8")])
4093 (define_split
4094 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4095 (compare:CC
4096 (zero_extend:SI
4097 (subreg:QI
4098 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4099 (match_operand:SI 2 "const_int_operand" "")) 0))
4100 (const_int 0)))
4101 (set (match_operand:SI 0 "gpc_reg_operand" "")
4102 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4103 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4104 [(set (match_dup 0)
4105 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4106 (set (match_dup 3)
4107 (compare:CC (match_dup 0)
4108 (const_int 0)))]
4109 "")
4111 (define_insn ""
4112 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4113 (zero_extend:SI
4114 (subreg:HI
4115 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4116 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4117 "includes_rshift_p (operands[2], GEN_INT (65535))"
4118 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4120 (define_insn ""
4121 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4122 (compare:CC
4123 (zero_extend:SI
4124 (subreg:HI
4125 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4126 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4127 (const_int 0)))
4128 (clobber (match_scratch:SI 3 "=r,r"))]
4129 "includes_rshift_p (operands[2], GEN_INT (65535))"
4130 "@
4131 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4132 #"
4133 [(set_attr "type" "delayed_compare")
4134 (set_attr "length" "4,8")])
4136 (define_split
4137 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4138 (compare:CC
4139 (zero_extend:SI
4140 (subreg:HI
4141 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4142 (match_operand:SI 2 "const_int_operand" "")) 0))
4143 (const_int 0)))
4144 (clobber (match_scratch:SI 3 ""))]
4145 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4146 [(set (match_dup 3)
4147 (zero_extend:SI (subreg:HI
4148 (lshiftrt:SI (match_dup 1)
4149 (match_dup 2)) 0)))
4150 (set (match_dup 0)
4151 (compare:CC (match_dup 3)
4152 (const_int 0)))]
4153 "")
4155 (define_insn ""
4156 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4157 (compare:CC
4158 (zero_extend:SI
4159 (subreg:HI
4160 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4161 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4162 (const_int 0)))
4163 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4164 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4165 "includes_rshift_p (operands[2], GEN_INT (65535))"
4166 "@
4167 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4168 #"
4169 [(set_attr "type" "delayed_compare")
4170 (set_attr "length" "4,8")])
4172 (define_split
4173 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4174 (compare:CC
4175 (zero_extend:SI
4176 (subreg:HI
4177 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4178 (match_operand:SI 2 "const_int_operand" "")) 0))
4179 (const_int 0)))
4180 (set (match_operand:SI 0 "gpc_reg_operand" "")
4181 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4182 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4183 [(set (match_dup 0)
4184 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4185 (set (match_dup 3)
4186 (compare:CC (match_dup 0)
4187 (const_int 0)))]
4188 "")
4190 (define_insn ""
4191 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4192 (const_int 1)
4193 (match_operand:SI 1 "gpc_reg_operand" "r"))
4194 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4195 (const_int 31)))]
4196 "TARGET_POWER"
4197 "rrib %0,%1,%2")
4199 (define_insn ""
4200 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4201 (const_int 1)
4202 (match_operand:SI 1 "gpc_reg_operand" "r"))
4203 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4204 (const_int 31)))]
4205 "TARGET_POWER"
4206 "rrib %0,%1,%2")
4208 (define_insn ""
4209 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4210 (const_int 1)
4211 (match_operand:SI 1 "gpc_reg_operand" "r"))
4212 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4213 (const_int 1)
4214 (const_int 0)))]
4215 "TARGET_POWER"
4216 "rrib %0,%1,%2")
4218 (define_expand "ashrsi3"
4219 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4220 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4221 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4222 ""
4223 "
4224 {
4225 if (TARGET_POWER)
4226 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4227 else
4228 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4229 DONE;
4230 }")
4232 (define_insn "ashrsi3_power"
4233 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4234 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4235 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4236 (clobber (match_scratch:SI 3 "=q,X"))]
4237 "TARGET_POWER"
4238 "@
4239 srea %0,%1,%2
4240 {srai|srawi} %0,%1,%h2")
4242 (define_insn "ashrsi3_no_power"
4243 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4244 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4245 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4246 "! TARGET_POWER"
4247 "{sra|sraw}%I2 %0,%1,%h2")
4249 (define_insn ""
4250 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4251 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4252 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4253 (const_int 0)))
4254 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4255 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4256 "TARGET_POWER"
4257 "@
4258 srea. %3,%1,%2
4259 {srai.|srawi.} %3,%1,%h2
4260 #
4261 #"
4262 [(set_attr "type" "delayed_compare")
4263 (set_attr "length" "4,4,8,8")])
4265 (define_split
4266 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4267 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4268 (match_operand:SI 2 "reg_or_cint_operand" ""))
4269 (const_int 0)))
4270 (clobber (match_scratch:SI 3 ""))
4271 (clobber (match_scratch:SI 4 ""))]
4272 "TARGET_POWER && reload_completed"
4273 [(parallel [(set (match_dup 3)
4274 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4275 (clobber (match_dup 4))])
4276 (set (match_dup 0)
4277 (compare:CC (match_dup 3)
4278 (const_int 0)))]
4279 "")
4281 (define_insn ""
4282 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4283 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4284 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4285 (const_int 0)))
4286 (clobber (match_scratch:SI 3 "=r,r"))]
4287 "! TARGET_POWER"
4288 "@
4289 {sra|sraw}%I2. %3,%1,%h2
4290 #"
4291 [(set_attr "type" "delayed_compare")
4292 (set_attr "length" "4,8")])
4294 (define_split
4295 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4296 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4297 (match_operand:SI 2 "reg_or_cint_operand" ""))
4298 (const_int 0)))
4299 (clobber (match_scratch:SI 3 ""))]
4300 "! TARGET_POWER && reload_completed"
4301 [(set (match_dup 3)
4302 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4303 (set (match_dup 0)
4304 (compare:CC (match_dup 3)
4305 (const_int 0)))]
4306 "")
4308 (define_insn ""
4309 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4310 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4311 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4312 (const_int 0)))
4313 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4314 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4315 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4316 "TARGET_POWER"
4317 "@
4318 srea. %0,%1,%2
4319 {srai.|srawi.} %0,%1,%h2
4320 #
4321 #"
4322 [(set_attr "type" "delayed_compare")
4323 (set_attr "length" "4,4,8,8")])
4325 (define_split
4326 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4327 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4328 (match_operand:SI 2 "reg_or_cint_operand" ""))
4329 (const_int 0)))
4330 (set (match_operand:SI 0 "gpc_reg_operand" "")
4331 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4332 (clobber (match_scratch:SI 4 ""))]
4333 "TARGET_POWER && reload_completed"
4334 [(parallel [(set (match_dup 0)
4335 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4336 (clobber (match_dup 4))])
4337 (set (match_dup 3)
4338 (compare:CC (match_dup 0)
4339 (const_int 0)))]
4340 "")
4342 (define_insn ""
4343 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4344 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4345 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4346 (const_int 0)))
4347 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4348 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4349 "! TARGET_POWER"
4350 "@
4351 {sra|sraw}%I2. %0,%1,%h2
4352 #"
4353 [(set_attr "type" "delayed_compare")
4354 (set_attr "length" "4,8")])
4355 \f
4356 (define_split
4357 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4358 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4359 (match_operand:SI 2 "reg_or_cint_operand" ""))
4360 (const_int 0)))
4361 (set (match_operand:SI 0 "gpc_reg_operand" "")
4362 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4363 "! TARGET_POWER && reload_completed"
4364 [(set (match_dup 0)
4365 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4366 (set (match_dup 3)
4367 (compare:CC (match_dup 0)
4368 (const_int 0)))]
4369 "")
4371 ;; Floating-point insns, excluding normal data motion.
4372 ;;
4373 ;; PowerPC has a full set of single-precision floating point instructions.
4374 ;;
4375 ;; For the POWER architecture, we pretend that we have both SFmode and
4376 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4377 ;; The only conversions we will do will be when storing to memory. In that
4378 ;; case, we will use the "frsp" instruction before storing.
4379 ;;
4380 ;; Note that when we store into a single-precision memory location, we need to
4381 ;; use the frsp insn first. If the register being stored isn't dead, we
4382 ;; need a scratch register for the frsp. But this is difficult when the store
4383 ;; is done by reload. It is not incorrect to do the frsp on the register in
4384 ;; this case, we just lose precision that we would have otherwise gotten but
4385 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4387 (define_expand "extendsfdf2"
4388 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4389 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
4390 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4391 "")
4393 (define_insn_and_split "*extendsfdf2_fpr"
4394 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
4395 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
4396 "TARGET_HARD_FLOAT && TARGET_FPRS"
4397 "@
4398 #
4399 fmr %0,%1
4400 lfs%U1%X1 %0,%1"
4401 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
4402 [(const_int 0)]
4403 {
4404 emit_note (NOTE_INSN_DELETED);
4405 DONE;
4406 }
4407 [(set_attr "type" "fp,fp,fpload")])
4409 (define_expand "truncdfsf2"
4410 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4411 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
4412 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4413 "")
4415 (define_insn "*truncdfsf2_fpr"
4416 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4417 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4418 "TARGET_HARD_FLOAT && TARGET_FPRS"
4419 "frsp %0,%1"
4420 [(set_attr "type" "fp")])
4422 (define_insn "aux_truncdfsf2"
4423 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4424 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
4425 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4426 "frsp %0,%1"
4427 [(set_attr "type" "fp")])
4429 (define_expand "negsf2"
4430 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4431 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4432 "TARGET_HARD_FLOAT"
4433 "")
4435 (define_insn "*negsf2"
4436 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4437 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4438 "TARGET_HARD_FLOAT && TARGET_FPRS"
4439 "fneg %0,%1"
4440 [(set_attr "type" "fp")])
4442 (define_expand "abssf2"
4443 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4444 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4445 "TARGET_HARD_FLOAT"
4446 "")
4448 (define_insn "*abssf2"
4449 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4450 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4451 "TARGET_HARD_FLOAT && TARGET_FPRS"
4452 "fabs %0,%1"
4453 [(set_attr "type" "fp")])
4455 (define_insn ""
4456 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4457 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
4458 "TARGET_HARD_FLOAT && TARGET_FPRS"
4459 "fnabs %0,%1"
4460 [(set_attr "type" "fp")])
4462 (define_expand "addsf3"
4463 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4464 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4465 (match_operand:SF 2 "gpc_reg_operand" "")))]
4466 "TARGET_HARD_FLOAT"
4467 "")
4469 (define_insn ""
4470 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4471 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4472 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4473 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4474 "fadds %0,%1,%2"
4475 [(set_attr "type" "fp")])
4477 (define_insn ""
4478 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4479 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4480 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4481 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4482 "{fa|fadd} %0,%1,%2"
4483 [(set_attr "type" "fp")])
4485 (define_expand "subsf3"
4486 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4487 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4488 (match_operand:SF 2 "gpc_reg_operand" "")))]
4489 "TARGET_HARD_FLOAT"
4490 "")
4492 (define_insn ""
4493 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4494 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4495 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4496 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4497 "fsubs %0,%1,%2"
4498 [(set_attr "type" "fp")])
4500 (define_insn ""
4501 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4502 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4503 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4504 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4505 "{fs|fsub} %0,%1,%2"
4506 [(set_attr "type" "fp")])
4508 (define_expand "mulsf3"
4509 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4510 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
4511 (match_operand:SF 2 "gpc_reg_operand" "")))]
4512 "TARGET_HARD_FLOAT"
4513 "")
4515 (define_insn ""
4516 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4517 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4518 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4519 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4520 "fmuls %0,%1,%2"
4521 [(set_attr "type" "fp")])
4523 (define_insn ""
4524 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4525 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4526 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4527 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4528 "{fm|fmul} %0,%1,%2"
4529 [(set_attr "type" "dmul")])
4531 (define_insn "fres"
4532 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4533 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
4534 "TARGET_PPC_GFXOPT && flag_finite_math_only"
4535 "fres %0,%1"
4536 [(set_attr "type" "fp")])
4538 (define_expand "divsf3"
4539 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4540 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
4541 (match_operand:SF 2 "gpc_reg_operand" "")))]
4542 "TARGET_HARD_FLOAT"
4543 {
4544 if (swdiv && !optimize_size && TARGET_PPC_GFXOPT
4545 && flag_finite_math_only && !flag_trapping_math)
4546 {
4547 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
4548 DONE;
4549 }
4550 })
4552 (define_insn ""
4553 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4554 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4555 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4556 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4557 "fdivs %0,%1,%2"
4558 [(set_attr "type" "sdiv")])
4560 (define_insn ""
4561 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4562 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4563 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4564 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4565 "{fd|fdiv} %0,%1,%2"
4566 [(set_attr "type" "ddiv")])
4568 (define_insn ""
4569 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4570 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4571 (match_operand:SF 2 "gpc_reg_operand" "f"))
4572 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4573 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4574 "fmadds %0,%1,%2,%3"
4575 [(set_attr "type" "fp")])
4577 (define_insn ""
4578 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4579 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4580 (match_operand:SF 2 "gpc_reg_operand" "f"))
4581 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4582 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4583 "{fma|fmadd} %0,%1,%2,%3"
4584 [(set_attr "type" "dmul")])
4586 (define_insn ""
4587 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4588 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4589 (match_operand:SF 2 "gpc_reg_operand" "f"))
4590 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4591 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4592 "fmsubs %0,%1,%2,%3"
4593 [(set_attr "type" "fp")])
4595 (define_insn ""
4596 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4597 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4598 (match_operand:SF 2 "gpc_reg_operand" "f"))
4599 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4600 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4601 "{fms|fmsub} %0,%1,%2,%3"
4602 [(set_attr "type" "dmul")])
4604 (define_insn ""
4605 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4606 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4607 (match_operand:SF 2 "gpc_reg_operand" "f"))
4608 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4609 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4610 && HONOR_SIGNED_ZEROS (SFmode)"
4611 "fnmadds %0,%1,%2,%3"
4612 [(set_attr "type" "fp")])
4614 (define_insn ""
4615 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4616 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4617 (match_operand:SF 2 "gpc_reg_operand" "f"))
4618 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4619 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4620 && ! HONOR_SIGNED_ZEROS (SFmode)"
4621 "fnmadds %0,%1,%2,%3"
4622 [(set_attr "type" "fp")])
4624 (define_insn ""
4625 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4626 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4627 (match_operand:SF 2 "gpc_reg_operand" "f"))
4628 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4629 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4630 "{fnma|fnmadd} %0,%1,%2,%3"
4631 [(set_attr "type" "dmul")])
4633 (define_insn ""
4634 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4635 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4636 (match_operand:SF 2 "gpc_reg_operand" "f"))
4637 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4638 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4639 && ! HONOR_SIGNED_ZEROS (SFmode)"
4640 "{fnma|fnmadd} %0,%1,%2,%3"
4641 [(set_attr "type" "dmul")])
4643 (define_insn ""
4644 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4645 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4646 (match_operand:SF 2 "gpc_reg_operand" "f"))
4647 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4648 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4649 && HONOR_SIGNED_ZEROS (SFmode)"
4650 "fnmsubs %0,%1,%2,%3"
4651 [(set_attr "type" "fp")])
4653 (define_insn ""
4654 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4655 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4656 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4657 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4658 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4659 && ! HONOR_SIGNED_ZEROS (SFmode)"
4660 "fnmsubs %0,%1,%2,%3"
4661 [(set_attr "type" "fp")])
4663 (define_insn ""
4664 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4665 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4666 (match_operand:SF 2 "gpc_reg_operand" "f"))
4667 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4668 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4669 "{fnms|fnmsub} %0,%1,%2,%3"
4670 [(set_attr "type" "dmul")])
4672 (define_insn ""
4673 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4674 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4675 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4676 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4677 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4678 && ! HONOR_SIGNED_ZEROS (SFmode)"
4679 "{fnms|fnmsub} %0,%1,%2,%3"
4680 [(set_attr "type" "dmul")])
4682 (define_expand "sqrtsf2"
4683 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4684 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4685 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
4686 "")
4688 (define_insn ""
4689 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4690 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4691 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4692 "fsqrts %0,%1"
4693 [(set_attr "type" "ssqrt")])
4695 (define_insn ""
4696 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4697 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4698 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
4699 "fsqrt %0,%1"
4700 [(set_attr "type" "dsqrt")])
4702 (define_expand "copysignsf3"
4703 [(set (match_dup 3)
4704 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
4705 (set (match_dup 4)
4706 (neg:SF (abs:SF (match_dup 1))))
4707 (set (match_operand:SF 0 "gpc_reg_operand" "")
4708 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
4709 (match_dup 5))
4710 (match_dup 3)
4711 (match_dup 4)))]
4712 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
4713 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
4714 {
4715 operands[3] = gen_reg_rtx (SFmode);
4716 operands[4] = gen_reg_rtx (SFmode);
4717 operands[5] = CONST0_RTX (SFmode);
4718 })
4720 (define_expand "copysigndf3"
4721 [(set (match_dup 3)
4722 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
4723 (set (match_dup 4)
4724 (neg:DF (abs:DF (match_dup 1))))
4725 (set (match_operand:DF 0 "gpc_reg_operand" "")
4726 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
4727 (match_dup 5))
4728 (match_dup 3)
4729 (match_dup 4)))]
4730 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
4731 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
4732 {
4733 operands[3] = gen_reg_rtx (DFmode);
4734 operands[4] = gen_reg_rtx (DFmode);
4735 operands[5] = CONST0_RTX (DFmode);
4736 })
4738 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
4739 ;; fsel instruction and some auxiliary computations. Then we just have a
4740 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
4741 ;; combine.
4742 (define_expand "smaxsf3"
4743 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4744 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4745 (match_operand:SF 2 "gpc_reg_operand" ""))
4746 (match_dup 1)
4747 (match_dup 2)))]
4748 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4749 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
4751 (define_expand "sminsf3"
4752 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4753 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4754 (match_operand:SF 2 "gpc_reg_operand" ""))
4755 (match_dup 2)
4756 (match_dup 1)))]
4757 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4758 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
4760 (define_split
4761 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4762 (match_operator:SF 3 "min_max_operator"
4763 [(match_operand:SF 1 "gpc_reg_operand" "")
4764 (match_operand:SF 2 "gpc_reg_operand" "")]))]
4765 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4766 [(const_int 0)]
4767 "
4768 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4769 operands[1], operands[2]);
4770 DONE;
4771 }")
4773 (define_expand "movsicc"
4774 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4775 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4776 (match_operand:SI 2 "gpc_reg_operand" "")
4777 (match_operand:SI 3 "gpc_reg_operand" "")))]
4778 "TARGET_ISEL"
4779 "
4780 {
4781 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4782 DONE;
4783 else
4784 FAIL;
4785 }")
4787 ;; We use the BASE_REGS for the isel input operands because, if rA is
4788 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
4789 ;; because we may switch the operands and rB may end up being rA.
4790 ;;
4791 ;; We need 2 patterns: an unsigned and a signed pattern. We could
4792 ;; leave out the mode in operand 4 and use one pattern, but reload can
4793 ;; change the mode underneath our feet and then gets confused trying
4794 ;; to reload the value.
4795 (define_insn "isel_signed"
4796 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4797 (if_then_else:SI
4798 (match_operator 1 "comparison_operator"
4799 [(match_operand:CC 4 "cc_reg_operand" "y")
4800 (const_int 0)])
4801 (match_operand:SI 2 "gpc_reg_operand" "b")
4802 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4803 "TARGET_ISEL"
4804 "*
4805 { return output_isel (operands); }"
4806 [(set_attr "length" "4")])
4808 (define_insn "isel_unsigned"
4809 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4810 (if_then_else:SI
4811 (match_operator 1 "comparison_operator"
4812 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
4813 (const_int 0)])
4814 (match_operand:SI 2 "gpc_reg_operand" "b")
4815 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4816 "TARGET_ISEL"
4817 "*
4818 { return output_isel (operands); }"
4819 [(set_attr "length" "4")])
4821 (define_expand "movsfcc"
4822 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4823 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4824 (match_operand:SF 2 "gpc_reg_operand" "")
4825 (match_operand:SF 3 "gpc_reg_operand" "")))]
4826 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4827 "
4828 {
4829 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4830 DONE;
4831 else
4832 FAIL;
4833 }")
4835 (define_insn "*fselsfsf4"
4836 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4837 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
4838 (match_operand:SF 4 "zero_fp_constant" "F"))
4839 (match_operand:SF 2 "gpc_reg_operand" "f")
4840 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4841 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4842 "fsel %0,%1,%2,%3"
4843 [(set_attr "type" "fp")])
4845 (define_insn "*fseldfsf4"
4846 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4847 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
4848 (match_operand:DF 4 "zero_fp_constant" "F"))
4849 (match_operand:SF 2 "gpc_reg_operand" "f")
4850 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4851 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4852 "fsel %0,%1,%2,%3"
4853 [(set_attr "type" "fp")])
4855 (define_expand "negdf2"
4856 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4857 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
4858 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4859 "")
4861 (define_insn "*negdf2_fpr"
4862 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4863 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4864 "TARGET_HARD_FLOAT && TARGET_FPRS"
4865 "fneg %0,%1"
4866 [(set_attr "type" "fp")])
4868 (define_expand "absdf2"
4869 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4870 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
4871 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4872 "")
4874 (define_insn "*absdf2_fpr"
4875 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4876 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4877 "TARGET_HARD_FLOAT && TARGET_FPRS"
4878 "fabs %0,%1"
4879 [(set_attr "type" "fp")])
4881 (define_insn "*nabsdf2_fpr"
4882 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4883 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
4884 "TARGET_HARD_FLOAT && TARGET_FPRS"
4885 "fnabs %0,%1"
4886 [(set_attr "type" "fp")])
4888 (define_expand "adddf3"
4889 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4890 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
4891 (match_operand:DF 2 "gpc_reg_operand" "")))]
4892 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4893 "")
4895 (define_insn "*adddf3_fpr"
4896 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4897 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4898 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4899 "TARGET_HARD_FLOAT && TARGET_FPRS"
4900 "{fa|fadd} %0,%1,%2"
4901 [(set_attr "type" "fp")])
4903 (define_expand "subdf3"
4904 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4905 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
4906 (match_operand:DF 2 "gpc_reg_operand" "")))]
4907 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4908 "")
4910 (define_insn "*subdf3_fpr"
4911 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4912 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4913 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4914 "TARGET_HARD_FLOAT && TARGET_FPRS"
4915 "{fs|fsub} %0,%1,%2"
4916 [(set_attr "type" "fp")])
4918 (define_expand "muldf3"
4919 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4920 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
4921 (match_operand:DF 2 "gpc_reg_operand" "")))]
4922 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4923 "")
4925 (define_insn "*muldf3_fpr"
4926 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4927 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4928 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4929 "TARGET_HARD_FLOAT && TARGET_FPRS"
4930 "{fm|fmul} %0,%1,%2"
4931 [(set_attr "type" "dmul")])
4933 (define_insn "fred"
4934 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4935 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
4936 "TARGET_POPCNTB && flag_finite_math_only"
4937 "fre %0,%1"
4938 [(set_attr "type" "fp")])
4940 (define_expand "divdf3"
4941 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4942 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
4943 (match_operand:DF 2 "gpc_reg_operand" "")))]
4944 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4945 {
4946 if (swdiv && !optimize_size && TARGET_POPCNTB
4947 && flag_finite_math_only && !flag_trapping_math)
4948 {
4949 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
4950 DONE;
4951 }
4952 })
4954 (define_insn "*divdf3_fpr"
4955 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4956 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4957 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4958 "TARGET_HARD_FLOAT && TARGET_FPRS"
4959 "{fd|fdiv} %0,%1,%2"
4960 [(set_attr "type" "ddiv")])
4962 (define_insn ""
4963 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4964 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4965 (match_operand:DF 2 "gpc_reg_operand" "f"))
4966 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4967 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4968 "{fma|fmadd} %0,%1,%2,%3"
4969 [(set_attr "type" "dmul")])
4971 (define_insn ""
4972 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4973 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4974 (match_operand:DF 2 "gpc_reg_operand" "f"))
4975 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4976 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4977 "{fms|fmsub} %0,%1,%2,%3"
4978 [(set_attr "type" "dmul")])
4980 (define_insn ""
4981 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4982 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4983 (match_operand:DF 2 "gpc_reg_operand" "f"))
4984 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
4985 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4986 && HONOR_SIGNED_ZEROS (DFmode)"
4987 "{fnma|fnmadd} %0,%1,%2,%3"
4988 [(set_attr "type" "dmul")])
4990 (define_insn ""
4991 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4992 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
4993 (match_operand:DF 2 "gpc_reg_operand" "f"))
4994 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4995 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4996 && ! HONOR_SIGNED_ZEROS (DFmode)"
4997 "{fnma|fnmadd} %0,%1,%2,%3"
4998 [(set_attr "type" "dmul")])
5000 (define_insn ""
5001 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5002 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5003 (match_operand:DF 2 "gpc_reg_operand" "f"))
5004 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5005 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5006 && HONOR_SIGNED_ZEROS (DFmode)"
5007 "{fnms|fnmsub} %0,%1,%2,%3"
5008 [(set_attr "type" "dmul")])
5010 (define_insn ""
5011 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5012 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
5013 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5014 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
5015 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5016 && ! HONOR_SIGNED_ZEROS (DFmode)"
5017 "{fnms|fnmsub} %0,%1,%2,%3"
5018 [(set_attr "type" "dmul")])
5020 (define_insn "sqrtdf2"
5021 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5022 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5023 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5024 "fsqrt %0,%1"
5025 [(set_attr "type" "dsqrt")])
5027 ;; The conditional move instructions allow us to perform max and min
5028 ;; operations even when
5030 (define_expand "smaxdf3"
5031 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5032 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5033 (match_operand:DF 2 "gpc_reg_operand" ""))
5034 (match_dup 1)
5035 (match_dup 2)))]
5036 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5037 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5039 (define_expand "smindf3"
5040 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5041 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5042 (match_operand:DF 2 "gpc_reg_operand" ""))
5043 (match_dup 2)
5044 (match_dup 1)))]
5045 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5046 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5048 (define_split
5049 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5050 (match_operator:DF 3 "min_max_operator"
5051 [(match_operand:DF 1 "gpc_reg_operand" "")
5052 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5053 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5054 [(const_int 0)]
5055 "
5056 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5057 operands[1], operands[2]);
5058 DONE;
5059 }")
5061 (define_expand "movdfcc"
5062 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5063 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5064 (match_operand:DF 2 "gpc_reg_operand" "")
5065 (match_operand:DF 3 "gpc_reg_operand" "")))]
5066 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5067 "
5068 {
5069 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5070 DONE;
5071 else
5072 FAIL;
5073 }")
5075 (define_insn "*fseldfdf4"
5076 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5077 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5078 (match_operand:DF 4 "zero_fp_constant" "F"))
5079 (match_operand:DF 2 "gpc_reg_operand" "f")
5080 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5081 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5082 "fsel %0,%1,%2,%3"
5083 [(set_attr "type" "fp")])
5085 (define_insn "*fselsfdf4"
5086 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5087 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5088 (match_operand:SF 4 "zero_fp_constant" "F"))
5089 (match_operand:DF 2 "gpc_reg_operand" "f")
5090 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5091 "TARGET_PPC_GFXOPT"
5092 "fsel %0,%1,%2,%3"
5093 [(set_attr "type" "fp")])
5094 \f
5095 ;; Conversions to and from floating-point.
5097 (define_expand "fixuns_truncsfsi2"
5098 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5099 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5100 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5101 "")
5103 (define_expand "fix_truncsfsi2"
5104 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5105 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5106 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5107 "")
5109 ; For each of these conversions, there is a define_expand, a define_insn
5110 ; with a '#' template, and a define_split (with C code). The idea is
5111 ; to allow constant folding with the template of the define_insn,
5112 ; then to have the insns split later (between sched1 and final).
5114 (define_expand "floatsidf2"
5115 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5116 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5117 (use (match_dup 2))
5118 (use (match_dup 3))
5119 (clobber (match_dup 4))
5120 (clobber (match_dup 5))
5121 (clobber (match_dup 6))])]
5122 "TARGET_HARD_FLOAT && TARGET_FPRS"
5123 "
5124 {
5125 if (TARGET_E500_DOUBLE)
5126 {
5127 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5128 DONE;
5129 }
5130 if (TARGET_POWERPC64)
5131 {
5132 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5133 rtx t1 = gen_reg_rtx (DImode);
5134 rtx t2 = gen_reg_rtx (DImode);
5135 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
5136 DONE;
5137 }
5139 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5140 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5141 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5142 operands[5] = gen_reg_rtx (DFmode);
5143 operands[6] = gen_reg_rtx (SImode);
5144 }")
5146 (define_insn_and_split "*floatsidf2_internal"
5147 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5148 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5149 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5150 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5151 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5152 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5153 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5154 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5155 "#"
5156 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5157 [(pc)]
5158 "
5159 {
5160 rtx lowword, highword;
5161 gcc_assert (MEM_P (operands[4]));
5162 highword = adjust_address (operands[4], SImode, 0);
5163 lowword = adjust_address (operands[4], SImode, 4);
5164 if (! WORDS_BIG_ENDIAN)
5165 {
5166 rtx tmp;
5167 tmp = highword; highword = lowword; lowword = tmp;
5168 }
5170 emit_insn (gen_xorsi3 (operands[6], operands[1],
5171 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5172 emit_move_insn (lowword, operands[6]);
5173 emit_move_insn (highword, operands[2]);
5174 emit_move_insn (operands[5], operands[4]);
5175 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5176 DONE;
5177 }"
5178 [(set_attr "length" "24")])
5180 (define_expand "floatunssisf2"
5181 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5182 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5183 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5184 "")
5186 (define_expand "floatunssidf2"
5187 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5188 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5189 (use (match_dup 2))
5190 (use (match_dup 3))
5191 (clobber (match_dup 4))
5192 (clobber (match_dup 5))])]
5193 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5194 "
5195 {
5196 if (TARGET_E500_DOUBLE)
5197 {
5198 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5199 DONE;
5200 }
5201 if (TARGET_POWERPC64)
5202 {
5203 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5204 rtx t1 = gen_reg_rtx (DImode);
5205 rtx t2 = gen_reg_rtx (DImode);
5206 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5207 t1, t2));
5208 DONE;
5209 }
5211 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5212 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5213 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5214 operands[5] = gen_reg_rtx (DFmode);
5215 }")
5217 (define_insn_and_split "*floatunssidf2_internal"
5218 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5219 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5220 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5221 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5222 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5223 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
5224 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5225 "#"
5226 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5227 [(pc)]
5228 "
5229 {
5230 rtx lowword, highword;
5231 gcc_assert (MEM_P (operands[4]));
5232 highword = adjust_address (operands[4], SImode, 0);
5233 lowword = adjust_address (operands[4], SImode, 4);
5234 if (! WORDS_BIG_ENDIAN)
5235 {
5236 rtx tmp;
5237 tmp = highword; highword = lowword; lowword = tmp;
5238 }
5240 emit_move_insn (lowword, operands[1]);
5241 emit_move_insn (highword, operands[2]);
5242 emit_move_insn (operands[5], operands[4]);
5243 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5244 DONE;
5245 }"
5246 [(set_attr "length" "20")])
5248 (define_expand "fix_truncdfsi2"
5249 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
5250 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5251 (clobber (match_dup 2))
5252 (clobber (match_dup 3))])]
5253 "(TARGET_POWER2 || TARGET_POWERPC)
5254 && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5255 "
5256 {
5257 if (TARGET_E500_DOUBLE)
5258 {
5259 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
5260 DONE;
5261 }
5262 operands[2] = gen_reg_rtx (DImode);
5263 if (TARGET_PPC_GFXOPT)
5264 {
5265 rtx orig_dest = operands[0];
5266 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
5267 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
5268 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
5269 operands[2]));
5270 if (operands[0] != orig_dest)
5271 emit_move_insn (orig_dest, operands[0]);
5272 DONE;
5273 }
5274 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5275 }")
5277 (define_insn_and_split "*fix_truncdfsi2_internal"
5278 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5279 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5280 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5281 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
5282 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5283 "#"
5284 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[3]))"
5285 [(pc)]
5286 "
5287 {
5288 rtx lowword;
5289 gcc_assert (MEM_P (operands[3]));
5290 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
5292 emit_insn (gen_fctiwz (operands[2], operands[1]));
5293 emit_move_insn (operands[3], operands[2]);
5294 emit_move_insn (operands[0], lowword);
5295 DONE;
5296 }"
5297 [(set_attr "length" "16")])
5299 (define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
5300 [(set (match_operand:SI 0 "memory_operand" "=Z")
5301 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5302 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
5303 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
5304 && TARGET_PPC_GFXOPT"
5305 "#"
5306 "&& 1"
5307 [(pc)]
5308 "
5309 {
5310 emit_insn (gen_fctiwz (operands[2], operands[1]));
5311 emit_insn (gen_stfiwx (operands[0], operands[2]));
5312 DONE;
5313 }"
5314 [(set_attr "length" "16")])
5316 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5317 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5318 ; because the first makes it clear that operand 0 is not live
5319 ; before the instruction.
5320 (define_insn "fctiwz"
5321 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
5322 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
5323 UNSPEC_FCTIWZ))]
5324 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5325 "{fcirz|fctiwz} %0,%1"
5326 [(set_attr "type" "fp")])
5328 (define_insn "btruncdf2"
5329 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5330 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
5331 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5332 "friz %0,%1"
5333 [(set_attr "type" "fp")])
5335 (define_insn "btruncsf2"
5336 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5337 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
5338 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5339 "friz %0,%1"
5340 [(set_attr "type" "fp")])
5342 (define_insn "ceildf2"
5343 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5344 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
5345 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5346 "frip %0,%1"
5347 [(set_attr "type" "fp")])
5349 (define_insn "ceilsf2"
5350 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5351 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
5352 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5353 "frip %0,%1"
5354 [(set_attr "type" "fp")])
5356 (define_insn "floordf2"
5357 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5358 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
5359 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5360 "frim %0,%1"
5361 [(set_attr "type" "fp")])
5363 (define_insn "floorsf2"
5364 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5365 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
5366 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5367 "frim %0,%1"
5368 [(set_attr "type" "fp")])
5370 (define_insn "rounddf2"
5371 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5372 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
5373 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5374 "frin %0,%1"
5375 [(set_attr "type" "fp")])
5377 (define_insn "roundsf2"
5378 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5379 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
5380 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5381 "frin %0,%1"
5382 [(set_attr "type" "fp")])
5384 ; An UNSPEC is used so we don't have to support SImode in FP registers.
5385 (define_insn "stfiwx"
5386 [(set (match_operand:SI 0 "memory_operand" "=Z")
5387 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")]
5388 UNSPEC_STFIWX))]
5389 "TARGET_PPC_GFXOPT"
5390 "stfiwx %1,%y0"
5391 [(set_attr "type" "fpstore")])
5393 (define_expand "floatsisf2"
5394 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5395 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5396 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5397 "")
5399 (define_insn "floatdidf2"
5400 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5401 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
5402 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5403 "fcfid %0,%1"
5404 [(set_attr "type" "fp")])
5406 (define_insn_and_split "floatsidf_ppc64"
5407 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5408 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5409 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5410 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5411 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5412 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5413 "#"
5414 "&& 1"
5415 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
5416 (set (match_dup 2) (match_dup 3))
5417 (set (match_dup 4) (match_dup 2))
5418 (set (match_dup 0) (float:DF (match_dup 4)))]
5419 "")
5421 (define_insn_and_split "floatunssidf_ppc64"
5422 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5423 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5424 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5425 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5426 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5427 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5428 "#"
5429 "&& 1"
5430 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
5431 (set (match_dup 2) (match_dup 3))
5432 (set (match_dup 4) (match_dup 2))
5433 (set (match_dup 0) (float:DF (match_dup 4)))]
5434 "")
5436 (define_insn "fix_truncdfdi2"
5437 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5438 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
5439 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5440 "fctidz %0,%1"
5441 [(set_attr "type" "fp")])
5443 (define_expand "floatdisf2"
5444 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5445 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
5446 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5447 "
5448 {
5449 rtx val = operands[1];
5450 if (!flag_unsafe_math_optimizations)
5451 {
5452 rtx label = gen_label_rtx ();
5453 val = gen_reg_rtx (DImode);
5454 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
5455 emit_label (label);
5456 }
5457 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
5458 DONE;
5459 }")
5461 ;; This is not IEEE compliant if rounding mode is "round to nearest".
5462 ;; If the DI->DF conversion is inexact, then it's possible to suffer
5463 ;; from double rounding.
5464 (define_insn_and_split "floatdisf2_internal1"
5465 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5466 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
5467 (clobber (match_scratch:DF 2 "=f"))]
5468 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5469 "#"
5470 "&& reload_completed"
5471 [(set (match_dup 2)
5472 (float:DF (match_dup 1)))
5473 (set (match_dup 0)
5474 (float_truncate:SF (match_dup 2)))]
5475 "")
5477 ;; Twiddles bits to avoid double rounding.
5478 ;; Bits that might be truncated when converting to DFmode are replaced
5479 ;; by a bit that won't be lost at that stage, but is below the SFmode
5480 ;; rounding position.
5481 (define_expand "floatdisf2_internal2"
5482 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
5483 (const_int 53)))
5484 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
5485 (const_int 2047)))
5486 (clobber (scratch:CC))])
5487 (set (match_dup 3) (plus:DI (match_dup 3)
5488 (const_int 1)))
5489 (set (match_dup 0) (plus:DI (match_dup 0)
5490 (const_int 2047)))
5491 (set (match_dup 4) (compare:CCUNS (match_dup 3)
5492 (const_int 2)))
5493 (set (match_dup 0) (ior:DI (match_dup 0)
5494 (match_dup 1)))
5495 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
5496 (const_int -2048)))
5497 (clobber (scratch:CC))])
5498 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
5499 (label_ref (match_operand:DI 2 "" ""))
5500 (pc)))
5501 (set (match_dup 0) (match_dup 1))]
5502 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5503 "
5504 {
5505 operands[3] = gen_reg_rtx (DImode);
5506 operands[4] = gen_reg_rtx (CCUNSmode);
5507 }")
5508 \f
5509 ;; Define the DImode operations that can be done in a small number
5510 ;; of instructions. The & constraints are to prevent the register
5511 ;; allocator from allocating registers that overlap with the inputs
5512 ;; (for example, having an input in 7,8 and an output in 6,7). We
5513 ;; also allow for the output being the same as one of the inputs.
5515 (define_insn "*adddi3_noppc64"
5516 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
5517 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
5518 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
5519 "! TARGET_POWERPC64"
5520 "*
5521 {
5522 if (WORDS_BIG_ENDIAN)
5523 return (GET_CODE (operands[2])) != CONST_INT
5524 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
5525 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
5526 else
5527 return (GET_CODE (operands[2])) != CONST_INT
5528 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
5529 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
5530 }"
5531 [(set_attr "type" "two")
5532 (set_attr "length" "8")])
5534 (define_insn "*subdi3_noppc64"
5535 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
5536 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
5537 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
5538 "! TARGET_POWERPC64"
5539 "*
5540 {
5541 if (WORDS_BIG_ENDIAN)
5542 return (GET_CODE (operands[1]) != CONST_INT)
5543 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
5544 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
5545 else
5546 return (GET_CODE (operands[1]) != CONST_INT)
5547 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
5548 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
5549 }"
5550 [(set_attr "type" "two")
5551 (set_attr "length" "8")])
5553 (define_insn "*negdi2_noppc64"
5554 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5555 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
5556 "! TARGET_POWERPC64"
5557 "*
5558 {
5559 return (WORDS_BIG_ENDIAN)
5560 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
5561 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
5562 }"
5563 [(set_attr "type" "two")
5564 (set_attr "length" "8")])
5566 (define_expand "mulsidi3"
5567 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5568 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5569 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5570 "! TARGET_POWERPC64"
5571 "
5572 {
5573 if (! TARGET_POWER && ! TARGET_POWERPC)
5574 {
5575 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5576 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5577 emit_insn (gen_mull_call ());
5578 if (WORDS_BIG_ENDIAN)
5579 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
5580 else
5581 {
5582 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
5583 gen_rtx_REG (SImode, 3));
5584 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
5585 gen_rtx_REG (SImode, 4));
5586 }
5587 DONE;
5588 }
5589 else if (TARGET_POWER)
5590 {
5591 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
5592 DONE;
5593 }
5594 }")
5596 (define_insn "mulsidi3_mq"
5597 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5598 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5599 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5600 (clobber (match_scratch:SI 3 "=q"))]
5601 "TARGET_POWER"
5602 "mul %0,%1,%2\;mfmq %L0"
5603 [(set_attr "type" "imul")
5604 (set_attr "length" "8")])
5606 (define_insn "*mulsidi3_no_mq"
5607 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5608 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5609 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5610 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5611 "*
5612 {
5613 return (WORDS_BIG_ENDIAN)
5614 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
5615 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
5616 }"
5617 [(set_attr "type" "imul")
5618 (set_attr "length" "8")])
5620 (define_split
5621 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5622 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5623 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5624 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5625 [(set (match_dup 3)
5626 (truncate:SI
5627 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
5628 (sign_extend:DI (match_dup 2)))
5629 (const_int 32))))
5630 (set (match_dup 4)
5631 (mult:SI (match_dup 1)
5632 (match_dup 2)))]
5633 "
5634 {
5635 int endian = (WORDS_BIG_ENDIAN == 0);
5636 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5637 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5638 }")
5640 (define_expand "umulsidi3"
5641 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5642 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5643 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5644 "TARGET_POWERPC && ! TARGET_POWERPC64"
5645 "
5646 {
5647 if (TARGET_POWER)
5648 {
5649 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
5650 DONE;
5651 }
5652 }")
5654 (define_insn "umulsidi3_mq"
5655 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5656 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5657 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5658 (clobber (match_scratch:SI 3 "=q"))]
5659 "TARGET_POWERPC && TARGET_POWER"
5660 "*
5661 {
5662 return (WORDS_BIG_ENDIAN)
5663 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5664 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5665 }"
5666 [(set_attr "type" "imul")
5667 (set_attr "length" "8")])
5669 (define_insn "*umulsidi3_no_mq"
5670 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5671 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5672 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5673 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5674 "*
5675 {
5676 return (WORDS_BIG_ENDIAN)
5677 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5678 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5679 }"
5680 [(set_attr "type" "imul")
5681 (set_attr "length" "8")])
5683 (define_split
5684 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5685 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5686 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5687 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5688 [(set (match_dup 3)
5689 (truncate:SI
5690 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
5691 (zero_extend:DI (match_dup 2)))
5692 (const_int 32))))
5693 (set (match_dup 4)
5694 (mult:SI (match_dup 1)
5695 (match_dup 2)))]
5696 "
5697 {
5698 int endian = (WORDS_BIG_ENDIAN == 0);
5699 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5700 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5701 }")
5703 (define_expand "smulsi3_highpart"
5704 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5705 (truncate:SI
5706 (lshiftrt:DI (mult:DI (sign_extend:DI
5707 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5708 (sign_extend:DI
5709 (match_operand:SI 2 "gpc_reg_operand" "r")))
5710 (const_int 32))))]
5711 ""
5712 "
5713 {
5714 if (! TARGET_POWER && ! TARGET_POWERPC)
5715 {
5716 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5717 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5718 emit_insn (gen_mulh_call ());
5719 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
5720 DONE;
5721 }
5722 else if (TARGET_POWER)
5723 {
5724 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5725 DONE;
5726 }
5727 }")
5729 (define_insn "smulsi3_highpart_mq"
5730 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5731 (truncate:SI
5732 (lshiftrt:DI (mult:DI (sign_extend:DI
5733 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5734 (sign_extend:DI
5735 (match_operand:SI 2 "gpc_reg_operand" "r")))
5736 (const_int 32))))
5737 (clobber (match_scratch:SI 3 "=q"))]
5738 "TARGET_POWER"
5739 "mul %0,%1,%2"
5740 [(set_attr "type" "imul")])
5742 (define_insn "*smulsi3_highpart_no_mq"
5743 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5744 (truncate:SI
5745 (lshiftrt:DI (mult:DI (sign_extend:DI
5746 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5747 (sign_extend:DI
5748 (match_operand:SI 2 "gpc_reg_operand" "r")))
5749 (const_int 32))))]
5750 "TARGET_POWERPC && ! TARGET_POWER"
5751 "mulhw %0,%1,%2"
5752 [(set_attr "type" "imul")])
5754 (define_expand "umulsi3_highpart"
5755 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5756 (truncate:SI
5757 (lshiftrt:DI (mult:DI (zero_extend:DI
5758 (match_operand:SI 1 "gpc_reg_operand" ""))
5759 (zero_extend:DI
5760 (match_operand:SI 2 "gpc_reg_operand" "")))
5761 (const_int 32))))]
5762 "TARGET_POWERPC"
5763 "
5764 {
5765 if (TARGET_POWER)
5766 {
5767 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5768 DONE;
5769 }
5770 }")
5772 (define_insn "umulsi3_highpart_mq"
5773 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5774 (truncate:SI
5775 (lshiftrt:DI (mult:DI (zero_extend:DI
5776 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5777 (zero_extend:DI
5778 (match_operand:SI 2 "gpc_reg_operand" "r")))
5779 (const_int 32))))
5780 (clobber (match_scratch:SI 3 "=q"))]
5781 "TARGET_POWERPC && TARGET_POWER"
5782 "mulhwu %0,%1,%2"
5783 [(set_attr "type" "imul")])
5785 (define_insn "*umulsi3_highpart_no_mq"
5786 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5787 (truncate:SI
5788 (lshiftrt:DI (mult:DI (zero_extend:DI
5789 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5790 (zero_extend:DI
5791 (match_operand:SI 2 "gpc_reg_operand" "r")))
5792 (const_int 32))))]
5793 "TARGET_POWERPC && ! TARGET_POWER"
5794 "mulhwu %0,%1,%2"
5795 [(set_attr "type" "imul")])
5797 ;; If operands 0 and 2 are in the same register, we have a problem. But
5798 ;; operands 0 and 1 (the usual case) can be in the same register. That's
5799 ;; why we have the strange constraints below.
5800 (define_insn "ashldi3_power"
5801 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5802 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5803 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5804 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5805 "TARGET_POWER"
5806 "@
5807 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
5808 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5809 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5810 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
5811 [(set_attr "length" "8")])
5813 (define_insn "lshrdi3_power"
5814 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5815 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5816 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5817 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5818 "TARGET_POWER"
5819 "@
5820 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
5821 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5822 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5823 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
5824 [(set_attr "length" "8")])
5826 ;; Shift by a variable amount is too complex to be worth open-coding. We
5827 ;; just handle shifts by constants.
5828 (define_insn "ashrdi3_power"
5829 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5830 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5831 (match_operand:SI 2 "const_int_operand" "M,i")))
5832 (clobber (match_scratch:SI 3 "=X,q"))]
5833 "TARGET_POWER"
5834 "@
5835 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5836 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
5837 [(set_attr "length" "8")])
5839 (define_insn "ashrdi3_no_power"
5840 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
5841 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5842 (match_operand:SI 2 "const_int_operand" "M,i")))]
5843 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
5844 "@
5845 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5846 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
5847 [(set_attr "type" "two,three")
5848 (set_attr "length" "8,12")])
5850 (define_insn "*ashrdisi3_noppc64"
5851 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5852 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5853 (const_int 32)) 4))]
5854 "TARGET_32BIT && !TARGET_POWERPC64"
5855 "*
5856 {
5857 if (REGNO (operands[0]) == REGNO (operands[1]))
5858 return \"\";
5859 else
5860 return \"mr %0,%1\";
5861 }"
5862 [(set_attr "length" "4")])
5864 \f
5865 ;; PowerPC64 DImode operations.
5867 (define_insn_and_split "absdi2"
5868 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5869 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
5870 (clobber (match_scratch:DI 2 "=&r,&r"))]
5871 "TARGET_POWERPC64"
5872 "#"
5873 "&& reload_completed"
5874 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
5875 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
5876 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
5877 "")
5879 (define_insn_and_split "*nabsdi2"
5880 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5881 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
5882 (clobber (match_scratch:DI 2 "=&r,&r"))]
5883 "TARGET_POWERPC64"
5884 "#"
5885 "&& reload_completed"
5886 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
5887 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
5888 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
5889 "")
5891 (define_insn "muldi3"
5892 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5893 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
5894 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
5895 "TARGET_POWERPC64"
5896 "@
5897 mulld %0,%1,%2
5898 mulli %0,%1,%2"
5899 [(set (attr "type")
5900 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
5901 (const_string "imul3")
5902 (match_operand:SI 2 "short_cint_operand" "")
5903 (const_string "imul2")]
5904 (const_string "lmul")))])
5906 (define_insn "*muldi3_internal1"
5907 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5908 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
5909 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5910 (const_int 0)))
5911 (clobber (match_scratch:DI 3 "=r,r"))]
5912 "TARGET_POWERPC64"
5913 "@
5914 mulld. %3,%1,%2
5915 #"
5916 [(set_attr "type" "lmul_compare")
5917 (set_attr "length" "4,8")])
5919 (define_split
5920 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5921 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
5922 (match_operand:DI 2 "gpc_reg_operand" ""))
5923 (const_int 0)))
5924 (clobber (match_scratch:DI 3 ""))]
5925 "TARGET_POWERPC64 && reload_completed"
5926 [(set (match_dup 3)
5927 (mult:DI (match_dup 1) (match_dup 2)))
5928 (set (match_dup 0)
5929 (compare:CC (match_dup 3)
5930 (const_int 0)))]
5931 "")
5933 (define_insn "*muldi3_internal2"
5934 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5935 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
5936 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5937 (const_int 0)))
5938 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5939 (mult:DI (match_dup 1) (match_dup 2)))]
5940 "TARGET_POWERPC64"
5941 "@
5942 mulld. %0,%1,%2
5943 #"
5944 [(set_attr "type" "lmul_compare")
5945 (set_attr "length" "4,8")])
5947 (define_split
5948 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5949 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
5950 (match_operand:DI 2 "gpc_reg_operand" ""))
5951 (const_int 0)))
5952 (set (match_operand:DI 0 "gpc_reg_operand" "")
5953 (mult:DI (match_dup 1) (match_dup 2)))]
5954 "TARGET_POWERPC64 && reload_completed"
5955 [(set (match_dup 0)
5956 (mult:DI (match_dup 1) (match_dup 2)))
5957 (set (match_dup 3)
5958 (compare:CC (match_dup 0)
5959 (const_int 0)))]
5960 "")
5962 (define_insn "smuldi3_highpart"
5963 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5964 (truncate:DI
5965 (lshiftrt:TI (mult:TI (sign_extend:TI
5966 (match_operand:DI 1 "gpc_reg_operand" "%r"))
5967 (sign_extend:TI
5968 (match_operand:DI 2 "gpc_reg_operand" "r")))
5969 (const_int 64))))]
5970 "TARGET_POWERPC64"
5971 "mulhd %0,%1,%2"
5972 [(set_attr "type" "lmul")])
5974 (define_insn "umuldi3_highpart"
5975 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5976 (truncate:DI
5977 (lshiftrt:TI (mult:TI (zero_extend:TI
5978 (match_operand:DI 1 "gpc_reg_operand" "%r"))
5979 (zero_extend:TI
5980 (match_operand:DI 2 "gpc_reg_operand" "r")))
5981 (const_int 64))))]
5982 "TARGET_POWERPC64"
5983 "mulhdu %0,%1,%2"
5984 [(set_attr "type" "lmul")])
5986 (define_insn "rotldi3"
5987 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5988 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5989 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
5990 "TARGET_POWERPC64"
5991 "rld%I2cl %0,%1,%H2,0")
5993 (define_insn "*rotldi3_internal2"
5994 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5995 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5996 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
5997 (const_int 0)))
5998 (clobber (match_scratch:DI 3 "=r,r"))]
5999 "TARGET_64BIT"
6000 "@
6001 rld%I2cl. %3,%1,%H2,0
6002 #"
6003 [(set_attr "type" "delayed_compare")
6004 (set_attr "length" "4,8")])
6006 (define_split
6007 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6008 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6009 (match_operand:DI 2 "reg_or_cint_operand" ""))
6010 (const_int 0)))
6011 (clobber (match_scratch:DI 3 ""))]
6012 "TARGET_POWERPC64 && reload_completed"
6013 [(set (match_dup 3)
6014 (rotate:DI (match_dup 1) (match_dup 2)))
6015 (set (match_dup 0)
6016 (compare:CC (match_dup 3)
6017 (const_int 0)))]
6018 "")
6020 (define_insn "*rotldi3_internal3"
6021 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6022 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6023 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6024 (const_int 0)))
6025 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6026 (rotate:DI (match_dup 1) (match_dup 2)))]
6027 "TARGET_64BIT"
6028 "@
6029 rld%I2cl. %0,%1,%H2,0
6030 #"
6031 [(set_attr "type" "delayed_compare")
6032 (set_attr "length" "4,8")])
6034 (define_split
6035 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6036 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6037 (match_operand:DI 2 "reg_or_cint_operand" ""))
6038 (const_int 0)))
6039 (set (match_operand:DI 0 "gpc_reg_operand" "")
6040 (rotate:DI (match_dup 1) (match_dup 2)))]
6041 "TARGET_POWERPC64 && reload_completed"
6042 [(set (match_dup 0)
6043 (rotate:DI (match_dup 1) (match_dup 2)))
6044 (set (match_dup 3)
6045 (compare:CC (match_dup 0)
6046 (const_int 0)))]
6047 "")
6049 (define_insn "*rotldi3_internal4"
6050 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6051 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6052 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
6053 (match_operand:DI 3 "mask64_operand" "n")))]
6054 "TARGET_POWERPC64"
6055 "rld%I2c%B3 %0,%1,%H2,%S3")
6057 (define_insn "*rotldi3_internal5"
6058 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6059 (compare:CC (and:DI
6060 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6061 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6062 (match_operand:DI 3 "mask64_operand" "n,n"))
6063 (const_int 0)))
6064 (clobber (match_scratch:DI 4 "=r,r"))]
6065 "TARGET_64BIT"
6066 "@
6067 rld%I2c%B3. %4,%1,%H2,%S3
6068 #"
6069 [(set_attr "type" "delayed_compare")
6070 (set_attr "length" "4,8")])
6072 (define_split
6073 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6074 (compare:CC (and:DI
6075 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6076 (match_operand:DI 2 "reg_or_cint_operand" ""))
6077 (match_operand:DI 3 "mask64_operand" ""))
6078 (const_int 0)))
6079 (clobber (match_scratch:DI 4 ""))]
6080 "TARGET_POWERPC64 && reload_completed"
6081 [(set (match_dup 4)
6082 (and:DI (rotate:DI (match_dup 1)
6083 (match_dup 2))
6084 (match_dup 3)))
6085 (set (match_dup 0)
6086 (compare:CC (match_dup 4)
6087 (const_int 0)))]
6088 "")
6090 (define_insn "*rotldi3_internal6"
6091 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6092 (compare:CC (and:DI
6093 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6094 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6095 (match_operand:DI 3 "mask64_operand" "n,n"))
6096 (const_int 0)))
6097 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6098 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6099 "TARGET_64BIT"
6100 "@
6101 rld%I2c%B3. %0,%1,%H2,%S3
6102 #"
6103 [(set_attr "type" "delayed_compare")
6104 (set_attr "length" "4,8")])
6106 (define_split
6107 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6108 (compare:CC (and:DI
6109 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6110 (match_operand:DI 2 "reg_or_cint_operand" ""))
6111 (match_operand:DI 3 "mask64_operand" ""))
6112 (const_int 0)))
6113 (set (match_operand:DI 0 "gpc_reg_operand" "")
6114 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6115 "TARGET_POWERPC64 && reload_completed"
6116 [(set (match_dup 0)
6117 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6118 (set (match_dup 4)
6119 (compare:CC (match_dup 0)
6120 (const_int 0)))]
6121 "")
6123 (define_insn "*rotldi3_internal7"
6124 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6125 (zero_extend:DI
6126 (subreg:QI
6127 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6128 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6129 "TARGET_POWERPC64"
6130 "rld%I2cl %0,%1,%H2,56")
6132 (define_insn "*rotldi3_internal8"
6133 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6134 (compare:CC (zero_extend:DI
6135 (subreg:QI
6136 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6137 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6138 (const_int 0)))
6139 (clobber (match_scratch:DI 3 "=r,r"))]
6140 "TARGET_64BIT"
6141 "@
6142 rld%I2cl. %3,%1,%H2,56
6143 #"
6144 [(set_attr "type" "delayed_compare")
6145 (set_attr "length" "4,8")])
6147 (define_split
6148 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6149 (compare:CC (zero_extend:DI
6150 (subreg:QI
6151 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6152 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6153 (const_int 0)))
6154 (clobber (match_scratch:DI 3 ""))]
6155 "TARGET_POWERPC64 && reload_completed"
6156 [(set (match_dup 3)
6157 (zero_extend:DI (subreg:QI
6158 (rotate:DI (match_dup 1)
6159 (match_dup 2)) 0)))
6160 (set (match_dup 0)
6161 (compare:CC (match_dup 3)
6162 (const_int 0)))]
6163 "")
6165 (define_insn "*rotldi3_internal9"
6166 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6167 (compare:CC (zero_extend:DI
6168 (subreg:QI
6169 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6170 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6171 (const_int 0)))
6172 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6173 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6174 "TARGET_64BIT"
6175 "@
6176 rld%I2cl. %0,%1,%H2,56
6177 #"
6178 [(set_attr "type" "delayed_compare")
6179 (set_attr "length" "4,8")])
6181 (define_split
6182 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6183 (compare:CC (zero_extend:DI
6184 (subreg:QI
6185 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6186 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6187 (const_int 0)))
6188 (set (match_operand:DI 0 "gpc_reg_operand" "")
6189 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6190 "TARGET_POWERPC64 && reload_completed"
6191 [(set (match_dup 0)
6192 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6193 (set (match_dup 3)
6194 (compare:CC (match_dup 0)
6195 (const_int 0)))]
6196 "")
6198 (define_insn "*rotldi3_internal10"
6199 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6200 (zero_extend:DI
6201 (subreg:HI
6202 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6203 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6204 "TARGET_POWERPC64"
6205 "rld%I2cl %0,%1,%H2,48")
6207 (define_insn "*rotldi3_internal11"
6208 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6209 (compare:CC (zero_extend:DI
6210 (subreg:HI
6211 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6212 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6213 (const_int 0)))
6214 (clobber (match_scratch:DI 3 "=r,r"))]
6215 "TARGET_64BIT"
6216 "@
6217 rld%I2cl. %3,%1,%H2,48
6218 #"
6219 [(set_attr "type" "delayed_compare")
6220 (set_attr "length" "4,8")])
6222 (define_split
6223 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6224 (compare:CC (zero_extend:DI
6225 (subreg:HI
6226 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6227 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6228 (const_int 0)))
6229 (clobber (match_scratch:DI 3 ""))]
6230 "TARGET_POWERPC64 && reload_completed"
6231 [(set (match_dup 3)
6232 (zero_extend:DI (subreg:HI
6233 (rotate:DI (match_dup 1)
6234 (match_dup 2)) 0)))
6235 (set (match_dup 0)
6236 (compare:CC (match_dup 3)
6237 (const_int 0)))]
6238 "")
6240 (define_insn "*rotldi3_internal12"
6241 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6242 (compare:CC (zero_extend:DI
6243 (subreg:HI
6244 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6245 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6246 (const_int 0)))
6247 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6248 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6249 "TARGET_64BIT"
6250 "@
6251 rld%I2cl. %0,%1,%H2,48
6252 #"
6253 [(set_attr "type" "delayed_compare")
6254 (set_attr "length" "4,8")])
6256 (define_split
6257 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6258 (compare:CC (zero_extend:DI
6259 (subreg:HI
6260 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6261 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6262 (const_int 0)))
6263 (set (match_operand:DI 0 "gpc_reg_operand" "")
6264 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6265 "TARGET_POWERPC64 && reload_completed"
6266 [(set (match_dup 0)
6267 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6268 (set (match_dup 3)
6269 (compare:CC (match_dup 0)
6270 (const_int 0)))]
6271 "")
6273 (define_insn "*rotldi3_internal13"
6274 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6275 (zero_extend:DI
6276 (subreg:SI
6277 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6278 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6279 "TARGET_POWERPC64"
6280 "rld%I2cl %0,%1,%H2,32")
6282 (define_insn "*rotldi3_internal14"
6283 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6284 (compare:CC (zero_extend:DI
6285 (subreg:SI
6286 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6287 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6288 (const_int 0)))
6289 (clobber (match_scratch:DI 3 "=r,r"))]
6290 "TARGET_64BIT"
6291 "@
6292 rld%I2cl. %3,%1,%H2,32
6293 #"
6294 [(set_attr "type" "delayed_compare")
6295 (set_attr "length" "4,8")])
6297 (define_split
6298 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6299 (compare:CC (zero_extend:DI
6300 (subreg:SI
6301 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6302 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6303 (const_int 0)))
6304 (clobber (match_scratch:DI 3 ""))]
6305 "TARGET_POWERPC64 && reload_completed"
6306 [(set (match_dup 3)
6307 (zero_extend:DI (subreg:SI
6308 (rotate:DI (match_dup 1)
6309 (match_dup 2)) 0)))
6310 (set (match_dup 0)
6311 (compare:CC (match_dup 3)
6312 (const_int 0)))]
6313 "")
6315 (define_insn "*rotldi3_internal15"
6316 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6317 (compare:CC (zero_extend:DI
6318 (subreg:SI
6319 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6320 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6321 (const_int 0)))
6322 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6323 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6324 "TARGET_64BIT"
6325 "@
6326 rld%I2cl. %0,%1,%H2,32
6327 #"
6328 [(set_attr "type" "delayed_compare")
6329 (set_attr "length" "4,8")])
6331 (define_split
6332 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6333 (compare:CC (zero_extend:DI
6334 (subreg:SI
6335 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6336 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6337 (const_int 0)))
6338 (set (match_operand:DI 0 "gpc_reg_operand" "")
6339 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6340 "TARGET_POWERPC64 && reload_completed"
6341 [(set (match_dup 0)
6342 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6343 (set (match_dup 3)
6344 (compare:CC (match_dup 0)
6345 (const_int 0)))]
6346 "")
6348 (define_expand "ashldi3"
6349 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6350 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6351 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6352 "TARGET_POWERPC64 || TARGET_POWER"
6353 "
6354 {
6355 if (TARGET_POWERPC64)
6356 ;
6357 else if (TARGET_POWER)
6358 {
6359 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
6360 DONE;
6361 }
6362 else
6363 FAIL;
6364 }")
6366 (define_insn "*ashldi3_internal1"
6367 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6368 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6369 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6370 "TARGET_POWERPC64"
6371 "sld%I2 %0,%1,%H2")
6373 (define_insn "*ashldi3_internal2"
6374 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6375 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6376 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6377 (const_int 0)))
6378 (clobber (match_scratch:DI 3 "=r,r"))]
6379 "TARGET_64BIT"
6380 "@
6381 sld%I2. %3,%1,%H2
6382 #"
6383 [(set_attr "type" "delayed_compare")
6384 (set_attr "length" "4,8")])
6386 (define_split
6387 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6388 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6389 (match_operand:SI 2 "reg_or_cint_operand" ""))
6390 (const_int 0)))
6391 (clobber (match_scratch:DI 3 ""))]
6392 "TARGET_POWERPC64 && reload_completed"
6393 [(set (match_dup 3)
6394 (ashift:DI (match_dup 1) (match_dup 2)))
6395 (set (match_dup 0)
6396 (compare:CC (match_dup 3)
6397 (const_int 0)))]
6398 "")
6400 (define_insn "*ashldi3_internal3"
6401 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6402 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6403 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6404 (const_int 0)))
6405 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6406 (ashift:DI (match_dup 1) (match_dup 2)))]
6407 "TARGET_64BIT"
6408 "@
6409 sld%I2. %0,%1,%H2
6410 #"
6411 [(set_attr "type" "delayed_compare")
6412 (set_attr "length" "4,8")])
6414 (define_split
6415 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6416 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6417 (match_operand:SI 2 "reg_or_cint_operand" ""))
6418 (const_int 0)))
6419 (set (match_operand:DI 0 "gpc_reg_operand" "")
6420 (ashift:DI (match_dup 1) (match_dup 2)))]
6421 "TARGET_POWERPC64 && reload_completed"
6422 [(set (match_dup 0)
6423 (ashift:DI (match_dup 1) (match_dup 2)))
6424 (set (match_dup 3)
6425 (compare:CC (match_dup 0)
6426 (const_int 0)))]
6427 "")
6429 (define_insn "*ashldi3_internal4"
6430 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6431 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6432 (match_operand:SI 2 "const_int_operand" "i"))
6433 (match_operand:DI 3 "const_int_operand" "n")))]
6434 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6435 "rldic %0,%1,%H2,%W3")
6437 (define_insn "ashldi3_internal5"
6438 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6439 (compare:CC
6440 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6441 (match_operand:SI 2 "const_int_operand" "i,i"))
6442 (match_operand:DI 3 "const_int_operand" "n,n"))
6443 (const_int 0)))
6444 (clobber (match_scratch:DI 4 "=r,r"))]
6445 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6446 "@
6447 rldic. %4,%1,%H2,%W3
6448 #"
6449 [(set_attr "type" "compare")
6450 (set_attr "length" "4,8")])
6452 (define_split
6453 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6454 (compare:CC
6455 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6456 (match_operand:SI 2 "const_int_operand" ""))
6457 (match_operand:DI 3 "const_int_operand" ""))
6458 (const_int 0)))
6459 (clobber (match_scratch:DI 4 ""))]
6460 "TARGET_POWERPC64 && reload_completed
6461 && includes_rldic_lshift_p (operands[2], operands[3])"
6462 [(set (match_dup 4)
6463 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6464 (match_dup 3)))
6465 (set (match_dup 0)
6466 (compare:CC (match_dup 4)
6467 (const_int 0)))]
6468 "")
6470 (define_insn "*ashldi3_internal6"
6471 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6472 (compare:CC
6473 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6474 (match_operand:SI 2 "const_int_operand" "i,i"))
6475 (match_operand:DI 3 "const_int_operand" "n,n"))
6476 (const_int 0)))
6477 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6478 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6479 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6480 "@
6481 rldic. %0,%1,%H2,%W3
6482 #"
6483 [(set_attr "type" "compare")
6484 (set_attr "length" "4,8")])
6486 (define_split
6487 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6488 (compare:CC
6489 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6490 (match_operand:SI 2 "const_int_operand" ""))
6491 (match_operand:DI 3 "const_int_operand" ""))
6492 (const_int 0)))
6493 (set (match_operand:DI 0 "gpc_reg_operand" "")
6494 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6495 "TARGET_POWERPC64 && reload_completed
6496 && includes_rldic_lshift_p (operands[2], operands[3])"
6497 [(set (match_dup 0)
6498 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6499 (match_dup 3)))
6500 (set (match_dup 4)
6501 (compare:CC (match_dup 0)
6502 (const_int 0)))]
6503 "")
6505 (define_insn "*ashldi3_internal7"
6506 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6507 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6508 (match_operand:SI 2 "const_int_operand" "i"))
6509 (match_operand:DI 3 "mask64_operand" "n")))]
6510 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6511 "rldicr %0,%1,%H2,%S3")
6513 (define_insn "ashldi3_internal8"
6514 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6515 (compare:CC
6516 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6517 (match_operand:SI 2 "const_int_operand" "i,i"))
6518 (match_operand:DI 3 "mask64_operand" "n,n"))
6519 (const_int 0)))
6520 (clobber (match_scratch:DI 4 "=r,r"))]
6521 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6522 "@
6523 rldicr. %4,%1,%H2,%S3
6524 #"
6525 [(set_attr "type" "compare")
6526 (set_attr "length" "4,8")])
6528 (define_split
6529 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6530 (compare:CC
6531 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6532 (match_operand:SI 2 "const_int_operand" ""))
6533 (match_operand:DI 3 "mask64_operand" ""))
6534 (const_int 0)))
6535 (clobber (match_scratch:DI 4 ""))]
6536 "TARGET_POWERPC64 && reload_completed
6537 && includes_rldicr_lshift_p (operands[2], operands[3])"
6538 [(set (match_dup 4)
6539 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6540 (match_dup 3)))
6541 (set (match_dup 0)
6542 (compare:CC (match_dup 4)
6543 (const_int 0)))]
6544 "")
6546 (define_insn "*ashldi3_internal9"
6547 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6548 (compare:CC
6549 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6550 (match_operand:SI 2 "const_int_operand" "i,i"))
6551 (match_operand:DI 3 "mask64_operand" "n,n"))
6552 (const_int 0)))
6553 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6554 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6555 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6556 "@
6557 rldicr. %0,%1,%H2,%S3
6558 #"
6559 [(set_attr "type" "compare")
6560 (set_attr "length" "4,8")])
6562 (define_split
6563 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6564 (compare:CC
6565 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6566 (match_operand:SI 2 "const_int_operand" ""))
6567 (match_operand:DI 3 "mask64_operand" ""))
6568 (const_int 0)))
6569 (set (match_operand:DI 0 "gpc_reg_operand" "")
6570 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6571 "TARGET_POWERPC64 && reload_completed
6572 && includes_rldicr_lshift_p (operands[2], operands[3])"
6573 [(set (match_dup 0)
6574 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6575 (match_dup 3)))
6576 (set (match_dup 4)
6577 (compare:CC (match_dup 0)
6578 (const_int 0)))]
6579 "")
6581 (define_expand "lshrdi3"
6582 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6583 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6584 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6585 "TARGET_POWERPC64 || TARGET_POWER"
6586 "
6587 {
6588 if (TARGET_POWERPC64)
6589 ;
6590 else if (TARGET_POWER)
6591 {
6592 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
6593 DONE;
6594 }
6595 else
6596 FAIL;
6597 }")
6599 (define_insn "*lshrdi3_internal1"
6600 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6601 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6602 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6603 "TARGET_POWERPC64"
6604 "srd%I2 %0,%1,%H2")
6606 (define_insn "*lshrdi3_internal2"
6607 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6608 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6609 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6610 (const_int 0)))
6611 (clobber (match_scratch:DI 3 "=r,r"))]
6612 "TARGET_64BIT "
6613 "@
6614 srd%I2. %3,%1,%H2
6615 #"
6616 [(set_attr "type" "delayed_compare")
6617 (set_attr "length" "4,8")])
6619 (define_split
6620 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6621 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6622 (match_operand:SI 2 "reg_or_cint_operand" ""))
6623 (const_int 0)))
6624 (clobber (match_scratch:DI 3 ""))]
6625 "TARGET_POWERPC64 && reload_completed"
6626 [(set (match_dup 3)
6627 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6628 (set (match_dup 0)
6629 (compare:CC (match_dup 3)
6630 (const_int 0)))]
6631 "")
6633 (define_insn "*lshrdi3_internal3"
6634 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6635 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6636 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6637 (const_int 0)))
6638 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6639 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6640 "TARGET_64BIT"
6641 "@
6642 srd%I2. %0,%1,%H2
6643 #"
6644 [(set_attr "type" "delayed_compare")
6645 (set_attr "length" "4,8")])
6647 (define_split
6648 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6649 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6650 (match_operand:SI 2 "reg_or_cint_operand" ""))
6651 (const_int 0)))
6652 (set (match_operand:DI 0 "gpc_reg_operand" "")
6653 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6654 "TARGET_POWERPC64 && reload_completed"
6655 [(set (match_dup 0)
6656 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6657 (set (match_dup 3)
6658 (compare:CC (match_dup 0)
6659 (const_int 0)))]
6660 "")
6662 (define_expand "ashrdi3"
6663 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6664 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6665 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6666 "WORDS_BIG_ENDIAN"
6667 "
6668 {
6669 if (TARGET_POWERPC64)
6670 ;
6671 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
6672 {
6673 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
6674 DONE;
6675 }
6676 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
6677 && WORDS_BIG_ENDIAN)
6678 {
6679 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
6680 DONE;
6681 }
6682 else
6683 FAIL;
6684 }")
6686 (define_insn "*ashrdi3_internal1"
6687 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6688 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6689 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6690 "TARGET_POWERPC64"
6691 "srad%I2 %0,%1,%H2")
6693 (define_insn "*ashrdi3_internal2"
6694 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6695 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6696 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6697 (const_int 0)))
6698 (clobber (match_scratch:DI 3 "=r,r"))]
6699 "TARGET_64BIT"
6700 "@
6701 srad%I2. %3,%1,%H2
6702 #"
6703 [(set_attr "type" "delayed_compare")
6704 (set_attr "length" "4,8")])
6706 (define_split
6707 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6708 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6709 (match_operand:SI 2 "reg_or_cint_operand" ""))
6710 (const_int 0)))
6711 (clobber (match_scratch:DI 3 ""))]
6712 "TARGET_POWERPC64 && reload_completed"
6713 [(set (match_dup 3)
6714 (ashiftrt:DI (match_dup 1) (match_dup 2)))
6715 (set (match_dup 0)
6716 (compare:CC (match_dup 3)
6717 (const_int 0)))]
6718 "")
6720 (define_insn "*ashrdi3_internal3"
6721 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6722 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6723 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6724 (const_int 0)))
6725 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6726 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6727 "TARGET_64BIT"
6728 "@
6729 srad%I2. %0,%1,%H2
6730 #"
6731 [(set_attr "type" "delayed_compare")
6732 (set_attr "length" "4,8")])
6734 (define_split
6735 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6736 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6737 (match_operand:SI 2 "reg_or_cint_operand" ""))
6738 (const_int 0)))
6739 (set (match_operand:DI 0 "gpc_reg_operand" "")
6740 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6741 "TARGET_POWERPC64 && reload_completed"
6742 [(set (match_dup 0)
6743 (ashiftrt:DI (match_dup 1) (match_dup 2)))
6744 (set (match_dup 3)
6745 (compare:CC (match_dup 0)
6746 (const_int 0)))]
6747 "")
6749 (define_insn "anddi3"
6750 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
6751 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
6752 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
6753 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
6754 "TARGET_POWERPC64"
6755 "@
6756 and %0,%1,%2
6757 rldic%B2 %0,%1,0,%S2
6758 rlwinm %0,%1,0,%m2,%M2
6759 andi. %0,%1,%b2
6760 andis. %0,%1,%u2
6761 #"
6762 [(set_attr "type" "*,*,*,compare,compare,*")
6763 (set_attr "length" "4,4,4,4,4,8")])
6765 (define_split
6766 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6767 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6768 (match_operand:DI 2 "mask64_2_operand" "")))
6769 (clobber (match_scratch:CC 3 ""))]
6770 "TARGET_POWERPC64
6771 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
6772 && !mask_operand (operands[2], DImode)
6773 && !mask64_operand (operands[2], DImode)"
6774 [(set (match_dup 0)
6775 (and:DI (rotate:DI (match_dup 1)
6776 (match_dup 4))
6777 (match_dup 5)))
6778 (set (match_dup 0)
6779 (and:DI (rotate:DI (match_dup 0)
6780 (match_dup 6))
6781 (match_dup 7)))]
6782 {
6783 build_mask64_2_operands (operands[2], &operands[4]);
6784 })
6786 (define_insn "*anddi3_internal2"
6787 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
6788 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
6789 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
6790 (const_int 0)))
6791 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
6792 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
6793 "TARGET_64BIT"
6794 "@
6795 and. %3,%1,%2
6796 rldic%B2. %3,%1,0,%S2
6797 rlwinm. %3,%1,0,%m2,%M2
6798 andi. %3,%1,%b2
6799 andis. %3,%1,%u2
6800 #
6801 #
6802 #
6803 #
6804 #
6805 #
6806 #"
6807 [(set_attr "type" "compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
6808 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
6810 (define_split
6811 [(set (match_operand:CC 0 "cc_reg_operand" "")
6812 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6813 (match_operand:DI 2 "mask64_2_operand" ""))
6814 (const_int 0)))
6815 (clobber (match_scratch:DI 3 ""))
6816 (clobber (match_scratch:CC 4 ""))]
6817 "TARGET_64BIT && reload_completed
6818 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
6819 && !mask_operand (operands[2], DImode)
6820 && !mask64_operand (operands[2], DImode)"
6821 [(set (match_dup 3)
6822 (and:DI (rotate:DI (match_dup 1)
6823 (match_dup 5))
6824 (match_dup 6)))
6825 (parallel [(set (match_dup 0)
6826 (compare:CC (and:DI (rotate:DI (match_dup 3)
6827 (match_dup 7))
6828 (match_dup 8))
6829 (const_int 0)))
6830 (clobber (match_dup 3))])]
6831 "
6832 {
6833 build_mask64_2_operands (operands[2], &operands[5]);
6834 }")
6836 (define_insn "*anddi3_internal3"
6837 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
6838 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
6839 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
6840 (const_int 0)))
6841 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
6842 (and:DI (match_dup 1) (match_dup 2)))
6843 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
6844 "TARGET_64BIT"
6845 "@
6846 and. %0,%1,%2
6847 rldic%B2. %0,%1,0,%S2
6848 rlwinm. %0,%1,0,%m2,%M2
6849 andi. %0,%1,%b2
6850 andis. %0,%1,%u2
6851 #
6852 #
6853 #
6854 #
6855 #
6856 #
6857 #"
6858 [(set_attr "type" "compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
6859 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
6861 (define_split
6862 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6863 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6864 (match_operand:DI 2 "and64_2_operand" ""))
6865 (const_int 0)))
6866 (set (match_operand:DI 0 "gpc_reg_operand" "")
6867 (and:DI (match_dup 1) (match_dup 2)))
6868 (clobber (match_scratch:CC 4 ""))]
6869 "TARGET_64BIT && reload_completed"
6870 [(parallel [(set (match_dup 0)
6871 (and:DI (match_dup 1) (match_dup 2)))
6872 (clobber (match_dup 4))])
6873 (set (match_dup 3)
6874 (compare:CC (match_dup 0)
6875 (const_int 0)))]
6876 "")
6878 (define_split
6879 [(set (match_operand:CC 3 "cc_reg_operand" "")
6880 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6881 (match_operand:DI 2 "mask64_2_operand" ""))
6882 (const_int 0)))
6883 (set (match_operand:DI 0 "gpc_reg_operand" "")
6884 (and:DI (match_dup 1) (match_dup 2)))
6885 (clobber (match_scratch:CC 4 ""))]
6886 "TARGET_64BIT && reload_completed
6887 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
6888 && !mask_operand (operands[2], DImode)
6889 && !mask64_operand (operands[2], DImode)"
6890 [(set (match_dup 0)
6891 (and:DI (rotate:DI (match_dup 1)
6892 (match_dup 5))
6893 (match_dup 6)))
6894 (parallel [(set (match_dup 3)
6895 (compare:CC (and:DI (rotate:DI (match_dup 0)
6896 (match_dup 7))
6897 (match_dup 8))
6898 (const_int 0)))
6899 (set (match_dup 0)
6900 (and:DI (rotate:DI (match_dup 0)
6901 (match_dup 7))
6902 (match_dup 8)))])]
6903 "
6904 {
6905 build_mask64_2_operands (operands[2], &operands[5]);
6906 }")
6908 (define_expand "iordi3"
6909 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6910 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
6911 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
6912 "TARGET_POWERPC64"
6913 "
6914 {
6915 if (non_logical_cint_operand (operands[2], DImode))
6916 {
6917 HOST_WIDE_INT value;
6918 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
6919 ? operands[0] : gen_reg_rtx (DImode));
6921 if (GET_CODE (operands[2]) == CONST_INT)
6922 {
6923 value = INTVAL (operands[2]);
6924 emit_insn (gen_iordi3 (tmp, operands[1],
6925 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
6926 }
6927 else
6928 {
6929 value = CONST_DOUBLE_LOW (operands[2]);
6930 emit_insn (gen_iordi3 (tmp, operands[1],
6931 immed_double_const (value
6932 & (~ (HOST_WIDE_INT) 0xffff),
6933 0, DImode)));
6934 }
6936 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
6937 DONE;
6938 }
6939 }")
6941 (define_expand "xordi3"
6942 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6943 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
6944 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
6945 "TARGET_POWERPC64"
6946 "
6947 {
6948 if (non_logical_cint_operand (operands[2], DImode))
6949 {
6950 HOST_WIDE_INT value;
6951 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
6952 ? operands[0] : gen_reg_rtx (DImode));
6954 if (GET_CODE (operands[2]) == CONST_INT)
6955 {
6956 value = INTVAL (operands[2]);
6957 emit_insn (gen_xordi3 (tmp, operands[1],
6958 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
6959 }
6960 else
6961 {
6962 value = CONST_DOUBLE_LOW (operands[2]);
6963 emit_insn (gen_xordi3 (tmp, operands[1],
6964 immed_double_const (value
6965 & (~ (HOST_WIDE_INT) 0xffff),
6966 0, DImode)));
6967 }
6969 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
6970 DONE;
6971 }
6972 }")
6974 (define_insn "*booldi3_internal1"
6975 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
6976 (match_operator:DI 3 "boolean_or_operator"
6977 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
6978 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
6979 "TARGET_POWERPC64"
6980 "@
6981 %q3 %0,%1,%2
6982 %q3i %0,%1,%b2
6983 %q3is %0,%1,%u2")
6985 (define_insn "*booldi3_internal2"
6986 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6987 (compare:CC (match_operator:DI 4 "boolean_or_operator"
6988 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
6989 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
6990 (const_int 0)))
6991 (clobber (match_scratch:DI 3 "=r,r"))]
6992 "TARGET_64BIT"
6993 "@
6994 %q4. %3,%1,%2
6995 #"
6996 [(set_attr "type" "compare")
6997 (set_attr "length" "4,8")])
6999 (define_split
7000 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7001 (compare:CC (match_operator:DI 4 "boolean_operator"
7002 [(match_operand:DI 1 "gpc_reg_operand" "")
7003 (match_operand:DI 2 "gpc_reg_operand" "")])
7004 (const_int 0)))
7005 (clobber (match_scratch:DI 3 ""))]
7006 "TARGET_POWERPC64 && reload_completed"
7007 [(set (match_dup 3) (match_dup 4))
7008 (set (match_dup 0)
7009 (compare:CC (match_dup 3)
7010 (const_int 0)))]
7011 "")
7013 (define_insn "*booldi3_internal3"
7014 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7015 (compare:CC (match_operator:DI 4 "boolean_operator"
7016 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7017 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7018 (const_int 0)))
7019 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7020 (match_dup 4))]
7021 "TARGET_64BIT"
7022 "@
7023 %q4. %0,%1,%2
7024 #"
7025 [(set_attr "type" "compare")
7026 (set_attr "length" "4,8")])
7028 (define_split
7029 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7030 (compare:CC (match_operator:DI 4 "boolean_operator"
7031 [(match_operand:DI 1 "gpc_reg_operand" "")
7032 (match_operand:DI 2 "gpc_reg_operand" "")])
7033 (const_int 0)))
7034 (set (match_operand:DI 0 "gpc_reg_operand" "")
7035 (match_dup 4))]
7036 "TARGET_POWERPC64 && reload_completed"
7037 [(set (match_dup 0) (match_dup 4))
7038 (set (match_dup 3)
7039 (compare:CC (match_dup 0)
7040 (const_int 0)))]
7041 "")
7043 ;; Split a logical operation that we can't do in one insn into two insns,
7044 ;; each of which does one 16-bit part. This is used by combine.
7046 (define_split
7047 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7048 (match_operator:DI 3 "boolean_or_operator"
7049 [(match_operand:DI 1 "gpc_reg_operand" "")
7050 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7051 "TARGET_POWERPC64"
7052 [(set (match_dup 0) (match_dup 4))
7053 (set (match_dup 0) (match_dup 5))]
7054 "
7055 {
7056 rtx i3,i4;
7058 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7059 {
7060 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7061 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7062 0, DImode);
7063 i4 = GEN_INT (value & 0xffff);
7064 }
7065 else
7066 {
7067 i3 = GEN_INT (INTVAL (operands[2])
7068 & (~ (HOST_WIDE_INT) 0xffff));
7069 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7070 }
7071 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7072 operands[1], i3);
7073 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7074 operands[0], i4);
7075 }")
7077 (define_insn "*boolcdi3_internal1"
7078 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7079 (match_operator:DI 3 "boolean_operator"
7080 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7081 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7082 "TARGET_POWERPC64"
7083 "%q3 %0,%2,%1")
7085 (define_insn "*boolcdi3_internal2"
7086 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7087 (compare:CC (match_operator:DI 4 "boolean_operator"
7088 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7089 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7090 (const_int 0)))
7091 (clobber (match_scratch:DI 3 "=r,r"))]
7092 "TARGET_64BIT"
7093 "@
7094 %q4. %3,%2,%1
7095 #"
7096 [(set_attr "type" "compare")
7097 (set_attr "length" "4,8")])
7099 (define_split
7100 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7101 (compare:CC (match_operator:DI 4 "boolean_operator"
7102 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7103 (match_operand:DI 2 "gpc_reg_operand" "")])
7104 (const_int 0)))
7105 (clobber (match_scratch:DI 3 ""))]
7106 "TARGET_POWERPC64 && reload_completed"
7107 [(set (match_dup 3) (match_dup 4))
7108 (set (match_dup 0)
7109 (compare:CC (match_dup 3)
7110 (const_int 0)))]
7111 "")
7113 (define_insn "*boolcdi3_internal3"
7114 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7115 (compare:CC (match_operator:DI 4 "boolean_operator"
7116 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7117 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7118 (const_int 0)))
7119 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7120 (match_dup 4))]
7121 "TARGET_64BIT"
7122 "@
7123 %q4. %0,%2,%1
7124 #"
7125 [(set_attr "type" "compare")
7126 (set_attr "length" "4,8")])
7128 (define_split
7129 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7130 (compare:CC (match_operator:DI 4 "boolean_operator"
7131 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7132 (match_operand:DI 2 "gpc_reg_operand" "")])
7133 (const_int 0)))
7134 (set (match_operand:DI 0 "gpc_reg_operand" "")
7135 (match_dup 4))]
7136 "TARGET_POWERPC64 && reload_completed"
7137 [(set (match_dup 0) (match_dup 4))
7138 (set (match_dup 3)
7139 (compare:CC (match_dup 0)
7140 (const_int 0)))]
7141 "")
7143 (define_insn "*boolccdi3_internal1"
7144 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7145 (match_operator:DI 3 "boolean_operator"
7146 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7147 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7148 "TARGET_POWERPC64"
7149 "%q3 %0,%1,%2")
7151 (define_insn "*boolccdi3_internal2"
7152 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7153 (compare:CC (match_operator:DI 4 "boolean_operator"
7154 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7155 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7156 (const_int 0)))
7157 (clobber (match_scratch:DI 3 "=r,r"))]
7158 "TARGET_64BIT"
7159 "@
7160 %q4. %3,%1,%2
7161 #"
7162 [(set_attr "type" "compare")
7163 (set_attr "length" "4,8")])
7165 (define_split
7166 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7167 (compare:CC (match_operator:DI 4 "boolean_operator"
7168 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7169 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7170 (const_int 0)))
7171 (clobber (match_scratch:DI 3 ""))]
7172 "TARGET_POWERPC64 && reload_completed"
7173 [(set (match_dup 3) (match_dup 4))
7174 (set (match_dup 0)
7175 (compare:CC (match_dup 3)
7176 (const_int 0)))]
7177 "")
7179 (define_insn "*boolccdi3_internal3"
7180 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7181 (compare:CC (match_operator:DI 4 "boolean_operator"
7182 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7183 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7184 (const_int 0)))
7185 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7186 (match_dup 4))]
7187 "TARGET_64BIT"
7188 "@
7189 %q4. %0,%1,%2
7190 #"
7191 [(set_attr "type" "compare")
7192 (set_attr "length" "4,8")])
7194 (define_split
7195 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7196 (compare:CC (match_operator:DI 4 "boolean_operator"
7197 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7198 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7199 (const_int 0)))
7200 (set (match_operand:DI 0 "gpc_reg_operand" "")
7201 (match_dup 4))]
7202 "TARGET_POWERPC64 && reload_completed"
7203 [(set (match_dup 0) (match_dup 4))
7204 (set (match_dup 3)
7205 (compare:CC (match_dup 0)
7206 (const_int 0)))]
7207 "")
7208 \f
7209 ;; Now define ways of moving data around.
7211 ;; Set up a register with a value from the GOT table
7213 (define_expand "movsi_got"
7214 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7215 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7216 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7217 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7218 "
7219 {
7220 if (GET_CODE (operands[1]) == CONST)
7221 {
7222 rtx offset = const0_rtx;
7223 HOST_WIDE_INT value;
7225 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7226 value = INTVAL (offset);
7227 if (value != 0)
7228 {
7229 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
7230 emit_insn (gen_movsi_got (tmp, operands[1]));
7231 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7232 DONE;
7233 }
7234 }
7236 operands[2] = rs6000_got_register (operands[1]);
7237 }")
7239 (define_insn "*movsi_got_internal"
7240 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7241 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7242 (match_operand:SI 2 "gpc_reg_operand" "b")]
7243 UNSPEC_MOVSI_GOT))]
7244 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7245 "{l|lwz} %0,%a1@got(%2)"
7246 [(set_attr "type" "load")])
7248 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7249 ;; didn't get allocated to a hard register.
7250 (define_split
7251 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7252 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7253 (match_operand:SI 2 "memory_operand" "")]
7254 UNSPEC_MOVSI_GOT))]
7255 "DEFAULT_ABI == ABI_V4
7256 && flag_pic == 1
7257 && (reload_in_progress || reload_completed)"
7258 [(set (match_dup 0) (match_dup 2))
7259 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7260 UNSPEC_MOVSI_GOT))]
7261 "")
7263 ;; For SI, we special-case integers that can't be loaded in one insn. We
7264 ;; do the load 16-bits at a time. We could do this by loading from memory,
7265 ;; and this is even supposed to be faster, but it is simpler not to get
7266 ;; integers in the TOC.
7267 (define_insn "movsi_low"
7268 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7269 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7270 (match_operand 2 "" ""))))]
7271 "TARGET_MACHO && ! TARGET_64BIT"
7272 "{l|lwz} %0,lo16(%2)(%1)"
7273 [(set_attr "type" "load")
7274 (set_attr "length" "4")])
7276 (define_insn "*movsi_internal1"
7277 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
7278 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
7279 "gpc_reg_operand (operands[0], SImode)
7280 || gpc_reg_operand (operands[1], SImode)"
7281 "@
7282 mr %0,%1
7283 {cal|la} %0,%a1
7284 {l%U1%X1|lwz%U1%X1} %0,%1
7285 {st%U0%X0|stw%U0%X0} %1,%0
7286 {lil|li} %0,%1
7287 {liu|lis} %0,%v1
7288 #
7289 {cal|la} %0,%a1
7290 mf%1 %0
7291 mt%0 %1
7292 mt%0 %1
7293 mt%0 %1
7294 {cror 0,0,0|nop}"
7295 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
7296 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7298 ;; Split a load of a large constant into the appropriate two-insn
7299 ;; sequence.
7301 (define_split
7302 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7303 (match_operand:SI 1 "const_int_operand" ""))]
7304 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7305 && (INTVAL (operands[1]) & 0xffff) != 0"
7306 [(set (match_dup 0)
7307 (match_dup 2))
7308 (set (match_dup 0)
7309 (ior:SI (match_dup 0)
7310 (match_dup 3)))]
7311 "
7312 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
7314 if (tem == operands[0])
7315 DONE;
7316 else
7317 FAIL;
7318 }")
7320 (define_insn "*mov<mode>_internal2"
7321 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
7322 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
7323 (const_int 0)))
7324 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
7325 ""
7326 "@
7327 {cmpi|cmp<wd>i} %2,%0,0
7328 mr. %0,%1
7329 #"
7330 [(set_attr "type" "cmp,compare,cmp")
7331 (set_attr "length" "4,4,8")])
7333 (define_split
7334 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
7335 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
7336 (const_int 0)))
7337 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
7338 "reload_completed"
7339 [(set (match_dup 0) (match_dup 1))
7340 (set (match_dup 2)
7341 (compare:CC (match_dup 0)
7342 (const_int 0)))]
7343 "")
7344 \f
7345 (define_insn "*movhi_internal"
7346 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7347 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7348 "gpc_reg_operand (operands[0], HImode)
7349 || gpc_reg_operand (operands[1], HImode)"
7350 "@
7351 mr %0,%1
7352 lhz%U1%X1 %0,%1
7353 sth%U0%X0 %1,%0
7354 {lil|li} %0,%w1
7355 mf%1 %0
7356 mt%0 %1
7357 mt%0 %1
7358 {cror 0,0,0|nop}"
7359 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7361 (define_expand "mov<mode>"
7362 [(set (match_operand:INT 0 "general_operand" "")
7363 (match_operand:INT 1 "any_operand" ""))]
7364 ""
7365 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
7367 (define_insn "*movqi_internal"
7368 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7369 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7370 "gpc_reg_operand (operands[0], QImode)
7371 || gpc_reg_operand (operands[1], QImode)"
7372 "@
7373 mr %0,%1
7374 lbz%U1%X1 %0,%1
7375 stb%U0%X0 %1,%0
7376 {lil|li} %0,%1
7377 mf%1 %0
7378 mt%0 %1
7379 mt%0 %1
7380 {cror 0,0,0|nop}"
7381 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7382 \f
7383 ;; Here is how to move condition codes around. When we store CC data in
7384 ;; an integer register or memory, we store just the high-order 4 bits.
7385 ;; This lets us not shift in the most common case of CR0.
7386 (define_expand "movcc"
7387 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7388 (match_operand:CC 1 "nonimmediate_operand" ""))]
7389 ""
7390 "")
7392 (define_insn "*movcc_internal1"
7393 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m")
7394 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))]
7395 "register_operand (operands[0], CCmode)
7396 || register_operand (operands[1], CCmode)"
7397 "@
7398 mcrf %0,%1
7399 mtcrf 128,%1
7400 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
7401 mfcr %0%Q1
7402 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
7403 mr %0,%1
7404 mf%1 %0
7405 mt%0 %1
7406 mt%0 %1
7407 {l%U1%X1|lwz%U1%X1} %0,%1
7408 {st%U0%U1|stw%U0%U1} %1,%0"
7409 [(set (attr "type")
7410 (cond [(eq_attr "alternative" "0")
7411 (const_string "cr_logical")
7412 (eq_attr "alternative" "1,2")
7413 (const_string "mtcr")
7414 (eq_attr "alternative" "5,7")
7415 (const_string "integer")
7416 (eq_attr "alternative" "6")
7417 (const_string "mfjmpr")
7418 (eq_attr "alternative" "8")
7419 (const_string "mtjmpr")
7420 (eq_attr "alternative" "9")
7421 (const_string "load")
7422 (eq_attr "alternative" "10")
7423 (const_string "store")
7424 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
7425 (const_string "mfcrf")
7426 ]
7427 (const_string "mfcr")))
7428 (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")])
7429 \f
7430 ;; For floating-point, we normally deal with the floating-point registers
7431 ;; unless -msoft-float is used. The sole exception is that parameter passing
7432 ;; can produce floating-point values in fixed-point registers. Unless the
7433 ;; value is a simple constant or already in memory, we deal with this by
7434 ;; allocating memory and copying the value explicitly via that memory location.
7435 (define_expand "movsf"
7436 [(set (match_operand:SF 0 "nonimmediate_operand" "")
7437 (match_operand:SF 1 "any_operand" ""))]
7438 ""
7439 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
7441 (define_split
7442 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7443 (match_operand:SF 1 "const_double_operand" ""))]
7444 "reload_completed
7445 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7446 || (GET_CODE (operands[0]) == SUBREG
7447 && GET_CODE (SUBREG_REG (operands[0])) == REG
7448 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7449 [(set (match_dup 2) (match_dup 3))]
7450 "
7451 {
7452 long l;
7453 REAL_VALUE_TYPE rv;
7455 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7456 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
7458 if (! TARGET_POWERPC64)
7459 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
7460 else
7461 operands[2] = gen_lowpart (SImode, operands[0]);
7463 operands[3] = gen_int_mode (l, SImode);
7464 }")
7466 (define_insn "*movsf_hardfloat"
7467 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
7468 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
7469 "(gpc_reg_operand (operands[0], SFmode)
7470 || gpc_reg_operand (operands[1], SFmode))
7471 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
7472 "@
7473 mr %0,%1
7474 {l%U1%X1|lwz%U1%X1} %0,%1
7475 {st%U0%X0|stw%U0%X0} %1,%0
7476 fmr %0,%1
7477 lfs%U1%X1 %0,%1
7478 stfs%U0%X0 %1,%0
7479 mt%0 %1
7480 mt%0 %1
7481 mf%1 %0
7482 {cror 0,0,0|nop}
7483 #
7484 #"
7485 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
7486 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
7488 (define_insn "*movsf_softfloat"
7489 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
7490 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
7491 "(gpc_reg_operand (operands[0], SFmode)
7492 || gpc_reg_operand (operands[1], SFmode))
7493 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
7494 "@
7495 mr %0,%1
7496 mt%0 %1
7497 mt%0 %1
7498 mf%1 %0
7499 {l%U1%X1|lwz%U1%X1} %0,%1
7500 {st%U0%X0|stw%U0%X0} %1,%0
7501 {lil|li} %0,%1
7502 {liu|lis} %0,%v1
7503 {cal|la} %0,%a1
7504 #
7505 #
7506 {cror 0,0,0|nop}"
7507 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
7508 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
7510 \f
7511 (define_expand "movdf"
7512 [(set (match_operand:DF 0 "nonimmediate_operand" "")
7513 (match_operand:DF 1 "any_operand" ""))]
7514 ""
7515 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
7517 (define_split
7518 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7519 (match_operand:DF 1 "const_int_operand" ""))]
7520 "! TARGET_POWERPC64 && reload_completed
7521 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7522 || (GET_CODE (operands[0]) == SUBREG
7523 && GET_CODE (SUBREG_REG (operands[0])) == REG
7524 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7525 [(set (match_dup 2) (match_dup 4))
7526 (set (match_dup 3) (match_dup 1))]
7527 "
7528 {
7529 int endian = (WORDS_BIG_ENDIAN == 0);
7530 HOST_WIDE_INT value = INTVAL (operands[1]);
7532 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7533 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7534 #if HOST_BITS_PER_WIDE_INT == 32
7535 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
7536 #else
7537 operands[4] = GEN_INT (value >> 32);
7538 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
7539 #endif
7540 }")
7542 (define_split
7543 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7544 (match_operand:DF 1 "const_double_operand" ""))]
7545 "! TARGET_POWERPC64 && reload_completed
7546 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7547 || (GET_CODE (operands[0]) == SUBREG
7548 && GET_CODE (SUBREG_REG (operands[0])) == REG
7549 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7550 [(set (match_dup 2) (match_dup 4))
7551 (set (match_dup 3) (match_dup 5))]
7552 "
7553 {
7554 int endian = (WORDS_BIG_ENDIAN == 0);
7555 long l[2];
7556 REAL_VALUE_TYPE rv;
7558 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7559 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7561 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7562 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7563 operands[4] = gen_int_mode (l[endian], SImode);
7564 operands[5] = gen_int_mode (l[1 - endian], SImode);
7565 }")
7567 (define_split
7568 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7569 (match_operand:DF 1 "const_double_operand" ""))]
7570 "TARGET_POWERPC64 && reload_completed
7571 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7572 || (GET_CODE (operands[0]) == SUBREG
7573 && GET_CODE (SUBREG_REG (operands[0])) == REG
7574 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7575 [(set (match_dup 2) (match_dup 3))]
7576 "
7577 {
7578 int endian = (WORDS_BIG_ENDIAN == 0);
7579 long l[2];
7580 REAL_VALUE_TYPE rv;
7581 #if HOST_BITS_PER_WIDE_INT >= 64
7582 HOST_WIDE_INT val;
7583 #endif
7585 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7586 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7588 operands[2] = gen_lowpart (DImode, operands[0]);
7589 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
7590 #if HOST_BITS_PER_WIDE_INT >= 64
7591 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
7592 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
7594 operands[3] = gen_int_mode (val, DImode);
7595 #else
7596 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
7597 #endif
7598 }")
7600 ;; Don't have reload use general registers to load a constant. First,
7601 ;; it might not work if the output operand is the equivalent of
7602 ;; a non-offsettable memref, but also it is less efficient than loading
7603 ;; the constant into an FP register, since it will probably be used there.
7604 ;; The "??" is a kludge until we can figure out a more reasonable way
7605 ;; of handling these non-offsettable values.
7606 (define_insn "*movdf_hardfloat32"
7607 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
7608 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
7609 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
7610 && (gpc_reg_operand (operands[0], DFmode)
7611 || gpc_reg_operand (operands[1], DFmode))"
7612 "*
7613 {
7614 switch (which_alternative)
7615 {
7616 default:
7617 gcc_unreachable ();
7618 case 0:
7619 /* We normally copy the low-numbered register first. However, if
7620 the first register operand 0 is the same as the second register
7621 of operand 1, we must copy in the opposite order. */
7622 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
7623 return \"mr %L0,%L1\;mr %0,%1\";
7624 else
7625 return \"mr %0,%1\;mr %L0,%L1\";
7626 case 1:
7627 if (GET_CODE (operands[1]) == MEM
7628 && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[1], 0),
7629 reload_completed || reload_in_progress)
7630 || rs6000_legitimate_small_data_p (DFmode, XEXP (operands[1], 0))
7631 || GET_CODE (XEXP (operands[1], 0)) == REG
7632 || GET_CODE (XEXP (operands[1], 0)) == LO_SUM
7633 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
7634 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC))
7635 {
7636 /* If the low-address word is used in the address, we must load
7637 it last. Otherwise, load it first. Note that we cannot have
7638 auto-increment in that case since the address register is
7639 known to be dead. */
7640 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
7641 operands[1], 0))
7642 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
7643 else
7644 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
7645 }
7646 else
7647 {
7648 rtx addreg;
7650 addreg = find_addr_reg (XEXP (operands[1], 0));
7651 if (refers_to_regno_p (REGNO (operands[0]),
7652 REGNO (operands[0]) + 1,
7653 operands[1], 0))
7654 {
7655 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7656 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
7657 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7658 return \"{lx|lwzx} %0,%1\";
7659 }
7660 else
7661 {
7662 output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
7663 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7664 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
7665 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7666 return \"\";
7667 }
7668 }
7669 case 2:
7670 if (GET_CODE (operands[0]) == MEM
7671 && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[0], 0),
7672 reload_completed || reload_in_progress)
7673 || rs6000_legitimate_small_data_p (DFmode, XEXP (operands[0], 0))
7674 || GET_CODE (XEXP (operands[0], 0)) == REG
7675 || GET_CODE (XEXP (operands[0], 0)) == LO_SUM
7676 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
7677 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC))
7678 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
7679 else
7680 {
7681 rtx addreg;
7683 addreg = find_addr_reg (XEXP (operands[0], 0));
7684 output_asm_insn (\"{stx|stwx} %1,%0\", operands);
7685 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7686 output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
7687 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7688 return \"\";
7689 }
7690 case 3:
7691 return \"fmr %0,%1\";
7692 case 4:
7693 return \"lfd%U1%X1 %0,%1\";
7694 case 5:
7695 return \"stfd%U0%X0 %1,%0\";
7696 case 6:
7697 case 7:
7698 case 8:
7699 return \"#\";
7700 }
7701 }"
7702 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
7703 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
7705 (define_insn "*movdf_softfloat32"
7706 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
7707 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
7708 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
7709 && (gpc_reg_operand (operands[0], DFmode)
7710 || gpc_reg_operand (operands[1], DFmode))"
7711 "*
7712 {
7713 switch (which_alternative)
7714 {
7715 default:
7716 gcc_unreachable ();
7717 case 0:
7718 /* We normally copy the low-numbered register first. However, if
7719 the first register operand 0 is the same as the second register of
7720 operand 1, we must copy in the opposite order. */
7721 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
7722 return \"mr %L0,%L1\;mr %0,%1\";
7723 else
7724 return \"mr %0,%1\;mr %L0,%L1\";
7725 case 1:
7726 /* If the low-address word is used in the address, we must load
7727 it last. Otherwise, load it first. Note that we cannot have
7728 auto-increment in that case since the address register is
7729 known to be dead. */
7730 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
7731 operands[1], 0))
7732 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
7733 else
7734 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
7735 case 2:
7736 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
7737 case 3:
7738 case 4:
7739 case 5:
7740 return \"#\";
7741 }
7742 }"
7743 [(set_attr "type" "two,load,store,*,*,*")
7744 (set_attr "length" "8,8,8,8,12,16")])
7746 ; ld/std require word-aligned displacements -> 'Y' constraint.
7747 ; List Y->r and r->Y before r->r for reload.
7748 (define_insn "*movdf_hardfloat64"
7749 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r")
7750 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
7751 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
7752 && (gpc_reg_operand (operands[0], DFmode)
7753 || gpc_reg_operand (operands[1], DFmode))"
7754 "@
7755 std%U0%X0 %1,%0
7756 ld%U1%X1 %0,%1
7757 mr %0,%1
7758 fmr %0,%1
7759 lfd%U1%X1 %0,%1
7760 stfd%U0%X0 %1,%0
7761 mt%0 %1
7762 mf%1 %0
7763 {cror 0,0,0|nop}
7764 #
7765 #
7766 #"
7767 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*")
7768 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
7770 (define_insn "*movdf_softfloat64"
7771 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
7772 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
7773 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
7774 && (gpc_reg_operand (operands[0], DFmode)
7775 || gpc_reg_operand (operands[1], DFmode))"
7776 "@
7777 ld%U1%X1 %0,%1
7778 std%U0%X0 %1,%0
7779 mr %0,%1
7780 mt%0 %1
7781 mf%1 %0
7782 #
7783 #
7784 #
7785 {cror 0,0,0|nop}"
7786 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
7787 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
7788 \f
7789 (define_expand "movtf"
7790 [(set (match_operand:TF 0 "general_operand" "")
7791 (match_operand:TF 1 "any_operand" ""))]
7792 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
7793 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
7795 ; It's important to list the o->f and f->o moves before f->f because
7796 ; otherwise reload, given m->f, will try to pick f->f and reload it,
7797 ; which doesn't make progress. Likewise r->Y must be before r->r.
7798 (define_insn_and_split "*movtf_internal"
7799 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
7800 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))]
7801 "!TARGET_IEEEQUAD
7802 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
7803 && (gpc_reg_operand (operands[0], TFmode)
7804 || gpc_reg_operand (operands[1], TFmode))"
7805 "#"
7806 "&& reload_completed"
7807 [(pc)]
7808 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
7809 [(set_attr "length" "8,8,8,20,20,16")])
7811 (define_insn_and_split "*movtf_softfloat"
7812 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,Y,r")
7813 (match_operand:TF 1 "input_operand" "YGHF,r,r"))]
7814 "!TARGET_IEEEQUAD
7815 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
7816 && (gpc_reg_operand (operands[0], TFmode)
7817 || gpc_reg_operand (operands[1], TFmode))"
7818 "#"
7819 "&& reload_completed"
7820 [(pc)]
7821 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
7822 [(set_attr "length" "20,20,16")])
7824 (define_expand "extenddftf2"
7825 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
7826 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
7827 (use (match_dup 2))])]
7828 "!TARGET_IEEEQUAD
7829 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7830 {
7831 operands[2] = CONST0_RTX (DFmode);
7832 if (DEFAULT_ABI == ABI_V4 && flag_pic)
7833 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
7834 })
7836 (define_insn_and_split "*extenddftf2_internal"
7837 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
7838 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
7839 (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
7840 "!TARGET_IEEEQUAD
7841 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7842 "#"
7843 "&& reload_completed"
7844 [(pc)]
7845 {
7846 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
7847 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
7848 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
7849 operands[1]);
7850 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
7851 operands[2]);
7852 DONE;
7853 })
7855 (define_expand "extendsftf2"
7856 [(set (match_operand:TF 0 "nonimmediate_operand" "")
7857 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
7858 "!TARGET_IEEEQUAD
7859 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7860 {
7861 rtx tmp = gen_reg_rtx (DFmode);
7862 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
7863 emit_insn (gen_extenddftf2 (operands[0], tmp));
7864 DONE;
7865 })
7867 (define_expand "trunctfdf2"
7868 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7869 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
7870 "!TARGET_IEEEQUAD
7871 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7872 "")
7874 (define_insn_and_split "trunctfdf2_internal1"
7875 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
7876 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
7877 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
7878 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7879 "@
7880 #
7881 fmr %0,%1"
7882 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
7883 [(const_int 0)]
7884 {
7885 emit_note (NOTE_INSN_DELETED);
7886 DONE;
7887 }
7888 [(set_attr "type" "fp")])
7890 (define_insn "trunctfdf2_internal2"
7891 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
7892 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
7893 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
7894 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7895 "fadd %0,%1,%L1"
7896 [(set_attr "type" "fp")])
7898 (define_insn_and_split "trunctfsf2"
7899 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
7900 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
7901 (clobber (match_scratch:DF 2 "=f"))]
7902 "!TARGET_IEEEQUAD
7903 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7904 "#"
7905 "&& reload_completed"
7906 [(set (match_dup 2)
7907 (float_truncate:DF (match_dup 1)))
7908 (set (match_dup 0)
7909 (float_truncate:SF (match_dup 2)))]
7910 "")
7912 (define_expand "floatsitf2"
7913 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
7914 (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))]
7915 "!TARGET_IEEEQUAD
7916 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7917 {
7918 rtx tmp = gen_reg_rtx (DFmode);
7919 expand_float (tmp, operands[1], false);
7920 emit_insn (gen_extenddftf2 (operands[0], tmp));
7921 DONE;
7922 })
7924 ; fadd, but rounding towards zero.
7925 ; This is probably not the optimal code sequence.
7926 (define_insn "fix_trunc_helper"
7927 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
7928 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
7929 UNSPEC_FIX_TRUNC_TF))
7930 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
7931 "TARGET_HARD_FLOAT && TARGET_FPRS"
7932 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
7933 [(set_attr "type" "fp")
7934 (set_attr "length" "20")])
7936 (define_expand "fix_trunctfsi2"
7937 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
7938 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
7939 (clobber (match_dup 2))
7940 (clobber (match_dup 3))
7941 (clobber (match_dup 4))
7942 (clobber (match_dup 5))])]
7943 "!TARGET_IEEEQUAD
7944 && (TARGET_POWER2 || TARGET_POWERPC)
7945 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7946 {
7947 operands[2] = gen_reg_rtx (DFmode);
7948 operands[3] = gen_reg_rtx (DFmode);
7949 operands[4] = gen_reg_rtx (DImode);
7950 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
7951 })
7953 (define_insn_and_split "*fix_trunctfsi2_internal"
7954 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7955 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
7956 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
7957 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
7958 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
7959 (clobber (match_operand:DI 5 "memory_operand" "=o"))]
7960 "!TARGET_IEEEQUAD
7961 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7962 "#"
7963 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[5]))"
7964 [(pc)]
7965 {
7966 rtx lowword;
7967 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
7969 gcc_assert (MEM_P (operands[5]));
7970 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
7972 emit_insn (gen_fctiwz (operands[4], operands[2]));
7973 emit_move_insn (operands[5], operands[4]);
7974 emit_move_insn (operands[0], lowword);
7975 DONE;
7976 })
7978 (define_insn "negtf2"
7979 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
7980 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
7981 "!TARGET_IEEEQUAD
7982 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7983 "*
7984 {
7985 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
7986 return \"fneg %L0,%L1\;fneg %0,%1\";
7987 else
7988 return \"fneg %0,%1\;fneg %L0,%L1\";
7989 }"
7990 [(set_attr "type" "fp")
7991 (set_attr "length" "8")])
7993 (define_expand "abstf2"
7994 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
7995 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
7996 "!TARGET_IEEEQUAD
7997 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7998 "
7999 {
8000 rtx label = gen_label_rtx ();
8001 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8002 emit_label (label);
8003 DONE;
8004 }")
8006 (define_expand "abstf2_internal"
8007 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8008 (match_operand:TF 1 "gpc_reg_operand" "f"))
8009 (set (match_dup 3) (match_dup 5))
8010 (set (match_dup 5) (abs:DF (match_dup 5)))
8011 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8012 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8013 (label_ref (match_operand 2 "" ""))
8014 (pc)))
8015 (set (match_dup 6) (neg:DF (match_dup 6)))]
8016 "!TARGET_IEEEQUAD
8017 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8018 "
8019 {
8020 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8021 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8022 operands[3] = gen_reg_rtx (DFmode);
8023 operands[4] = gen_reg_rtx (CCFPmode);
8024 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8025 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8026 }")
8027 \f
8028 ;; Next come the multi-word integer load and store and the load and store
8029 ;; multiple insns.
8031 ; List r->r after r->"o<>", otherwise reload will try to reload a
8032 ; non-offsettable address by using r->r which won't make progress.
8033 (define_insn "*movdi_internal32"
8034 [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
8035 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
8036 "! TARGET_POWERPC64
8037 && (gpc_reg_operand (operands[0], DImode)
8038 || gpc_reg_operand (operands[1], DImode))"
8039 "@
8040 #
8041 #
8042 #
8043 fmr %0,%1
8044 lfd%U1%X1 %0,%1
8045 stfd%U0%X0 %1,%0
8046 #"
8047 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
8049 (define_split
8050 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8051 (match_operand:DI 1 "const_int_operand" ""))]
8052 "! TARGET_POWERPC64 && reload_completed"
8053 [(set (match_dup 2) (match_dup 4))
8054 (set (match_dup 3) (match_dup 1))]
8055 "
8056 {
8057 HOST_WIDE_INT value = INTVAL (operands[1]);
8058 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8059 DImode);
8060 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8061 DImode);
8062 #if HOST_BITS_PER_WIDE_INT == 32
8063 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8064 #else
8065 operands[4] = GEN_INT (value >> 32);
8066 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8067 #endif
8068 }")
8070 (define_split
8071 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8072 (match_operand:DI 1 "input_operand" ""))]
8073 "reload_completed && !TARGET_POWERPC64
8074 && gpr_or_gpr_p (operands[0], operands[1])"
8075 [(pc)]
8076 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8078 (define_insn "*movdi_internal64"
8079 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
8080 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
8081 "TARGET_POWERPC64
8082 && (gpc_reg_operand (operands[0], DImode)
8083 || gpc_reg_operand (operands[1], DImode))"
8084 "@
8085 mr %0,%1
8086 ld%U1%X1 %0,%1
8087 std%U0%X0 %1,%0
8088 li %0,%1
8089 lis %0,%v1
8090 #
8091 {cal|la} %0,%a1
8092 fmr %0,%1
8093 lfd%U1%X1 %0,%1
8094 stfd%U0%X0 %1,%0
8095 mf%1 %0
8096 mt%0 %1
8097 {cror 0,0,0|nop}"
8098 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
8099 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8101 ;; immediate value valid for a single instruction hiding in a const_double
8102 (define_insn ""
8103 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8104 (match_operand:DI 1 "const_double_operand" "F"))]
8105 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8106 && GET_CODE (operands[1]) == CONST_DOUBLE
8107 && num_insns_constant (operands[1], DImode) == 1"
8108 "*
8109 {
8110 return ((unsigned HOST_WIDE_INT)
8111 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8112 ? \"li %0,%1\" : \"lis %0,%v1\";
8113 }")
8115 ;; Generate all one-bits and clear left or right.
8116 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8117 (define_split
8118 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8119 (match_operand:DI 1 "mask64_operand" ""))]
8120 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8121 [(set (match_dup 0) (const_int -1))
8122 (set (match_dup 0)
8123 (and:DI (rotate:DI (match_dup 0)
8124 (const_int 0))
8125 (match_dup 1)))]
8126 "")
8128 ;; Split a load of a large constant into the appropriate five-instruction
8129 ;; sequence. Handle anything in a constant number of insns.
8130 ;; When non-easy constants can go in the TOC, this should use
8131 ;; easy_fp_constant predicate.
8132 (define_split
8133 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8134 (match_operand:DI 1 "const_int_operand" ""))]
8135 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8136 [(set (match_dup 0) (match_dup 2))
8137 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8138 "
8139 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8141 if (tem == operands[0])
8142 DONE;
8143 else
8144 FAIL;
8145 }")
8147 (define_split
8148 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8149 (match_operand:DI 1 "const_double_operand" ""))]
8150 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8151 [(set (match_dup 0) (match_dup 2))
8152 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8153 "
8154 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8156 if (tem == operands[0])
8157 DONE;
8158 else
8159 FAIL;
8160 }")
8161 \f
8162 ;; TImode is similar, except that we usually want to compute the address into
8163 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
8164 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
8166 ;; We say that MQ is clobbered in the last alternative because the first
8167 ;; alternative would never get used otherwise since it would need a reload
8168 ;; while the 2nd alternative would not. We put memory cases first so they
8169 ;; are preferred. Otherwise, we'd try to reload the output instead of
8170 ;; giving the SCRATCH mq.
8172 (define_insn "*movti_power"
8173 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
8174 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
8175 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
8176 "TARGET_POWER && ! TARGET_POWERPC64
8177 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8178 "*
8179 {
8180 switch (which_alternative)
8181 {
8182 default:
8183 gcc_unreachable ();
8185 case 0:
8186 if (TARGET_STRING)
8187 return \"{stsi|stswi} %1,%P0,16\";
8188 case 1:
8189 case 2:
8190 return \"#\";
8191 case 3:
8192 /* If the address is not used in the output, we can use lsi. Otherwise,
8193 fall through to generating four loads. */
8194 if (TARGET_STRING
8195 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8196 return \"{lsi|lswi} %0,%P1,16\";
8197 /* ... fall through ... */
8198 case 4:
8199 case 5:
8200 return \"#\";
8201 }
8202 }"
8203 [(set_attr "type" "store,store,*,load,load,*")])
8205 (define_insn "*movti_string"
8206 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
8207 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
8208 "! TARGET_POWER && ! TARGET_POWERPC64
8209 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8210 "*
8211 {
8212 switch (which_alternative)
8213 {
8214 default:
8215 gcc_unreachable ();
8216 case 0:
8217 if (TARGET_STRING)
8218 return \"{stsi|stswi} %1,%P0,16\";
8219 case 1:
8220 case 2:
8221 return \"#\";
8222 case 3:
8223 /* If the address is not used in the output, we can use lsi. Otherwise,
8224 fall through to generating four loads. */
8225 if (TARGET_STRING
8226 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8227 return \"{lsi|lswi} %0,%P1,16\";
8228 /* ... fall through ... */
8229 case 4:
8230 case 5:
8231 return \"#\";
8232 }
8233 }"
8234 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")])
8236 (define_insn "*movti_ppc64"
8237 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
8238 (match_operand:TI 1 "input_operand" "r,r,m"))]
8239 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8240 || gpc_reg_operand (operands[1], TImode))"
8241 "#"
8242 [(set_attr "type" "*,load,store")])
8244 (define_split
8245 [(set (match_operand:TI 0 "gpc_reg_operand" "")
8246 (match_operand:TI 1 "const_double_operand" ""))]
8247 "TARGET_POWERPC64"
8248 [(set (match_dup 2) (match_dup 4))
8249 (set (match_dup 3) (match_dup 5))]
8250 "
8251 {
8252 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8253 TImode);
8254 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8255 TImode);
8256 if (GET_CODE (operands[1]) == CONST_DOUBLE)
8257 {
8258 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8259 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8260 }
8261 else if (GET_CODE (operands[1]) == CONST_INT)
8262 {
8263 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8264 operands[5] = operands[1];
8265 }
8266 else
8267 FAIL;
8268 }")
8270 (define_split
8271 [(set (match_operand:TI 0 "nonimmediate_operand" "")
8272 (match_operand:TI 1 "input_operand" ""))]
8273 "reload_completed
8274 && gpr_or_gpr_p (operands[0], operands[1])"
8275 [(pc)]
8276 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8277 \f
8278 (define_expand "load_multiple"
8279 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8280 (match_operand:SI 1 "" ""))
8281 (use (match_operand:SI 2 "" ""))])]
8282 "TARGET_STRING && !TARGET_POWERPC64"
8283 "
8284 {
8285 int regno;
8286 int count;
8287 rtx op1;
8288 int i;
8290 /* Support only loading a constant number of fixed-point registers from
8291 memory and only bother with this if more than two; the machine
8292 doesn't support more than eight. */
8293 if (GET_CODE (operands[2]) != CONST_INT
8294 || INTVAL (operands[2]) <= 2
8295 || INTVAL (operands[2]) > 8
8296 || GET_CODE (operands[1]) != MEM
8297 || GET_CODE (operands[0]) != REG
8298 || REGNO (operands[0]) >= 32)
8299 FAIL;
8301 count = INTVAL (operands[2]);
8302 regno = REGNO (operands[0]);
8304 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8305 op1 = replace_equiv_address (operands[1],
8306 force_reg (SImode, XEXP (operands[1], 0)));
8308 for (i = 0; i < count; i++)
8309 XVECEXP (operands[3], 0, i)
8310 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8311 adjust_address_nv (op1, SImode, i * 4));
8312 }")
8314 (define_insn "*ldmsi8"
8315 [(match_parallel 0 "load_multiple_operation"
8316 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8317 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8318 (set (match_operand:SI 3 "gpc_reg_operand" "")
8319 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8320 (set (match_operand:SI 4 "gpc_reg_operand" "")
8321 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8322 (set (match_operand:SI 5 "gpc_reg_operand" "")
8323 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8324 (set (match_operand:SI 6 "gpc_reg_operand" "")
8325 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8326 (set (match_operand:SI 7 "gpc_reg_operand" "")
8327 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8328 (set (match_operand:SI 8 "gpc_reg_operand" "")
8329 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8330 (set (match_operand:SI 9 "gpc_reg_operand" "")
8331 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8332 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8333 "*
8334 { return rs6000_output_load_multiple (operands); }"
8335 [(set_attr "type" "load_ux")
8336 (set_attr "length" "32")])
8338 (define_insn "*ldmsi7"
8339 [(match_parallel 0 "load_multiple_operation"
8340 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8341 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8342 (set (match_operand:SI 3 "gpc_reg_operand" "")
8343 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8344 (set (match_operand:SI 4 "gpc_reg_operand" "")
8345 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8346 (set (match_operand:SI 5 "gpc_reg_operand" "")
8347 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8348 (set (match_operand:SI 6 "gpc_reg_operand" "")
8349 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8350 (set (match_operand:SI 7 "gpc_reg_operand" "")
8351 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8352 (set (match_operand:SI 8 "gpc_reg_operand" "")
8353 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
8354 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8355 "*
8356 { return rs6000_output_load_multiple (operands); }"
8357 [(set_attr "type" "load_ux")
8358 (set_attr "length" "32")])
8360 (define_insn "*ldmsi6"
8361 [(match_parallel 0 "load_multiple_operation"
8362 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8363 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8364 (set (match_operand:SI 3 "gpc_reg_operand" "")
8365 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8366 (set (match_operand:SI 4 "gpc_reg_operand" "")
8367 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8368 (set (match_operand:SI 5 "gpc_reg_operand" "")
8369 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8370 (set (match_operand:SI 6 "gpc_reg_operand" "")
8371 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8372 (set (match_operand:SI 7 "gpc_reg_operand" "")
8373 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
8374 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8375 "*
8376 { return rs6000_output_load_multiple (operands); }"
8377 [(set_attr "type" "load_ux")
8378 (set_attr "length" "32")])
8380 (define_insn "*ldmsi5"
8381 [(match_parallel 0 "load_multiple_operation"
8382 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8383 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8384 (set (match_operand:SI 3 "gpc_reg_operand" "")
8385 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8386 (set (match_operand:SI 4 "gpc_reg_operand" "")
8387 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8388 (set (match_operand:SI 5 "gpc_reg_operand" "")
8389 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8390 (set (match_operand:SI 6 "gpc_reg_operand" "")
8391 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
8392 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
8393 "*
8394 { return rs6000_output_load_multiple (operands); }"
8395 [(set_attr "type" "load_ux")
8396 (set_attr "length" "32")])
8398 (define_insn "*ldmsi4"
8399 [(match_parallel 0 "load_multiple_operation"
8400 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8401 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8402 (set (match_operand:SI 3 "gpc_reg_operand" "")
8403 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8404 (set (match_operand:SI 4 "gpc_reg_operand" "")
8405 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8406 (set (match_operand:SI 5 "gpc_reg_operand" "")
8407 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
8408 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
8409 "*
8410 { return rs6000_output_load_multiple (operands); }"
8411 [(set_attr "type" "load_ux")
8412 (set_attr "length" "32")])
8414 (define_insn "*ldmsi3"
8415 [(match_parallel 0 "load_multiple_operation"
8416 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8417 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8418 (set (match_operand:SI 3 "gpc_reg_operand" "")
8419 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8420 (set (match_operand:SI 4 "gpc_reg_operand" "")
8421 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
8422 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
8423 "*
8424 { return rs6000_output_load_multiple (operands); }"
8425 [(set_attr "type" "load_ux")
8426 (set_attr "length" "32")])
8428 (define_expand "store_multiple"
8429 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8430 (match_operand:SI 1 "" ""))
8431 (clobber (scratch:SI))
8432 (use (match_operand:SI 2 "" ""))])]
8433 "TARGET_STRING && !TARGET_POWERPC64"
8434 "
8435 {
8436 int regno;
8437 int count;
8438 rtx to;
8439 rtx op0;
8440 int i;
8442 /* Support only storing a constant number of fixed-point registers to
8443 memory and only bother with this if more than two; the machine
8444 doesn't support more than eight. */
8445 if (GET_CODE (operands[2]) != CONST_INT
8446 || INTVAL (operands[2]) <= 2
8447 || INTVAL (operands[2]) > 8
8448 || GET_CODE (operands[0]) != MEM
8449 || GET_CODE (operands[1]) != REG
8450 || REGNO (operands[1]) >= 32)
8451 FAIL;
8453 count = INTVAL (operands[2]);
8454 regno = REGNO (operands[1]);
8456 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
8457 to = force_reg (SImode, XEXP (operands[0], 0));
8458 op0 = replace_equiv_address (operands[0], to);
8460 XVECEXP (operands[3], 0, 0)
8461 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
8462 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
8463 gen_rtx_SCRATCH (SImode));
8465 for (i = 1; i < count; i++)
8466 XVECEXP (operands[3], 0, i + 1)
8467 = gen_rtx_SET (VOIDmode,
8468 adjust_address_nv (op0, SImode, i * 4),
8469 gen_rtx_REG (SImode, regno + i));
8470 }")
8472 (define_insn "*stmsi8"
8473 [(match_parallel 0 "store_multiple_operation"
8474 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8475 (match_operand:SI 2 "gpc_reg_operand" "r"))
8476 (clobber (match_scratch:SI 3 "X"))
8477 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8478 (match_operand:SI 4 "gpc_reg_operand" "r"))
8479 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8480 (match_operand:SI 5 "gpc_reg_operand" "r"))
8481 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8482 (match_operand:SI 6 "gpc_reg_operand" "r"))
8483 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8484 (match_operand:SI 7 "gpc_reg_operand" "r"))
8485 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8486 (match_operand:SI 8 "gpc_reg_operand" "r"))
8487 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8488 (match_operand:SI 9 "gpc_reg_operand" "r"))
8489 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
8490 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
8491 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
8492 "{stsi|stswi} %2,%1,%O0"
8493 [(set_attr "type" "store_ux")])
8495 (define_insn "*stmsi7"
8496 [(match_parallel 0 "store_multiple_operation"
8497 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8498 (match_operand:SI 2 "gpc_reg_operand" "r"))
8499 (clobber (match_scratch:SI 3 "X"))
8500 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8501 (match_operand:SI 4 "gpc_reg_operand" "r"))
8502 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8503 (match_operand:SI 5 "gpc_reg_operand" "r"))
8504 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8505 (match_operand:SI 6 "gpc_reg_operand" "r"))
8506 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8507 (match_operand:SI 7 "gpc_reg_operand" "r"))
8508 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8509 (match_operand:SI 8 "gpc_reg_operand" "r"))
8510 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8511 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
8512 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
8513 "{stsi|stswi} %2,%1,%O0"
8514 [(set_attr "type" "store_ux")])
8516 (define_insn "*stmsi6"
8517 [(match_parallel 0 "store_multiple_operation"
8518 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8519 (match_operand:SI 2 "gpc_reg_operand" "r"))
8520 (clobber (match_scratch:SI 3 "X"))
8521 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8522 (match_operand:SI 4 "gpc_reg_operand" "r"))
8523 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8524 (match_operand:SI 5 "gpc_reg_operand" "r"))
8525 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8526 (match_operand:SI 6 "gpc_reg_operand" "r"))
8527 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8528 (match_operand:SI 7 "gpc_reg_operand" "r"))
8529 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8530 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
8531 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
8532 "{stsi|stswi} %2,%1,%O0"
8533 [(set_attr "type" "store_ux")])
8535 (define_insn "*stmsi5"
8536 [(match_parallel 0 "store_multiple_operation"
8537 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8538 (match_operand:SI 2 "gpc_reg_operand" "r"))
8539 (clobber (match_scratch:SI 3 "X"))
8540 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8541 (match_operand:SI 4 "gpc_reg_operand" "r"))
8542 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8543 (match_operand:SI 5 "gpc_reg_operand" "r"))
8544 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8545 (match_operand:SI 6 "gpc_reg_operand" "r"))
8546 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8547 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
8548 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
8549 "{stsi|stswi} %2,%1,%O0"
8550 [(set_attr "type" "store_ux")])
8552 (define_insn "*stmsi4"
8553 [(match_parallel 0 "store_multiple_operation"
8554 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8555 (match_operand:SI 2 "gpc_reg_operand" "r"))
8556 (clobber (match_scratch:SI 3 "X"))
8557 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8558 (match_operand:SI 4 "gpc_reg_operand" "r"))
8559 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8560 (match_operand:SI 5 "gpc_reg_operand" "r"))
8561 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8562 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
8563 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
8564 "{stsi|stswi} %2,%1,%O0"
8565 [(set_attr "type" "store_ux")])
8567 (define_insn "*stmsi3"
8568 [(match_parallel 0 "store_multiple_operation"
8569 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8570 (match_operand:SI 2 "gpc_reg_operand" "r"))
8571 (clobber (match_scratch:SI 3 "X"))
8572 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8573 (match_operand:SI 4 "gpc_reg_operand" "r"))
8574 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8575 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
8576 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
8577 "{stsi|stswi} %2,%1,%O0"
8578 [(set_attr "type" "store_ux")])
8580 (define_insn "*stmsi8_power"
8581 [(match_parallel 0 "store_multiple_operation"
8582 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8583 (match_operand:SI 2 "gpc_reg_operand" "r"))
8584 (clobber (match_scratch:SI 3 "=q"))
8585 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8586 (match_operand:SI 4 "gpc_reg_operand" "r"))
8587 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8588 (match_operand:SI 5 "gpc_reg_operand" "r"))
8589 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8590 (match_operand:SI 6 "gpc_reg_operand" "r"))
8591 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8592 (match_operand:SI 7 "gpc_reg_operand" "r"))
8593 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8594 (match_operand:SI 8 "gpc_reg_operand" "r"))
8595 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8596 (match_operand:SI 9 "gpc_reg_operand" "r"))
8597 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
8598 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
8599 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
8600 "{stsi|stswi} %2,%1,%O0"
8601 [(set_attr "type" "store_ux")])
8603 (define_insn "*stmsi7_power"
8604 [(match_parallel 0 "store_multiple_operation"
8605 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8606 (match_operand:SI 2 "gpc_reg_operand" "r"))
8607 (clobber (match_scratch:SI 3 "=q"))
8608 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8609 (match_operand:SI 4 "gpc_reg_operand" "r"))
8610 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8611 (match_operand:SI 5 "gpc_reg_operand" "r"))
8612 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8613 (match_operand:SI 6 "gpc_reg_operand" "r"))
8614 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8615 (match_operand:SI 7 "gpc_reg_operand" "r"))
8616 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8617 (match_operand:SI 8 "gpc_reg_operand" "r"))
8618 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8619 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
8620 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
8621 "{stsi|stswi} %2,%1,%O0"
8622 [(set_attr "type" "store_ux")])
8624 (define_insn "*stmsi6_power"
8625 [(match_parallel 0 "store_multiple_operation"
8626 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8627 (match_operand:SI 2 "gpc_reg_operand" "r"))
8628 (clobber (match_scratch:SI 3 "=q"))
8629 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8630 (match_operand:SI 4 "gpc_reg_operand" "r"))
8631 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8632 (match_operand:SI 5 "gpc_reg_operand" "r"))
8633 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8634 (match_operand:SI 6 "gpc_reg_operand" "r"))
8635 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8636 (match_operand:SI 7 "gpc_reg_operand" "r"))
8637 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8638 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
8639 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
8640 "{stsi|stswi} %2,%1,%O0"
8641 [(set_attr "type" "store_ux")])
8643 (define_insn "*stmsi5_power"
8644 [(match_parallel 0 "store_multiple_operation"
8645 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8646 (match_operand:SI 2 "gpc_reg_operand" "r"))
8647 (clobber (match_scratch:SI 3 "=q"))
8648 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8649 (match_operand:SI 4 "gpc_reg_operand" "r"))
8650 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8651 (match_operand:SI 5 "gpc_reg_operand" "r"))
8652 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8653 (match_operand:SI 6 "gpc_reg_operand" "r"))
8654 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8655 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
8656 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
8657 "{stsi|stswi} %2,%1,%O0"
8658 [(set_attr "type" "store_ux")])
8660 (define_insn "*stmsi4_power"
8661 [(match_parallel 0 "store_multiple_operation"
8662 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8663 (match_operand:SI 2 "gpc_reg_operand" "r"))
8664 (clobber (match_scratch:SI 3 "=q"))
8665 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8666 (match_operand:SI 4 "gpc_reg_operand" "r"))
8667 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8668 (match_operand:SI 5 "gpc_reg_operand" "r"))
8669 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8670 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
8671 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
8672 "{stsi|stswi} %2,%1,%O0"
8673 [(set_attr "type" "store_ux")])
8675 (define_insn "*stmsi3_power"
8676 [(match_parallel 0 "store_multiple_operation"
8677 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8678 (match_operand:SI 2 "gpc_reg_operand" "r"))
8679 (clobber (match_scratch:SI 3 "=q"))
8680 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8681 (match_operand:SI 4 "gpc_reg_operand" "r"))
8682 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8683 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
8684 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
8685 "{stsi|stswi} %2,%1,%O0"
8686 [(set_attr "type" "store_ux")])
8687 \f
8688 (define_expand "setmemsi"
8689 [(parallel [(set (match_operand:BLK 0 "" "")
8690 (match_operand 2 "const_int_operand" ""))
8691 (use (match_operand:SI 1 "" ""))
8692 (use (match_operand:SI 3 "" ""))])]
8693 ""
8694 "
8695 {
8696 /* If value to set is not zero, use the library routine. */
8697 if (operands[2] != const0_rtx)
8698 FAIL;
8700 if (expand_block_clear (operands))
8701 DONE;
8702 else
8703 FAIL;
8704 }")
8706 ;; String/block move insn.
8707 ;; Argument 0 is the destination
8708 ;; Argument 1 is the source
8709 ;; Argument 2 is the length
8710 ;; Argument 3 is the alignment
8712 (define_expand "movmemsi"
8713 [(parallel [(set (match_operand:BLK 0 "" "")
8714 (match_operand:BLK 1 "" ""))
8715 (use (match_operand:SI 2 "" ""))
8716 (use (match_operand:SI 3 "" ""))])]
8717 ""
8718 "
8719 {
8720 if (expand_block_move (operands))
8721 DONE;
8722 else
8723 FAIL;
8724 }")
8726 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
8727 ;; register allocator doesn't have a clue about allocating 8 word registers.
8728 ;; rD/rS = r5 is preferred, efficient form.
8729 (define_expand "movmemsi_8reg"
8730 [(parallel [(set (match_operand 0 "" "")
8731 (match_operand 1 "" ""))
8732 (use (match_operand 2 "" ""))
8733 (use (match_operand 3 "" ""))
8734 (clobber (reg:SI 5))
8735 (clobber (reg:SI 6))
8736 (clobber (reg:SI 7))
8737 (clobber (reg:SI 8))
8738 (clobber (reg:SI 9))
8739 (clobber (reg:SI 10))
8740 (clobber (reg:SI 11))
8741 (clobber (reg:SI 12))
8742 (clobber (match_scratch:SI 4 ""))])]
8743 "TARGET_STRING"
8744 "")
8746 (define_insn ""
8747 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8748 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8749 (use (match_operand:SI 2 "immediate_operand" "i"))
8750 (use (match_operand:SI 3 "immediate_operand" "i"))
8751 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8752 (clobber (reg:SI 6))
8753 (clobber (reg:SI 7))
8754 (clobber (reg:SI 8))
8755 (clobber (reg:SI 9))
8756 (clobber (reg:SI 10))
8757 (clobber (reg:SI 11))
8758 (clobber (reg:SI 12))
8759 (clobber (match_scratch:SI 5 "=q"))]
8760 "TARGET_STRING && TARGET_POWER
8761 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
8762 || INTVAL (operands[2]) == 0)
8763 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
8764 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
8765 && REGNO (operands[4]) == 5"
8766 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8767 [(set_attr "type" "store_ux")
8768 (set_attr "length" "8")])
8770 (define_insn ""
8771 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
8772 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
8773 (use (match_operand:SI 2 "immediate_operand" "i"))
8774 (use (match_operand:SI 3 "immediate_operand" "i"))
8775 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8776 (clobber (reg:SI 6))
8777 (clobber (reg:SI 7))
8778 (clobber (reg:SI 8))
8779 (clobber (reg:SI 9))
8780 (clobber (reg:SI 10))
8781 (clobber (reg:SI 11))
8782 (clobber (reg:SI 12))
8783 (clobber (match_scratch:SI 5 "X"))]
8784 "TARGET_STRING && ! TARGET_POWER
8785 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
8786 || INTVAL (operands[2]) == 0)
8787 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
8788 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
8789 && REGNO (operands[4]) == 5"
8790 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8791 [(set_attr "type" "store_ux")
8792 (set_attr "length" "8")])
8794 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
8795 ;; register allocator doesn't have a clue about allocating 6 word registers.
8796 ;; rD/rS = r5 is preferred, efficient form.
8797 (define_expand "movmemsi_6reg"
8798 [(parallel [(set (match_operand 0 "" "")
8799 (match_operand 1 "" ""))
8800 (use (match_operand 2 "" ""))
8801 (use (match_operand 3 "" ""))
8802 (clobber (reg:SI 5))
8803 (clobber (reg:SI 6))
8804 (clobber (reg:SI 7))
8805 (clobber (reg:SI 8))
8806 (clobber (reg:SI 9))
8807 (clobber (reg:SI 10))
8808 (clobber (match_scratch:SI 4 ""))])]
8809 "TARGET_STRING"
8810 "")
8812 (define_insn ""
8813 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8814 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8815 (use (match_operand:SI 2 "immediate_operand" "i"))
8816 (use (match_operand:SI 3 "immediate_operand" "i"))
8817 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8818 (clobber (reg:SI 6))
8819 (clobber (reg:SI 7))
8820 (clobber (reg:SI 8))
8821 (clobber (reg:SI 9))
8822 (clobber (reg:SI 10))
8823 (clobber (match_scratch:SI 5 "=q"))]
8824 "TARGET_STRING && TARGET_POWER
8825 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
8826 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
8827 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
8828 && REGNO (operands[4]) == 5"
8829 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8830 [(set_attr "type" "store_ux")
8831 (set_attr "length" "8")])
8833 (define_insn ""
8834 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
8835 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
8836 (use (match_operand:SI 2 "immediate_operand" "i"))
8837 (use (match_operand:SI 3 "immediate_operand" "i"))
8838 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8839 (clobber (reg:SI 6))
8840 (clobber (reg:SI 7))
8841 (clobber (reg:SI 8))
8842 (clobber (reg:SI 9))
8843 (clobber (reg:SI 10))
8844 (clobber (match_scratch:SI 5 "X"))]
8845 "TARGET_STRING && ! TARGET_POWER
8846 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
8847 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
8848 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
8849 && REGNO (operands[4]) == 5"
8850 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8851 [(set_attr "type" "store_ux")
8852 (set_attr "length" "8")])
8854 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
8855 ;; problems with TImode.
8856 ;; rD/rS = r5 is preferred, efficient form.
8857 (define_expand "movmemsi_4reg"
8858 [(parallel [(set (match_operand 0 "" "")
8859 (match_operand 1 "" ""))
8860 (use (match_operand 2 "" ""))
8861 (use (match_operand 3 "" ""))
8862 (clobber (reg:SI 5))
8863 (clobber (reg:SI 6))
8864 (clobber (reg:SI 7))
8865 (clobber (reg:SI 8))
8866 (clobber (match_scratch:SI 4 ""))])]
8867 "TARGET_STRING"
8868 "")
8870 (define_insn ""
8871 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8872 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8873 (use (match_operand:SI 2 "immediate_operand" "i"))
8874 (use (match_operand:SI 3 "immediate_operand" "i"))
8875 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8876 (clobber (reg:SI 6))
8877 (clobber (reg:SI 7))
8878 (clobber (reg:SI 8))
8879 (clobber (match_scratch:SI 5 "=q"))]
8880 "TARGET_STRING && TARGET_POWER
8881 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
8882 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
8883 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
8884 && REGNO (operands[4]) == 5"
8885 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8886 [(set_attr "type" "store_ux")
8887 (set_attr "length" "8")])
8889 (define_insn ""
8890 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
8891 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
8892 (use (match_operand:SI 2 "immediate_operand" "i"))
8893 (use (match_operand:SI 3 "immediate_operand" "i"))
8894 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8895 (clobber (reg:SI 6))
8896 (clobber (reg:SI 7))
8897 (clobber (reg:SI 8))
8898 (clobber (match_scratch:SI 5 "X"))]
8899 "TARGET_STRING && ! TARGET_POWER
8900 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
8901 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
8902 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
8903 && REGNO (operands[4]) == 5"
8904 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8905 [(set_attr "type" "store_ux")
8906 (set_attr "length" "8")])
8908 ;; Move up to 8 bytes at a time.
8909 (define_expand "movmemsi_2reg"
8910 [(parallel [(set (match_operand 0 "" "")
8911 (match_operand 1 "" ""))
8912 (use (match_operand 2 "" ""))
8913 (use (match_operand 3 "" ""))
8914 (clobber (match_scratch:DI 4 ""))
8915 (clobber (match_scratch:SI 5 ""))])]
8916 "TARGET_STRING && ! TARGET_POWERPC64"
8917 "")
8919 (define_insn ""
8920 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8921 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8922 (use (match_operand:SI 2 "immediate_operand" "i"))
8923 (use (match_operand:SI 3 "immediate_operand" "i"))
8924 (clobber (match_scratch:DI 4 "=&r"))
8925 (clobber (match_scratch:SI 5 "=q"))]
8926 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
8927 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
8928 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8929 [(set_attr "type" "store_ux")
8930 (set_attr "length" "8")])
8932 (define_insn ""
8933 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8934 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8935 (use (match_operand:SI 2 "immediate_operand" "i"))
8936 (use (match_operand:SI 3 "immediate_operand" "i"))
8937 (clobber (match_scratch:DI 4 "=&r"))
8938 (clobber (match_scratch:SI 5 "X"))]
8939 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
8940 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
8941 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8942 [(set_attr "type" "store_ux")
8943 (set_attr "length" "8")])
8945 ;; Move up to 4 bytes at a time.
8946 (define_expand "movmemsi_1reg"
8947 [(parallel [(set (match_operand 0 "" "")
8948 (match_operand 1 "" ""))
8949 (use (match_operand 2 "" ""))
8950 (use (match_operand 3 "" ""))
8951 (clobber (match_scratch:SI 4 ""))
8952 (clobber (match_scratch:SI 5 ""))])]
8953 "TARGET_STRING"
8954 "")
8956 (define_insn ""
8957 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8958 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8959 (use (match_operand:SI 2 "immediate_operand" "i"))
8960 (use (match_operand:SI 3 "immediate_operand" "i"))
8961 (clobber (match_scratch:SI 4 "=&r"))
8962 (clobber (match_scratch:SI 5 "=q"))]
8963 "TARGET_STRING && TARGET_POWER
8964 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
8965 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8966 [(set_attr "type" "store_ux")
8967 (set_attr "length" "8")])
8969 (define_insn ""
8970 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
8971 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
8972 (use (match_operand:SI 2 "immediate_operand" "i"))
8973 (use (match_operand:SI 3 "immediate_operand" "i"))
8974 (clobber (match_scratch:SI 4 "=&r"))
8975 (clobber (match_scratch:SI 5 "X"))]
8976 "TARGET_STRING && ! TARGET_POWER
8977 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
8978 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8979 [(set_attr "type" "store_ux")
8980 (set_attr "length" "8")])
8981 \f
8982 ;; Define insns that do load or store with update. Some of these we can
8983 ;; get by using pre-decrement or pre-increment, but the hardware can also
8984 ;; do cases where the increment is not the size of the object.
8985 ;;
8986 ;; In all these cases, we use operands 0 and 1 for the register being
8987 ;; incremented because those are the operands that local-alloc will
8988 ;; tie and these are the pair most likely to be tieable (and the ones
8989 ;; that will benefit the most).
8991 (define_insn "*movdi_update1"
8992 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
8993 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
8994 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
8995 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
8996 (plus:DI (match_dup 1) (match_dup 2)))]
8997 "TARGET_POWERPC64 && TARGET_UPDATE"
8998 "@
8999 ldux %3,%0,%2
9000 ldu %3,%2(%0)"
9001 [(set_attr "type" "load_ux,load_u")])
9003 (define_insn "movdi_<mode>_update"
9004 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9005 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9006 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9007 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9008 (plus:P (match_dup 1) (match_dup 2)))]
9009 "TARGET_POWERPC64 && TARGET_UPDATE"
9010 "@
9011 stdux %3,%0,%2
9012 stdu %3,%2(%0)"
9013 [(set_attr "type" "store_ux,store_u")])
9015 (define_insn "*movsi_update1"
9016 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9017 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9018 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9019 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9020 (plus:SI (match_dup 1) (match_dup 2)))]
9021 "TARGET_UPDATE"
9022 "@
9023 {lux|lwzux} %3,%0,%2
9024 {lu|lwzu} %3,%2(%0)"
9025 [(set_attr "type" "load_ux,load_u")])
9027 (define_insn "*movsi_update2"
9028 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9029 (sign_extend:DI
9030 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9031 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9032 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9033 (plus:DI (match_dup 1) (match_dup 2)))]
9034 "TARGET_POWERPC64"
9035 "lwaux %3,%0,%2"
9036 [(set_attr "type" "load_ext_ux")])
9038 (define_insn "movsi_update"
9039 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9040 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9041 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9042 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9043 (plus:SI (match_dup 1) (match_dup 2)))]
9044 "TARGET_UPDATE"
9045 "@
9046 {stux|stwux} %3,%0,%2
9047 {stu|stwu} %3,%2(%0)"
9048 [(set_attr "type" "store_ux,store_u")])
9050 (define_insn "*movhi_update1"
9051 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9052 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9053 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9054 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9055 (plus:SI (match_dup 1) (match_dup 2)))]
9056 "TARGET_UPDATE"
9057 "@
9058 lhzux %3,%0,%2
9059 lhzu %3,%2(%0)"
9060 [(set_attr "type" "load_ux,load_u")])
9062 (define_insn "*movhi_update2"
9063 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9064 (zero_extend:SI
9065 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9066 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9067 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9068 (plus:SI (match_dup 1) (match_dup 2)))]
9069 "TARGET_UPDATE"
9070 "@
9071 lhzux %3,%0,%2
9072 lhzu %3,%2(%0)"
9073 [(set_attr "type" "load_ux,load_u")])
9075 (define_insn "*movhi_update3"
9076 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9077 (sign_extend:SI
9078 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9079 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9080 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9081 (plus:SI (match_dup 1) (match_dup 2)))]
9082 "TARGET_UPDATE"
9083 "@
9084 lhaux %3,%0,%2
9085 lhau %3,%2(%0)"
9086 [(set_attr "type" "load_ext_ux,load_ext_u")])
9088 (define_insn "*movhi_update4"
9089 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9090 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9091 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9092 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9093 (plus:SI (match_dup 1) (match_dup 2)))]
9094 "TARGET_UPDATE"
9095 "@
9096 sthux %3,%0,%2
9097 sthu %3,%2(%0)"
9098 [(set_attr "type" "store_ux,store_u")])
9100 (define_insn "*movqi_update1"
9101 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9102 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9103 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9104 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9105 (plus:SI (match_dup 1) (match_dup 2)))]
9106 "TARGET_UPDATE"
9107 "@
9108 lbzux %3,%0,%2
9109 lbzu %3,%2(%0)"
9110 [(set_attr "type" "load_ux,load_u")])
9112 (define_insn "*movqi_update2"
9113 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9114 (zero_extend:SI
9115 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9116 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9117 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9118 (plus:SI (match_dup 1) (match_dup 2)))]
9119 "TARGET_UPDATE"
9120 "@
9121 lbzux %3,%0,%2
9122 lbzu %3,%2(%0)"
9123 [(set_attr "type" "load_ux,load_u")])
9125 (define_insn "*movqi_update3"
9126 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9127 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9128 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9129 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9130 (plus:SI (match_dup 1) (match_dup 2)))]
9131 "TARGET_UPDATE"
9132 "@
9133 stbux %3,%0,%2
9134 stbu %3,%2(%0)"
9135 [(set_attr "type" "store_ux,store_u")])
9137 (define_insn "*movsf_update1"
9138 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9139 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9140 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9141 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9142 (plus:SI (match_dup 1) (match_dup 2)))]
9143 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9144 "@
9145 lfsux %3,%0,%2
9146 lfsu %3,%2(%0)"
9147 [(set_attr "type" "fpload_ux,fpload_u")])
9149 (define_insn "*movsf_update2"
9150 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9151 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9152 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9153 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9154 (plus:SI (match_dup 1) (match_dup 2)))]
9155 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9156 "@
9157 stfsux %3,%0,%2
9158 stfsu %3,%2(%0)"
9159 [(set_attr "type" "fpstore_ux,fpstore_u")])
9161 (define_insn "*movsf_update3"
9162 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9163 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9164 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9165 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9166 (plus:SI (match_dup 1) (match_dup 2)))]
9167 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9168 "@
9169 {lux|lwzux} %3,%0,%2
9170 {lu|lwzu} %3,%2(%0)"
9171 [(set_attr "type" "load_ux,load_u")])
9173 (define_insn "*movsf_update4"
9174 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9175 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9176 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9177 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9178 (plus:SI (match_dup 1) (match_dup 2)))]
9179 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9180 "@
9181 {stux|stwux} %3,%0,%2
9182 {stu|stwu} %3,%2(%0)"
9183 [(set_attr "type" "store_ux,store_u")])
9185 (define_insn "*movdf_update1"
9186 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
9187 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9188 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9189 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9190 (plus:SI (match_dup 1) (match_dup 2)))]
9191 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9192 "@
9193 lfdux %3,%0,%2
9194 lfdu %3,%2(%0)"
9195 [(set_attr "type" "fpload_ux,fpload_u")])
9197 (define_insn "*movdf_update2"
9198 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9199 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9200 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
9201 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9202 (plus:SI (match_dup 1) (match_dup 2)))]
9203 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9204 "@
9205 stfdux %3,%0,%2
9206 stfdu %3,%2(%0)"
9207 [(set_attr "type" "fpstore_ux,fpstore_u")])
9209 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
9211 (define_insn "*lfq_power2"
9212 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
9213 (match_operand:V2DF 1 "memory_operand" ""))]
9214 "TARGET_POWER2
9215 && TARGET_HARD_FLOAT && TARGET_FPRS"
9216 "lfq%U1%X1 %0,%1")
9218 (define_peephole2
9219 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9220 (match_operand:DF 1 "memory_operand" ""))
9221 (set (match_operand:DF 2 "gpc_reg_operand" "")
9222 (match_operand:DF 3 "memory_operand" ""))]
9223 "TARGET_POWER2
9224 && TARGET_HARD_FLOAT && TARGET_FPRS
9225 && registers_ok_for_quad_peep (operands[0], operands[2])
9226 && mems_ok_for_quad_peep (operands[1], operands[3])"
9227 [(set (match_dup 0)
9228 (match_dup 1))]
9229 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
9230 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
9232 (define_insn "*stfq_power2"
9233 [(set (match_operand:V2DF 0 "memory_operand" "")
9234 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
9235 "TARGET_POWER2
9236 && TARGET_HARD_FLOAT && TARGET_FPRS"
9237 "stfq%U0%X0 %1,%0")
9240 (define_peephole2
9241 [(set (match_operand:DF 0 "memory_operand" "")
9242 (match_operand:DF 1 "gpc_reg_operand" ""))
9243 (set (match_operand:DF 2 "memory_operand" "")
9244 (match_operand:DF 3 "gpc_reg_operand" ""))]
9245 "TARGET_POWER2
9246 && TARGET_HARD_FLOAT && TARGET_FPRS
9247 && registers_ok_for_quad_peep (operands[1], operands[3])
9248 && mems_ok_for_quad_peep (operands[0], operands[2])"
9249 [(set (match_dup 0)
9250 (match_dup 1))]
9251 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
9252 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
9254 ;; After inserting conditional returns we can sometimes have
9255 ;; unnecessary register moves. Unfortunately we cannot have a
9256 ;; modeless peephole here, because some single SImode sets have early
9257 ;; clobber outputs. Although those sets expand to multi-ppc-insn
9258 ;; sequences, using get_attr_length here will smash the operands
9259 ;; array. Neither is there an early_cobbler_p predicate.
9260 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
9261 (define_peephole2
9262 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9263 (match_operand:DF 1 "any_operand" ""))
9264 (set (match_operand:DF 2 "gpc_reg_operand" "")
9265 (match_dup 0))]
9266 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
9267 && peep2_reg_dead_p (2, operands[0])"
9268 [(set (match_dup 2) (match_dup 1))])
9270 (define_peephole2
9271 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9272 (match_operand:SF 1 "any_operand" ""))
9273 (set (match_operand:SF 2 "gpc_reg_operand" "")
9274 (match_dup 0))]
9275 "peep2_reg_dead_p (2, operands[0])"
9276 [(set (match_dup 2) (match_dup 1))])
9278 \f
9279 ;; TLS support.
9281 ;; "b" output constraint here and on tls_ld to support tls linker optimization.
9282 (define_insn "tls_gd_32"
9283 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9284 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9285 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9286 UNSPEC_TLSGD))]
9287 "HAVE_AS_TLS && !TARGET_64BIT"
9288 "addi %0,%1,%2@got@tlsgd")
9290 (define_insn "tls_gd_64"
9291 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9292 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9293 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9294 UNSPEC_TLSGD))]
9295 "HAVE_AS_TLS && TARGET_64BIT"
9296 "addi %0,%1,%2@got@tlsgd")
9298 (define_insn "tls_ld_32"
9299 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9300 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")]
9301 UNSPEC_TLSLD))]
9302 "HAVE_AS_TLS && !TARGET_64BIT"
9303 "addi %0,%1,%&@got@tlsld")
9305 (define_insn "tls_ld_64"
9306 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9307 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")]
9308 UNSPEC_TLSLD))]
9309 "HAVE_AS_TLS && TARGET_64BIT"
9310 "addi %0,%1,%&@got@tlsld")
9312 (define_insn "tls_dtprel_32"
9313 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9314 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9315 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9316 UNSPEC_TLSDTPREL))]
9317 "HAVE_AS_TLS && !TARGET_64BIT"
9318 "addi %0,%1,%2@dtprel")
9320 (define_insn "tls_dtprel_64"
9321 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9322 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9323 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9324 UNSPEC_TLSDTPREL))]
9325 "HAVE_AS_TLS && TARGET_64BIT"
9326 "addi %0,%1,%2@dtprel")
9328 (define_insn "tls_dtprel_ha_32"
9329 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9330 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9331 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9332 UNSPEC_TLSDTPRELHA))]
9333 "HAVE_AS_TLS && !TARGET_64BIT"
9334 "addis %0,%1,%2@dtprel@ha")
9336 (define_insn "tls_dtprel_ha_64"
9337 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9338 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9339 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9340 UNSPEC_TLSDTPRELHA))]
9341 "HAVE_AS_TLS && TARGET_64BIT"
9342 "addis %0,%1,%2@dtprel@ha")
9344 (define_insn "tls_dtprel_lo_32"
9345 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9346 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9347 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9348 UNSPEC_TLSDTPRELLO))]
9349 "HAVE_AS_TLS && !TARGET_64BIT"
9350 "addi %0,%1,%2@dtprel@l")
9352 (define_insn "tls_dtprel_lo_64"
9353 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9354 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9355 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9356 UNSPEC_TLSDTPRELLO))]
9357 "HAVE_AS_TLS && TARGET_64BIT"
9358 "addi %0,%1,%2@dtprel@l")
9360 (define_insn "tls_got_dtprel_32"
9361 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9362 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9363 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9364 UNSPEC_TLSGOTDTPREL))]
9365 "HAVE_AS_TLS && !TARGET_64BIT"
9366 "lwz %0,%2@got@dtprel(%1)")
9368 (define_insn "tls_got_dtprel_64"
9369 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9370 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9371 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9372 UNSPEC_TLSGOTDTPREL))]
9373 "HAVE_AS_TLS && TARGET_64BIT"
9374 "ld %0,%2@got@dtprel(%1)")
9376 (define_insn "tls_tprel_32"
9377 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9378 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9379 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9380 UNSPEC_TLSTPREL))]
9381 "HAVE_AS_TLS && !TARGET_64BIT"
9382 "addi %0,%1,%2@tprel")
9384 (define_insn "tls_tprel_64"
9385 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9386 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9387 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9388 UNSPEC_TLSTPREL))]
9389 "HAVE_AS_TLS && TARGET_64BIT"
9390 "addi %0,%1,%2@tprel")
9392 (define_insn "tls_tprel_ha_32"
9393 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9394 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9395 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9396 UNSPEC_TLSTPRELHA))]
9397 "HAVE_AS_TLS && !TARGET_64BIT"
9398 "addis %0,%1,%2@tprel@ha")
9400 (define_insn "tls_tprel_ha_64"
9401 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9402 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9403 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9404 UNSPEC_TLSTPRELHA))]
9405 "HAVE_AS_TLS && TARGET_64BIT"
9406 "addis %0,%1,%2@tprel@ha")
9408 (define_insn "tls_tprel_lo_32"
9409 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9410 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9411 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9412 UNSPEC_TLSTPRELLO))]
9413 "HAVE_AS_TLS && !TARGET_64BIT"
9414 "addi %0,%1,%2@tprel@l")
9416 (define_insn "tls_tprel_lo_64"
9417 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9418 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9419 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9420 UNSPEC_TLSTPRELLO))]
9421 "HAVE_AS_TLS && TARGET_64BIT"
9422 "addi %0,%1,%2@tprel@l")
9424 ;; "b" output constraint here and on tls_tls input to support linker tls
9425 ;; optimization. The linker may edit the instructions emitted by a
9426 ;; tls_got_tprel/tls_tls pair to addis,addi.
9427 (define_insn "tls_got_tprel_32"
9428 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9429 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9430 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9431 UNSPEC_TLSGOTTPREL))]
9432 "HAVE_AS_TLS && !TARGET_64BIT"
9433 "lwz %0,%2@got@tprel(%1)")
9435 (define_insn "tls_got_tprel_64"
9436 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9437 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9438 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9439 UNSPEC_TLSGOTTPREL))]
9440 "HAVE_AS_TLS && TARGET_64BIT"
9441 "ld %0,%2@got@tprel(%1)")
9443 (define_insn "tls_tls_32"
9444 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9445 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9446 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9447 UNSPEC_TLSTLS))]
9448 "HAVE_AS_TLS && !TARGET_64BIT"
9449 "add %0,%1,%2@tls")
9451 (define_insn "tls_tls_64"
9452 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9453 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9454 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9455 UNSPEC_TLSTLS))]
9456 "HAVE_AS_TLS && TARGET_64BIT"
9457 "add %0,%1,%2@tls")
9458 \f
9459 ;; Next come insns related to the calling sequence.
9460 ;;
9461 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
9462 ;; We move the back-chain and decrement the stack pointer.
9464 (define_expand "allocate_stack"
9465 [(set (match_operand 0 "gpc_reg_operand" "=r")
9466 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
9467 (set (reg 1)
9468 (minus (reg 1) (match_dup 1)))]
9469 ""
9470 "
9471 { rtx chain = gen_reg_rtx (Pmode);
9472 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
9473 rtx neg_op0;
9475 emit_move_insn (chain, stack_bot);
9477 /* Check stack bounds if necessary. */
9478 if (current_function_limit_stack)
9479 {
9480 rtx available;
9481 available = expand_binop (Pmode, sub_optab,
9482 stack_pointer_rtx, stack_limit_rtx,
9483 NULL_RTX, 1, OPTAB_WIDEN);
9484 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
9485 }
9487 if (GET_CODE (operands[1]) != CONST_INT
9488 || INTVAL (operands[1]) < -32767
9489 || INTVAL (operands[1]) > 32768)
9490 {
9491 neg_op0 = gen_reg_rtx (Pmode);
9492 if (TARGET_32BIT)
9493 emit_insn (gen_negsi2 (neg_op0, operands[1]));
9494 else
9495 emit_insn (gen_negdi2 (neg_op0, operands[1]));
9496 }
9497 else
9498 neg_op0 = GEN_INT (- INTVAL (operands[1]));
9500 if (TARGET_UPDATE)
9501 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update))
9502 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
9504 else
9505 {
9506 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
9507 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
9508 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
9509 }
9511 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9512 DONE;
9513 }")
9515 ;; These patterns say how to save and restore the stack pointer. We need not
9516 ;; save the stack pointer at function level since we are careful to
9517 ;; preserve the backchain. At block level, we have to restore the backchain
9518 ;; when we restore the stack pointer.
9519 ;;
9520 ;; For nonlocal gotos, we must save both the stack pointer and its
9521 ;; backchain and restore both. Note that in the nonlocal case, the
9522 ;; save area is a memory location.
9524 (define_expand "save_stack_function"
9525 [(match_operand 0 "any_operand" "")
9526 (match_operand 1 "any_operand" "")]
9527 ""
9528 "DONE;")
9530 (define_expand "restore_stack_function"
9531 [(match_operand 0 "any_operand" "")
9532 (match_operand 1 "any_operand" "")]
9533 ""
9534 "DONE;")
9536 ;; Adjust stack pointer (op0) to a new value (op1).
9537 ;; First copy old stack backchain to new location, and ensure that the
9538 ;; scheduler won't reorder the sp assignment before the backchain write.
9539 (define_expand "restore_stack_block"
9540 [(set (match_dup 2) (match_dup 3))
9541 (set (match_dup 4) (match_dup 2))
9542 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
9543 (set (match_operand 0 "register_operand" "")
9544 (match_operand 1 "register_operand" ""))]
9545 ""
9546 "
9547 {
9548 operands[1] = force_reg (Pmode, operands[1]);
9549 operands[2] = gen_reg_rtx (Pmode);
9550 operands[3] = gen_frame_mem (Pmode, operands[0]);
9551 operands[4] = gen_frame_mem (Pmode, operands[1]);
9552 operands[5] = gen_frame_mem (BLKmode, operands[0]);
9553 }")
9555 (define_expand "save_stack_nonlocal"
9556 [(set (match_dup 3) (match_dup 4))
9557 (set (match_operand 0 "memory_operand" "") (match_dup 3))
9558 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
9559 ""
9560 "
9561 {
9562 int units_per_word = (TARGET_32BIT) ? 4 : 8;
9564 /* Copy the backchain to the first word, sp to the second. */
9565 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
9566 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
9567 operands[3] = gen_reg_rtx (Pmode);
9568 operands[4] = gen_frame_mem (Pmode, operands[1]);
9569 }")
9571 (define_expand "restore_stack_nonlocal"
9572 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
9573 (set (match_dup 3) (match_dup 4))
9574 (set (match_dup 5) (match_dup 2))
9575 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
9576 (set (match_operand 0 "register_operand" "") (match_dup 3))]
9577 ""
9578 "
9579 {
9580 int units_per_word = (TARGET_32BIT) ? 4 : 8;
9582 /* Restore the backchain from the first word, sp from the second. */
9583 operands[2] = gen_reg_rtx (Pmode);
9584 operands[3] = gen_reg_rtx (Pmode);
9585 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
9586 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
9587 operands[5] = gen_frame_mem (Pmode, operands[3]);
9588 operands[6] = gen_frame_mem (BLKmode, operands[0]);
9589 }")
9590 \f
9591 ;; TOC register handling.
9593 ;; Code to initialize the TOC register...
9595 (define_insn "load_toc_aix_si"
9596 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9597 (unspec:SI [(const_int 0)] UNSPEC_TOC))
9598 (use (reg:SI 2))])]
9599 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
9600 "*
9601 {
9602 char buf[30];
9603 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
9604 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9605 operands[2] = gen_rtx_REG (Pmode, 2);
9606 return \"{l|lwz} %0,%1(%2)\";
9607 }"
9608 [(set_attr "type" "load")])
9610 (define_insn "load_toc_aix_di"
9611 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9612 (unspec:DI [(const_int 0)] UNSPEC_TOC))
9613 (use (reg:DI 2))])]
9614 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
9615 "*
9616 {
9617 char buf[30];
9618 #ifdef TARGET_RELOCATABLE
9619 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
9620 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
9621 #else
9622 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
9623 #endif
9624 if (TARGET_ELF)
9625 strcat (buf, \"@toc\");
9626 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9627 operands[2] = gen_rtx_REG (Pmode, 2);
9628 return \"ld %0,%1(%2)\";
9629 }"
9630 [(set_attr "type" "load")])
9632 (define_insn "load_toc_v4_pic_si"
9633 [(set (match_operand:SI 0 "register_operand" "=l")
9634 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
9635 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
9636 "bl _GLOBAL_OFFSET_TABLE_@local-4"
9637 [(set_attr "type" "branch")
9638 (set_attr "length" "4")])
9640 (define_insn "load_toc_v4_PIC_1"
9641 [(set (match_operand:SI 0 "register_operand" "=l")
9642 (match_operand:SI 1 "immediate_operand" "s"))
9643 (use (unspec [(match_dup 1)] UNSPEC_TOC))]
9644 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
9645 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
9646 "bcl 20,31,%1\\n%1:"
9647 [(set_attr "type" "branch")
9648 (set_attr "length" "4")])
9650 (define_insn "load_toc_v4_PIC_1b"
9651 [(set (match_operand:SI 0 "register_operand" "=l")
9652 (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")]
9653 UNSPEC_TOCPTR))]
9654 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9655 "bcl 20,31,$+8\\n\\t.long %1-$"
9656 [(set_attr "type" "branch")
9657 (set_attr "length" "8")])
9659 (define_insn "load_toc_v4_PIC_2"
9660 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9661 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9662 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
9663 (match_operand:SI 3 "immediate_operand" "s")))))]
9664 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9665 "{l|lwz} %0,%2-%3(%1)"
9666 [(set_attr "type" "load")])
9668 (define_insn "load_toc_v4_PIC_3b"
9669 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9670 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9671 (high:SI
9672 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
9673 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
9674 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
9675 "{cau|addis} %0,%1,%2-%3@ha")
9677 (define_insn "load_toc_v4_PIC_3c"
9678 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9679 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9680 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
9681 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
9682 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
9683 "{cal|addi} %0,%1,%2-%3@l")
9685 ;; If the TOC is shared over a translation unit, as happens with all
9686 ;; the kinds of PIC that we support, we need to restore the TOC
9687 ;; pointer only when jumping over units of translation.
9688 ;; On Darwin, we need to reload the picbase.
9690 (define_expand "builtin_setjmp_receiver"
9691 [(use (label_ref (match_operand 0 "" "")))]
9692 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
9693 || (TARGET_TOC && TARGET_MINIMAL_TOC)
9694 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
9695 "
9696 {
9697 #if TARGET_MACHO
9698 if (DEFAULT_ABI == ABI_DARWIN)
9699 {
9700 const char *picbase = machopic_function_base_name ();
9701 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
9702 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
9703 rtx tmplabrtx;
9704 char tmplab[20];
9706 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
9707 CODE_LABEL_NUMBER (operands[0]));
9708 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
9710 emit_insn (gen_load_macho_picbase (picreg, tmplabrtx));
9711 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
9712 }
9713 else
9714 #endif
9715 rs6000_emit_load_toc_table (FALSE);
9716 DONE;
9717 }")
9719 ;; Elf specific ways of loading addresses for non-PIC code.
9720 ;; The output of this could be r0, but we make a very strong
9721 ;; preference for a base register because it will usually
9722 ;; be needed there.
9723 (define_insn "elf_high"
9724 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
9725 (high:SI (match_operand 1 "" "")))]
9726 "TARGET_ELF && ! TARGET_64BIT"
9727 "{liu|lis} %0,%1@ha")
9729 (define_insn "elf_low"
9730 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
9731 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
9732 (match_operand 2 "" "")))]
9733 "TARGET_ELF && ! TARGET_64BIT"
9734 "@
9735 {cal|la} %0,%2@l(%1)
9736 {ai|addic} %0,%1,%K2")
9737 \f
9738 ;; A function pointer under AIX is a pointer to a data area whose first word
9739 ;; contains the actual address of the function, whose second word contains a
9740 ;; pointer to its TOC, and whose third word contains a value to place in the
9741 ;; static chain register (r11). Note that if we load the static chain, our
9742 ;; "trampoline" need not have any executable code.
9744 (define_expand "call_indirect_aix32"
9745 [(set (match_dup 2)
9746 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
9747 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
9748 (reg:SI 2))
9749 (set (reg:SI 2)
9750 (mem:SI (plus:SI (match_dup 0)
9751 (const_int 4))))
9752 (set (reg:SI 11)
9753 (mem:SI (plus:SI (match_dup 0)
9754 (const_int 8))))
9755 (parallel [(call (mem:SI (match_dup 2))
9756 (match_operand 1 "" ""))
9757 (use (reg:SI 2))
9758 (use (reg:SI 11))
9759 (set (reg:SI 2)
9760 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9761 (clobber (scratch:SI))])]
9762 "TARGET_32BIT"
9763 "
9764 { operands[2] = gen_reg_rtx (SImode); }")
9766 (define_expand "call_indirect_aix64"
9767 [(set (match_dup 2)
9768 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
9769 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
9770 (reg:DI 2))
9771 (set (reg:DI 2)
9772 (mem:DI (plus:DI (match_dup 0)
9773 (const_int 8))))
9774 (set (reg:DI 11)
9775 (mem:DI (plus:DI (match_dup 0)
9776 (const_int 16))))
9777 (parallel [(call (mem:SI (match_dup 2))
9778 (match_operand 1 "" ""))
9779 (use (reg:DI 2))
9780 (use (reg:DI 11))
9781 (set (reg:DI 2)
9782 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9783 (clobber (scratch:SI))])]
9784 "TARGET_64BIT"
9785 "
9786 { operands[2] = gen_reg_rtx (DImode); }")
9788 (define_expand "call_value_indirect_aix32"
9789 [(set (match_dup 3)
9790 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
9791 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
9792 (reg:SI 2))
9793 (set (reg:SI 2)
9794 (mem:SI (plus:SI (match_dup 1)
9795 (const_int 4))))
9796 (set (reg:SI 11)
9797 (mem:SI (plus:SI (match_dup 1)
9798 (const_int 8))))
9799 (parallel [(set (match_operand 0 "" "")
9800 (call (mem:SI (match_dup 3))
9801 (match_operand 2 "" "")))
9802 (use (reg:SI 2))
9803 (use (reg:SI 11))
9804 (set (reg:SI 2)
9805 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9806 (clobber (scratch:SI))])]
9807 "TARGET_32BIT"
9808 "
9809 { operands[3] = gen_reg_rtx (SImode); }")
9811 (define_expand "call_value_indirect_aix64"
9812 [(set (match_dup 3)
9813 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
9814 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
9815 (reg:DI 2))
9816 (set (reg:DI 2)
9817 (mem:DI (plus:DI (match_dup 1)
9818 (const_int 8))))
9819 (set (reg:DI 11)
9820 (mem:DI (plus:DI (match_dup 1)
9821 (const_int 16))))
9822 (parallel [(set (match_operand 0 "" "")
9823 (call (mem:SI (match_dup 3))
9824 (match_operand 2 "" "")))
9825 (use (reg:DI 2))
9826 (use (reg:DI 11))
9827 (set (reg:DI 2)
9828 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9829 (clobber (scratch:SI))])]
9830 "TARGET_64BIT"
9831 "
9832 { operands[3] = gen_reg_rtx (DImode); }")
9834 ;; Now the definitions for the call and call_value insns
9835 (define_expand "call"
9836 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
9837 (match_operand 1 "" ""))
9838 (use (match_operand 2 "" ""))
9839 (clobber (scratch:SI))])]
9840 ""
9841 "
9842 {
9843 #if TARGET_MACHO
9844 if (MACHOPIC_INDIRECT)
9845 operands[0] = machopic_indirect_call_target (operands[0]);
9846 #endif
9848 gcc_assert (GET_CODE (operands[0]) == MEM);
9849 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
9851 operands[0] = XEXP (operands[0], 0);
9853 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
9854 && flag_pic
9855 && GET_CODE (operands[0]) == SYMBOL_REF
9856 && !SYMBOL_REF_LOCAL_P (operands[0]))
9857 {
9858 rtx call;
9859 rtvec tmp;
9861 tmp = gen_rtvec (3,
9862 gen_rtx_CALL (VOIDmode,
9863 gen_rtx_MEM (SImode, operands[0]),
9864 operands[1]),
9865 gen_rtx_USE (VOIDmode, operands[2]),
9866 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
9867 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
9868 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
9869 DONE;
9870 }
9872 if (GET_CODE (operands[0]) != SYMBOL_REF
9873 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
9874 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
9875 {
9876 if (INTVAL (operands[2]) & CALL_LONG)
9877 operands[0] = rs6000_longcall_ref (operands[0]);
9879 switch (DEFAULT_ABI)
9880 {
9881 case ABI_V4:
9882 case ABI_DARWIN:
9883 operands[0] = force_reg (Pmode, operands[0]);
9884 break;
9886 case ABI_AIX:
9887 /* AIX function pointers are really pointers to a three word
9888 area. */
9889 emit_call_insn (TARGET_32BIT
9890 ? gen_call_indirect_aix32 (force_reg (SImode,
9891 operands[0]),
9892 operands[1])
9893 : gen_call_indirect_aix64 (force_reg (DImode,
9894 operands[0]),
9895 operands[1]));
9896 DONE;
9898 default:
9899 gcc_unreachable ();
9900 }
9901 }
9902 }")
9904 (define_expand "call_value"
9905 [(parallel [(set (match_operand 0 "" "")
9906 (call (mem:SI (match_operand 1 "address_operand" ""))
9907 (match_operand 2 "" "")))
9908 (use (match_operand 3 "" ""))
9909 (clobber (scratch:SI))])]
9910 ""
9911 "
9912 {
9913 #if TARGET_MACHO
9914 if (MACHOPIC_INDIRECT)
9915 operands[1] = machopic_indirect_call_target (operands[1]);
9916 #endif
9918 gcc_assert (GET_CODE (operands[1]) == MEM);
9919 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
9921 operands[1] = XEXP (operands[1], 0);
9923 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
9924 && flag_pic
9925 && GET_CODE (operands[1]) == SYMBOL_REF
9926 && !SYMBOL_REF_LOCAL_P (operands[1]))
9927 {
9928 rtx call;
9929 rtvec tmp;
9931 tmp = gen_rtvec (3,
9932 gen_rtx_SET (VOIDmode,
9933 operands[0],
9934 gen_rtx_CALL (VOIDmode,
9935 gen_rtx_MEM (SImode,
9936 operands[1]),
9937 operands[2])),
9938 gen_rtx_USE (VOIDmode, operands[3]),
9939 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
9940 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
9941 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
9942 DONE;
9943 }
9945 if (GET_CODE (operands[1]) != SYMBOL_REF
9946 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
9947 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
9948 {
9949 if (INTVAL (operands[3]) & CALL_LONG)
9950 operands[1] = rs6000_longcall_ref (operands[1]);
9952 switch (DEFAULT_ABI)
9953 {
9954 case ABI_V4:
9955 case ABI_DARWIN:
9956 operands[1] = force_reg (Pmode, operands[1]);
9957 break;
9959 case ABI_AIX:
9960 /* AIX function pointers are really pointers to a three word
9961 area. */
9962 emit_call_insn (TARGET_32BIT
9963 ? gen_call_value_indirect_aix32 (operands[0],
9964 force_reg (SImode,
9965 operands[1]),
9966 operands[2])
9967 : gen_call_value_indirect_aix64 (operands[0],
9968 force_reg (DImode,
9969 operands[1]),
9970 operands[2]));
9971 DONE;
9973 default:
9974 gcc_unreachable ();
9975 }
9976 }
9977 }")
9979 ;; Call to function in current module. No TOC pointer reload needed.
9980 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
9981 ;; either the function was not prototyped, or it was prototyped as a
9982 ;; variable argument function. It is > 0 if FP registers were passed
9983 ;; and < 0 if they were not.
9985 (define_insn "*call_local32"
9986 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
9987 (match_operand 1 "" "g,g"))
9988 (use (match_operand:SI 2 "immediate_operand" "O,n"))
9989 (clobber (match_scratch:SI 3 "=l,l"))]
9990 "(INTVAL (operands[2]) & CALL_LONG) == 0"
9991 "*
9992 {
9993 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
9994 output_asm_insn (\"crxor 6,6,6\", operands);
9996 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
9997 output_asm_insn (\"creqv 6,6,6\", operands);
9999 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10000 }"
10001 [(set_attr "type" "branch")
10002 (set_attr "length" "4,8")])
10004 (define_insn "*call_local64"
10005 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10006 (match_operand 1 "" "g,g"))
10007 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10008 (clobber (match_scratch:SI 3 "=l,l"))]
10009 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10010 "*
10011 {
10012 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10013 output_asm_insn (\"crxor 6,6,6\", operands);
10015 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10016 output_asm_insn (\"creqv 6,6,6\", operands);
10018 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10019 }"
10020 [(set_attr "type" "branch")
10021 (set_attr "length" "4,8")])
10023 (define_insn "*call_value_local32"
10024 [(set (match_operand 0 "" "")
10025 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10026 (match_operand 2 "" "g,g")))
10027 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10028 (clobber (match_scratch:SI 4 "=l,l"))]
10029 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10030 "*
10031 {
10032 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10033 output_asm_insn (\"crxor 6,6,6\", operands);
10035 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10036 output_asm_insn (\"creqv 6,6,6\", operands);
10038 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10039 }"
10040 [(set_attr "type" "branch")
10041 (set_attr "length" "4,8")])
10044 (define_insn "*call_value_local64"
10045 [(set (match_operand 0 "" "")
10046 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10047 (match_operand 2 "" "g,g")))
10048 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10049 (clobber (match_scratch:SI 4 "=l,l"))]
10050 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10051 "*
10052 {
10053 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10054 output_asm_insn (\"crxor 6,6,6\", operands);
10056 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10057 output_asm_insn (\"creqv 6,6,6\", operands);
10059 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10060 }"
10061 [(set_attr "type" "branch")
10062 (set_attr "length" "4,8")])
10064 ;; Call to function which may be in another module. Restore the TOC
10065 ;; pointer (r2) after the call unless this is System V.
10066 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10067 ;; either the function was not prototyped, or it was prototyped as a
10068 ;; variable argument function. It is > 0 if FP registers were passed
10069 ;; and < 0 if they were not.
10071 (define_insn "*call_indirect_nonlocal_aix32"
10072 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
10073 (match_operand 1 "" "g,g"))
10074 (use (reg:SI 2))
10075 (use (reg:SI 11))
10076 (set (reg:SI 2)
10077 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10078 (clobber (match_scratch:SI 2 "=l,l"))]
10079 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10080 "b%T0l\;{l|lwz} 2,20(1)"
10081 [(set_attr "type" "jmpreg")
10082 (set_attr "length" "8")])
10084 (define_insn "*call_nonlocal_aix32"
10085 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10086 (match_operand 1 "" "g"))
10087 (use (match_operand:SI 2 "immediate_operand" "O"))
10088 (clobber (match_scratch:SI 3 "=l"))]
10089 "TARGET_32BIT
10090 && DEFAULT_ABI == ABI_AIX
10091 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10092 "bl %z0\;%."
10093 [(set_attr "type" "branch")
10094 (set_attr "length" "8")])
10096 (define_insn "*call_indirect_nonlocal_aix64"
10097 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
10098 (match_operand 1 "" "g,g"))
10099 (use (reg:DI 2))
10100 (use (reg:DI 11))
10101 (set (reg:DI 2)
10102 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10103 (clobber (match_scratch:SI 2 "=l,l"))]
10104 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10105 "b%T0l\;ld 2,40(1)"
10106 [(set_attr "type" "jmpreg")
10107 (set_attr "length" "8")])
10109 (define_insn "*call_nonlocal_aix64"
10110 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10111 (match_operand 1 "" "g"))
10112 (use (match_operand:SI 2 "immediate_operand" "O"))
10113 (clobber (match_scratch:SI 3 "=l"))]
10114 "TARGET_64BIT
10115 && DEFAULT_ABI == ABI_AIX
10116 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10117 "bl %z0\;%."
10118 [(set_attr "type" "branch")
10119 (set_attr "length" "8")])
10121 (define_insn "*call_value_indirect_nonlocal_aix32"
10122 [(set (match_operand 0 "" "")
10123 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
10124 (match_operand 2 "" "g,g")))
10125 (use (reg:SI 2))
10126 (use (reg:SI 11))
10127 (set (reg:SI 2)
10128 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10129 (clobber (match_scratch:SI 3 "=l,l"))]
10130 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10131 "b%T1l\;{l|lwz} 2,20(1)"
10132 [(set_attr "type" "jmpreg")
10133 (set_attr "length" "8")])
10135 (define_insn "*call_value_nonlocal_aix32"
10136 [(set (match_operand 0 "" "")
10137 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10138 (match_operand 2 "" "g")))
10139 (use (match_operand:SI 3 "immediate_operand" "O"))
10140 (clobber (match_scratch:SI 4 "=l"))]
10141 "TARGET_32BIT
10142 && DEFAULT_ABI == ABI_AIX
10143 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10144 "bl %z1\;%."
10145 [(set_attr "type" "branch")
10146 (set_attr "length" "8")])
10148 (define_insn "*call_value_indirect_nonlocal_aix64"
10149 [(set (match_operand 0 "" "")
10150 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
10151 (match_operand 2 "" "g,g")))
10152 (use (reg:DI 2))
10153 (use (reg:DI 11))
10154 (set (reg:DI 2)
10155 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10156 (clobber (match_scratch:SI 3 "=l,l"))]
10157 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10158 "b%T1l\;ld 2,40(1)"
10159 [(set_attr "type" "jmpreg")
10160 (set_attr "length" "8")])
10162 (define_insn "*call_value_nonlocal_aix64"
10163 [(set (match_operand 0 "" "")
10164 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10165 (match_operand 2 "" "g")))
10166 (use (match_operand:SI 3 "immediate_operand" "O"))
10167 (clobber (match_scratch:SI 4 "=l"))]
10168 "TARGET_64BIT
10169 && DEFAULT_ABI == ABI_AIX
10170 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10171 "bl %z1\;%."
10172 [(set_attr "type" "branch")
10173 (set_attr "length" "8")])
10175 ;; A function pointer under System V is just a normal pointer
10176 ;; operands[0] is the function pointer
10177 ;; operands[1] is the stack size to clean up
10178 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10179 ;; which indicates how to set cr1
10181 (define_insn "*call_indirect_nonlocal_sysv"
10182 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l,c,*l"))
10183 (match_operand 1 "" "g,g,g,g"))
10184 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
10185 (clobber (match_scratch:SI 3 "=l,l,l,l"))]
10186 "DEFAULT_ABI == ABI_V4
10187 || DEFAULT_ABI == ABI_DARWIN"
10188 {
10189 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10190 output_asm_insn ("crxor 6,6,6", operands);
10192 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10193 output_asm_insn ("creqv 6,6,6", operands);
10195 return "b%T0l";
10196 }
10197 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10198 (set_attr "length" "4,4,8,8")])
10200 (define_insn "*call_nonlocal_sysv"
10201 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10202 (match_operand 1 "" "g,g"))
10203 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10204 (clobber (match_scratch:SI 3 "=l,l"))]
10205 "(DEFAULT_ABI == ABI_DARWIN
10206 || (DEFAULT_ABI == ABI_V4
10207 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
10208 {
10209 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10210 output_asm_insn ("crxor 6,6,6", operands);
10212 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10213 output_asm_insn ("creqv 6,6,6", operands);
10215 #if TARGET_MACHO
10216 return output_call(insn, operands, 0, 2);
10217 #else
10218 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10219 {
10220 if (TARGET_SECURE_PLT && flag_pic == 2)
10221 /* The magic 32768 offset here and in the other sysv call insns
10222 corresponds to the offset of r30 in .got2, as given by LCTOC1.
10223 See sysv4.h:toc_section. */
10224 return "bl %z0+32768@plt";
10225 else
10226 return "bl %z0@plt";
10227 }
10228 else
10229 return "bl %z0";
10230 #endif
10231 }
10232 [(set_attr "type" "branch,branch")
10233 (set_attr "length" "4,8")])
10235 (define_insn "*call_value_indirect_nonlocal_sysv"
10236 [(set (match_operand 0 "" "")
10237 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l,c,*l"))
10238 (match_operand 2 "" "g,g,g,g")))
10239 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
10240 (clobber (match_scratch:SI 4 "=l,l,l,l"))]
10241 "DEFAULT_ABI == ABI_V4
10242 || DEFAULT_ABI == ABI_DARWIN"
10243 {
10244 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10245 output_asm_insn ("crxor 6,6,6", operands);
10247 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10248 output_asm_insn ("creqv 6,6,6", operands);
10250 return "b%T1l";
10251 }
10252 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10253 (set_attr "length" "4,4,8,8")])
10255 (define_insn "*call_value_nonlocal_sysv"
10256 [(set (match_operand 0 "" "")
10257 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10258 (match_operand 2 "" "g,g")))
10259 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10260 (clobber (match_scratch:SI 4 "=l,l"))]
10261 "(DEFAULT_ABI == ABI_DARWIN
10262 || (DEFAULT_ABI == ABI_V4
10263 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
10264 {
10265 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10266 output_asm_insn ("crxor 6,6,6", operands);
10268 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10269 output_asm_insn ("creqv 6,6,6", operands);
10271 #if TARGET_MACHO
10272 return output_call(insn, operands, 1, 3);
10273 #else
10274 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10275 {
10276 if (TARGET_SECURE_PLT && flag_pic == 2)
10277 return "bl %z1+32768@plt";
10278 else
10279 return "bl %z1@plt";
10280 }
10281 else
10282 return "bl %z1";
10283 #endif
10284 }
10285 [(set_attr "type" "branch,branch")
10286 (set_attr "length" "4,8")])
10288 ;; Call subroutine returning any type.
10289 (define_expand "untyped_call"
10290 [(parallel [(call (match_operand 0 "" "")
10291 (const_int 0))
10292 (match_operand 1 "" "")
10293 (match_operand 2 "" "")])]
10294 ""
10295 "
10296 {
10297 int i;
10299 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
10301 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10302 {
10303 rtx set = XVECEXP (operands[2], 0, i);
10304 emit_move_insn (SET_DEST (set), SET_SRC (set));
10305 }
10307 /* The optimizer does not know that the call sets the function value
10308 registers we stored in the result block. We avoid problems by
10309 claiming that all hard registers are used and clobbered at this
10310 point. */
10311 emit_insn (gen_blockage ());
10313 DONE;
10314 }")
10316 ;; sibling call patterns
10317 (define_expand "sibcall"
10318 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10319 (match_operand 1 "" ""))
10320 (use (match_operand 2 "" ""))
10321 (use (match_operand 3 "" ""))
10322 (return)])]
10323 ""
10324 "
10325 {
10326 #if TARGET_MACHO
10327 if (MACHOPIC_INDIRECT)
10328 operands[0] = machopic_indirect_call_target (operands[0]);
10329 #endif
10331 gcc_assert (GET_CODE (operands[0]) == MEM);
10332 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10334 operands[0] = XEXP (operands[0], 0);
10335 operands[3] = gen_reg_rtx (SImode);
10337 }")
10339 ;; this and similar patterns must be marked as using LR, otherwise
10340 ;; dataflow will try to delete the store into it. This is true
10341 ;; even when the actual reg to jump to is in CTR, when LR was
10342 ;; saved and restored around the PIC-setting BCL.
10343 (define_insn "*sibcall_local32"
10344 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10345 (match_operand 1 "" "g,g"))
10346 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10347 (use (match_operand:SI 3 "register_operand" "l,l"))
10348 (return)]
10349 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10350 "*
10351 {
10352 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10353 output_asm_insn (\"crxor 6,6,6\", operands);
10355 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10356 output_asm_insn (\"creqv 6,6,6\", operands);
10358 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10359 }"
10360 [(set_attr "type" "branch")
10361 (set_attr "length" "4,8")])
10363 (define_insn "*sibcall_local64"
10364 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10365 (match_operand 1 "" "g,g"))
10366 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10367 (use (match_operand:SI 3 "register_operand" "l,l"))
10368 (return)]
10369 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10370 "*
10371 {
10372 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10373 output_asm_insn (\"crxor 6,6,6\", operands);
10375 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10376 output_asm_insn (\"creqv 6,6,6\", operands);
10378 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10379 }"
10380 [(set_attr "type" "branch")
10381 (set_attr "length" "4,8")])
10383 (define_insn "*sibcall_value_local32"
10384 [(set (match_operand 0 "" "")
10385 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10386 (match_operand 2 "" "g,g")))
10387 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10388 (use (match_operand:SI 4 "register_operand" "l,l"))
10389 (return)]
10390 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10391 "*
10392 {
10393 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10394 output_asm_insn (\"crxor 6,6,6\", operands);
10396 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10397 output_asm_insn (\"creqv 6,6,6\", operands);
10399 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10400 }"
10401 [(set_attr "type" "branch")
10402 (set_attr "length" "4,8")])
10405 (define_insn "*sibcall_value_local64"
10406 [(set (match_operand 0 "" "")
10407 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10408 (match_operand 2 "" "g,g")))
10409 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10410 (use (match_operand:SI 4 "register_operand" "l,l"))
10411 (return)]
10412 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10413 "*
10414 {
10415 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10416 output_asm_insn (\"crxor 6,6,6\", operands);
10418 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10419 output_asm_insn (\"creqv 6,6,6\", operands);
10421 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10422 }"
10423 [(set_attr "type" "branch")
10424 (set_attr "length" "4,8")])
10426 (define_insn "*sibcall_nonlocal_aix32"
10427 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10428 (match_operand 1 "" "g"))
10429 (use (match_operand:SI 2 "immediate_operand" "O"))
10430 (use (match_operand:SI 3 "register_operand" "l"))
10431 (return)]
10432 "TARGET_32BIT
10433 && DEFAULT_ABI == ABI_AIX
10434 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10435 "b %z0"
10436 [(set_attr "type" "branch")
10437 (set_attr "length" "4")])
10439 (define_insn "*sibcall_nonlocal_aix64"
10440 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10441 (match_operand 1 "" "g"))
10442 (use (match_operand:SI 2 "immediate_operand" "O"))
10443 (use (match_operand:SI 3 "register_operand" "l"))
10444 (return)]
10445 "TARGET_64BIT
10446 && DEFAULT_ABI == ABI_AIX
10447 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10448 "b %z0"
10449 [(set_attr "type" "branch")
10450 (set_attr "length" "4")])
10452 (define_insn "*sibcall_value_nonlocal_aix32"
10453 [(set (match_operand 0 "" "")
10454 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10455 (match_operand 2 "" "g")))
10456 (use (match_operand:SI 3 "immediate_operand" "O"))
10457 (use (match_operand:SI 4 "register_operand" "l"))
10458 (return)]
10459 "TARGET_32BIT
10460 && DEFAULT_ABI == ABI_AIX
10461 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10462 "b %z1"
10463 [(set_attr "type" "branch")
10464 (set_attr "length" "4")])
10466 (define_insn "*sibcall_value_nonlocal_aix64"
10467 [(set (match_operand 0 "" "")
10468 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10469 (match_operand 2 "" "g")))
10470 (use (match_operand:SI 3 "immediate_operand" "O"))
10471 (use (match_operand:SI 4 "register_operand" "l"))
10472 (return)]
10473 "TARGET_64BIT
10474 && DEFAULT_ABI == ABI_AIX
10475 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10476 "b %z1"
10477 [(set_attr "type" "branch")
10478 (set_attr "length" "4")])
10480 (define_insn "*sibcall_nonlocal_sysv"
10481 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10482 (match_operand 1 "" ""))
10483 (use (match_operand 2 "immediate_operand" "O,n"))
10484 (use (match_operand:SI 3 "register_operand" "l,l"))
10485 (return)]
10486 "(DEFAULT_ABI == ABI_DARWIN
10487 || DEFAULT_ABI == ABI_V4)
10488 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10489 "*
10490 {
10491 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10492 output_asm_insn (\"crxor 6,6,6\", operands);
10494 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10495 output_asm_insn (\"creqv 6,6,6\", operands);
10497 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10498 {
10499 if (TARGET_SECURE_PLT && flag_pic == 2)
10500 return \"b %z0+32768@plt\";
10501 else
10502 return \"b %z0@plt\";
10503 }
10504 else
10505 return \"b %z0\";
10506 }"
10507 [(set_attr "type" "branch,branch")
10508 (set_attr "length" "4,8")])
10510 (define_expand "sibcall_value"
10511 [(parallel [(set (match_operand 0 "register_operand" "")
10512 (call (mem:SI (match_operand 1 "address_operand" ""))
10513 (match_operand 2 "" "")))
10514 (use (match_operand 3 "" ""))
10515 (use (match_operand 4 "" ""))
10516 (return)])]
10517 ""
10518 "
10519 {
10520 #if TARGET_MACHO
10521 if (MACHOPIC_INDIRECT)
10522 operands[1] = machopic_indirect_call_target (operands[1]);
10523 #endif
10525 gcc_assert (GET_CODE (operands[1]) == MEM);
10526 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10528 operands[1] = XEXP (operands[1], 0);
10529 operands[4] = gen_reg_rtx (SImode);
10531 }")
10533 (define_insn "*sibcall_value_nonlocal_sysv"
10534 [(set (match_operand 0 "" "")
10535 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10536 (match_operand 2 "" "")))
10537 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10538 (use (match_operand:SI 4 "register_operand" "l,l"))
10539 (return)]
10540 "(DEFAULT_ABI == ABI_DARWIN
10541 || DEFAULT_ABI == ABI_V4)
10542 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10543 "*
10544 {
10545 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10546 output_asm_insn (\"crxor 6,6,6\", operands);
10548 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10549 output_asm_insn (\"creqv 6,6,6\", operands);
10551 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10552 {
10553 if (TARGET_SECURE_PLT && flag_pic == 2)
10554 return \"b %z1+32768@plt\";
10555 else
10556 return \"b %z1@plt\";
10557 }
10558 else
10559 return \"b %z1\";
10560 }"
10561 [(set_attr "type" "branch,branch")
10562 (set_attr "length" "4,8")])
10564 (define_expand "sibcall_epilogue"
10565 [(use (const_int 0))]
10566 "TARGET_SCHED_PROLOG"
10567 "
10568 {
10569 rs6000_emit_epilogue (TRUE);
10570 DONE;
10571 }")
10573 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
10574 ;; all of memory. This blocks insns from being moved across this point.
10576 (define_insn "blockage"
10577 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
10578 ""
10579 "")
10580 \f
10581 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
10582 ;; signed & unsigned, and one type of branch.
10583 ;;
10584 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
10585 ;; insns, and branches. We store the operands of compares until we see
10586 ;; how it is used.
10587 (define_expand "cmp<mode>"
10588 [(set (cc0)
10589 (compare (match_operand:GPR 0 "gpc_reg_operand" "")
10590 (match_operand:GPR 1 "reg_or_short_operand" "")))]
10591 ""
10592 "
10593 {
10594 /* Take care of the possibility that operands[1] might be negative but
10595 this might be a logical operation. That insn doesn't exist. */
10596 if (GET_CODE (operands[1]) == CONST_INT
10597 && INTVAL (operands[1]) < 0)
10598 operands[1] = force_reg (<MODE>mode, operands[1]);
10600 rs6000_compare_op0 = operands[0];
10601 rs6000_compare_op1 = operands[1];
10602 rs6000_compare_fp_p = 0;
10603 DONE;
10604 }")
10606 (define_expand "cmp<mode>"
10607 [(set (cc0) (compare (match_operand:FP 0 "gpc_reg_operand" "")
10608 (match_operand:FP 1 "gpc_reg_operand" "")))]
10609 ""
10610 "
10611 {
10612 rs6000_compare_op0 = operands[0];
10613 rs6000_compare_op1 = operands[1];
10614 rs6000_compare_fp_p = 1;
10615 DONE;
10616 }")
10618 (define_expand "beq"
10619 [(use (match_operand 0 "" ""))]
10620 ""
10621 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
10623 (define_expand "bne"
10624 [(use (match_operand 0 "" ""))]
10625 ""
10626 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
10628 (define_expand "bge"
10629 [(use (match_operand 0 "" ""))]
10630 ""
10631 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
10633 (define_expand "bgt"
10634 [(use (match_operand 0 "" ""))]
10635 ""
10636 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
10638 (define_expand "ble"
10639 [(use (match_operand 0 "" ""))]
10640 ""
10641 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
10643 (define_expand "blt"
10644 [(use (match_operand 0 "" ""))]
10645 ""
10646 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
10648 (define_expand "bgeu"
10649 [(use (match_operand 0 "" ""))]
10650 ""
10651 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
10653 (define_expand "bgtu"
10654 [(use (match_operand 0 "" ""))]
10655 ""
10656 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
10658 (define_expand "bleu"
10659 [(use (match_operand 0 "" ""))]
10660 ""
10661 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
10663 (define_expand "bltu"
10664 [(use (match_operand 0 "" ""))]
10665 ""
10666 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
10668 (define_expand "bunordered"
10669 [(use (match_operand 0 "" ""))]
10670 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
10671 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
10673 (define_expand "bordered"
10674 [(use (match_operand 0 "" ""))]
10675 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
10676 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
10678 (define_expand "buneq"
10679 [(use (match_operand 0 "" ""))]
10680 ""
10681 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
10683 (define_expand "bunge"
10684 [(use (match_operand 0 "" ""))]
10685 ""
10686 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
10688 (define_expand "bungt"
10689 [(use (match_operand 0 "" ""))]
10690 ""
10691 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
10693 (define_expand "bunle"
10694 [(use (match_operand 0 "" ""))]
10695 ""
10696 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
10698 (define_expand "bunlt"
10699 [(use (match_operand 0 "" ""))]
10700 ""
10701 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
10703 (define_expand "bltgt"
10704 [(use (match_operand 0 "" ""))]
10705 ""
10706 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
10708 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
10709 ;; For SEQ, likewise, except that comparisons with zero should be done
10710 ;; with an scc insns. However, due to the order that combine see the
10711 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
10712 ;; the cases we don't want to handle.
10713 (define_expand "seq"
10714 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10715 ""
10716 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
10718 (define_expand "sne"
10719 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10720 ""
10721 "
10722 {
10723 if (! rs6000_compare_fp_p)
10724 FAIL;
10726 rs6000_emit_sCOND (NE, operands[0]);
10727 DONE;
10728 }")
10730 ;; A >= 0 is best done the portable way for A an integer.
10731 (define_expand "sge"
10732 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10733 ""
10734 "
10735 {
10736 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
10737 FAIL;
10739 rs6000_emit_sCOND (GE, operands[0]);
10740 DONE;
10741 }")
10743 ;; A > 0 is best done using the portable sequence, so fail in that case.
10744 (define_expand "sgt"
10745 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10746 ""
10747 "
10748 {
10749 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
10750 FAIL;
10752 rs6000_emit_sCOND (GT, operands[0]);
10753 DONE;
10754 }")
10756 ;; A <= 0 is best done the portable way for A an integer.
10757 (define_expand "sle"
10758 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10759 ""
10760 "
10761 {
10762 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
10763 FAIL;
10765 rs6000_emit_sCOND (LE, operands[0]);
10766 DONE;
10767 }")
10769 ;; A < 0 is best done in the portable way for A an integer.
10770 (define_expand "slt"
10771 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10772 ""
10773 "
10774 {
10775 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
10776 FAIL;
10778 rs6000_emit_sCOND (LT, operands[0]);
10779 DONE;
10780 }")
10782 (define_expand "sgeu"
10783 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10784 ""
10785 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
10787 (define_expand "sgtu"
10788 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10789 ""
10790 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
10792 (define_expand "sleu"
10793 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10794 ""
10795 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
10797 (define_expand "sltu"
10798 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10799 ""
10800 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
10802 (define_expand "sunordered"
10803 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10804 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
10805 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
10807 (define_expand "sordered"
10808 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10809 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
10810 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
10812 (define_expand "suneq"
10813 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10814 ""
10815 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
10817 (define_expand "sunge"
10818 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10819 ""
10820 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
10822 (define_expand "sungt"
10823 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10824 ""
10825 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
10827 (define_expand "sunle"
10828 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10829 ""
10830 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
10832 (define_expand "sunlt"
10833 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10834 ""
10835 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
10837 (define_expand "sltgt"
10838 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10839 ""
10840 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
10842 (define_expand "stack_protect_set"
10843 [(match_operand 0 "memory_operand" "")
10844 (match_operand 1 "memory_operand" "")]
10845 ""
10846 {
10847 #ifdef TARGET_THREAD_SSP_OFFSET
10848 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
10849 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
10850 operands[1] = gen_rtx_MEM (Pmode, addr);
10851 #endif
10852 if (TARGET_64BIT)
10853 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
10854 else
10855 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
10856 DONE;
10857 })
10859 (define_insn "stack_protect_setsi"
10860 [(set (match_operand:SI 0 "memory_operand" "=m")
10861 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
10862 (set (match_scratch:SI 2 "=&r") (const_int 0))]
10863 "TARGET_32BIT"
10864 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
10865 [(set_attr "type" "three")
10866 (set_attr "length" "12")])
10868 (define_insn "stack_protect_setdi"
10869 [(set (match_operand:DI 0 "memory_operand" "=m")
10870 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
10871 (set (match_scratch:DI 2 "=&r") (const_int 0))]
10872 "TARGET_64BIT"
10873 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
10874 [(set_attr "type" "three")
10875 (set_attr "length" "12")])
10877 (define_expand "stack_protect_test"
10878 [(match_operand 0 "memory_operand" "")
10879 (match_operand 1 "memory_operand" "")
10880 (match_operand 2 "" "")]
10881 ""
10882 {
10883 #ifdef TARGET_THREAD_SSP_OFFSET
10884 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
10885 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
10886 operands[1] = gen_rtx_MEM (Pmode, addr);
10887 #endif
10888 rs6000_compare_op0 = operands[0];
10889 rs6000_compare_op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]),
10890 UNSPEC_SP_TEST);
10891 rs6000_compare_fp_p = 0;
10892 emit_jump_insn (gen_beq (operands[2]));
10893 DONE;
10894 })
10896 (define_insn "stack_protect_testsi"
10897 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
10898 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
10899 (match_operand:SI 2 "memory_operand" "m,m")]
10900 UNSPEC_SP_TEST))
10901 (set (match_scratch:SI 4 "=r,r") (const_int 0))
10902 (clobber (match_scratch:SI 3 "=&r,&r"))]
10903 "TARGET_32BIT"
10904 "@
10905 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
10906 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
10907 [(set_attr "length" "16,20")])
10909 (define_insn "stack_protect_testdi"
10910 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
10911 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
10912 (match_operand:DI 2 "memory_operand" "m,m")]
10913 UNSPEC_SP_TEST))
10914 (set (match_scratch:DI 4 "=r,r") (const_int 0))
10915 (clobber (match_scratch:DI 3 "=&r,&r"))]
10916 "TARGET_64BIT"
10917 "@
10918 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
10919 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
10920 [(set_attr "length" "16,20")])
10922 \f
10923 ;; Here are the actual compare insns.
10924 (define_insn "*cmp<mode>_internal1"
10925 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
10926 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
10927 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
10928 ""
10929 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
10930 [(set_attr "type" "cmp")])
10932 ;; If we are comparing a register for equality with a large constant,
10933 ;; we can do this with an XOR followed by a compare. But this is profitable
10934 ;; only if the large constant is only used for the comparison (and in this
10935 ;; case we already have a register to reuse as scratch).
10936 ;;
10937 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
10938 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
10940 (define_peephole2
10941 [(set (match_operand:SI 0 "register_operand")
10942 (match_operand:SI 1 "logical_const_operand" ""))
10943 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
10944 [(match_dup 0)
10945 (match_operand:SI 2 "logical_const_operand" "")]))
10946 (set (match_operand:CC 4 "cc_reg_operand" "")
10947 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
10948 (match_dup 0)))
10949 (set (pc)
10950 (if_then_else (match_operator 6 "equality_operator"
10951 [(match_dup 4) (const_int 0)])
10952 (match_operand 7 "" "")
10953 (match_operand 8 "" "")))]
10954 "peep2_reg_dead_p (3, operands[0])
10955 && peep2_reg_dead_p (4, operands[4])"
10956 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
10957 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
10958 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
10960 {
10961 /* Get the constant we are comparing against, and see what it looks like
10962 when sign-extended from 16 to 32 bits. Then see what constant we could
10963 XOR with SEXTC to get the sign-extended value. */
10964 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
10965 SImode,
10966 operands[1], operands[2]);
10967 HOST_WIDE_INT c = INTVAL (cnst);
10968 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
10969 HOST_WIDE_INT xorv = c ^ sextc;
10971 operands[9] = GEN_INT (xorv);
10972 operands[10] = GEN_INT (sextc);
10973 })
10975 (define_insn "*cmpsi_internal2"
10976 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
10977 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
10978 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
10979 ""
10980 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
10981 [(set_attr "type" "cmp")])
10983 (define_insn "*cmpdi_internal2"
10984 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
10985 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
10986 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
10987 ""
10988 "cmpld%I2 %0,%1,%b2"
10989 [(set_attr "type" "cmp")])
10991 ;; The following two insns don't exist as single insns, but if we provide
10992 ;; them, we can swap an add and compare, which will enable us to overlap more
10993 ;; of the required delay between a compare and branch. We generate code for
10994 ;; them by splitting.
10996 (define_insn ""
10997 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
10998 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
10999 (match_operand:SI 2 "short_cint_operand" "i")))
11000 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11001 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11002 ""
11003 "#"
11004 [(set_attr "length" "8")])
11006 (define_insn ""
11007 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11008 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11009 (match_operand:SI 2 "u_short_cint_operand" "i")))
11010 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11011 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11012 ""
11013 "#"
11014 [(set_attr "length" "8")])
11016 (define_split
11017 [(set (match_operand:CC 3 "cc_reg_operand" "")
11018 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11019 (match_operand:SI 2 "short_cint_operand" "")))
11020 (set (match_operand:SI 0 "gpc_reg_operand" "")
11021 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11022 ""
11023 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11024 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11026 (define_split
11027 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11028 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11029 (match_operand:SI 2 "u_short_cint_operand" "")))
11030 (set (match_operand:SI 0 "gpc_reg_operand" "")
11031 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11032 ""
11033 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11034 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11036 (define_insn "*cmpsf_internal1"
11037 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11038 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11039 (match_operand:SF 2 "gpc_reg_operand" "f")))]
11040 "TARGET_HARD_FLOAT && TARGET_FPRS"
11041 "fcmpu %0,%1,%2"
11042 [(set_attr "type" "fpcompare")])
11044 (define_insn "*cmpdf_internal1"
11045 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11046 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11047 (match_operand:DF 2 "gpc_reg_operand" "f")))]
11048 "TARGET_HARD_FLOAT && TARGET_FPRS"
11049 "fcmpu %0,%1,%2"
11050 [(set_attr "type" "fpcompare")])
11052 ;; Only need to compare second words if first words equal
11053 (define_insn "*cmptf_internal1"
11054 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11055 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11056 (match_operand:TF 2 "gpc_reg_operand" "f")))]
11057 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
11058 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11059 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11060 [(set_attr "type" "fpcompare")
11061 (set_attr "length" "12")])
11063 (define_insn_and_split "*cmptf_internal2"
11064 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11065 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11066 (match_operand:TF 2 "gpc_reg_operand" "f")))
11067 (clobber (match_scratch:DF 3 "=f"))
11068 (clobber (match_scratch:DF 4 "=f"))
11069 (clobber (match_scratch:DF 5 "=f"))
11070 (clobber (match_scratch:DF 6 "=f"))
11071 (clobber (match_scratch:DF 7 "=f"))
11072 (clobber (match_scratch:DF 8 "=f"))
11073 (clobber (match_scratch:DF 9 "=f"))
11074 (clobber (match_scratch:DF 10 "=f"))]
11075 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
11076 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11077 "#"
11078 "&& reload_completed"
11079 [(set (match_dup 3) (match_dup 13))
11080 (set (match_dup 4) (match_dup 14))
11081 (set (match_dup 9) (abs:DF (match_dup 5)))
11082 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
11083 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
11084 (label_ref (match_dup 11))
11085 (pc)))
11086 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
11087 (set (pc) (label_ref (match_dup 12)))
11088 (match_dup 11)
11089 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
11090 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
11091 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
11092 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
11093 (match_dup 12)]
11094 {
11095 REAL_VALUE_TYPE rv;
11096 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
11097 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
11099 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
11100 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
11101 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
11102 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
11103 operands[11] = gen_label_rtx ();
11104 operands[12] = gen_label_rtx ();
11105 real_inf (&rv);
11106 operands[13] = force_const_mem (DFmode,
11107 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
11108 operands[14] = force_const_mem (DFmode,
11109 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
11110 DFmode));
11111 if (TARGET_TOC)
11112 {
11113 operands[13] = gen_const_mem (DFmode,
11114 create_TOC_reference (XEXP (operands[13], 0)));
11115 operands[14] = gen_const_mem (DFmode,
11116 create_TOC_reference (XEXP (operands[14], 0)));
11117 set_mem_alias_set (operands[13], get_TOC_alias_set ());
11118 set_mem_alias_set (operands[14], get_TOC_alias_set ());
11119 }
11120 })
11121 \f
11122 ;; Now we have the scc insns. We can do some combinations because of the
11123 ;; way the machine works.
11124 ;;
11125 ;; Note that this is probably faster if we can put an insn between the
11126 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11127 ;; cases the insns below which don't use an intermediate CR field will
11128 ;; be used instead.
11129 (define_insn ""
11130 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11131 (match_operator:SI 1 "scc_comparison_operator"
11132 [(match_operand 2 "cc_reg_operand" "y")
11133 (const_int 0)]))]
11134 ""
11135 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11136 [(set (attr "type")
11137 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11138 (const_string "mfcrf")
11139 ]
11140 (const_string "mfcr")))
11141 (set_attr "length" "8")])
11143 ;; Same as above, but get the GT bit.
11144 (define_insn "move_from_CR_gt_bit"
11145 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11146 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
11147 "TARGET_E500"
11148 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
11149 [(set_attr "type" "mfcr")
11150 (set_attr "length" "8")])
11152 ;; Same as above, but get the OV/ORDERED bit.
11153 (define_insn "move_from_CR_ov_bit"
11154 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11155 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
11156 "TARGET_ISEL"
11157 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
11158 [(set_attr "type" "mfcr")
11159 (set_attr "length" "8")])
11161 (define_insn ""
11162 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11163 (match_operator:DI 1 "scc_comparison_operator"
11164 [(match_operand 2 "cc_reg_operand" "y")
11165 (const_int 0)]))]
11166 "TARGET_POWERPC64"
11167 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11168 [(set (attr "type")
11169 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11170 (const_string "mfcrf")
11171 ]
11172 (const_string "mfcr")))
11173 (set_attr "length" "8")])
11175 (define_insn ""
11176 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11177 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11178 [(match_operand 2 "cc_reg_operand" "y,y")
11179 (const_int 0)])
11180 (const_int 0)))
11181 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11182 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11183 "TARGET_32BIT"
11184 "@
11185 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
11186 #"
11187 [(set_attr "type" "delayed_compare")
11188 (set_attr "length" "8,16")])
11190 (define_split
11191 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11192 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11193 [(match_operand 2 "cc_reg_operand" "")
11194 (const_int 0)])
11195 (const_int 0)))
11196 (set (match_operand:SI 3 "gpc_reg_operand" "")
11197 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11198 "TARGET_32BIT && reload_completed"
11199 [(set (match_dup 3)
11200 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11201 (set (match_dup 0)
11202 (compare:CC (match_dup 3)
11203 (const_int 0)))]
11204 "")
11206 (define_insn ""
11207 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11208 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11209 [(match_operand 2 "cc_reg_operand" "y")
11210 (const_int 0)])
11211 (match_operand:SI 3 "const_int_operand" "n")))]
11212 ""
11213 "*
11214 {
11215 int is_bit = ccr_bit (operands[1], 1);
11216 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11217 int count;
11219 if (is_bit >= put_bit)
11220 count = is_bit - put_bit;
11221 else
11222 count = 32 - (put_bit - is_bit);
11224 operands[4] = GEN_INT (count);
11225 operands[5] = GEN_INT (put_bit);
11227 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
11228 }"
11229 [(set (attr "type")
11230 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11231 (const_string "mfcrf")
11232 ]
11233 (const_string "mfcr")))
11234 (set_attr "length" "8")])
11236 (define_insn ""
11237 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11238 (compare:CC
11239 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11240 [(match_operand 2 "cc_reg_operand" "y,y")
11241 (const_int 0)])
11242 (match_operand:SI 3 "const_int_operand" "n,n"))
11243 (const_int 0)))
11244 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11245 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11246 (match_dup 3)))]
11247 ""
11248 "*
11249 {
11250 int is_bit = ccr_bit (operands[1], 1);
11251 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11252 int count;
11254 /* Force split for non-cc0 compare. */
11255 if (which_alternative == 1)
11256 return \"#\";
11258 if (is_bit >= put_bit)
11259 count = is_bit - put_bit;
11260 else
11261 count = 32 - (put_bit - is_bit);
11263 operands[5] = GEN_INT (count);
11264 operands[6] = GEN_INT (put_bit);
11266 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
11267 }"
11268 [(set_attr "type" "delayed_compare")
11269 (set_attr "length" "8,16")])
11271 (define_split
11272 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11273 (compare:CC
11274 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11275 [(match_operand 2 "cc_reg_operand" "")
11276 (const_int 0)])
11277 (match_operand:SI 3 "const_int_operand" ""))
11278 (const_int 0)))
11279 (set (match_operand:SI 4 "gpc_reg_operand" "")
11280 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11281 (match_dup 3)))]
11282 "reload_completed"
11283 [(set (match_dup 4)
11284 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11285 (match_dup 3)))
11286 (set (match_dup 0)
11287 (compare:CC (match_dup 4)
11288 (const_int 0)))]
11289 "")
11291 ;; There is a 3 cycle delay between consecutive mfcr instructions
11292 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
11294 (define_peephole
11295 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11296 (match_operator:SI 1 "scc_comparison_operator"
11297 [(match_operand 2 "cc_reg_operand" "y")
11298 (const_int 0)]))
11299 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
11300 (match_operator:SI 4 "scc_comparison_operator"
11301 [(match_operand 5 "cc_reg_operand" "y")
11302 (const_int 0)]))]
11303 "REGNO (operands[2]) != REGNO (operands[5])"
11304 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11305 [(set_attr "type" "mfcr")
11306 (set_attr "length" "12")])
11308 (define_peephole
11309 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11310 (match_operator:DI 1 "scc_comparison_operator"
11311 [(match_operand 2 "cc_reg_operand" "y")
11312 (const_int 0)]))
11313 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
11314 (match_operator:DI 4 "scc_comparison_operator"
11315 [(match_operand 5 "cc_reg_operand" "y")
11316 (const_int 0)]))]
11317 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
11318 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11319 [(set_attr "type" "mfcr")
11320 (set_attr "length" "12")])
11322 ;; There are some scc insns that can be done directly, without a compare.
11323 ;; These are faster because they don't involve the communications between
11324 ;; the FXU and branch units. In fact, we will be replacing all of the
11325 ;; integer scc insns here or in the portable methods in emit_store_flag.
11326 ;;
11327 ;; Also support (neg (scc ..)) since that construct is used to replace
11328 ;; branches, (plus (scc ..) ..) since that construct is common and
11329 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
11330 ;; cases where it is no more expensive than (neg (scc ..)).
11332 ;; Have reload force a constant into a register for the simple insns that
11333 ;; otherwise won't accept constants. We do this because it is faster than
11334 ;; the cmp/mfcr sequence we would otherwise generate.
11336 (define_mode_attr scc_eq_op2 [(SI "rKLI")
11337 (DI "rKJI")])
11339 (define_insn_and_split "*eq<mode>"
11340 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
11341 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
11342 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
11343 "!TARGET_POWER"
11344 "#"
11345 "!TARGET_POWER"
11346 [(set (match_dup 0)
11347 (clz:GPR (match_dup 3)))
11348 (set (match_dup 0)
11349 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
11350 {
11351 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11352 {
11353 /* Use output operand as intermediate. */
11354 operands[3] = operands[0];
11356 if (logical_operand (operands[2], <MODE>mode))
11357 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11358 gen_rtx_XOR (<MODE>mode,
11359 operands[1], operands[2])));
11360 else
11361 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11362 gen_rtx_PLUS (<MODE>mode, operands[1],
11363 negate_rtx (<MODE>mode,
11364 operands[2]))));
11365 }
11366 else
11367 operands[3] = operands[1];
11369 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
11370 })
11372 (define_insn_and_split "*eq<mode>_compare"
11373 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11374 (compare:CC
11375 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
11376 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
11377 (const_int 0)))
11378 (set (match_operand:P 0 "gpc_reg_operand" "=r")
11379 (eq:P (match_dup 1) (match_dup 2)))]
11380 "!TARGET_POWER && optimize_size"
11381 "#"
11382 "!TARGET_POWER && optimize_size"
11383 [(set (match_dup 0)
11384 (clz:P (match_dup 4)))
11385 (parallel [(set (match_dup 3)
11386 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
11387 (const_int 0)))
11388 (set (match_dup 0)
11389 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
11390 {
11391 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11392 {
11393 /* Use output operand as intermediate. */
11394 operands[4] = operands[0];
11396 if (logical_operand (operands[2], <MODE>mode))
11397 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11398 gen_rtx_XOR (<MODE>mode,
11399 operands[1], operands[2])));
11400 else
11401 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11402 gen_rtx_PLUS (<MODE>mode, operands[1],
11403 negate_rtx (<MODE>mode,
11404 operands[2]))));
11405 }
11406 else
11407 operands[4] = operands[1];
11409 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
11410 })
11412 (define_insn "*eqsi_power"
11413 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11414 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11415 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
11416 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
11417 "TARGET_POWER"
11418 "@
11419 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11420 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
11421 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11422 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11423 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
11424 [(set_attr "type" "three,two,three,three,three")
11425 (set_attr "length" "12,8,12,12,12")])
11427 ;; We have insns of the form shown by the first define_insn below. If
11428 ;; there is something inside the comparison operation, we must split it.
11429 (define_split
11430 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11431 (plus:SI (match_operator 1 "comparison_operator"
11432 [(match_operand:SI 2 "" "")
11433 (match_operand:SI 3
11434 "reg_or_cint_operand" "")])
11435 (match_operand:SI 4 "gpc_reg_operand" "")))
11436 (clobber (match_operand:SI 5 "register_operand" ""))]
11437 "! gpc_reg_operand (operands[2], SImode)"
11438 [(set (match_dup 5) (match_dup 2))
11439 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
11440 (match_dup 4)))])
11442 (define_insn "*plus_eqsi"
11443 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
11444 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11445 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
11446 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
11447 "TARGET_32BIT"
11448 "@
11449 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11450 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
11451 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11452 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11453 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
11454 [(set_attr "type" "three,two,three,three,three")
11455 (set_attr "length" "12,8,12,12,12")])
11457 (define_insn "*compare_plus_eqsi"
11458 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11459 (compare:CC
11460 (plus:SI
11461 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11462 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
11463 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11464 (const_int 0)))
11465 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
11466 "TARGET_32BIT && optimize_size"
11467 "@
11468 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11469 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
11470 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11471 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11472 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11473 #
11474 #
11475 #
11476 #
11477 #"
11478 [(set_attr "type" "compare")
11479 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11481 (define_split
11482 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11483 (compare:CC
11484 (plus:SI
11485 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11486 (match_operand:SI 2 "scc_eq_operand" ""))
11487 (match_operand:SI 3 "gpc_reg_operand" ""))
11488 (const_int 0)))
11489 (clobber (match_scratch:SI 4 ""))]
11490 "TARGET_32BIT && optimize_size && reload_completed"
11491 [(set (match_dup 4)
11492 (plus:SI (eq:SI (match_dup 1)
11493 (match_dup 2))
11494 (match_dup 3)))
11495 (set (match_dup 0)
11496 (compare:CC (match_dup 4)
11497 (const_int 0)))]
11498 "")
11500 (define_insn "*plus_eqsi_compare"
11501 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11502 (compare:CC
11503 (plus:SI
11504 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11505 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
11506 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11507 (const_int 0)))
11508 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
11509 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11510 "TARGET_32BIT && optimize_size"
11511 "@
11512 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11513 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
11514 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11515 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11516 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11517 #
11518 #
11519 #
11520 #
11521 #"
11522 [(set_attr "type" "compare")
11523 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11525 (define_split
11526 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11527 (compare:CC
11528 (plus:SI
11529 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11530 (match_operand:SI 2 "scc_eq_operand" ""))
11531 (match_operand:SI 3 "gpc_reg_operand" ""))
11532 (const_int 0)))
11533 (set (match_operand:SI 0 "gpc_reg_operand" "")
11534 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11535 "TARGET_32BIT && optimize_size && reload_completed"
11536 [(set (match_dup 0)
11537 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11538 (set (match_dup 4)
11539 (compare:CC (match_dup 0)
11540 (const_int 0)))]
11541 "")
11543 (define_insn "*neg_eq0<mode>"
11544 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11545 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
11546 (const_int 0))))]
11547 ""
11548 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
11549 [(set_attr "type" "two")
11550 (set_attr "length" "8")])
11552 (define_insn_and_split "*neg_eq<mode>"
11553 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11554 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
11555 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
11556 ""
11557 "#"
11558 ""
11559 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
11560 {
11561 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11562 {
11563 /* Use output operand as intermediate. */
11564 operands[3] = operands[0];
11566 if (logical_operand (operands[2], <MODE>mode))
11567 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11568 gen_rtx_XOR (<MODE>mode,
11569 operands[1], operands[2])));
11570 else
11571 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11572 gen_rtx_PLUS (<MODE>mode, operands[1],
11573 negate_rtx (<MODE>mode,
11574 operands[2]))));
11575 }
11576 else
11577 operands[3] = operands[1];
11578 })
11580 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
11581 ;; since it nabs/sr is just as fast.
11582 (define_insn "*ne0si"
11583 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
11584 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11585 (const_int 31)))
11586 (clobber (match_scratch:SI 2 "=&r"))]
11587 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
11588 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
11589 [(set_attr "type" "two")
11590 (set_attr "length" "8")])
11592 (define_insn "*ne0di"
11593 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11594 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11595 (const_int 63)))
11596 (clobber (match_scratch:DI 2 "=&r"))]
11597 "TARGET_64BIT"
11598 "addic %2,%1,-1\;subfe %0,%2,%1"
11599 [(set_attr "type" "two")
11600 (set_attr "length" "8")])
11602 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
11603 (define_insn "*plus_ne0si"
11604 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11605 (plus:SI (lshiftrt:SI
11606 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11607 (const_int 31))
11608 (match_operand:SI 2 "gpc_reg_operand" "r")))
11609 (clobber (match_scratch:SI 3 "=&r"))]
11610 "TARGET_32BIT"
11611 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
11612 [(set_attr "type" "two")
11613 (set_attr "length" "8")])
11615 (define_insn "*plus_ne0di"
11616 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11617 (plus:DI (lshiftrt:DI
11618 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11619 (const_int 63))
11620 (match_operand:DI 2 "gpc_reg_operand" "r")))
11621 (clobber (match_scratch:DI 3 "=&r"))]
11622 "TARGET_64BIT"
11623 "addic %3,%1,-1\;addze %0,%2"
11624 [(set_attr "type" "two")
11625 (set_attr "length" "8")])
11627 (define_insn "*compare_plus_ne0si"
11628 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11629 (compare:CC
11630 (plus:SI (lshiftrt:SI
11631 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11632 (const_int 31))
11633 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11634 (const_int 0)))
11635 (clobber (match_scratch:SI 3 "=&r,&r"))
11636 (clobber (match_scratch:SI 4 "=X,&r"))]
11637 "TARGET_32BIT"
11638 "@
11639 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
11640 #"
11641 [(set_attr "type" "compare")
11642 (set_attr "length" "8,12")])
11644 (define_split
11645 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11646 (compare:CC
11647 (plus:SI (lshiftrt:SI
11648 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11649 (const_int 31))
11650 (match_operand:SI 2 "gpc_reg_operand" ""))
11651 (const_int 0)))
11652 (clobber (match_scratch:SI 3 ""))
11653 (clobber (match_scratch:SI 4 ""))]
11654 "TARGET_32BIT && reload_completed"
11655 [(parallel [(set (match_dup 3)
11656 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
11657 (const_int 31))
11658 (match_dup 2)))
11659 (clobber (match_dup 4))])
11660 (set (match_dup 0)
11661 (compare:CC (match_dup 3)
11662 (const_int 0)))]
11663 "")
11665 (define_insn "*compare_plus_ne0di"
11666 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11667 (compare:CC
11668 (plus:DI (lshiftrt:DI
11669 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11670 (const_int 63))
11671 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11672 (const_int 0)))
11673 (clobber (match_scratch:DI 3 "=&r,&r"))]
11674 "TARGET_64BIT"
11675 "@
11676 addic %3,%1,-1\;addze. %3,%2
11677 #"
11678 [(set_attr "type" "compare")
11679 (set_attr "length" "8,12")])
11681 (define_split
11682 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11683 (compare:CC
11684 (plus:DI (lshiftrt:DI
11685 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11686 (const_int 63))
11687 (match_operand:DI 2 "gpc_reg_operand" ""))
11688 (const_int 0)))
11689 (clobber (match_scratch:DI 3 ""))]
11690 "TARGET_64BIT && reload_completed"
11691 [(set (match_dup 3)
11692 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
11693 (const_int 63))
11694 (match_dup 2)))
11695 (set (match_dup 0)
11696 (compare:CC (match_dup 3)
11697 (const_int 0)))]
11698 "")
11700 (define_insn "*plus_ne0si_compare"
11701 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11702 (compare:CC
11703 (plus:SI (lshiftrt:SI
11704 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11705 (const_int 31))
11706 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11707 (const_int 0)))
11708 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11709 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11710 (match_dup 2)))
11711 (clobber (match_scratch:SI 3 "=&r,&r"))]
11712 "TARGET_32BIT"
11713 "@
11714 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
11715 #"
11716 [(set_attr "type" "compare")
11717 (set_attr "length" "8,12")])
11719 (define_split
11720 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11721 (compare:CC
11722 (plus:SI (lshiftrt:SI
11723 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11724 (const_int 31))
11725 (match_operand:SI 2 "gpc_reg_operand" ""))
11726 (const_int 0)))
11727 (set (match_operand:SI 0 "gpc_reg_operand" "")
11728 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11729 (match_dup 2)))
11730 (clobber (match_scratch:SI 3 ""))]
11731 "TARGET_32BIT && reload_completed"
11732 [(parallel [(set (match_dup 0)
11733 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11734 (match_dup 2)))
11735 (clobber (match_dup 3))])
11736 (set (match_dup 4)
11737 (compare:CC (match_dup 0)
11738 (const_int 0)))]
11739 "")
11741 (define_insn "*plus_ne0di_compare"
11742 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11743 (compare:CC
11744 (plus:DI (lshiftrt:DI
11745 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11746 (const_int 63))
11747 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11748 (const_int 0)))
11749 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11750 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11751 (match_dup 2)))
11752 (clobber (match_scratch:DI 3 "=&r,&r"))]
11753 "TARGET_64BIT"
11754 "@
11755 addic %3,%1,-1\;addze. %0,%2
11756 #"
11757 [(set_attr "type" "compare")
11758 (set_attr "length" "8,12")])
11760 (define_split
11761 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11762 (compare:CC
11763 (plus:DI (lshiftrt:DI
11764 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11765 (const_int 63))
11766 (match_operand:DI 2 "gpc_reg_operand" ""))
11767 (const_int 0)))
11768 (set (match_operand:DI 0 "gpc_reg_operand" "")
11769 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11770 (match_dup 2)))
11771 (clobber (match_scratch:DI 3 ""))]
11772 "TARGET_64BIT && reload_completed"
11773 [(parallel [(set (match_dup 0)
11774 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11775 (match_dup 2)))
11776 (clobber (match_dup 3))])
11777 (set (match_dup 4)
11778 (compare:CC (match_dup 0)
11779 (const_int 0)))]
11780 "")
11782 (define_insn ""
11783 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11784 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11785 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
11786 (clobber (match_scratch:SI 3 "=r,X"))]
11787 "TARGET_POWER"
11788 "@
11789 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
11790 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
11791 [(set_attr "length" "12")])
11793 (define_insn ""
11794 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
11795 (compare:CC
11796 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11797 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11798 (const_int 0)))
11799 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
11800 (le:SI (match_dup 1) (match_dup 2)))
11801 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
11802 "TARGET_POWER"
11803 "@
11804 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
11805 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
11806 #
11807 #"
11808 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
11809 (set_attr "length" "12,12,16,16")])
11811 (define_split
11812 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11813 (compare:CC
11814 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11815 (match_operand:SI 2 "reg_or_short_operand" ""))
11816 (const_int 0)))
11817 (set (match_operand:SI 0 "gpc_reg_operand" "")
11818 (le:SI (match_dup 1) (match_dup 2)))
11819 (clobber (match_scratch:SI 3 ""))]
11820 "TARGET_POWER && reload_completed"
11821 [(parallel [(set (match_dup 0)
11822 (le:SI (match_dup 1) (match_dup 2)))
11823 (clobber (match_dup 3))])
11824 (set (match_dup 4)
11825 (compare:CC (match_dup 0)
11826 (const_int 0)))]
11827 "")
11829 (define_insn ""
11830 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
11831 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11832 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
11833 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
11834 "TARGET_POWER"
11835 "@
11836 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11837 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
11838 [(set_attr "length" "12")])
11840 (define_insn ""
11841 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
11842 (compare:CC
11843 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11844 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11845 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11846 (const_int 0)))
11847 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
11848 "TARGET_POWER"
11849 "@
11850 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11851 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
11852 #
11853 #"
11854 [(set_attr "type" "compare")
11855 (set_attr "length" "12,12,16,16")])
11857 (define_split
11858 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11859 (compare:CC
11860 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11861 (match_operand:SI 2 "reg_or_short_operand" ""))
11862 (match_operand:SI 3 "gpc_reg_operand" ""))
11863 (const_int 0)))
11864 (clobber (match_scratch:SI 4 ""))]
11865 "TARGET_POWER && reload_completed"
11866 [(set (match_dup 4)
11867 (plus:SI (le:SI (match_dup 1) (match_dup 2))
11868 (match_dup 3)))
11869 (set (match_dup 0)
11870 (compare:CC (match_dup 4)
11871 (const_int 0)))]
11872 "")
11874 (define_insn ""
11875 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
11876 (compare:CC
11877 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11878 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11879 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11880 (const_int 0)))
11881 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
11882 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11883 "TARGET_POWER"
11884 "@
11885 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11886 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
11887 #
11888 #"
11889 [(set_attr "type" "compare")
11890 (set_attr "length" "12,12,16,16")])
11892 (define_split
11893 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11894 (compare:CC
11895 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11896 (match_operand:SI 2 "reg_or_short_operand" ""))
11897 (match_operand:SI 3 "gpc_reg_operand" ""))
11898 (const_int 0)))
11899 (set (match_operand:SI 0 "gpc_reg_operand" "")
11900 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11901 "TARGET_POWER && reload_completed"
11902 [(set (match_dup 0)
11903 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11904 (set (match_dup 4)
11905 (compare:CC (match_dup 0)
11906 (const_int 0)))]
11907 "")
11909 (define_insn ""
11910 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11911 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11912 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
11913 "TARGET_POWER"
11914 "@
11915 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11916 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
11917 [(set_attr "length" "12")])
11919 (define_insn "*leu<mode>"
11920 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11921 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
11922 (match_operand:P 2 "reg_or_short_operand" "rI")))]
11923 ""
11924 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
11925 [(set_attr "type" "three")
11926 (set_attr "length" "12")])
11928 (define_insn "*leu<mode>_compare"
11929 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
11930 (compare:CC
11931 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
11932 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
11933 (const_int 0)))
11934 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
11935 (leu:P (match_dup 1) (match_dup 2)))]
11936 ""
11937 "@
11938 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
11939 #"
11940 [(set_attr "type" "compare")
11941 (set_attr "length" "12,16")])
11943 (define_split
11944 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11945 (compare:CC
11946 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
11947 (match_operand:P 2 "reg_or_short_operand" ""))
11948 (const_int 0)))
11949 (set (match_operand:P 0 "gpc_reg_operand" "")
11950 (leu:P (match_dup 1) (match_dup 2)))]
11951 "reload_completed"
11952 [(set (match_dup 0)
11953 (leu:P (match_dup 1) (match_dup 2)))
11954 (set (match_dup 3)
11955 (compare:CC (match_dup 0)
11956 (const_int 0)))]
11957 "")
11959 (define_insn "*plus_leu<mode>"
11960 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
11961 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
11962 (match_operand:P 2 "reg_or_short_operand" "rI"))
11963 (match_operand:P 3 "gpc_reg_operand" "r")))]
11964 ""
11965 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
11966 [(set_attr "type" "two")
11967 (set_attr "length" "8")])
11969 (define_insn ""
11970 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11971 (compare:CC
11972 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11973 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11974 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11975 (const_int 0)))
11976 (clobber (match_scratch:SI 4 "=&r,&r"))]
11977 "TARGET_32BIT"
11978 "@
11979 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
11980 #"
11981 [(set_attr "type" "compare")
11982 (set_attr "length" "8,12")])
11984 (define_split
11985 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11986 (compare:CC
11987 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11988 (match_operand:SI 2 "reg_or_short_operand" ""))
11989 (match_operand:SI 3 "gpc_reg_operand" ""))
11990 (const_int 0)))
11991 (clobber (match_scratch:SI 4 ""))]
11992 "TARGET_32BIT && reload_completed"
11993 [(set (match_dup 4)
11994 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
11995 (match_dup 3)))
11996 (set (match_dup 0)
11997 (compare:CC (match_dup 4)
11998 (const_int 0)))]
11999 "")
12001 (define_insn ""
12002 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12003 (compare:CC
12004 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12005 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12006 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12007 (const_int 0)))
12008 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12009 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12010 "TARGET_32BIT"
12011 "@
12012 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
12013 #"
12014 [(set_attr "type" "compare")
12015 (set_attr "length" "8,12")])
12017 (define_split
12018 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12019 (compare:CC
12020 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12021 (match_operand:SI 2 "reg_or_short_operand" ""))
12022 (match_operand:SI 3 "gpc_reg_operand" ""))
12023 (const_int 0)))
12024 (set (match_operand:SI 0 "gpc_reg_operand" "")
12025 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12026 "TARGET_32BIT && reload_completed"
12027 [(set (match_dup 0)
12028 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12029 (set (match_dup 4)
12030 (compare:CC (match_dup 0)
12031 (const_int 0)))]
12032 "")
12034 (define_insn "*neg_leu<mode>"
12035 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12036 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12037 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12038 ""
12039 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
12040 [(set_attr "type" "three")
12041 (set_attr "length" "12")])
12043 (define_insn "*and_neg_leu<mode>"
12044 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12045 (and:P (neg:P
12046 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12047 (match_operand:P 2 "reg_or_short_operand" "rI")))
12048 (match_operand:P 3 "gpc_reg_operand" "r")))]
12049 ""
12050 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12051 [(set_attr "type" "three")
12052 (set_attr "length" "12")])
12054 (define_insn ""
12055 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12056 (compare:CC
12057 (and:SI (neg:SI
12058 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12059 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12060 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12061 (const_int 0)))
12062 (clobber (match_scratch:SI 4 "=&r,&r"))]
12063 "TARGET_32BIT"
12064 "@
12065 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12066 #"
12067 [(set_attr "type" "compare")
12068 (set_attr "length" "12,16")])
12070 (define_split
12071 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12072 (compare:CC
12073 (and:SI (neg:SI
12074 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12075 (match_operand:SI 2 "reg_or_short_operand" "")))
12076 (match_operand:SI 3 "gpc_reg_operand" ""))
12077 (const_int 0)))
12078 (clobber (match_scratch:SI 4 ""))]
12079 "TARGET_32BIT && reload_completed"
12080 [(set (match_dup 4)
12081 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12082 (match_dup 3)))
12083 (set (match_dup 0)
12084 (compare:CC (match_dup 4)
12085 (const_int 0)))]
12086 "")
12088 (define_insn ""
12089 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12090 (compare:CC
12091 (and:SI (neg:SI
12092 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12093 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12094 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12095 (const_int 0)))
12096 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12097 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12098 "TARGET_32BIT"
12099 "@
12100 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12101 #"
12102 [(set_attr "type" "compare")
12103 (set_attr "length" "12,16")])
12105 (define_split
12106 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12107 (compare:CC
12108 (and:SI (neg:SI
12109 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12110 (match_operand:SI 2 "reg_or_short_operand" "")))
12111 (match_operand:SI 3 "gpc_reg_operand" ""))
12112 (const_int 0)))
12113 (set (match_operand:SI 0 "gpc_reg_operand" "")
12114 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12115 "TARGET_32BIT && reload_completed"
12116 [(set (match_dup 0)
12117 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12118 (match_dup 3)))
12119 (set (match_dup 4)
12120 (compare:CC (match_dup 0)
12121 (const_int 0)))]
12122 "")
12124 (define_insn ""
12125 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12126 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12127 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12128 "TARGET_POWER"
12129 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12130 [(set_attr "length" "12")])
12132 (define_insn ""
12133 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12134 (compare:CC
12135 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12136 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12137 (const_int 0)))
12138 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12139 (lt:SI (match_dup 1) (match_dup 2)))]
12140 "TARGET_POWER"
12141 "@
12142 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12143 #"
12144 [(set_attr "type" "delayed_compare")
12145 (set_attr "length" "12,16")])
12147 (define_split
12148 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12149 (compare:CC
12150 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12151 (match_operand:SI 2 "reg_or_short_operand" ""))
12152 (const_int 0)))
12153 (set (match_operand:SI 0 "gpc_reg_operand" "")
12154 (lt:SI (match_dup 1) (match_dup 2)))]
12155 "TARGET_POWER && reload_completed"
12156 [(set (match_dup 0)
12157 (lt:SI (match_dup 1) (match_dup 2)))
12158 (set (match_dup 3)
12159 (compare:CC (match_dup 0)
12160 (const_int 0)))]
12161 "")
12163 (define_insn ""
12164 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12165 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12166 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12167 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12168 "TARGET_POWER"
12169 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
12170 [(set_attr "length" "12")])
12172 (define_insn ""
12173 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12174 (compare:CC
12175 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12176 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12177 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12178 (const_int 0)))
12179 (clobber (match_scratch:SI 4 "=&r,&r"))]
12180 "TARGET_POWER"
12181 "@
12182 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12183 #"
12184 [(set_attr "type" "compare")
12185 (set_attr "length" "12,16")])
12187 (define_split
12188 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12189 (compare:CC
12190 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12191 (match_operand:SI 2 "reg_or_short_operand" ""))
12192 (match_operand:SI 3 "gpc_reg_operand" ""))
12193 (const_int 0)))
12194 (clobber (match_scratch:SI 4 ""))]
12195 "TARGET_POWER && reload_completed"
12196 [(set (match_dup 4)
12197 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
12198 (match_dup 3)))
12199 (set (match_dup 0)
12200 (compare:CC (match_dup 4)
12201 (const_int 0)))]
12202 "")
12204 (define_insn ""
12205 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12206 (compare:CC
12207 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12208 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12209 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12210 (const_int 0)))
12211 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12212 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12213 "TARGET_POWER"
12214 "@
12215 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
12216 #"
12217 [(set_attr "type" "compare")
12218 (set_attr "length" "12,16")])
12220 (define_split
12221 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12222 (compare:CC
12223 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12224 (match_operand:SI 2 "reg_or_short_operand" ""))
12225 (match_operand:SI 3 "gpc_reg_operand" ""))
12226 (const_int 0)))
12227 (set (match_operand:SI 0 "gpc_reg_operand" "")
12228 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12229 "TARGET_POWER && reload_completed"
12230 [(set (match_dup 0)
12231 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12232 (set (match_dup 4)
12233 (compare:CC (match_dup 0)
12234 (const_int 0)))]
12235 "")
12237 (define_insn ""
12238 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12239 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12240 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12241 "TARGET_POWER"
12242 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12243 [(set_attr "length" "12")])
12245 (define_insn_and_split "*ltu<mode>"
12246 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12247 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12248 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12249 ""
12250 "#"
12251 ""
12252 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12253 (set (match_dup 0) (neg:P (match_dup 0)))]
12254 "")
12256 (define_insn_and_split "*ltu<mode>_compare"
12257 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12258 (compare:CC
12259 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12260 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12261 (const_int 0)))
12262 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12263 (ltu:P (match_dup 1) (match_dup 2)))]
12264 ""
12265 "#"
12266 ""
12267 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12268 (parallel [(set (match_dup 3)
12269 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
12270 (set (match_dup 0) (neg:P (match_dup 0)))])]
12271 "")
12273 (define_insn_and_split "*plus_ltu<mode>"
12274 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
12275 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12276 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12277 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
12278 ""
12279 "#"
12280 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12281 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12282 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
12283 "")
12285 (define_insn_and_split "*plus_ltu<mode>_compare"
12286 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12287 (compare:CC
12288 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12289 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12290 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
12291 (const_int 0)))
12292 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12293 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
12294 ""
12295 "#"
12296 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12297 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12298 (parallel [(set (match_dup 4)
12299 (compare:CC (minus:P (match_dup 3) (match_dup 0))
12300 (const_int 0)))
12301 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
12302 "")
12304 (define_insn "*neg_ltu<mode>"
12305 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12306 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12307 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
12308 ""
12309 "@
12310 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12311 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12312 [(set_attr "type" "two")
12313 (set_attr "length" "8")])
12315 (define_insn ""
12316 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12317 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12318 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12319 (clobber (match_scratch:SI 3 "=r"))]
12320 "TARGET_POWER"
12321 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
12322 [(set_attr "length" "12")])
12324 (define_insn ""
12325 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12326 (compare:CC
12327 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12328 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12329 (const_int 0)))
12330 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12331 (ge:SI (match_dup 1) (match_dup 2)))
12332 (clobber (match_scratch:SI 3 "=r,r"))]
12333 "TARGET_POWER"
12334 "@
12335 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12336 #"
12337 [(set_attr "type" "compare")
12338 (set_attr "length" "12,16")])
12340 (define_split
12341 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12342 (compare:CC
12343 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12344 (match_operand:SI 2 "reg_or_short_operand" ""))
12345 (const_int 0)))
12346 (set (match_operand:SI 0 "gpc_reg_operand" "")
12347 (ge:SI (match_dup 1) (match_dup 2)))
12348 (clobber (match_scratch:SI 3 ""))]
12349 "TARGET_POWER && reload_completed"
12350 [(parallel [(set (match_dup 0)
12351 (ge:SI (match_dup 1) (match_dup 2)))
12352 (clobber (match_dup 3))])
12353 (set (match_dup 4)
12354 (compare:CC (match_dup 0)
12355 (const_int 0)))]
12356 "")
12358 (define_insn ""
12359 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12360 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12361 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12362 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12363 "TARGET_POWER"
12364 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12365 [(set_attr "length" "12")])
12367 (define_insn ""
12368 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12369 (compare:CC
12370 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12371 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12372 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12373 (const_int 0)))
12374 (clobber (match_scratch:SI 4 "=&r,&r"))]
12375 "TARGET_POWER"
12376 "@
12377 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12378 #"
12379 [(set_attr "type" "compare")
12380 (set_attr "length" "12,16")])
12382 (define_split
12383 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12384 (compare:CC
12385 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12386 (match_operand:SI 2 "reg_or_short_operand" ""))
12387 (match_operand:SI 3 "gpc_reg_operand" ""))
12388 (const_int 0)))
12389 (clobber (match_scratch:SI 4 ""))]
12390 "TARGET_POWER && reload_completed"
12391 [(set (match_dup 4)
12392 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
12393 (match_dup 3)))
12394 (set (match_dup 0)
12395 (compare:CC (match_dup 4)
12396 (const_int 0)))]
12397 "")
12399 (define_insn ""
12400 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12401 (compare:CC
12402 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12403 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12404 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12405 (const_int 0)))
12406 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12407 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12408 "TARGET_POWER"
12409 "@
12410 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12411 #"
12412 [(set_attr "type" "compare")
12413 (set_attr "length" "12,16")])
12415 (define_split
12416 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12417 (compare:CC
12418 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12419 (match_operand:SI 2 "reg_or_short_operand" ""))
12420 (match_operand:SI 3 "gpc_reg_operand" ""))
12421 (const_int 0)))
12422 (set (match_operand:SI 0 "gpc_reg_operand" "")
12423 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12424 "TARGET_POWER && reload_completed"
12425 [(set (match_dup 0)
12426 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12427 (set (match_dup 4)
12428 (compare:CC (match_dup 0)
12429 (const_int 0)))]
12430 "")
12432 (define_insn ""
12433 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12434 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12435 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12436 "TARGET_POWER"
12437 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
12438 [(set_attr "length" "12")])
12440 (define_insn "*geu<mode>"
12441 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12442 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12443 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12444 ""
12445 "@
12446 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
12447 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12448 [(set_attr "type" "three")
12449 (set_attr "length" "12")])
12451 (define_insn "*geu<mode>_compare"
12452 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12453 (compare:CC
12454 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12455 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12456 (const_int 0)))
12457 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12458 (geu:P (match_dup 1) (match_dup 2)))]
12459 ""
12460 "@
12461 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12462 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12463 #
12464 #"
12465 [(set_attr "type" "compare")
12466 (set_attr "length" "12,12,16,16")])
12468 (define_split
12469 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12470 (compare:CC
12471 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
12472 (match_operand:P 2 "reg_or_neg_short_operand" ""))
12473 (const_int 0)))
12474 (set (match_operand:P 0 "gpc_reg_operand" "")
12475 (geu:P (match_dup 1) (match_dup 2)))]
12476 "reload_completed"
12477 [(set (match_dup 0)
12478 (geu:P (match_dup 1) (match_dup 2)))
12479 (set (match_dup 3)
12480 (compare:CC (match_dup 0)
12481 (const_int 0)))]
12482 "")
12484 (define_insn "*plus_geu<mode>"
12485 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
12486 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12487 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12488 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
12489 ""
12490 "@
12491 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
12492 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
12493 [(set_attr "type" "two")
12494 (set_attr "length" "8")])
12496 (define_insn ""
12497 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12498 (compare:CC
12499 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12500 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12501 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12502 (const_int 0)))
12503 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12504 "TARGET_32BIT"
12505 "@
12506 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
12507 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
12508 #
12509 #"
12510 [(set_attr "type" "compare")
12511 (set_attr "length" "8,8,12,12")])
12513 (define_split
12514 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12515 (compare:CC
12516 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12517 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12518 (match_operand:SI 3 "gpc_reg_operand" ""))
12519 (const_int 0)))
12520 (clobber (match_scratch:SI 4 ""))]
12521 "TARGET_32BIT && reload_completed"
12522 [(set (match_dup 4)
12523 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
12524 (match_dup 3)))
12525 (set (match_dup 0)
12526 (compare:CC (match_dup 4)
12527 (const_int 0)))]
12528 "")
12530 (define_insn ""
12531 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12532 (compare:CC
12533 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12534 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12535 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12536 (const_int 0)))
12537 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12538 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12539 "TARGET_32BIT"
12540 "@
12541 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
12542 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
12543 #
12544 #"
12545 [(set_attr "type" "compare")
12546 (set_attr "length" "8,8,12,12")])
12548 (define_split
12549 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12550 (compare:CC
12551 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12552 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12553 (match_operand:SI 3 "gpc_reg_operand" ""))
12554 (const_int 0)))
12555 (set (match_operand:SI 0 "gpc_reg_operand" "")
12556 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12557 "TARGET_32BIT && reload_completed"
12558 [(set (match_dup 0)
12559 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12560 (set (match_dup 4)
12561 (compare:CC (match_dup 0)
12562 (const_int 0)))]
12563 "")
12565 (define_insn "*neg_geu<mode>"
12566 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12567 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12568 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
12569 ""
12570 "@
12571 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
12572 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
12573 [(set_attr "type" "three")
12574 (set_attr "length" "12")])
12576 (define_insn "*and_neg_geu<mode>"
12577 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
12578 (and:P (neg:P
12579 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12580 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
12581 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
12582 ""
12583 "@
12584 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
12585 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12586 [(set_attr "type" "three")
12587 (set_attr "length" "12")])
12589 (define_insn ""
12590 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12591 (compare:CC
12592 (and:SI (neg:SI
12593 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12594 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12595 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12596 (const_int 0)))
12597 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12598 "TARGET_32BIT"
12599 "@
12600 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12601 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12602 #
12603 #"
12604 [(set_attr "type" "compare")
12605 (set_attr "length" "12,12,16,16")])
12607 (define_split
12608 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12609 (compare:CC
12610 (and:SI (neg:SI
12611 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12612 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12613 (match_operand:SI 3 "gpc_reg_operand" ""))
12614 (const_int 0)))
12615 (clobber (match_scratch:SI 4 ""))]
12616 "TARGET_32BIT && reload_completed"
12617 [(set (match_dup 4)
12618 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
12619 (match_dup 3)))
12620 (set (match_dup 0)
12621 (compare:CC (match_dup 4)
12622 (const_int 0)))]
12623 "")
12625 (define_insn ""
12626 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12627 (compare:CC
12628 (and:SI (neg:SI
12629 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12630 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12631 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12632 (const_int 0)))
12633 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12634 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12635 "TARGET_32BIT"
12636 "@
12637 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12638 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12639 #
12640 #"
12641 [(set_attr "type" "compare")
12642 (set_attr "length" "12,12,16,16")])
12644 (define_split
12645 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12646 (compare:CC
12647 (and:SI (neg:SI
12648 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12649 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12650 (match_operand:SI 3 "gpc_reg_operand" ""))
12651 (const_int 0)))
12652 (set (match_operand:SI 0 "gpc_reg_operand" "")
12653 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12654 "TARGET_32BIT && reload_completed"
12655 [(set (match_dup 0)
12656 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
12657 (set (match_dup 4)
12658 (compare:CC (match_dup 0)
12659 (const_int 0)))]
12660 "")
12662 (define_insn ""
12663 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12664 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12665 (match_operand:SI 2 "reg_or_short_operand" "r")))]
12666 "TARGET_POWER"
12667 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12668 [(set_attr "length" "12")])
12670 (define_insn ""
12671 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12672 (compare:CC
12673 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12674 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
12675 (const_int 0)))
12676 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12677 (gt:SI (match_dup 1) (match_dup 2)))]
12678 "TARGET_POWER"
12679 "@
12680 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12681 #"
12682 [(set_attr "type" "delayed_compare")
12683 (set_attr "length" "12,16")])
12685 (define_split
12686 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12687 (compare:CC
12688 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12689 (match_operand:SI 2 "reg_or_short_operand" ""))
12690 (const_int 0)))
12691 (set (match_operand:SI 0 "gpc_reg_operand" "")
12692 (gt:SI (match_dup 1) (match_dup 2)))]
12693 "TARGET_POWER && reload_completed"
12694 [(set (match_dup 0)
12695 (gt:SI (match_dup 1) (match_dup 2)))
12696 (set (match_dup 3)
12697 (compare:CC (match_dup 0)
12698 (const_int 0)))]
12699 "")
12701 (define_insn "*plus_gt0<mode>"
12702 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12703 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
12704 (const_int 0))
12705 (match_operand:P 2 "gpc_reg_operand" "r")))]
12706 ""
12707 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
12708 [(set_attr "type" "three")
12709 (set_attr "length" "12")])
12711 (define_insn ""
12712 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12713 (compare:CC
12714 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12715 (const_int 0))
12716 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12717 (const_int 0)))
12718 (clobber (match_scratch:SI 3 "=&r,&r"))]
12719 "TARGET_32BIT"
12720 "@
12721 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
12722 #"
12723 [(set_attr "type" "compare")
12724 (set_attr "length" "12,16")])
12726 (define_split
12727 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12728 (compare:CC
12729 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12730 (const_int 0))
12731 (match_operand:SI 2 "gpc_reg_operand" ""))
12732 (const_int 0)))
12733 (clobber (match_scratch:SI 3 ""))]
12734 "TARGET_32BIT && reload_completed"
12735 [(set (match_dup 3)
12736 (plus:SI (gt:SI (match_dup 1) (const_int 0))
12737 (match_dup 2)))
12738 (set (match_dup 0)
12739 (compare:CC (match_dup 3)
12740 (const_int 0)))]
12741 "")
12743 (define_insn ""
12744 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12745 (compare:CC
12746 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12747 (const_int 0))
12748 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12749 (const_int 0)))
12750 (clobber (match_scratch:DI 3 "=&r,&r"))]
12751 "TARGET_64BIT"
12752 "@
12753 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
12754 #"
12755 [(set_attr "type" "compare")
12756 (set_attr "length" "12,16")])
12758 (define_split
12759 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12760 (compare:CC
12761 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12762 (const_int 0))
12763 (match_operand:DI 2 "gpc_reg_operand" ""))
12764 (const_int 0)))
12765 (clobber (match_scratch:DI 3 ""))]
12766 "TARGET_64BIT && reload_completed"
12767 [(set (match_dup 3)
12768 (plus:DI (gt:DI (match_dup 1) (const_int 0))
12769 (match_dup 2)))
12770 (set (match_dup 0)
12771 (compare:CC (match_dup 3)
12772 (const_int 0)))]
12773 "")
12775 (define_insn ""
12776 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12777 (compare:CC
12778 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12779 (const_int 0))
12780 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12781 (const_int 0)))
12782 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12783 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
12784 "TARGET_32BIT"
12785 "@
12786 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
12787 #"
12788 [(set_attr "type" "compare")
12789 (set_attr "length" "12,16")])
12791 (define_split
12792 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12793 (compare:CC
12794 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12795 (const_int 0))
12796 (match_operand:SI 2 "gpc_reg_operand" ""))
12797 (const_int 0)))
12798 (set (match_operand:SI 0 "gpc_reg_operand" "")
12799 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
12800 "TARGET_32BIT && reload_completed"
12801 [(set (match_dup 0)
12802 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
12803 (set (match_dup 3)
12804 (compare:CC (match_dup 0)
12805 (const_int 0)))]
12806 "")
12808 (define_insn ""
12809 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12810 (compare:CC
12811 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12812 (const_int 0))
12813 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12814 (const_int 0)))
12815 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
12816 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
12817 "TARGET_64BIT"
12818 "@
12819 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
12820 #"
12821 [(set_attr "type" "compare")
12822 (set_attr "length" "12,16")])
12824 (define_split
12825 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12826 (compare:CC
12827 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12828 (const_int 0))
12829 (match_operand:DI 2 "gpc_reg_operand" ""))
12830 (const_int 0)))
12831 (set (match_operand:DI 0 "gpc_reg_operand" "")
12832 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
12833 "TARGET_64BIT && reload_completed"
12834 [(set (match_dup 0)
12835 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
12836 (set (match_dup 3)
12837 (compare:CC (match_dup 0)
12838 (const_int 0)))]
12839 "")
12841 (define_insn ""
12842 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12843 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12844 (match_operand:SI 2 "reg_or_short_operand" "r"))
12845 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12846 "TARGET_POWER"
12847 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
12848 [(set_attr "length" "12")])
12850 (define_insn ""
12851 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12852 (compare:CC
12853 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12854 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
12855 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12856 (const_int 0)))
12857 (clobber (match_scratch:SI 4 "=&r,&r"))]
12858 "TARGET_POWER"
12859 "@
12860 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12861 #"
12862 [(set_attr "type" "compare")
12863 (set_attr "length" "12,16")])
12865 (define_split
12866 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12867 (compare:CC
12868 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12869 (match_operand:SI 2 "reg_or_short_operand" ""))
12870 (match_operand:SI 3 "gpc_reg_operand" ""))
12871 (const_int 0)))
12872 (clobber (match_scratch:SI 4 ""))]
12873 "TARGET_POWER && reload_completed"
12874 [(set (match_dup 4)
12875 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12876 (set (match_dup 0)
12877 (compare:CC (match_dup 4)
12878 (const_int 0)))]
12879 "")
12881 (define_insn ""
12882 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12883 (compare:CC
12884 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12885 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
12886 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12887 (const_int 0)))
12888 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12889 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12890 "TARGET_POWER"
12891 "@
12892 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
12893 #"
12894 [(set_attr "type" "compare")
12895 (set_attr "length" "12,16")])
12897 (define_split
12898 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12899 (compare:CC
12900 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12901 (match_operand:SI 2 "reg_or_short_operand" ""))
12902 (match_operand:SI 3 "gpc_reg_operand" ""))
12903 (const_int 0)))
12904 (set (match_operand:SI 0 "gpc_reg_operand" "")
12905 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12906 "TARGET_POWER && reload_completed"
12907 [(set (match_dup 0)
12908 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12909 (set (match_dup 4)
12910 (compare:CC (match_dup 0)
12911 (const_int 0)))]
12912 "")
12914 (define_insn ""
12915 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12916 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12917 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
12918 "TARGET_POWER"
12919 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12920 [(set_attr "length" "12")])
12922 (define_insn_and_split "*gtu<mode>"
12923 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12924 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
12925 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12926 ""
12927 "#"
12928 ""
12929 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
12930 (set (match_dup 0) (neg:P (match_dup 0)))]
12931 "")
12933 (define_insn_and_split "*gtu<mode>_compare"
12934 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12935 (compare:CC
12936 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12937 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
12938 (const_int 0)))
12939 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12940 (gtu:P (match_dup 1) (match_dup 2)))]
12941 ""
12942 "#"
12943 ""
12944 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
12945 (parallel [(set (match_dup 3)
12946 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
12947 (set (match_dup 0) (neg:P (match_dup 0)))])]
12948 "")
12950 (define_insn_and_split "*plus_gtu<mode>"
12951 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12952 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
12953 (match_operand:P 2 "reg_or_short_operand" "rI"))
12954 (match_operand:P 3 "reg_or_short_operand" "rI")))]
12955 ""
12956 "#"
12957 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12958 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
12959 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
12960 "")
12962 (define_insn_and_split "*plus_gtu<mode>_compare"
12963 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12964 (compare:CC
12965 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12966 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
12967 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
12968 (const_int 0)))
12969 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12970 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
12971 ""
12972 "#"
12973 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12974 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
12975 (parallel [(set (match_dup 4)
12976 (compare:CC (minus:P (match_dup 3) (match_dup 0))
12977 (const_int 0)))
12978 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
12979 "")
12981 (define_insn "*neg_gtu<mode>"
12982 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12983 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
12984 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12985 ""
12986 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
12987 [(set_attr "type" "two")
12988 (set_attr "length" "8")])
12990 \f
12991 ;; Define both directions of branch and return. If we need a reload
12992 ;; register, we'd rather use CR0 since it is much easier to copy a
12993 ;; register CC value to there.
12995 (define_insn ""
12996 [(set (pc)
12997 (if_then_else (match_operator 1 "branch_comparison_operator"
12998 [(match_operand 2
12999 "cc_reg_operand" "y")
13000 (const_int 0)])
13001 (label_ref (match_operand 0 "" ""))
13002 (pc)))]
13003 ""
13004 "*
13005 {
13006 return output_cbranch (operands[1], \"%l0\", 0, insn);
13007 }"
13008 [(set_attr "type" "branch")])
13010 (define_insn ""
13011 [(set (pc)
13012 (if_then_else (match_operator 0 "branch_comparison_operator"
13013 [(match_operand 1
13014 "cc_reg_operand" "y")
13015 (const_int 0)])
13016 (return)
13017 (pc)))]
13018 "direct_return ()"
13019 "*
13020 {
13021 return output_cbranch (operands[0], NULL, 0, insn);
13022 }"
13023 [(set_attr "type" "jmpreg")
13024 (set_attr "length" "4")])
13026 (define_insn ""
13027 [(set (pc)
13028 (if_then_else (match_operator 1 "branch_comparison_operator"
13029 [(match_operand 2
13030 "cc_reg_operand" "y")
13031 (const_int 0)])
13032 (pc)
13033 (label_ref (match_operand 0 "" ""))))]
13034 ""
13035 "*
13036 {
13037 return output_cbranch (operands[1], \"%l0\", 1, insn);
13038 }"
13039 [(set_attr "type" "branch")])
13041 (define_insn ""
13042 [(set (pc)
13043 (if_then_else (match_operator 0 "branch_comparison_operator"
13044 [(match_operand 1
13045 "cc_reg_operand" "y")
13046 (const_int 0)])
13047 (pc)
13048 (return)))]
13049 "direct_return ()"
13050 "*
13051 {
13052 return output_cbranch (operands[0], NULL, 1, insn);
13053 }"
13054 [(set_attr "type" "jmpreg")
13055 (set_attr "length" "4")])
13057 ;; Logic on condition register values.
13059 ; This pattern matches things like
13060 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13061 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13062 ; (const_int 1)))
13063 ; which are generated by the branch logic.
13064 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13066 (define_insn "*cceq_ior_compare"
13067 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13068 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13069 [(match_operator:SI 2
13070 "branch_positive_comparison_operator"
13071 [(match_operand 3
13072 "cc_reg_operand" "y,y")
13073 (const_int 0)])
13074 (match_operator:SI 4
13075 "branch_positive_comparison_operator"
13076 [(match_operand 5
13077 "cc_reg_operand" "0,y")
13078 (const_int 0)])])
13079 (const_int 1)))]
13080 ""
13081 "cr%q1 %E0,%j2,%j4"
13082 [(set_attr "type" "cr_logical,delayed_cr")])
13084 ; Why is the constant -1 here, but 1 in the previous pattern?
13085 ; Because ~1 has all but the low bit set.
13086 (define_insn ""
13087 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13088 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13089 [(not:SI (match_operator:SI 2
13090 "branch_positive_comparison_operator"
13091 [(match_operand 3
13092 "cc_reg_operand" "y,y")
13093 (const_int 0)]))
13094 (match_operator:SI 4
13095 "branch_positive_comparison_operator"
13096 [(match_operand 5
13097 "cc_reg_operand" "0,y")
13098 (const_int 0)])])
13099 (const_int -1)))]
13100 ""
13101 "cr%q1 %E0,%j2,%j4"
13102 [(set_attr "type" "cr_logical,delayed_cr")])
13104 (define_insn "*cceq_rev_compare"
13105 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13106 (compare:CCEQ (match_operator:SI 1
13107 "branch_positive_comparison_operator"
13108 [(match_operand 2
13109 "cc_reg_operand" "0,y")
13110 (const_int 0)])
13111 (const_int 0)))]
13112 ""
13113 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
13114 [(set_attr "type" "cr_logical,delayed_cr")])
13116 ;; If we are comparing the result of two comparisons, this can be done
13117 ;; using creqv or crxor.
13119 (define_insn_and_split ""
13120 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13121 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13122 [(match_operand 2 "cc_reg_operand" "y")
13123 (const_int 0)])
13124 (match_operator 3 "branch_comparison_operator"
13125 [(match_operand 4 "cc_reg_operand" "y")
13126 (const_int 0)])))]
13127 ""
13128 "#"
13129 ""
13130 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13131 (match_dup 5)))]
13132 "
13133 {
13134 int positive_1, positive_2;
13136 positive_1 = branch_positive_comparison_operator (operands[1],
13137 GET_MODE (operands[1]));
13138 positive_2 = branch_positive_comparison_operator (operands[3],
13139 GET_MODE (operands[3]));
13141 if (! positive_1)
13142 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
13143 GET_CODE (operands[1])),
13144 SImode,
13145 operands[2], const0_rtx);
13146 else if (GET_MODE (operands[1]) != SImode)
13147 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
13148 operands[2], const0_rtx);
13150 if (! positive_2)
13151 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
13152 GET_CODE (operands[3])),
13153 SImode,
13154 operands[4], const0_rtx);
13155 else if (GET_MODE (operands[3]) != SImode)
13156 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
13157 operands[4], const0_rtx);
13159 if (positive_1 == positive_2)
13160 {
13161 operands[1] = gen_rtx_NOT (SImode, operands[1]);
13162 operands[5] = constm1_rtx;
13163 }
13164 else
13165 {
13166 operands[5] = const1_rtx;
13167 }
13168 }")
13170 ;; Unconditional branch and return.
13172 (define_insn "jump"
13173 [(set (pc)
13174 (label_ref (match_operand 0 "" "")))]
13175 ""
13176 "b %l0"
13177 [(set_attr "type" "branch")])
13179 (define_insn "return"
13180 [(return)]
13181 "direct_return ()"
13182 "{br|blr}"
13183 [(set_attr "type" "jmpreg")])
13185 (define_expand "indirect_jump"
13186 [(set (pc) (match_operand 0 "register_operand" ""))])
13188 (define_insn "*indirect_jump<mode>"
13189 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
13190 ""
13191 "@
13192 bctr
13193 {br|blr}"
13194 [(set_attr "type" "jmpreg")])
13196 ;; Table jump for switch statements:
13197 (define_expand "tablejump"
13198 [(use (match_operand 0 "" ""))
13199 (use (label_ref (match_operand 1 "" "")))]
13200 ""
13201 "
13202 {
13203 if (TARGET_32BIT)
13204 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13205 else
13206 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13207 DONE;
13208 }")
13210 (define_expand "tablejumpsi"
13211 [(set (match_dup 3)
13212 (plus:SI (match_operand:SI 0 "" "")
13213 (match_dup 2)))
13214 (parallel [(set (pc) (match_dup 3))
13215 (use (label_ref (match_operand 1 "" "")))])]
13216 "TARGET_32BIT"
13217 "
13218 { operands[0] = force_reg (SImode, operands[0]);
13219 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
13220 operands[3] = gen_reg_rtx (SImode);
13221 }")
13223 (define_expand "tablejumpdi"
13224 [(set (match_dup 4)
13225 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm")))
13226 (set (match_dup 3)
13227 (plus:DI (match_dup 4)
13228 (match_dup 2)))
13229 (parallel [(set (pc) (match_dup 3))
13230 (use (label_ref (match_operand 1 "" "")))])]
13231 "TARGET_64BIT"
13232 "
13233 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
13234 operands[3] = gen_reg_rtx (DImode);
13235 operands[4] = gen_reg_rtx (DImode);
13236 }")
13238 (define_insn "*tablejump<mode>_internal1"
13239 [(set (pc)
13240 (match_operand:P 0 "register_operand" "c,*l"))
13241 (use (label_ref (match_operand 1 "" "")))]
13242 ""
13243 "@
13244 bctr
13245 {br|blr}"
13246 [(set_attr "type" "jmpreg")])
13248 (define_insn "nop"
13249 [(const_int 0)]
13250 ""
13251 "{cror 0,0,0|nop}")
13252 \f
13253 ;; Define the subtract-one-and-jump insns, starting with the template
13254 ;; so loop.c knows what to generate.
13256 (define_expand "doloop_end"
13257 [(use (match_operand 0 "" "")) ; loop pseudo
13258 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13259 (use (match_operand 2 "" "")) ; max iterations
13260 (use (match_operand 3 "" "")) ; loop level
13261 (use (match_operand 4 "" ""))] ; label
13262 ""
13263 "
13264 {
13265 /* Only use this on innermost loops. */
13266 if (INTVAL (operands[3]) > 1)
13267 FAIL;
13268 if (TARGET_64BIT)
13269 {
13270 if (GET_MODE (operands[0]) != DImode)
13271 FAIL;
13272 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
13273 }
13274 else
13275 {
13276 if (GET_MODE (operands[0]) != SImode)
13277 FAIL;
13278 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
13279 }
13280 DONE;
13281 }")
13283 (define_expand "ctr<mode>"
13284 [(parallel [(set (pc)
13285 (if_then_else (ne (match_operand:P 0 "register_operand" "")
13286 (const_int 1))
13287 (label_ref (match_operand 1 "" ""))
13288 (pc)))
13289 (set (match_dup 0)
13290 (plus:P (match_dup 0)
13291 (const_int -1)))
13292 (clobber (match_scratch:CC 2 ""))
13293 (clobber (match_scratch:P 3 ""))])]
13294 ""
13295 "")
13297 ;; We need to be able to do this for any operand, including MEM, or we
13298 ;; will cause reload to blow up since we don't allow output reloads on
13299 ;; JUMP_INSNs.
13300 ;; For the length attribute to be calculated correctly, the
13301 ;; label MUST be operand 0.
13303 (define_insn "*ctr<mode>_internal1"
13304 [(set (pc)
13305 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13306 (const_int 1))
13307 (label_ref (match_operand 0 "" ""))
13308 (pc)))
13309 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13310 (plus:P (match_dup 1)
13311 (const_int -1)))
13312 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13313 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13314 ""
13315 "*
13316 {
13317 if (which_alternative != 0)
13318 return \"#\";
13319 else if (get_attr_length (insn) == 4)
13320 return \"{bdn|bdnz} %l0\";
13321 else
13322 return \"bdz $+8\;b %l0\";
13323 }"
13324 [(set_attr "type" "branch")
13325 (set_attr "length" "*,12,16,16")])
13327 (define_insn "*ctr<mode>_internal2"
13328 [(set (pc)
13329 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13330 (const_int 1))
13331 (pc)
13332 (label_ref (match_operand 0 "" ""))))
13333 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13334 (plus:P (match_dup 1)
13335 (const_int -1)))
13336 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13337 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13338 ""
13339 "*
13340 {
13341 if (which_alternative != 0)
13342 return \"#\";
13343 else if (get_attr_length (insn) == 4)
13344 return \"bdz %l0\";
13345 else
13346 return \"{bdn|bdnz} $+8\;b %l0\";
13347 }"
13348 [(set_attr "type" "branch")
13349 (set_attr "length" "*,12,16,16")])
13351 ;; Similar but use EQ
13353 (define_insn "*ctr<mode>_internal5"
13354 [(set (pc)
13355 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13356 (const_int 1))
13357 (label_ref (match_operand 0 "" ""))
13358 (pc)))
13359 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13360 (plus:P (match_dup 1)
13361 (const_int -1)))
13362 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13363 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13364 ""
13365 "*
13366 {
13367 if (which_alternative != 0)
13368 return \"#\";
13369 else if (get_attr_length (insn) == 4)
13370 return \"bdz %l0\";
13371 else
13372 return \"{bdn|bdnz} $+8\;b %l0\";
13373 }"
13374 [(set_attr "type" "branch")
13375 (set_attr "length" "*,12,16,16")])
13377 (define_insn "*ctr<mode>_internal6"
13378 [(set (pc)
13379 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13380 (const_int 1))
13381 (pc)
13382 (label_ref (match_operand 0 "" ""))))
13383 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13384 (plus:P (match_dup 1)
13385 (const_int -1)))
13386 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13387 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13388 ""
13389 "*
13390 {
13391 if (which_alternative != 0)
13392 return \"#\";
13393 else if (get_attr_length (insn) == 4)
13394 return \"{bdn|bdnz} %l0\";
13395 else
13396 return \"bdz $+8\;b %l0\";
13397 }"
13398 [(set_attr "type" "branch")
13399 (set_attr "length" "*,12,16,16")])
13401 ;; Now the splitters if we could not allocate the CTR register
13403 (define_split
13404 [(set (pc)
13405 (if_then_else (match_operator 2 "comparison_operator"
13406 [(match_operand:P 1 "gpc_reg_operand" "")
13407 (const_int 1)])
13408 (match_operand 5 "" "")
13409 (match_operand 6 "" "")))
13410 (set (match_operand:P 0 "gpc_reg_operand" "")
13411 (plus:P (match_dup 1) (const_int -1)))
13412 (clobber (match_scratch:CC 3 ""))
13413 (clobber (match_scratch:P 4 ""))]
13414 "reload_completed"
13415 [(parallel [(set (match_dup 3)
13416 (compare:CC (plus:P (match_dup 1)
13417 (const_int -1))
13418 (const_int 0)))
13419 (set (match_dup 0)
13420 (plus:P (match_dup 1)
13421 (const_int -1)))])
13422 (set (pc) (if_then_else (match_dup 7)
13423 (match_dup 5)
13424 (match_dup 6)))]
13425 "
13426 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13427 operands[3], const0_rtx); }")
13429 (define_split
13430 [(set (pc)
13431 (if_then_else (match_operator 2 "comparison_operator"
13432 [(match_operand:P 1 "gpc_reg_operand" "")
13433 (const_int 1)])
13434 (match_operand 5 "" "")
13435 (match_operand 6 "" "")))
13436 (set (match_operand:P 0 "nonimmediate_operand" "")
13437 (plus:P (match_dup 1) (const_int -1)))
13438 (clobber (match_scratch:CC 3 ""))
13439 (clobber (match_scratch:P 4 ""))]
13440 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
13441 [(parallel [(set (match_dup 3)
13442 (compare:CC (plus:P (match_dup 1)
13443 (const_int -1))
13444 (const_int 0)))
13445 (set (match_dup 4)
13446 (plus:P (match_dup 1)
13447 (const_int -1)))])
13448 (set (match_dup 0)
13449 (match_dup 4))
13450 (set (pc) (if_then_else (match_dup 7)
13451 (match_dup 5)
13452 (match_dup 6)))]
13453 "
13454 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13455 operands[3], const0_rtx); }")
13456 \f
13457 (define_insn "trap"
13458 [(trap_if (const_int 1) (const_int 0))]
13459 ""
13460 "{t 31,0,0|trap}")
13462 (define_expand "conditional_trap"
13463 [(trap_if (match_operator 0 "trap_comparison_operator"
13464 [(match_dup 2) (match_dup 3)])
13465 (match_operand 1 "const_int_operand" ""))]
13466 ""
13467 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
13468 operands[2] = rs6000_compare_op0;
13469 operands[3] = rs6000_compare_op1;")
13471 (define_insn ""
13472 [(trap_if (match_operator 0 "trap_comparison_operator"
13473 [(match_operand:GPR 1 "register_operand" "r")
13474 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
13475 (const_int 0))]
13476 ""
13477 "{t|t<wd>}%V0%I2 %1,%2")
13478 \f
13479 ;; Insns related to generating the function prologue and epilogue.
13481 (define_expand "prologue"
13482 [(use (const_int 0))]
13483 "TARGET_SCHED_PROLOG"
13484 "
13485 {
13486 rs6000_emit_prologue ();
13487 DONE;
13488 }")
13490 (define_insn "*movesi_from_cr_one"
13491 [(match_parallel 0 "mfcr_operation"
13492 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13493 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
13494 (match_operand 3 "immediate_operand" "n")]
13495 UNSPEC_MOVESI_FROM_CR))])]
13496 "TARGET_MFCRF"
13497 "*
13498 {
13499 int mask = 0;
13500 int i;
13501 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13502 {
13503 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13504 operands[4] = GEN_INT (mask);
13505 output_asm_insn (\"mfcr %1,%4\", operands);
13506 }
13507 return \"\";
13508 }"
13509 [(set_attr "type" "mfcrf")])
13511 (define_insn "movesi_from_cr"
13512 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13513 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
13514 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)]
13515 UNSPEC_MOVESI_FROM_CR))]
13516 ""
13517 "mfcr %0"
13518 [(set_attr "type" "mfcr")])
13520 (define_insn "*stmw"
13521 [(match_parallel 0 "stmw_operation"
13522 [(set (match_operand:SI 1 "memory_operand" "=m")
13523 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
13524 "TARGET_MULTIPLE"
13525 "{stm|stmw} %2,%1"
13526 [(set_attr "type" "store_ux")])
13528 (define_insn "*save_fpregs_<mode>"
13529 [(match_parallel 0 "any_parallel_operand"
13530 [(clobber (match_operand:P 1 "register_operand" "=l"))
13531 (use (match_operand:P 2 "call_operand" "s"))
13532 (set (match_operand:DF 3 "memory_operand" "=m")
13533 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
13534 ""
13535 "bl %z2"
13536 [(set_attr "type" "branch")
13537 (set_attr "length" "4")])
13539 ; These are to explain that changes to the stack pointer should
13540 ; not be moved over stores to stack memory.
13541 (define_insn "stack_tie"
13542 [(set (match_operand:BLK 0 "memory_operand" "+m")
13543 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
13544 ""
13545 ""
13546 [(set_attr "length" "0")])
13549 (define_expand "epilogue"
13550 [(use (const_int 0))]
13551 "TARGET_SCHED_PROLOG"
13552 "
13553 {
13554 rs6000_emit_epilogue (FALSE);
13555 DONE;
13556 }")
13558 ; On some processors, doing the mtcrf one CC register at a time is
13559 ; faster (like on the 604e). On others, doing them all at once is
13560 ; faster; for instance, on the 601 and 750.
13562 (define_expand "movsi_to_cr_one"
13563 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13564 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
13565 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
13566 ""
13567 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
13569 (define_insn "*movsi_to_cr"
13570 [(match_parallel 0 "mtcrf_operation"
13571 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
13572 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
13573 (match_operand 3 "immediate_operand" "n")]
13574 UNSPEC_MOVESI_TO_CR))])]
13575 ""
13576 "*
13577 {
13578 int mask = 0;
13579 int i;
13580 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13581 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13582 operands[4] = GEN_INT (mask);
13583 return \"mtcrf %4,%2\";
13584 }"
13585 [(set_attr "type" "mtcr")])
13587 (define_insn "*mtcrfsi"
13588 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13589 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
13590 (match_operand 2 "immediate_operand" "n")]
13591 UNSPEC_MOVESI_TO_CR))]
13592 "GET_CODE (operands[0]) == REG
13593 && CR_REGNO_P (REGNO (operands[0]))
13594 && GET_CODE (operands[2]) == CONST_INT
13595 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
13596 "mtcrf %R0,%1"
13597 [(set_attr "type" "mtcr")])
13599 ; The load-multiple instructions have similar properties.
13600 ; Note that "load_multiple" is a name known to the machine-independent
13601 ; code that actually corresponds to the PowerPC load-string.
13603 (define_insn "*lmw"
13604 [(match_parallel 0 "lmw_operation"
13605 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13606 (match_operand:SI 2 "memory_operand" "m"))])]
13607 "TARGET_MULTIPLE"
13608 "{lm|lmw} %1,%2"
13609 [(set_attr "type" "load_ux")])
13611 (define_insn "*return_internal_<mode>"
13612 [(return)
13613 (use (match_operand:P 0 "register_operand" "lc"))]
13614 ""
13615 "b%T0"
13616 [(set_attr "type" "jmpreg")])
13618 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
13619 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
13621 (define_insn "*return_and_restore_fpregs_<mode>"
13622 [(match_parallel 0 "any_parallel_operand"
13623 [(return)
13624 (use (match_operand:P 1 "register_operand" "l"))
13625 (use (match_operand:P 2 "call_operand" "s"))
13626 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
13627 (match_operand:DF 4 "memory_operand" "m"))])]
13628 ""
13629 "b %z2")
13631 ; This is used in compiling the unwind routines.
13632 (define_expand "eh_return"
13633 [(use (match_operand 0 "general_operand" ""))]
13634 ""
13635 "
13636 {
13637 if (TARGET_32BIT)
13638 emit_insn (gen_eh_set_lr_si (operands[0]));
13639 else
13640 emit_insn (gen_eh_set_lr_di (operands[0]));
13641 DONE;
13642 }")
13644 ; We can't expand this before we know where the link register is stored.
13645 (define_insn "eh_set_lr_<mode>"
13646 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
13647 UNSPECV_EH_RR)
13648 (clobber (match_scratch:P 1 "=&b"))]
13649 ""
13650 "#")
13652 (define_split
13653 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
13654 (clobber (match_scratch 1 ""))]
13655 "reload_completed"
13656 [(const_int 0)]
13657 "
13658 {
13659 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
13660 DONE;
13661 }")
13663 (define_insn "prefetch"
13664 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
13665 (match_operand:SI 1 "const_int_operand" "n")
13666 (match_operand:SI 2 "const_int_operand" "n"))]
13667 "TARGET_POWERPC"
13668 "*
13669 {
13670 if (GET_CODE (operands[0]) == REG)
13671 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
13672 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
13673 }"
13674 [(set_attr "type" "load")])
13675 \f
13677 (include "sync.md")
13678 (include "altivec.md")
13679 (include "spe.md")