gnu/dist/gcc4/gcc/config/s390/s390-modes.def

   1 /* Definitions of target machine for GNU compiler, for IBM S/390
   2    Copyright (C) 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
   3    Contributed by Hartmut Penner (hpenner@de.ibm.com) and
   4                   Ulrich Weigand (uweigand@de.ibm.com).
   5
   6 This file is part of GCC.
   7
   8 GCC is free software; you can redistribute it and/or modify it under
   9 the terms of the GNU General Public License as published by the Free
  10 Software Foundation; either version 2, or (at your option) any later
  11 version.
  12
  13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16 for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with GCC; see the file COPYING.  If not, write to the Free
  20 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
  21 02110-1301, USA.  */
  22
  23 /* 256-bit integer mode is needed for STACK_SAVEAREA_MODE.  */
  24 INT_MODE (OI, 32);
  25
  26 /* Define TFmode to work around reload problem PR 20927.  */
  27 FLOAT_MODE (TF, 16, ieee_quad_format);
  28
  29 /* Add any extra modes needed to represent the condition code.  */
  30
  31 /*
  32
  33 Condition Codes
  34
  35 Check for zero
  36
  37 CCZ:  EQ          NE           NE          NE
  38 CCZ1: EQ          NE                                  (CS)
  39
  40 Unsigned compares
  41
  42 CCU:  EQ          LTU          GTU         NE         (CLG/R, CL/R/Y, CLM/Y, CLI/Y)
  43 CCUR: EQ          GTU          LTU         NE         (CLGF/R)
  44
  45 Signed compares
  46
  47 CCS:  EQ          LT           GT          UNORDERED  (LTGFR, LTGR, LTR, ICM/Y,
  48                                                        LTDBR, LTDR, LTEBR, LTER,
  49                                                        CG/R, C/R/Y, CGHI, CHI,
  50                                                        CDB/R, CD/R, CEB/R, CE/R,
  51                                                        ADB/R, AEB/R, SDB/R, SEB/R,
  52                                                        SRAG, SRA, SRDA)
  53 CCSR: EQ          GT           LT          UNORDERED  (CGF/R, CH/Y)
  54
  55 Condition codes resulting from add with overflow
  56
  57 CCA:  EQ          LT           GT          Overflow
  58 CCAP: EQ          LT           GT          LT         (AGHI, AHI)
  59 CCAN: EQ          LT           GT          GT         (AGHI, AHI)
  60
  61 Condition codes of unsigned adds and subs
  62
  63 CCL:  EQ          NE           EQ          NE         (ALGF/R, ALG/R, AL/R/Y,
  64                                                        ALCG/R, ALC/R,
  65                                                        SLGF/R, SLG/R, SL/R/Y,
  66                                                        SLBG/R, SLB/R)
  67 CCL1: GEU         GEU          LTU         LTU        (ALG/R, AL/R/Y)
  68 CCL2: GTU         GTU          LEU         LEU        (SLG/R, SL/R/Y)
  69 CCL3: EQ          LTU          EQ          GTU        (SLG/R, SL/R/Y)
  70
  71 Test under mask checks
  72
  73 CCT:  EQ          NE           NE          NE         (ICM/Y, TML, CG/R, CGHI,
  74                                                        C/R/Y, CHI, NG/R, N/R/Y,
  75                                                        OG/R, O/R/Y, XG/R, X/R/Y)
  76 CCT1: NE          EQ           NE          NE         (TMH, TML)
  77 CCT2: NE          NE           EQ          NE         (TMH, TML)
  78 CCT3: NE          NE           NE          EQ         (TMH, TML)
  79
  80 CCA and CCT modes are request only modes. These modes are never returned by
  81 s390_select_cc_mode. They are only intended to match other modes.
  82
  83 Requested mode            -> Destination CC register mode
  84
  85 CCS, CCU, CCT, CCSR, CCUR -> CCZ
  86 CCA                       -> CCAP, CCAN
  87
  88
  89 *** Comments ***
  90
  91 CCAP, CCAN
  92
  93 The CC obtained from add instruction usually can't be used for comparisons
  94 because its coupling with overflow flag. In case of an overflow the
  95 less than/greater than data are lost. Nevertheless a comparison can be done
  96 whenever immediate values are involved because they are known at compile time.
  97 If you know whether the used constant is positive or negative you can predict
  98 the sign of the result even in case of an overflow.
  99
 100
 101 CCT, CCT1, CCT2, CCT3
 102
 103 If bits of an integer masked with an AND instruction are checked, the test under
 104 mask instructions turn out to be very handy for a set of special cases.
 105 The simple cases are checks whether all masked bits are zero or ones:
 106
 107   int a;
 108   if ((a & (16 + 128)) == 0)          -> CCT/CCZ
 109   if ((a & (16 + 128)) == 16 + 128)   -> CCT3
 110
 111 Using two extra modes makes it possible to do complete checks on two bits of an
 112 integer (This is possible on register operands only. TM does not provide the
 113 information necessary for CCT1 and CCT2 modes.):
 114
 115   int a;
 116   if ((a & (16 + 128)) == 16)         -> CCT1
 117   if ((a & (16 + 128)) == 128)        -> CCT2
 118
 119
 120 CCSR, CCUR
 121
 122 There are several instructions comparing 32 bit with 64 bit unsigned/signed
 123 values. Such instructions can be considered to have a builtin zero/sign_extend.
 124 The problem is that in the RTL (to be canonical) the zero/sign extended operand
 125 has to be the first one but the machine instructions like it the other way
 126 around. The following both modes can be considered as CCS and CCU modes with
 127 exchanged operands.
 128
 129
 130 CCL1, CCL2
 131
 132 These modes represent the result of overflow checks.
 133
 134 if (a + b < a) -> CCL1 state of the carry bit   (CC2 | CC3)
 135 if (a - b > a) -> CCL2 state of the borrow bit  (CC0 | CC1)
 136
 137 They are used when multi word numbers are computed dealing one SImode part after
 138 another or whenever manual overflow checks like the examples above are
 139 compiled.
 140
 141
 142 CCL3
 143
 144 A logical subtract instruction sets the borrow bit in case of an overflow.
 145 The resulting condition code of those instructions is represented by the
 146 CCL3 mode. Together with the CCU mode this mode is used for jumpless
 147 implementations of several if-constructs - see s390_expand_addcc for more
 148 details.
 149
 150 CCZ1
 151
 152 The compare and swap instructions sets the condition code to 0/1 if the
 153 operands were equal/unequal. The CCZ1 mode ensures the result can be
 154 effectively placed into a register.
 155
 156 */
 157
 158
 159 CC_MODE (CCZ);
 160 CC_MODE (CCZ1);
 161 CC_MODE (CCA);
 162 CC_MODE (CCAP);
 163 CC_MODE (CCAN);
 164 CC_MODE (CCL);
 165 CC_MODE (CCL1);
 166 CC_MODE (CCL2);
 167 CC_MODE (CCL3);
 168 CC_MODE (CCU);
 169 CC_MODE (CCUR);
 170 CC_MODE (CCS);
 171 CC_MODE (CCSR);
 172 CC_MODE (CCT);
 173 CC_MODE (CCT1);
 174 CC_MODE (CCT2);
 175 CC_MODE (CCT3);