gnu/dist/gcc4/gcc/config/sh/crt1.asm

   1 /* Copyright (C) 2000, 2001, 2003, 2004, 2005 Free Software Foundation, Inc.
   2    This file was pretty much copied from newlib.
   3
   4 This file is part of GCC.
   5
   6 GCC is free software; you can redistribute it and/or modify it
   7 under the terms of the GNU General Public License as published by the
   8 Free Software Foundation; either version 2, or (at your option) any
   9 later version.
  10
  11 In addition to the permissions in the GNU General Public License, the
  12 Free Software Foundation gives you unlimited permission to link the
  13 compiled version of this file into combinations with other programs,
  14 and to distribute those combinations without any restriction coming
  15 from the use of this file.  (The General Public License restrictions
  16 do apply in other respects; for example, they cover modification of
  17 the file, and distribution when not linked into a combine
  18 executable.)
  19
  20 GCC is distributed in the hope that it will be useful,
  21 but WITHOUT ANY WARRANTY; without even the implied warranty of
  22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  23 General Public License for more details.
  24
  25 You should have received a copy of the GNU General Public License
  26 along with this program; see the file COPYING.  If not, write to
  27 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
  28 Boston, MA 02110-1301, USA.  */
  29
  30 #ifdef MMU_SUPPORT
  31         /* Section used for exception/timer interrupt stack area */
  32         .section .data.vbr.stack,"aw"
  33         .align 4
  34         .global __ST_VBR
  35 __ST_VBR:
  36         .zero 1024 * 2          /* ; 2k for VBR handlers */
  37 /* Label at the highest stack address where the stack grows from */
  38 __timer_stack:
  39 #endif /* MMU_SUPPORT */
  40
  41         /* ;----------------------------------------
  42         Normal newlib crt1.asm */
  43
  44 #ifdef __SH5__
  45         .section .data,"aw"
  46         .global ___data
  47 ___data:
  48
  49         .section .rodata,"a"
  50         .global ___rodata
  51 ___rodata:
  52
  53 #define ICCR_BASE  0x01600000
  54 #define OCCR_BASE  0x01e00000
  55 #define MMUIR_BASE 0x00000000
  56 #define MMUDR_BASE 0x00800000
  57
  58 #define PTE_ENABLED     1
  59 #define PTE_DISABLED    0
  60
  61 #define PTE_SHARED (1 << 1)
  62 #define PTE_NOT_SHARED  0
  63
  64 #define PTE_CB_UNCACHEABLE  0
  65 #define PTE_CB_DEVICE       1
  66 #define PTE_CB_CACHEABLE_WB 2
  67 #define PTE_CB_CACHEABLE_WT 3
  68
  69 #define PTE_SZ_4KB   (0 << 3)
  70 #define PTE_SZ_64KB  (1 << 3)
  71 #define PTE_SZ_1MB   (2 << 3)
  72 #define PTE_SZ_512MB (3 << 3)
  73
  74 #define PTE_PRR      (1 << 6)
  75 #define PTE_PRX      (1 << 7)
  76 #define PTE_PRW      (1 << 8)
  77 #define PTE_PRU      (1 << 9)
  78
  79 #define SR_MMU_BIT          31
  80 #define SR_BL_BIT           28
  81
  82 #define ALIGN_4KB  (0xfff)
  83 #define ALIGN_1MB  (0xfffff)
  84 #define ALIGN_512MB (0x1fffffff)
  85
  86 #define DYNACON_BASE               0x0f000000
  87 #define DM_CB_DLINK_BASE           0x0c000000
  88 #define DM_DB_DLINK_BASE           0x0b000000
  89
  90 #define FEMI_AREA_0                0x00000000
  91 #define FEMI_AREA_1                0x04000000
  92 #define FEMI_AREA_2                0x05000000
  93 #define FEMI_AREA_3                0x06000000
  94 #define FEMI_AREA_4                0x07000000
  95 #define FEMI_CB                    0x08000000
  96
  97 #define EMI_BASE                   0X80000000
  98
  99 #define DMA_BASE                   0X0e000000
 100
 101 #define CPU_BASE                   0X0d000000
 102
 103 #define PERIPH_BASE                0X09000000
 104 #define DMAC_BASE                  0x0e000000
 105 #define INTC_BASE                  0x0a000000
 106 #define CPRC_BASE                  0x0a010000
 107 #define TMU_BASE                   0x0a020000
 108 #define SCIF_BASE                  0x0a030000
 109 #define RTC_BASE                   0x0a040000
 110
 111
 112
 113 #define LOAD_CONST32(val, reg) \
 114         movi    ((val) >> 16) & 65535, reg; \
 115         shori   (val) & 65535, reg
 116
 117 #define LOAD_PTEH_VAL(sym, align, bits, scratch_reg, reg) \
 118         LOAD_ADDR (sym, reg); \
 119         LOAD_CONST32 ((align), scratch_reg); \
 120         andc    reg, scratch_reg, reg; \
 121         LOAD_CONST32 ((bits), scratch_reg); \
 122         or      reg, scratch_reg, reg
 123
 124 #define LOAD_PTEL_VAL(sym, align, bits, scratch_reg, reg) \
 125         LOAD_ADDR (sym, reg); \
 126         LOAD_CONST32 ((align), scratch_reg); \
 127         andc    reg, scratch_reg, reg; \
 128         LOAD_CONST32 ((bits), scratch_reg); \
 129         or      reg, scratch_reg, reg
 130
 131 #define SET_PTE(pte_addr_reg, pteh_val_reg, ptel_val_reg) \
 132         putcfg  pte_addr_reg, 0, r63; \
 133         putcfg  pte_addr_reg, 1, ptel_val_reg; \
 134         putcfg  pte_addr_reg, 0, pteh_val_reg
 135
 136 #if __SH5__ == 64
 137         .section .text,"ax"
 138 #define LOAD_ADDR(sym, reg) \
 139         movi    (sym >> 48) & 65535, reg; \
 140         shori   (sym >> 32) & 65535, reg; \
 141         shori   (sym >> 16) & 65535, reg; \
 142         shori   sym & 65535, reg
 143 #else
 144         .mode   SHmedia
 145         .section .text..SHmedia32,"ax"
 146 #define LOAD_ADDR(sym, reg) \
 147         movi    (sym >> 16) & 65535, reg; \
 148         shori   sym & 65535, reg
 149 #endif
 150         .global start
 151 start:
 152         LOAD_ADDR (_stack, r15)
 153
 154 #ifdef MMU_SUPPORT
 155         ! Set up the VM using the MMU and caches
 156
 157         ! .vm_ep is first instruction to execute
 158         ! after VM initialization
 159         pt/l    .vm_ep, tr1
 160
 161         ! Configure instruction cache (ICCR)
 162         movi    3, r2
 163         movi    0, r3
 164         LOAD_ADDR (ICCR_BASE, r1)
 165         putcfg  r1, 0, r2
 166         putcfg  r1, 1, r3
 167
 168         ! movi  7, r2 ! write through
 169         ! Configure operand cache (OCCR)
 170         LOAD_ADDR (OCCR_BASE, r1)
 171         putcfg  r1, 0, r2
 172         putcfg  r1, 1, r3
 173
 174         ! Disable all PTE translations
 175         LOAD_ADDR (MMUIR_BASE, r1)
 176         LOAD_ADDR (MMUDR_BASE, r2)
 177         movi    64, r3
 178         pt/l    .disable_ptes_loop, tr0
 179 .disable_ptes_loop:
 180         putcfg  r1, 0, r63
 181         putcfg  r2, 0, r63
 182         addi    r1, 16, r1
 183         addi    r2, 16, r2
 184         addi    r3, -1, r3
 185         bgt     r3, r63, tr0
 186
 187         LOAD_ADDR (MMUIR_BASE, r1)
 188
 189         ! FEMI instruction mappings
 190         !   Area 0 - 1Mb cacheable at 0x00000000
 191         !   Area 1 - None
 192         !   Area 2 - 1Mb cacheable at 0x05000000
 193         !          - 1Mb cacheable at 0x05100000
 194         !   Area 3 - None
 195         !   Area 4 - None
 196
 197         ! Map a 1Mb page for instructions at 0x00000000
 198         LOAD_PTEH_VAL (FEMI_AREA_0, ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 199         LOAD_PTEL_VAL (FEMI_AREA_0, ALIGN_1MB, PTE_CB_CACHEABLE_WB | PTE_SZ_1MB | PTE_PRX | PTE_PRU, r25, r3)
 200         SET_PTE (r1, r2, r3)
 201
 202         ! Map a 1Mb page for instructions at 0x05000000
 203         addi    r1, 16, r1
 204         LOAD_PTEH_VAL (FEMI_AREA_2, ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 205         LOAD_PTEL_VAL (FEMI_AREA_2, ALIGN_1MB, PTE_CB_CACHEABLE_WB | PTE_SZ_1MB | PTE_PRX | PTE_PRU, r25, r3)
 206         SET_PTE (r1, r2, r3)
 207
 208         ! Map a 1Mb page for instructions at 0x05100000
 209         addi    r1, 16, r1
 210         LOAD_PTEH_VAL ((FEMI_AREA_2+0x100000), ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 211         LOAD_PTEL_VAL ((FEMI_AREA_2+0x100000), ALIGN_1MB, PTE_CB_CACHEABLE_WB | PTE_SZ_1MB | PTE_PRX | PTE_PRU, r25, r3)
 212         SET_PTE (r1, r2, r3)
 213
 214         ! Map a 512M page for instructions at EMI base
 215         addi    r1, 16, r1
 216         LOAD_PTEH_VAL (EMI_BASE, ALIGN_512MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 217         LOAD_PTEL_VAL (EMI_BASE, ALIGN_512MB, PTE_CB_CACHEABLE_WB | PTE_SZ_512MB | PTE_PRX | PTE_PRU, r25, r3)
 218         SET_PTE (r1, r2, r3)
 219
 220         ! Map a 4K page for instructions at DM_DB_DLINK_BASE
 221         addi    r1, 16, r1
 222         LOAD_PTEH_VAL (DM_DB_DLINK_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 223         LOAD_PTEL_VAL (DM_DB_DLINK_BASE, ALIGN_4KB, PTE_CB_CACHEABLE_WB | PTE_SZ_4KB | PTE_PRX | PTE_PRU, r25, r3)
 224         SET_PTE (r1, r2, r3)
 225
 226         LOAD_ADDR (MMUDR_BASE, r1)
 227
 228         ! FEMI data mappings
 229         !   Area 0 - 1Mb cacheable at 0x00000000
 230         !   Area 1 - 1Mb device at 0x04000000
 231         !   Area 2 - 1Mb cacheable at 0x05000000
 232         !          - 1Mb cacheable at 0x05100000
 233         !   Area 3 - None
 234         !   Area 4 - None
 235         !   CB     - 1Mb device at 0x08000000
 236
 237         ! Map a 1Mb page for data at 0x00000000
 238         LOAD_PTEH_VAL (FEMI_AREA_0, ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 239         LOAD_PTEL_VAL (FEMI_AREA_0, ALIGN_1MB, PTE_CB_CACHEABLE_WB | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 240         SET_PTE (r1, r2, r3)
 241
 242         ! Map a 1Mb page for data at 0x04000000
 243         addi    r1, 16, r1
 244         LOAD_PTEH_VAL (FEMI_AREA_1, ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 245         LOAD_PTEL_VAL (FEMI_AREA_1, ALIGN_1MB, PTE_CB_DEVICE | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 246         SET_PTE (r1, r2, r3)
 247
 248         ! Map a 1Mb page for data at 0x05000000
 249         addi    r1, 16, r1
 250         LOAD_PTEH_VAL (FEMI_AREA_2, ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 251         LOAD_PTEL_VAL (FEMI_AREA_2, ALIGN_1MB, PTE_CB_CACHEABLE_WB | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 252         SET_PTE (r1, r2, r3)
 253
 254         ! Map a 1Mb page for data at 0x05100000
 255         addi    r1, 16, r1
 256         LOAD_PTEH_VAL ((FEMI_AREA_2+0x100000), ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 257         LOAD_PTEL_VAL ((FEMI_AREA_2+0x100000), ALIGN_1MB, PTE_CB_CACHEABLE_WB | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 258         SET_PTE (r1, r2, r3)
 259
 260         ! Map a 4K page for registers at 0x08000000
 261         addi    r1, 16, r1
 262         LOAD_PTEH_VAL (FEMI_CB, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 263         LOAD_PTEL_VAL (FEMI_CB, ALIGN_4KB, PTE_CB_DEVICE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 264         SET_PTE (r1, r2, r3)
 265
 266         ! Map a 512M page for data at EMI
 267         addi    r1, 16, r1
 268         LOAD_PTEH_VAL (EMI_BASE, ALIGN_512MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 269         LOAD_PTEL_VAL (EMI_BASE, ALIGN_512MB, PTE_CB_CACHEABLE_WB | PTE_SZ_512MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 270         SET_PTE (r1, r2, r3)
 271
 272         ! Map a 4K page for DYNACON at DYNACON_BASE
 273         addi    r1, 16, r1
 274         LOAD_PTEH_VAL (DYNACON_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 275         LOAD_PTEL_VAL (DYNACON_BASE, ALIGN_4KB, PTE_CB_DEVICE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 276         SET_PTE (r1, r2, r3)
 277
 278         ! Map a 4K page for instructions at DM_DB_DLINK_BASE
 279         addi    r1, 16, r1
 280         LOAD_PTEH_VAL (DM_DB_DLINK_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 281         LOAD_PTEL_VAL (DM_DB_DLINK_BASE, ALIGN_4KB, PTE_CB_CACHEABLE_WB | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 282         SET_PTE (r1, r2, r3)
 283
 284         ! Map a 4K page for data at DM_DB_DLINK_BASE+0x1000
 285         addi    r1, 16, r1
 286         LOAD_PTEH_VAL ((DM_DB_DLINK_BASE+0x1000), ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 287         LOAD_PTEL_VAL ((DM_DB_DLINK_BASE+0x1000), ALIGN_4KB, PTE_CB_UNCACHEABLE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 288         SET_PTE (r1, r2, r3)
 289
 290         ! Map a 4K page for stack DM_DB_DLINK_BASE+0x2000
 291         addi    r1, 16, r1
 292         LOAD_PTEH_VAL ((DM_DB_DLINK_BASE+0x2000), ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 293         LOAD_PTEL_VAL ((DM_DB_DLINK_BASE+0x2000), ALIGN_4KB, PTE_CB_CACHEABLE_WB | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 294         SET_PTE (r1, r2, r3)
 295
 296         ! Map a 1M page for DM_CB_BASE2 at DM_CB_DLINK
 297         ! 0x0c000000 - 0x0c0fffff
 298         addi    r1, 16, r1
 299         LOAD_PTEH_VAL (DM_CB_DLINK_BASE, ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 300         LOAD_PTEL_VAL (DM_CB_DLINK_BASE, ALIGN_1MB, PTE_CB_DEVICE | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 301         SET_PTE (r1, r2, r3)
 302
 303         ! Map a 1M page for DM_CB_BASE2 at DM_CB_DLINK
 304         ! 0x0c100000 - 0x0c1fffff
 305         addi    r1, 16, r1
 306         LOAD_PTEH_VAL ((DM_CB_DLINK_BASE+0x100000), ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 307         LOAD_PTEL_VAL ((DM_CB_DLINK_BASE+0x100000), ALIGN_1MB, PTE_CB_DEVICE | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 308         SET_PTE (r1, r2, r3)
 309
 310         ! Map a 1M page for DM_CB_BASE2 at DM_CB_DLINK
 311         ! 0x0c200000 - 0x0c2fffff
 312         addi    r1, 16, r1
 313         LOAD_PTEH_VAL ((DM_CB_DLINK_BASE+0x200000), ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 314         LOAD_PTEL_VAL ((DM_CB_DLINK_BASE+0x200000), ALIGN_1MB, PTE_CB_DEVICE | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 315         SET_PTE (r1, r2, r3)
 316
 317         ! Map a 1M page for DM_CB_BASE2 at DM_CB_DLINK
 318         ! 0x0c400000 - 0x0c4fffff
 319         addi    r1, 16, r1
 320         LOAD_PTEH_VAL ((DM_CB_DLINK_BASE+0x400000), ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 321         LOAD_PTEL_VAL ((DM_CB_DLINK_BASE+0x400000), ALIGN_1MB, PTE_CB_DEVICE | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 322         SET_PTE (r1, r2, r3)
 323
 324         ! Map a 1M page for DM_CB_BASE2 at DM_CB_DLINK
 325         ! 0x0c800000 - 0x0c8fffff
 326         addi    r1, 16, r1
 327         LOAD_PTEH_VAL ((DM_CB_DLINK_BASE+0x800000), ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 328         LOAD_PTEL_VAL ((DM_CB_DLINK_BASE+0x800000), ALIGN_1MB, PTE_CB_DEVICE | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 329         SET_PTE (r1, r2, r3)
 330
 331         ! Map a 4K page for DMA control registers
 332         addi    r1, 16, r1
 333         LOAD_PTEH_VAL (DMA_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 334         LOAD_PTEL_VAL (DMA_BASE, ALIGN_4KB, PTE_CB_DEVICE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 335         SET_PTE (r1, r2, r3)
 336
 337         ! Map lots of 4K pages for peripherals
 338
 339         ! /* peripheral */
 340         addi    r1, 16, r1
 341         LOAD_PTEH_VAL (PERIPH_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 342         LOAD_PTEL_VAL (PERIPH_BASE, ALIGN_4KB, PTE_CB_DEVICE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 343         SET_PTE (r1, r2, r3)
 344         ! /* dmac */
 345         addi    r1, 16, r1
 346         LOAD_PTEH_VAL (DMAC_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 347         LOAD_PTEL_VAL (DMAC_BASE, ALIGN_4KB, PTE_CB_DEVICE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 348         SET_PTE (r1, r2, r3)
 349         ! /* intc */
 350         addi    r1, 16, r1
 351         LOAD_PTEH_VAL (INTC_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 352         LOAD_PTEL_VAL (INTC_BASE, ALIGN_4KB, PTE_CB_DEVICE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 353         SET_PTE (r1, r2, r3)
 354         ! /* rtc */
 355         addi    r1, 16, r1
 356         LOAD_PTEH_VAL (RTC_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 357         LOAD_PTEL_VAL (RTC_BASE, ALIGN_4KB, PTE_CB_DEVICE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 358         SET_PTE (r1, r2, r3)
 359         ! /* dmac */
 360         addi    r1, 16, r1
 361         LOAD_PTEH_VAL (TMU_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 362         LOAD_PTEL_VAL (TMU_BASE, ALIGN_4KB, PTE_CB_DEVICE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 363         SET_PTE (r1, r2, r3)
 364         ! /* scif */
 365         addi    r1, 16, r1
 366         LOAD_PTEH_VAL (SCIF_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 367         LOAD_PTEL_VAL (SCIF_BASE, ALIGN_4KB, PTE_CB_DEVICE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 368         SET_PTE (r1, r2, r3)
 369         ! /* cprc */
 370         addi    r1, 16, r1
 371         LOAD_PTEH_VAL (CPRC_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 372         LOAD_PTEL_VAL (CPRC_BASE, ALIGN_4KB, PTE_CB_DEVICE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 373         SET_PTE (r1, r2, r3)
 374
 375         ! Map CPU WPC registers
 376         addi    r1, 16, r1
 377         LOAD_PTEH_VAL (CPU_BASE, ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 378         LOAD_PTEL_VAL (CPU_BASE, ALIGN_1MB, PTE_CB_DEVICE | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 379         SET_PTE (r1, r2, r3)
 380         addi    r1, 16, r1
 381
 382         LOAD_PTEH_VAL ((CPU_BASE+0x100000), ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 383         LOAD_PTEL_VAL ((CPU_BASE+0x100000), ALIGN_1MB, PTE_CB_DEVICE | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 384         SET_PTE (r1, r2, r3)
 385
 386         addi    r1, 16, r1
 387         LOAD_PTEH_VAL ((CPU_BASE+0x200000), ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 388         LOAD_PTEL_VAL ((CPU_BASE+0x200000), ALIGN_1MB, PTE_CB_DEVICE | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 389         SET_PTE (r1, r2, r3)
 390
 391         addi    r1, 16, r1
 392         LOAD_PTEH_VAL ((CPU_BASE+0x400000), ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 393         LOAD_PTEL_VAL ((CPU_BASE+0x400000), ALIGN_1MB, PTE_CB_DEVICE | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 394         SET_PTE (r1, r2, r3)
 395
 396         ! Switch over to virtual addressing and enabled cache
 397         getcon  sr, r1
 398         movi    1, r2
 399         shlli   r2, SR_BL_BIT, r2
 400         or      r1, r2, r1
 401         putcon  r1, ssr
 402         getcon  sr, r1
 403         movi    1, r2
 404         shlli   r2, SR_MMU_BIT, r2
 405         or      r1, r2, r1
 406         putcon  r1, ssr
 407         gettr   tr1, r1
 408         putcon  r1, spc
 409         synco
 410         rte
 411
 412         ! VM entry point.  From now on, we are in VM mode.
 413 .vm_ep:
 414
 415         ! Install the trap handler, by seeding vbr with the
 416         ! correct value, and by assigning sr.bl = 0.
 417
 418         LOAD_ADDR (vbr_start, r1)
 419         putcon  r1, vbr
 420         movi    ~(1<<28), r1
 421         getcon  sr, r2
 422         and     r1, r2, r2
 423         putcon  r2, sr
 424 #endif /* MMU_SUPPORT */
 425
 426         pt/l    .Lzero_bss_loop, tr0
 427         pt/l    _init, tr5
 428         pt/l    ___setup_argv_and_call_main, tr6
 429         pt/l    _exit, tr7
 430
 431         ! zero out bss
 432         LOAD_ADDR (_edata, r0)
 433         LOAD_ADDR (_end, r1)
 434 .Lzero_bss_loop:
 435         stx.q   r0, r63, r63
 436         addi    r0, 8, r0
 437         bgt/l   r1, r0, tr0
 438
 439         LOAD_ADDR (___data, r26)
 440         LOAD_ADDR (___rodata, r27)
 441
 442 #ifdef __SH_FPU_ANY__
 443         getcon  sr, r0
 444         ! enable the FP unit, by resetting SR.FD
 445         ! also zero out SR.FR, SR.SZ and SR.PR, as mandated by the ABI
 446         movi    0, r1
 447         shori   0xf000, r1
 448         andc    r0, r1, r0
 449         putcon  r0, sr
 450 #if __SH5__ == 32
 451         pt/l ___set_fpscr, tr0
 452         movi    0, r4
 453         blink   tr0, r18
 454 #endif
 455 #endif
 456
 457         ! arrange for exit to call fini
 458         pt/l    _atexit, tr1
 459         LOAD_ADDR (_fini, r2)
 460         blink   tr1, r18
 461
 462         ! call init
 463         blink   tr5, r18
 464
 465         ! call the mainline
 466         blink   tr6, r18
 467
 468         ! call exit
 469         blink   tr7, r18
 470         ! We should never return from _exit but in case we do we would enter the
 471         ! the following tight loop. This avoids executing any data that might follow.
 472 limbo:
 473         pt/l limbo, tr0
 474         blink tr0, r63
 475
 476 #ifdef MMU_SUPPORT
 477         ! All these traps are handled in the same place.
 478         .balign 256
 479 vbr_start:
 480         pt/l handler, tr0       ! tr0 trashed.
 481         blink tr0, r63
 482         .balign 256
 483 vbr_100:
 484         pt/l handler, tr0       ! tr0 trashed.
 485         blink tr0, r63
 486 vbr_100_end:
 487         .balign 256
 488 vbr_200:
 489         pt/l handler, tr0       ! tr0 trashed.
 490         blink tr0, r63
 491         .balign 256
 492 vbr_300:
 493         pt/l handler, tr0       ! tr0 trashed.
 494         blink tr0, r63
 495         .balign 256
 496 vbr_400:        ! Should be at vbr+0x400
 497 handler:
 498         /* If the trap handler is there call it */
 499         LOAD_ADDR (__superh_trap_handler, r2)
 500         pta chandler,tr2
 501         beq r2, r63, tr2 /* If zero, ie not present branch around to chandler */
 502         /* Now call the trap handler with as much of the context unchanged as possible.
 503            Move trapping address into R18 to make it look like the trap point */
 504         getcon spc, r18
 505         pt/l __superh_trap_handler, tr0
 506         blink tr0, r7
 507 chandler:
 508         getcon  spc, r62
 509         getcon expevt, r2
 510         pt/l    _exit, tr0
 511         blink   tr0, r63
 512
 513         /* Simulated trap handler */
 514         .section        .text..SHmedia32,"ax"
 515 gcc2_compiled.:
 516         .section        .debug_abbrev
 517 .Ldebug_abbrev0:
 518         .section        .text..SHmedia32
 519 .Ltext0:
 520         .section        .debug_info
 521 .Ldebug_info0:
 522         .section        .debug_line
 523 .Ldebug_line0:
 524         .section        .text..SHmedia32,"ax"
 525         .align 5
 526         .global __superh_trap_handler
 527         .type   __superh_trap_handler,@function
 528 __superh_trap_handler:
 529 .LFB1:
 530         ptabs   r18, tr0
 531         addi.l  r15, -8, r15
 532         st.l    r15, 4, r14
 533         addi.l  r15, -8, r15
 534         add.l   r15, r63, r14
 535         st.l    r14, 0, r2
 536          ptabs r7, tr0
 537         addi.l  r14, 8, r14
 538         add.l   r14, r63, r15
 539         ld.l    r15, 4, r14
 540         addi.l  r15, 8, r15
 541         blink   tr0, r63
 542 .LFE1:
 543 .Lfe1:
 544         .size   __superh_trap_handler,.Lfe1-__superh_trap_handler
 545
 546         .section        .text..SHmedia32
 547 .Letext0:
 548
 549         .section        .debug_info
 550         .ualong 0xa7
 551         .uaword 0x2
 552         .ualong .Ldebug_abbrev0
 553         .byte   0x4
 554         .byte   0x1
 555         .ualong .Ldebug_line0
 556         .ualong .Letext0
 557         .ualong .Ltext0
 558         .string "trap_handler.c"
 559
 560         .string "xxxxxxxxxxxxxxxxxxxxxxxxxxxx"
 561
 562         .string "GNU C 2.97-sh5-010522"
 563
 564         .byte   0x1
 565         .byte   0x2
 566         .ualong 0x9a
 567         .byte   0x1
 568         .string "_superh_trap_handler"
 569
 570         .byte   0x1
 571         .byte   0x2
 572         .byte   0x1
 573         .ualong .LFB1
 574         .ualong .LFE1
 575         .byte   0x1
 576         .byte   0x5e
 577         .byte   0x3
 578         .string "trap_reason"
 579
 580         .byte   0x1
 581         .byte   0x1
 582         .ualong 0x9a
 583         .byte   0x2
 584         .byte   0x91
 585         .byte   0x0
 586         .byte   0x0
 587         .byte   0x4
 588         .string "unsigned int"
 589
 590         .byte   0x4
 591         .byte   0x7
 592         .byte   0x0
 593
 594         .section        .debug_abbrev
 595         .byte   0x1
 596         .byte   0x11
 597         .byte   0x1
 598         .byte   0x10
 599         .byte   0x6
 600         .byte   0x12
 601         .byte   0x1
 602         .byte   0x11
 603         .byte   0x1
 604         .byte   0x3
 605         .byte   0x8
 606         .byte   0x1b
 607         .byte   0x8
 608         .byte   0x25
 609         .byte   0x8
 610         .byte   0x13
 611         .byte   0xb
 612         .byte   0,0
 613         .byte   0x2
 614         .byte   0x2e
 615         .byte   0x1
 616         .byte   0x1
 617         .byte   0x13
 618         .byte   0x3f
 619         .byte   0xc
 620         .byte   0x3
 621         .byte   0x8
 622         .byte   0x3a
 623         .byte   0xb
 624         .byte   0x3b
 625         .byte   0xb
 626         .byte   0x27
 627         .byte   0xc
 628         .byte   0x11
 629         .byte   0x1
 630         .byte   0x12
 631         .byte   0x1
 632         .byte   0x40
 633         .byte   0xa
 634         .byte   0,0
 635         .byte   0x3
 636         .byte   0x5
 637         .byte   0x0
 638         .byte   0x3
 639         .byte   0x8
 640         .byte   0x3a
 641         .byte   0xb
 642         .byte   0x3b
 643         .byte   0xb
 644         .byte   0x49
 645         .byte   0x13
 646         .byte   0x2
 647         .byte   0xa
 648         .byte   0,0
 649         .byte   0x4
 650         .byte   0x24
 651         .byte   0x0
 652         .byte   0x3
 653         .byte   0x8
 654         .byte   0xb
 655         .byte   0xb
 656         .byte   0x3e
 657         .byte   0xb
 658         .byte   0,0
 659         .byte   0
 660
 661         .section        .debug_pubnames
 662         .ualong 0x27
 663         .uaword 0x2
 664         .ualong .Ldebug_info0
 665         .ualong 0xab
 666         .ualong 0x5b
 667         .string "_superh_trap_handler"
 668
 669         .ualong 0x0
 670
 671         .section        .debug_aranges
 672         .ualong 0x1c
 673         .uaword 0x2
 674         .ualong .Ldebug_info0
 675         .byte   0x4
 676         .byte   0x0
 677         .uaword 0x0,0
 678         .ualong .Ltext0
 679         .ualong .Letext0-.Ltext0
 680         .ualong 0x0
 681         .ualong 0x0
 682         .ident  "GCC: (GNU) 2.97-sh5-010522"
 683 #endif /* MMU_SUPPORT */
 684 #else /* ! __SH5__ */
 685
 686         ! make a place to keep any previous value of the vbr register
 687         ! this will only have a value if it has been set by redboot (for example)
 688         .section .bss
 689 old_vbr:
 690         .long 0
 691
 692         .section .text
 693         .global start
 694         .import ___rtos_profiler_start_timer
 695         .weak   ___rtos_profiler_start_timer
 696 start:
 697         mov.l   stack_k,r15
 698
 699 #if defined (__SH3__) || (defined (__SH_FPU_ANY__) && ! defined (__SH2A__)) || defined (__SH4_NOFPU__)
 700 #define VBR_SETUP
 701         ! before zeroing the bss ...
 702         ! if the vbr is already set to vbr_start then the program has been restarted
 703         ! (i.e. it is not the first time the program has been run since reset)
 704         ! reset the vbr to its old value before old_vbr (in bss) is wiped
 705         ! this ensures that the later code does not create a circular vbr chain
 706         stc     vbr, r1
 707         mov.l   vbr_start_k, r2
 708         cmp/eq  r1, r2
 709         bf      0f
 710         ! reset the old vbr value
 711         mov.l   old_vbr_k, r1
 712         mov.l   @r1, r2
 713         ldc     r2, vbr
 714 0:
 715 #endif /* VBR_SETUP */
 716
 717         ! zero out bss
 718         mov.l   edata_k,r0
 719         mov.l   end_k,r1
 720         mov     #0,r2
 721 start_l:
 722         mov.l   r2,@r0
 723         add     #4,r0
 724         cmp/ge  r0,r1
 725         bt      start_l
 726
 727 #if defined (__SH_FPU_ANY__)
 728         mov.l set_fpscr_k, r1
 729         mov #4,r4
 730         jsr @r1
 731         shll16 r4       ! Set DN bit (flush denormal inputs to zero)
 732         lds r3,fpscr    ! Switch to default precision
 733 #endif /* defined (__SH_FPU_ANY__) */
 734
 735 #ifdef VBR_SETUP
 736         ! save the existing contents of the vbr
 737         ! there will only be a prior value when using something like redboot
 738         ! otherwise it will be zero
 739         stc     vbr, r1
 740         mov.l   old_vbr_k, r2
 741         mov.l   r1, @r2
 742         ! setup vbr
 743         mov.l   vbr_start_k, r1
 744         ldc     r1,vbr
 745 #endif /* VBR_SETUP */
 746
 747         ! if an rtos is exporting a timer start fn,
 748         ! then pick up an SR which does not enable ints
 749         ! (the rtos will take care of this)
 750         mov.l rtos_start_fn, r0
 751         mov.l sr_initial_bare, r1
 752         tst     r0, r0
 753         bt      set_sr
 754
 755         mov.l sr_initial_rtos, r1
 756
 757 set_sr:
 758         ! Set status register (sr)
 759         ldc     r1, sr
 760
 761         ! arrange for exit to call fini
 762         mov.l   atexit_k,r0
 763         mov.l   fini_k,r4
 764         jsr     @r0
 765         nop
 766
 767         ! call init
 768         mov.l   init_k,r0
 769         jsr     @r0
 770         nop
 771
 772         ! call the mainline
 773         mov.l   main_k,r0
 774         jsr     @r0
 775         nop
 776
 777         ! call exit
 778         mov     r0,r4
 779         mov.l   exit_k,r0
 780         jsr     @r0
 781         nop
 782
 783         .align 2
 784 #if defined (__SH_FPU_ANY__)
 785 set_fpscr_k:
 786         .long   ___set_fpscr
 787 #endif /*  defined (__SH_FPU_ANY__) */
 788
 789 stack_k:
 790         .long   _stack
 791 edata_k:
 792         .long   _edata
 793 end_k:
 794         .long   _end
 795 main_k:
 796         .long   ___setup_argv_and_call_main
 797 exit_k:
 798         .long   _exit
 799 atexit_k:
 800         .long   _atexit
 801 init_k:
 802         .long   _init
 803 fini_k:
 804         .long   _fini
 805 #ifdef VBR_SETUP
 806 old_vbr_k:
 807         .long   old_vbr
 808 vbr_start_k:
 809         .long   vbr_start
 810 #endif /* VBR_SETUP */
 811
 812 sr_initial_rtos:
 813         ! Privileged mode RB 1 BL 0. Keep BL 0 to allow default trap handlers to work.
 814         ! Whether profiling or not, keep interrupts masked,
 815         ! the RTOS will enable these if required.
 816         .long 0x600000f1
 817
 818 rtos_start_fn:
 819         .long ___rtos_profiler_start_timer
 820
 821 sr_initial_bare:
 822         ! Privileged mode RB 1 BL 0. Keep BL 0 to allow default trap handlers to work.
 823         ! Keep interrupts disabled - the application will enable as required.
 824         .long 0x600000f1
 825
 826         ! supplied for backward compatibility only, in case of linking
 827         ! code whose main() was compiled with an older version of GCC.
 828         .global ___main
 829 ___main:
 830         rts
 831         nop
 832 #ifdef VBR_SETUP
 833 ! Exception handlers
 834         .balign 256
 835 vbr_start:
 836         mov.l 2f, r0     ! load the old vbr setting (if any)
 837         mov.l @r0, r0
 838         cmp/eq #0, r0
 839         bf 1f
 840         ! no previous vbr - jump to own generic handler
 841         bra handler
 842         nop
 843 1:      ! there was a previous handler - chain them
 844         jmp @r0
 845         nop
 846         .balign 4
 847 2:
 848         .long old_vbr
 849
 850         .balign 256
 851 vbr_100:
 852         ! Non profiling case.
 853 handler_100:
 854         mov.l 2f, r0     ! load the old vbr setting (if any)
 855         mov.l @r0, r0
 856         cmp/eq #0, r0
 857         bf 1f
 858         ! no previous vbr - jump to own generic handler
 859         bra handler
 860         nop
 861 1:      ! there was a previous handler - chain them
 862         add #0x7f, r0    ! 0x7f
 863         add #0x7f, r0    ! 0xfe
 864         add #0x2, r0     ! add 0x100 without corrupting another register
 865         jmp @r0
 866         nop
 867         .balign 4
 868 2:
 869         .long old_vbr
 870
 871         .balign 256
 872 vbr_200:
 873         mov.l 2f, r0     ! load the old vbr setting (if any)
 874         mov.l @r0, r0
 875         cmp/eq #0, r0
 876         bf 1f
 877         ! no previous vbr - jump to own generic handler
 878         bra handler
 879         nop
 880 1:      ! there was a previous handler - chain them
 881         add #0x7f, r0    ! 0x7f
 882         add #0x7f, r0    ! 0xfe
 883         add #0x7f, r0    ! 0x17d
 884         add #0x7f, r0    ! 0x1fc
 885         add #0x4, r0     ! add 0x200 without corrupting another register
 886         jmp @r0
 887         nop
 888         .balign 4
 889 2:
 890         .long old_vbr
 891
 892         .balign 256
 893 vbr_300:
 894         mov.l 2f, r0     ! load the old vbr setting (if any)
 895         mov.l @r0, r0
 896         cmp/eq #0, r0
 897         bf 1f
 898         ! no previous vbr - jump to own generic handler
 899         bra handler
 900         nop
 901 1:      ! there was a previous handler - chain them
 902         add #0x7f, r0    ! 0x7f
 903         add #0x7f, r0    ! 0xfe
 904         add #0x7f, r0    ! 0x17d
 905         add #0x7f, r0    ! 0x1fc
 906         add #0x7f, r0    ! 0x27b
 907         add #0x7f, r0    ! 0x2fa
 908         add #0x6, r0     ! add 0x300 without corrupting another register
 909         jmp @r0
 910         nop
 911         .balign 4
 912 2:
 913         .long old_vbr
 914
 915         .balign 256
 916 vbr_400:        ! Should be at vbr+0x400
 917         mov.l 2f, r0     ! load the old vbr setting (if any)
 918         mov.l @r0, r0
 919         cmp/eq #0, r0
 920         ! no previous vbr - jump to own generic handler
 921         bt handler
 922         ! there was a previous handler - chain them
 923         add #0x7f, r0    ! 0x7f
 924         add #0x7f, r0    ! 0xfe
 925         add #0x7f, r0    ! 0x17d
 926         add #0x7f, r0    ! 0x1fc
 927         add #0x7f, r0    ! 0x27b
 928         add #0x7f, r0    ! 0x2fa
 929         add #0x7f, r0    ! 0x379
 930         add #0x7f, r0    ! 0x3f8
 931         add #0x8, r0     ! add 0x400 without corrupting another register
 932         jmp @r0
 933         nop
 934         .balign 4
 935 2:
 936         .long old_vbr
 937 handler:
 938         /* If the trap handler is there call it */
 939         mov.l   superh_trap_handler_k, r0
 940         cmp/eq  #0, r0       ! True if zero.
 941         bf 3f
 942         bra   chandler
 943         nop
 944 3:
 945         ! Here handler available, call it.
 946         /* Now call the trap handler with as much of the context unchanged as possible.
 947            Move trapping address into PR to make it look like the trap point */
 948         stc spc, r1
 949         lds r1, pr
 950         mov.l expevt_k, r4
 951         mov.l @r4, r4 ! r4 is value of expevt, first parameter.
 952         mov r1, r5   ! Remember trapping pc.
 953         mov r1, r6   ! Remember trapping pc.
 954         mov.l chandler_k, r1
 955         mov.l superh_trap_handler_k, r2
 956         ! jmp to trap handler to avoid disturbing pr.
 957         jmp @r2
 958         nop
 959
 960         .balign 256
 961 vbr_500:
 962         mov.l 2f, r0     ! load the old vbr setting (if any)
 963         mov.l @r0, r0
 964         cmp/eq #0, r0
 965         ! no previous vbr - jump to own generic handler
 966         bt handler
 967         ! there was a previous handler - chain them
 968         add #0x7f, r0    ! 0x7f
 969         add #0x7f, r0    ! 0xfe
 970         add #0x7f, r0    ! 0x17d
 971         add #0x7f, r0    ! 0x1fc
 972         add #0x7f, r0    ! 0x27b
 973         add #0x7f, r0    ! 0x2fa
 974         add #0x7f, r0    ! 0x379
 975         add #0x7f, r0    ! 0x3f8
 976         add #0x7f, r0    ! 0x477
 977         add #0x7f, r0    ! 0x4f6
 978         add #0xa, r0     ! add 0x500 without corrupting another register
 979         jmp @r0
 980         nop
 981         .balign 4
 982 2:
 983         .long old_vbr
 984
 985         .balign 256
 986 vbr_600:
 987         mov.l 2f, r0     ! load the old vbr setting (if any)
 988         mov.l @r0, r0
 989         cmp/eq #0, r0
 990         ! no previous vbr - jump to own handler
 991         bt chandler
 992         ! there was a previous handler - chain them
 993         add #0x7f, r0    ! 0x7f
 994         add #0x7f, r0    ! 0xfe
 995         add #0x7f, r0    ! 0x17d
 996         add #0x7f, r0    ! 0x1fc
 997         add #0x7f, r0    ! 0x27b
 998         add #0x7f, r0    ! 0x2fa
 999         add #0x7f, r0    ! 0x379
1000         add #0x7f, r0    ! 0x3f8
1001         add #0x7f, r0    ! 0x477
1002         add #0x7f, r0    ! 0x4f6
1003         add #0x7f, r0    ! 0x575
1004         add #0x7f, r0    ! 0x5f4
1005         add #0xc, r0     ! add 0x600 without corrupting another register
1006         jmp @r0
1007         nop
1008         .balign 4
1009 2:
1010         .long old_vbr
1011 chandler:
1012         mov.l expevt_k, r4
1013         mov.l @r4, r4 ! r4 is value of expevt hence making this the return code
1014         mov.l handler_exit_k,r0
1015         jsr   @r0
1016         nop
1017         ! We should never return from _exit but in case we do we would enter the
1018         ! the following tight loop
1019 limbo:
1020         bra limbo
1021         nop
1022         .balign 4
1023 expevt_k:
1024         .long 0xff000024 ! Address of expevt
1025 chandler_k:
1026         .long chandler
1027 superh_trap_handler_k:
1028         .long   __superh_trap_handler
1029 handler_exit_k:
1030         .long _exit
1031         .align 2
1032 ! Simulated compile of trap handler.
1033         .section        .debug_abbrev,"",@progbits
1034 .Ldebug_abbrev0:
1035         .section        .debug_info,"",@progbits
1036 .Ldebug_info0:
1037         .section        .debug_line,"",@progbits
1038 .Ldebug_line0:
1039         .text
1040 .Ltext0:
1041         .align 5
1042         .type   __superh_trap_handler,@function
1043 __superh_trap_handler:
1044 .LFB1:
1045         mov.l   r14,@-r15
1046 .LCFI0:
1047         add     #-4,r15
1048 .LCFI1:
1049         mov     r15,r14
1050 .LCFI2:
1051         mov.l   r4,@r14
1052         lds     r1, pr
1053         add     #4,r14
1054         mov     r14,r15
1055         mov.l   @r15+,r14
1056         rts
1057         nop
1058 .LFE1:
1059 .Lfe1:
1060         .size   __superh_trap_handler,.Lfe1-__superh_trap_handler
1061         .section        .debug_frame,"",@progbits
1062 .Lframe0:
1063         .ualong .LECIE0-.LSCIE0
1064 .LSCIE0:
1065         .ualong 0xffffffff
1066         .byte   0x1
1067         .string ""
1068         .uleb128 0x1
1069         .sleb128 -4
1070         .byte   0x11
1071         .byte   0xc
1072         .uleb128 0xf
1073         .uleb128 0x0
1074         .align 2
1075 .LECIE0:
1076 .LSFDE0:
1077         .ualong .LEFDE0-.LASFDE0
1078 .LASFDE0:
1079         .ualong .Lframe0
1080         .ualong .LFB1
1081         .ualong .LFE1-.LFB1
1082         .byte   0x4
1083         .ualong .LCFI0-.LFB1
1084         .byte   0xe
1085         .uleb128 0x4
1086         .byte   0x4
1087         .ualong .LCFI1-.LCFI0
1088         .byte   0xe
1089         .uleb128 0x8
1090         .byte   0x8e
1091         .uleb128 0x1
1092         .byte   0x4
1093         .ualong .LCFI2-.LCFI1
1094         .byte   0xd
1095         .uleb128 0xe
1096         .align 2
1097 .LEFDE0:
1098         .text
1099 .Letext0:
1100         .section        .debug_info
1101         .ualong 0xb3
1102         .uaword 0x2
1103         .ualong .Ldebug_abbrev0
1104         .byte   0x4
1105         .uleb128 0x1
1106         .ualong .Ldebug_line0
1107         .ualong .Letext0
1108         .ualong .Ltext0
1109         .string "trap_handler.c"
1110         .string "xxxxxxxxxxxxxxxxxxxxxxxxxxxx"
1111         .string "GNU C 3.2 20020529 (experimental)"
1112         .byte   0x1
1113         .uleb128 0x2
1114         .ualong 0xa6
1115         .byte   0x1
1116         .string "_superh_trap_handler"
1117         .byte   0x1
1118         .byte   0x2
1119         .byte   0x1
1120         .ualong .LFB1
1121         .ualong .LFE1
1122         .byte   0x1
1123         .byte   0x5e
1124         .uleb128 0x3
1125         .string "trap_reason"
1126         .byte   0x1
1127         .byte   0x1
1128         .ualong 0xa6
1129         .byte   0x2
1130         .byte   0x91
1131         .sleb128 0
1132         .byte   0x0
1133         .uleb128 0x4
1134         .string "unsigned int"
1135         .byte   0x4
1136         .byte   0x7
1137         .byte   0x0
1138         .section        .debug_abbrev
1139         .uleb128 0x1
1140         .uleb128 0x11
1141         .byte   0x1
1142         .uleb128 0x10
1143         .uleb128 0x6
1144         .uleb128 0x12
1145         .uleb128 0x1
1146         .uleb128 0x11
1147         .uleb128 0x1
1148         .uleb128 0x3
1149         .uleb128 0x8
1150         .uleb128 0x1b
1151         .uleb128 0x8
1152         .uleb128 0x25
1153         .uleb128 0x8
1154         .uleb128 0x13
1155         .uleb128 0xb
1156         .byte   0x0
1157         .byte   0x0
1158         .uleb128 0x2
1159         .uleb128 0x2e
1160         .byte   0x1
1161         .uleb128 0x1
1162         .uleb128 0x13
1163         .uleb128 0x3f
1164         .uleb128 0xc
1165         .uleb128 0x3
1166         .uleb128 0x8
1167         .uleb128 0x3a
1168         .uleb128 0xb
1169         .uleb128 0x3b
1170         .uleb128 0xb
1171         .uleb128 0x27
1172         .uleb128 0xc
1173         .uleb128 0x11
1174         .uleb128 0x1
1175         .uleb128 0x12
1176         .uleb128 0x1
1177         .uleb128 0x40
1178         .uleb128 0xa
1179         .byte   0x0
1180         .byte   0x0
1181         .uleb128 0x3
1182         .uleb128 0x5
1183         .byte   0x0
1184         .uleb128 0x3
1185         .uleb128 0x8
1186         .uleb128 0x3a
1187         .uleb128 0xb
1188         .uleb128 0x3b
1189         .uleb128 0xb
1190         .uleb128 0x49
1191         .uleb128 0x13
1192         .uleb128 0x2
1193         .uleb128 0xa
1194         .byte   0x0
1195         .byte   0x0
1196         .uleb128 0x4
1197         .uleb128 0x24
1198         .byte   0x0
1199         .uleb128 0x3
1200         .uleb128 0x8
1201         .uleb128 0xb
1202         .uleb128 0xb
1203         .uleb128 0x3e
1204         .uleb128 0xb
1205         .byte   0x0
1206         .byte   0x0
1207         .byte   0x0
1208         .section        .debug_pubnames,"",@progbits
1209         .ualong 0x27
1210         .uaword 0x2
1211         .ualong .Ldebug_info0
1212         .ualong 0xb7
1213         .ualong 0x67
1214         .string "_superh_trap_handler"
1215         .ualong 0x0
1216         .section        .debug_aranges,"",@progbits
1217         .ualong 0x1c
1218         .uaword 0x2
1219         .ualong .Ldebug_info0
1220         .byte   0x4
1221         .byte   0x0
1222         .uaword 0x0
1223         .uaword 0x0
1224         .ualong .Ltext0
1225         .ualong .Letext0-.Ltext0
1226         .ualong 0x0
1227         .ualong 0x0
1228 #endif /* VBR_SETUP */
1229 #endif /* ! __SH5__ */