| blob | a79b2c8bd319e62a99e94114b021c90ea4dc11ab |
1 ;; Machine description for GNU compiler, VAX Version
2 ;; Copyright (C) 1987, 1988, 1991, 1994, 1995, 1996, 1998, 1999, 2000, 2001,
3 ;; 2002, 2004, 2005 Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
10 ;; any later version.
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 ;; Boston, MA 02110-1301, USA.
23 ;;- Instruction patterns. When multiple patterns apply,
24 ;;- the first one in the file is chosen.
25 ;;-
26 ;;- See file "rtl.def" for documentation on define_insn, match_*, et al.
27 ;;-
28 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
29 ;;- updates for most instructions.
31 ;; UNSPEC_VOLATILE usage:
33 (define_constants
34 [(VUNSPEC_BLOCKAGE 0) ; `blockage' insn to prevent scheduling across an
35 ; insn in the code.
36 (VUNSPEC_SYNC_ISTREAM 1) ; sequence of insns to sync the I-stream
37 (VAX_AP_REGNUM 12) ; Register 12 contains the argument pointer
38 (VAX_FP_REGNUM 13) ; Register 13 contains the frame pointer
39 (VAX_SP_REGNUM 14) ; Register 14 contains the stack pointer
40 (VAX_PC_REGNUM 15) ; Register 15 contains the program counter
41 ]
42 )
44 ;; Integer modes supported on VAX, with a mapping from machine mode
45 ;; to mnemonic suffix. DImode is always a special case.
46 (define_mode_macro VAXint [QI HI SI])
47 (define_mode_macro VAXintQH [QI HI])
48 (define_mode_macro VAXintQHSD [QI HI SI DI])
49 (define_mode_attr isfx [(QI "b") (HI "w") (SI "l") (DI "q")])
51 ;; Similar for float modes supported on VAX.
52 (define_mode_macro VAXfp [SF DF])
53 (define_mode_attr fsfx [(SF "f") (DF "%#")])
55 ;; Some output patterns want integer immediates with a prefix...
56 (define_mode_attr iprefx [(QI "B") (HI "H") (SI "N")])
58 ;;
59 (include "predicates.md")
61 ;; We don't want to allow a constant operand for test insns because
62 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
63 ;; be folded while optimizing anyway.
65 (define_insn "tst<mode>"
66 [(set (cc0)
67 (match_operand:VAXint 0 "nonimmediate_operand" "nrmT"))]
68 ""
69 "tst<VAXint:isfx> %0")
71 (define_insn "tst<mode>"
72 [(set (cc0)
73 (match_operand:VAXfp 0 "general_operand" "gF"))]
74 ""
75 "tst<VAXfp:fsfx> %0")
77 (define_insn "cmp<mode>"
78 [(set (cc0)
79 (compare (match_operand:VAXint 0 "nonimmediate_operand" "nrmT")
80 (match_operand:VAXint 1 "general_operand" "nrmT")))]
81 ""
82 "cmp<VAXint:isfx> %0,%1")
84 (define_insn "cmp<mode>"
85 [(set (cc0)
86 (compare (match_operand:VAXfp 0 "general_operand" "gF,gF")
87 (match_operand:VAXfp 1 "general_operand" "G,gF")))]
88 ""
89 "@
90 tst<VAXfp:fsfx> %0
91 cmp<VAXfp:fsfx> %0,%1")
93 (define_insn "*bit<mode>"
94 [(set (cc0)
95 (and:VAXint (match_operand:VAXint 0 "general_operand" "nrmT")
96 (match_operand:VAXint 1 "general_operand" "nrmT")))]
97 ""
98 "bit<VAXint:isfx> %0,%1")
100 ;; The VAX has no sCOND insns. It does have add/subtract with carry
101 ;; which could be used to implement the sltu and sgeu patterns. However,
102 ;; to do this properly requires a complete rewrite of the compare insns
103 ;; to keep them together with the sltu/sgeu insns until after the
104 ;; reload pass is complete. The previous implementation didn't do this
105 ;; and has been deleted.
107 \f
108 (define_insn "mov<mode>"
109 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g")
110 (match_operand:VAXfp 1 "general_operand" "G,gF"))]
111 ""
112 "@
113 clr<VAXfp:fsfx> %0
114 mov<VAXfp:fsfx> %1,%0")
116 ;; Some VAXen don't support this instruction.
117 ;;(define_insn "movti"
118 ;; [(set (match_operand:TI 0 "general_operand" "=g")
119 ;; (match_operand:TI 1 "general_operand" "g"))]
120 ;; ""
121 ;; "movh %1,%0")
123 (define_insn "movdi"
124 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
125 (match_operand:DI 1 "general_operand" "g"))]
126 ""
127 "* return vax_output_int_move (insn, operands, DImode);")
129 ;; The VAX move instructions have space-time tradeoffs. On a MicroVAX
130 ;; register-register mov instructions take 3 bytes and 2 CPU cycles. clrl
131 ;; takes 2 bytes and 3 cycles. mov from constant to register takes 2 cycles
132 ;; if the constant is smaller than 4 bytes, 3 cycles for a longword
133 ;; constant. movz, mneg, and mcom are as fast as mov, so movzwl is faster
134 ;; than movl for positive constants that fit in 16 bits but not 6 bits. cvt
135 ;; instructions take 4 cycles. inc takes 3 cycles. The machine description
136 ;; is willing to trade 1 byte for 1 cycle (clrl instead of movl $0; cvtwl
137 ;; instead of movl).
139 ;; Cycle counts for other models may vary (on a VAX 750 they are similar,
140 ;; but on a VAX 9000 most move and add instructions with one constant
141 ;; operand take 1 cycle).
143 ;; Loads of constants between 64 and 128 used to be done with
144 ;; "addl3 $63,#,dst" but this is slower than movzbl and takes as much space.
146 (define_expand "movsi"
147 [(set (match_operand:SI 0 "nonimmediate_operand" "")
148 (match_operand:SI 1 "general_operand" ""))]
149 ""
150 "
151 {
152 #ifdef NO_EXTERNAL_INDIRECT_ADDRESS
153 if (flag_pic
154 && GET_CODE (operands[1]) == CONST
155 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF
156 && !SYMBOL_REF_LOCAL_P (XEXP (XEXP (operands[1], 0), 0)))
157 {
158 rtx symbol_ref = XEXP (XEXP (operands[1], 0), 0);
159 rtx const_int = XEXP (XEXP (operands[1], 0), 1);
160 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
161 #if 0
162 if (reload_in_progress)
163 debug_rtx (temp);
164 emit_insn (gen_movgblsym (temp, symbol_ref));
165 #endif
166 emit_move_insn (temp, symbol_ref);
167 emit_move_insn (operands[0], gen_rtx_PLUS (SImode, temp, const_int));
168 #if 0
169 debug_rtx (operands[1]);
170 #endif
171 DONE;
172 }
173 #endif
174 }")
176 (define_insn "movsi_2"
177 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
178 (match_operand:SI 1 "nonsymbolic_operand" "nrmT"))]
179 ""
180 "* return vax_output_int_move (insn, operands, SImode);")
182 (define_insn "mov<mode>"
183 [(set (match_operand:VAXintQH 0 "nonimmediate_operand" "=g")
184 (match_operand:VAXintQH 1 "general_operand" "g"))]
185 ""
186 "* return vax_output_int_move (insn, operands, <MODE>mode);")
188 (define_insn "movstricthi"
189 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+g"))
190 (match_operand:HI 1 "general_operand" "g"))]
191 ""
192 "*
193 {
194 if (GET_CODE (operands[1]) == CONST_INT)
195 {
196 int i = INTVAL (operands[1]);
197 if (i == 0)
198 return \"clrw %0\";
199 else if ((unsigned int)i < 64)
200 return \"movw %1,%0\";
201 else if ((unsigned int)~i < 64)
202 return \"mcomw %H1,%0\";
203 else if ((unsigned int)i < 256)
204 return \"movzbw %1,%0\";
205 }
206 return \"movw %1,%0\";
207 }")
209 (define_insn "movstrictqi"
210 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+g"))
211 (match_operand:QI 1 "general_operand" "g"))]
212 ""
213 "*
214 {
215 if (GET_CODE (operands[1]) == CONST_INT)
216 {
217 int i = INTVAL (operands[1]);
218 if (i == 0)
219 return \"clrb %0\";
220 else if ((unsigned int)~i < 64)
221 return \"mcomb %B1,%0\";
222 }
223 return \"movb %1,%0\";
224 }")
226 ;; This is here to accept 4 arguments and pass the first 3 along
227 ;; to the movmemhi1 pattern that really does the work.
228 (define_expand "movmemhi"
229 [(set (match_operand:BLK 0 "general_operand" "=g")
230 (match_operand:BLK 1 "general_operand" "g"))
231 (use (match_operand:HI 2 "general_operand" "g"))
232 (match_operand 3 "" "")]
233 ""
234 "
235 {
236 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) <= 48)
237 {
238 emit_insn (gen_movmemsi1_2 (operands[0], operands[1], operands[2]));
239 DONE;
240 }
241 emit_insn (gen_movmemhi1 (operands[0], operands[1], operands[2]));
242 DONE;
243 }")
245 ;; The definition of this insn does not really explain what it does,
246 ;; but it should suffice
247 ;; that anything generated as this insn will be recognized as one
248 ;; and that it won't successfully combine with anything.
250 (define_insn "movmemsi1_2"
251 [(set (match_operand:BLK 0 "memory_operand" "=R")
252 (match_operand:BLK 1 "memory_operand" "R"))
253 (use (match_operand:SI 2 "const_int_operand" "g"))]
254 "INTVAL (operands[2]) <= 48"
255 "* return vax_output_movmemsi (insn, operands);")
257 (define_insn "movmemhi1"
258 [(set (match_operand:BLK 0 "memory_operand" "=o")
259 (match_operand:BLK 1 "memory_operand" "o"))
260 (use (match_operand:HI 2 "general_operand" "g"))
261 (clobber (reg:SI 0))
262 (clobber (reg:SI 1))
263 (clobber (reg:SI 2))
264 (clobber (reg:SI 3))
265 (clobber (reg:SI 4))
266 (clobber (reg:SI 5))]
267 ""
268 "movc3 %2,%1,%0")
269 \f
270 ;; Extension and truncation insns.
272 (define_insn "truncsiqi2"
273 [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
274 (truncate:QI (match_operand:SI 1 "nonimmediate_operand" "nrmT")))]
275 ""
276 "cvtlb %1,%0")
278 (define_insn "truncsihi2"
279 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
280 (truncate:HI (match_operand:SI 1 "nonimmediate_operand" "nrmT")))]
281 ""
282 "cvtlw %1,%0")
284 (define_insn "trunchiqi2"
285 [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
286 (truncate:QI (match_operand:HI 1 "nonimmediate_operand" "g")))]
287 ""
288 "cvtwb %1,%0")
290 (define_insn "extendhisi2"
291 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
292 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
293 ""
294 "cvtwl %1,%0")
296 (define_insn "extendqihi2"
297 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
298 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
299 ""
300 "cvtbw %1,%0")
302 (define_insn "extendqisi2"
303 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
304 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
305 ""
306 "cvtbl %1,%0")
308 (define_insn "extendsfdf2"
309 [(set (match_operand:DF 0 "nonimmediate_operand" "=g")
310 (float_extend:DF (match_operand:SF 1 "general_operand" "gF")))]
311 ""
312 "cvtf%# %1,%0")
314 (define_insn "truncdfsf2"
315 [(set (match_operand:SF 0 "nonimmediate_operand" "=g")
316 (float_truncate:SF (match_operand:DF 1 "general_operand" "gF")))]
317 ""
318 "cvt%#f %1,%0")
320 (define_insn "zero_extendhisi2"
321 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
322 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
323 ""
324 "movzwl %1,%0")
326 (define_insn "zero_extendqihi2"
327 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
328 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
329 ""
330 "movzbw %1,%0")
332 (define_insn "zero_extendqisi2"
333 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
334 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
335 ""
336 "movzbl %1,%0")
337 \f
338 ;; Fix-to-float conversion insns.
340 (define_insn "float<VAXint:mode><VAXfp:mode>2"
341 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g")
342 (float:VAXfp (match_operand:VAXint 1 "nonimmediate_operand" "g")))]
343 ""
344 "cvt<VAXint:isfx><VAXfp:fsfx> %1,%0")
346 ;; Float-to-fix conversion insns.
348 (define_insn "fix_trunc<VAXfp:mode><VAXint:mode>2"
349 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
350 (fix:VAXint (fix:VAXfp (match_operand:VAXfp 1 "general_operand" "gF"))))]
351 ""
352 "cvt<VAXfp:fsfx><VAXint:isfx> %1,%0")
353 \f
354 ;;- All kinds of add instructions.
356 (define_insn "add<mode>3"
357 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g,g")
358 (plus:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF,gF")
359 (match_operand:VAXfp 2 "general_operand" "gF,0,gF")))]
360 ""
361 "@
362 add<VAXfp:fsfx>2 %2,%0
363 add<VAXfp:fsfx>2 %1,%0
364 add<VAXfp:fsfx>3 %1,%2,%0")
366 (define_insn "pushlclsymreg"
367 [(set (match_operand:SI 0 "push_operand" "=g")
368 (plus:SI (match_operand:SI 1 "register_operand" "%r")
369 (match_operand:SI 2 "local_symbolic_operand" "i")))]
370 "flag_pic"
371 "pushab %a2[%1]")
373 (define_insn "pushextsymreg"
374 [(set (match_operand:SI 0 "push_operand" "=g")
375 (plus:SI (match_operand:SI 1 "register_operand" "%r")
376 (match_operand:SI 2 "external_symbolic_operand" "i")))]
377 "flag_pic"
378 "pushab %a2[%1]")
380 (define_insn "movlclsymreg"
381 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
382 (plus:SI (match_operand:SI 1 "register_operand" "%r")
383 (match_operand:SI 2 "local_symbolic_operand" "i")))]
384 "flag_pic"
385 "movab %a2[%1],%0")
387 (define_insn "movextsymreg"
388 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
389 (plus:SI (match_operand:SI 1 "register_operand" "%r")
390 (match_operand:SI 2 "external_symbolic_operand" "i")))]
391 "flag_pic"
392 "movab %a2[%1],%0")
394 (define_insn "add<mode>3"
395 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
396 (plus:VAXint (match_operand:VAXint 1 "general_operand" "nrmT")
397 (match_operand:VAXint 2 "general_operand" "nrmT")))]
398 ""
399 "* return vax_output_int_add (insn, operands, <MODE>mode);")
401 (define_expand "adddi3"
402 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
403 (plus:DI (match_operand:DI 1 "general_operand" "g")
404 (match_operand:DI 2 "general_operand" "g")))]
405 "!reload_in_progress"
406 "vax_expand_addsub_di_operands (operands, PLUS); DONE;")
408 (define_insn "adcdi3"
409 [(set (match_operand:DI 0 "nonimmediate_addsub_di_operand" "=Rr")
410 (plus:DI (match_operand:DI 1 "general_addsub_di_operand" "%0")
411 (match_operand:DI 2 "general_addsub_di_operand" "nRr")))]
412 "TARGET_QMATH"
413 "* return vax_output_int_add (insn, operands, DImode);")
415 ;; The add-with-carry (adwc) instruction only accepts two operands.
416 (define_insn "adddi3_old"
417 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro>,ro>")
418 (plus:DI (match_operand:DI 1 "general_operand" "%0,ro>")
419 (match_operand:DI 2 "general_operand" "Fsro,Fs")))]
420 "!TARGET_QMATH"
421 "* return vax_output_int_add (insn, operands, DImode);")
422 \f
423 ;;- All kinds of subtract instructions.
425 (define_insn "sub<mode>3"
426 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g")
427 (minus:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF")
428 (match_operand:VAXfp 2 "general_operand" "gF,gF")))]
429 ""
430 "@
431 sub<VAXfp:fsfx>2 %2,%0
432 sub<VAXfp:fsfx>3 %2,%1,%0")
434 (define_insn "sub<mode>3"
435 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
436 (minus:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT")
437 (match_operand:VAXint 2 "general_operand" "nrmT,nrmT")))]
438 ""
439 "@
440 sub<VAXint:isfx>2 %2,%0
441 sub<VAXint:isfx>3 %2,%1,%0")
443 (define_expand "subdi3"
444 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
445 (minus:DI (match_operand:DI 1 "general_operand" "g")
446 (match_operand:DI 2 "general_operand" "g")))]
447 "!reload_in_progress"
448 "vax_expand_addsub_di_operands (operands, MINUS); DONE;")
450 (define_insn "sbcdi3"
451 [(set (match_operand:DI 0 "nonimmediate_addsub_di_operand" "=Rr,=Rr")
452 (minus:DI (match_operand:DI 1 "general_addsub_di_operand" "0,I")
453 (match_operand:DI 2 "general_addsub_di_operand" "nRr,Rr")))]
454 "TARGET_QMATH"
455 "* return vax_output_int_subtract (insn, operands, DImode);")
457 ;; The subtract-with-carry (sbwc) instruction only takes two operands.
458 (define_insn "subdi3_old"
459 [(set (match_operand:DI 0 "nonimmediate_operand" "=or>,or>")
460 (minus:DI (match_operand:DI 1 "general_operand" "0,or>")
461 (match_operand:DI 2 "general_operand" "Fsor,Fs")))]
462 "!TARGET_QMATH"
463 "* return vax_output_int_subtract (insn, operands, DImode);")
464 \f
465 ;;- Multiply instructions.
467 (define_insn "mul<mode>3"
468 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g,g")
469 (mult:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF,gF")
470 (match_operand:VAXfp 2 "general_operand" "gF,0,gF")))]
471 ""
472 "@
473 mul<VAXfp:fsfx>2 %2,%0
474 mul<VAXfp:fsfx>2 %1,%0
475 mul<VAXfp:fsfx>3 %1,%2,%0")
477 (define_insn "mul<mode>3"
478 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
479 (mult:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT")
480 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))]
481 ""
482 "@
483 mul<VAXint:isfx>2 %2,%0
484 mul<VAXint:isfx>2 %1,%0
485 mul<VAXint:isfx>3 %1,%2,%0")
487 (define_insn "mulsidi3"
488 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
489 (mult:DI (sign_extend:DI
490 (match_operand:SI 1 "nonimmediate_operand" "nrmT"))
491 (sign_extend:DI
492 (match_operand:SI 2 "nonimmediate_operand" "nrmT"))))]
493 ""
494 "emul %1,%2,$0,%0")
496 (define_insn ""
497 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
498 (plus:DI
499 (mult:DI (sign_extend:DI
500 (match_operand:SI 1 "nonimmediate_operand" "nrmT"))
501 (sign_extend:DI
502 (match_operand:SI 2 "nonimmediate_operand" "nrmT")))
503 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "g"))))]
504 ""
505 "emul %1,%2,%3,%0")
507 ;; 'F' constraint means type CONST_DOUBLE
508 (define_insn ""
509 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
510 (plus:DI
511 (mult:DI (sign_extend:DI
512 (match_operand:SI 1 "nonimmediate_operand" "nrmT"))
513 (sign_extend:DI
514 (match_operand:SI 2 "nonimmediate_operand" "nrmT")))
515 (match_operand:DI 3 "immediate_operand" "F")))]
516 "GET_CODE (operands[3]) == CONST_DOUBLE
517 && CONST_DOUBLE_HIGH (operands[3]) == (CONST_DOUBLE_LOW (operands[3]) >> 31)"
518 "*
519 {
520 if (CONST_DOUBLE_HIGH (operands[3]))
521 operands[3] = GEN_INT (CONST_DOUBLE_LOW (operands[3]));
522 return \"emul %1,%2,%3,%0\";
523 }")
524 \f
525 ;;- Divide instructions.
527 (define_insn "div<mode>3"
528 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g")
529 (div:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF")
530 (match_operand:VAXfp 2 "general_operand" "gF,gF")))]
531 ""
532 "@
533 div<VAXfp:fsfx>2 %2,%0
534 div<VAXfp:fsfx>3 %2,%1,%0")
536 (define_insn "div<mode>3"
537 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
538 (div:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT")
539 (match_operand:VAXint 2 "general_operand" "nrmT,nrmT")))]
540 ""
541 "@
542 div<VAXint:isfx>2 %2,%0
543 div<VAXint:isfx>3 %2,%1,%0")
545 ;This is left out because it is very slow;
546 ;we are better off programming around the "lack" of this insn.
547 ;(define_insn "divmoddisi4"
548 ; [(set (match_operand:SI 0 "general_operand" "=g")
549 ; (div:SI (match_operand:DI 1 "general_operand" "g")
550 ; (match_operand:SI 2 "general_operand" "g")))
551 ; (set (match_operand:SI 3 "general_operand" "=g")
552 ; (mod:SI (match_operand:DI 1 "general_operand" "g")
553 ; (match_operand:SI 2 "general_operand" "g")))]
554 ; ""
555 ; "ediv %2,%1,%0,%3")
556 \f
557 ;; Bit-and on the VAX is done with a clear-bits insn.
558 (define_expand "and<mode>3"
559 [(set (match_operand:VAXint 0 "nonimmediate_operand" "")
560 (and:VAXint (not:VAXint (match_operand:VAXint 1 "general_operand" ""))
561 (match_operand:VAXint 2 "general_operand" "")))]
562 ""
563 "
564 {
565 rtx op1 = operands[1];
567 /* If there is a constant argument, complement that one. */
568 if (GET_CODE (operands[2]) == CONST_INT && GET_CODE (op1) != CONST_INT)
569 {
570 operands[1] = operands[2];
571 operands[2] = op1;
572 op1 = operands[1];
573 }
575 if (GET_CODE (op1) == CONST_INT)
576 operands[1] = GEN_INT (~INTVAL (op1));
577 else
578 operands[1] = expand_unop (<MODE>mode, one_cmpl_optab, op1, 0, 1);
579 }")
581 (define_insn "*and<mode>"
582 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
583 (and:VAXint (not:VAXint (match_operand:VAXint 1 "general_operand" "nrmT,nrmT"))
584 (match_operand:VAXint 2 "general_operand" "0,nrmT")))]
585 ""
586 "@
587 bic<VAXint:isfx>2 %1,%0
588 bic<VAXint:isfx>3 %1,%2,%0")
590 ;; The following used to be needed because constant propagation can
591 ;; create them starting from the bic insn patterns above. This is no
592 ;; longer a problem. However, having these patterns allows optimization
593 ;; opportunities in combine.c.
595 (define_insn "*and<mode>_const_int"
596 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
597 (and:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT")
598 (match_operand:VAXint 2 "const_int_operand" "n,n")))]
599 ""
600 "@
601 bic<VAXint:isfx>2 %<VAXint:iprefx>2,%0
602 bic<VAXint:isfx>3 %<VAXint:iprefx>2,%1,%0")
604 \f
605 ;;- Bit set instructions.
607 (define_insn "ior<mode>3"
608 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
609 (ior:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT")
610 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))]
611 ""
612 "@
613 bis<VAXint:isfx>2 %2,%0
614 bis<VAXint:isfx>2 %1,%0
615 bis<VAXint:isfx>3 %2,%1,%0")
617 ;;- xor instructions.
619 (define_insn "xor<mode>3"
620 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
621 (xor:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT")
622 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))]
623 ""
624 "@
625 xor<VAXint:isfx>2 %2,%0
626 xor<VAXint:isfx>2 %1,%0
627 xor<VAXint:isfx>3 %2,%1,%0")
629 \f
630 (define_insn "neg<mode>2"
631 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g")
632 (neg:VAXfp (match_operand:VAXfp 1 "general_operand" "gF")))]
633 ""
634 "mneg<VAXfp:fsfx> %1,%0")
636 (define_insn "neg<mode>2"
637 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
638 (neg:VAXint (match_operand:VAXint 1 "general_operand" "nrmT")))]
639 ""
640 "mneg<VAXint:isfx> %1,%0")
642 (define_insn "one_cmpl<mode>2"
643 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
644 (not:VAXint (match_operand:VAXint 1 "general_operand" "nrmT")))]
645 ""
646 "mcom<VAXint:isfx> %1,%0")
648 \f
649 ;; Arithmetic right shift on the VAX works by negating the shift count,
650 ;; then emitting a right shift with the shift count negated. This means
651 ;; that all actual shift counts in the RTL will be positive. This
652 ;; prevents converting shifts to ZERO_EXTRACTs with negative positions,
653 ;; which isn't valid.
654 (define_expand "ashrsi3"
655 [(set (match_operand:SI 0 "general_operand" "=g")
656 (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
657 (match_operand:QI 2 "general_operand" "g")))]
658 ""
659 "
660 {
661 if (GET_CODE (operands[2]) != CONST_INT)
662 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
663 }")
665 (define_insn ""
666 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
667 (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT")
668 (match_operand:QI 2 "const_int_operand" "n")))]
669 ""
670 "ashl $%n2,%1,%0")
672 (define_insn ""
673 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
674 (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT")
675 (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
676 ""
677 "ashl %2,%1,%0")
679 (define_insn "ashlsi3"
680 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
681 (ashift:SI (match_operand:SI 1 "general_operand" "nrmT")
682 (match_operand:QI 2 "general_operand" "g")))]
683 ""
684 "*
685 {
686 if (operands[2] == const1_rtx && rtx_equal_p (operands[0], operands[1]))
687 return \"addl2 %0,%0\";
688 if (GET_CODE (operands[1]) == REG
689 && GET_CODE (operands[2]) == CONST_INT)
690 {
691 int i = INTVAL (operands[2]);
692 if (i == 1)
693 return \"addl3 %1,%1,%0\";
694 if (i == 2 && !optimize_size)
695 {
696 if (push_operand (operands[0], SImode))
697 return \"pushal 0[%1]\";
698 return \"moval 0[%1],%0\";
699 }
700 if (i == 3 && !optimize_size)
701 {
702 if (push_operand (operands[0], SImode))
703 return \"pushaq 0[%1]\";
704 return \"movaq 0[%1],%0\";
705 }
706 }
707 return \"ashl %2,%1,%0\";
708 }")
710 ;; Arithmetic right shift on the VAX works by negating the shift count.
711 (define_expand "ashrdi3"
712 [(set (match_operand:DI 0 "general_operand" "=g")
713 (ashiftrt:DI (match_operand:DI 1 "general_operand" "g")
714 (match_operand:QI 2 "general_operand" "g")))]
715 ""
716 "
717 {
718 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
719 }")
721 (define_insn "ashldi3"
722 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
723 (ashift:DI (match_operand:DI 1 "general_operand" "g")
724 (match_operand:QI 2 "general_operand" "g")))]
725 ""
726 "ashq %2,%1,%0")
728 (define_insn ""
729 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
730 (ashiftrt:DI (match_operand:DI 1 "general_operand" "g")
731 (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
732 ""
733 "ashq %2,%1,%0")
735 ;; We used to have expand_shift handle logical right shifts by using extzv,
736 ;; but this make it very difficult to do lshrdi3. Since the VAX is the
737 ;; only machine with this kludge, it's better to just do this with a
738 ;; define_expand and remove that case from expand_shift.
740 (define_expand "lshrsi3"
741 [(set (match_dup 3)
742 (minus:QI (const_int 32)
743 (match_dup 4)))
744 (set (match_operand:SI 0 "nonimmediate_operand" "=g")
745 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
746 (match_dup 3)
747 (match_operand:SI 2 "register_operand" "g")))]
748 ""
749 "
750 {
751 operands[3] = gen_reg_rtx (QImode);
752 operands[4] = gen_lowpart (QImode, operands[2]);
753 }")
755 ;; Rotate right on the VAX works by negating the shift count.
756 (define_expand "rotrsi3"
757 [(set (match_operand:SI 0 "general_operand" "=g")
758 (rotatert:SI (match_operand:SI 1 "general_operand" "g")
759 (match_operand:QI 2 "general_operand" "g")))]
760 ""
761 "
762 {
763 if (GET_CODE (operands[2]) != CONST_INT)
764 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
765 }")
767 (define_insn "rotlsi3"
768 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
769 (rotate:SI (match_operand:SI 1 "general_operand" "nrmT")
770 (match_operand:QI 2 "general_operand" "g")))]
771 ""
772 "rotl %2,%1,%0")
774 (define_insn ""
775 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
776 (rotatert:SI (match_operand:SI 1 "general_operand" "nrmT")
777 (match_operand:QI 2 "const_int_operand" "n")))]
778 ""
779 "rotl %R2,%1,%0")
781 (define_insn ""
782 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
783 (rotatert:SI (match_operand:SI 1 "general_operand" "nrmT")
784 (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
785 ""
786 "rotl %2,%1,%0")
788 ;This insn is probably slower than a multiply and an add.
789 ;(define_insn ""
790 ; [(set (match_operand:SI 0 "general_operand" "=g")
791 ; (mult:SI (plus:SI (match_operand:SI 1 "general_operand" "g")
792 ; (match_operand:SI 2 "general_operand" "g"))
793 ; (match_operand:SI 3 "general_operand" "g")))]
794 ; ""
795 ; "index %1,$0x80000000,$0x7fffffff,%3,%2,%0")
796 \f
797 ;; Special cases of bit-field insns which we should
798 ;; recognize in preference to the general case.
799 ;; These handle aligned 8-bit and 16-bit fields,
800 ;; which can usually be done with move instructions.
802 (define_insn ""
803 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+ro")
804 (match_operand:QI 1 "const_int_operand" "n")
805 (match_operand:SI 2 "const_int_operand" "n"))
806 (match_operand:SI 3 "general_operand" "g"))]
807 "(INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
808 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
809 && (GET_CODE (operands[0]) == REG
810 || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
811 "*
812 {
813 if (REG_P (operands[0]))
814 {
815 if (INTVAL (operands[2]) != 0)
816 return \"insv %3,%2,%1,%0\";
817 }
818 else
819 operands[0]
820 = adjust_address (operands[0],
821 INTVAL (operands[1]) == 8 ? QImode : HImode,
822 INTVAL (operands[2]) / 8);
824 CC_STATUS_INIT;
825 if (INTVAL (operands[1]) == 8)
826 return \"movb %3,%0\";
827 return \"movw %3,%0\";
828 }")
830 (define_insn ""
831 [(set (match_operand:SI 0 "nonimmediate_operand" "=&g")
832 (zero_extract:SI (match_operand:SI 1 "register_operand" "ro")
833 (match_operand:QI 2 "const_int_operand" "n")
834 (match_operand:SI 3 "const_int_operand" "n")))]
835 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
836 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
837 && (GET_CODE (operands[1]) == REG
838 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
839 "*
840 {
841 if (REG_P (operands[1]))
842 {
843 if (INTVAL (operands[3]) != 0)
844 return \"extzv %3,%2,%1,%0\";
845 }
846 else
847 operands[1]
848 = adjust_address (operands[1],
849 INTVAL (operands[2]) == 8 ? QImode : HImode,
850 INTVAL (operands[3]) / 8);
852 if (INTVAL (operands[2]) == 8)
853 return \"movzbl %1,%0\";
854 return \"movzwl %1,%0\";
855 }")
857 (define_insn ""
858 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
859 (sign_extract:SI (match_operand:SI 1 "register_operand" "ro")
860 (match_operand:QI 2 "const_int_operand" "n")
861 (match_operand:SI 3 "const_int_operand" "n")))]
862 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
863 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
864 && (GET_CODE (operands[1]) == REG
865 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
866 "*
867 {
868 if (REG_P (operands[1]))
869 {
870 if (INTVAL (operands[3]) != 0)
871 return \"extv %3,%2,%1,%0\";
872 }
873 else
874 operands[1]
875 = adjust_address (operands[1],
876 INTVAL (operands[2]) == 8 ? QImode : HImode,
877 INTVAL (operands[3]) / 8);
879 if (INTVAL (operands[2]) == 8)
880 return \"cvtbl %1,%0\";
881 return \"cvtwl %1,%0\";
882 }")
883 \f
884 ;; Register-only SImode cases of bit-field insns.
886 (define_insn ""
887 [(set (cc0)
888 (compare
889 (sign_extract:SI (match_operand:SI 0 "register_operand" "r")
890 (match_operand:QI 1 "general_operand" "g")
891 (match_operand:SI 2 "general_operand" "nrmT"))
892 (match_operand:SI 3 "general_operand" "nrmT")))]
893 ""
894 "cmpv %2,%1,%0,%3")
896 (define_insn ""
897 [(set (cc0)
898 (compare
899 (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
900 (match_operand:QI 1 "general_operand" "g")
901 (match_operand:SI 2 "general_operand" "nrmT"))
902 (match_operand:SI 3 "general_operand" "nrmT")))]
903 ""
904 "cmpzv %2,%1,%0,%3")
906 ;; When the field position and size are constant and the destination
907 ;; is a register, extv and extzv are much slower than a rotate followed
908 ;; by a bicl or sign extension. Because we might end up choosing ext[z]v
909 ;; anyway, we can't allow immediate values for the primary source operand.
911 (define_insn ""
912 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
913 (sign_extract:SI (match_operand:SI 1 "register_operand" "ro")
914 (match_operand:QI 2 "general_operand" "g")
915 (match_operand:SI 3 "general_operand" "nrmT")))]
916 ""
917 "*
918 {
919 if (GET_CODE (operands[3]) != CONST_INT || GET_CODE (operands[2]) != CONST_INT
920 || GET_CODE (operands[0]) != REG
921 || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16))
922 return \"extv %3,%2,%1,%0\";
923 if (INTVAL (operands[2]) == 8)
924 return \"rotl %R3,%1,%0\;cvtbl %0,%0\";
925 return \"rotl %R3,%1,%0\;cvtwl %0,%0\";
926 }")
928 (define_insn ""
929 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
930 (zero_extract:SI (match_operand:SI 1 "register_operand" "ro")
931 (match_operand:QI 2 "general_operand" "g")
932 (match_operand:SI 3 "general_operand" "nrmT")))]
933 ""
934 "*
935 {
936 if (GET_CODE (operands[3]) != CONST_INT || GET_CODE (operands[2]) != CONST_INT
937 || GET_CODE (operands[0]) != REG)
938 return \"extzv %3,%2,%1,%0\";
939 if (INTVAL (operands[2]) == 8)
940 return \"rotl %R3,%1,%0\;movzbl %0,%0\";
941 if (INTVAL (operands[2]) == 16)
942 return \"rotl %R3,%1,%0\;movzwl %0,%0\";
943 if (INTVAL (operands[3]) & 31)
944 return \"rotl %R3,%1,%0\;bicl2 %M2,%0\";
945 if (rtx_equal_p (operands[0], operands[1]))
946 return \"bicl2 %M2,%0\";
947 return \"bicl3 %M2,%1,%0\";
948 }")
950 ;; Non-register cases.
951 ;; nonimmediate_operand is used to make sure that mode-ambiguous cases
952 ;; don't match these (and therefore match the cases above instead).
954 (define_insn ""
955 [(set (cc0)
956 (compare
957 (sign_extract:SI (match_operand:QI 0 "memory_operand" "m")
958 (match_operand:QI 1 "general_operand" "g")
959 (match_operand:SI 2 "general_operand" "nrmT"))
960 (match_operand:SI 3 "general_operand" "nrmT")))]
961 ""
962 "cmpv %2,%1,%0,%3")
964 (define_insn ""
965 [(set (cc0)
966 (compare
967 (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rm")
968 (match_operand:QI 1 "general_operand" "g")
969 (match_operand:SI 2 "general_operand" "nrmT"))
970 (match_operand:SI 3 "general_operand" "nrmT")))]
971 ""
972 "cmpzv %2,%1,%0,%3")
974 (define_insn "extv"
975 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
976 (sign_extract:SI (match_operand:QI 1 "memory_operand" "m")
977 (match_operand:QI 2 "general_operand" "g")
978 (match_operand:SI 3 "general_operand" "nrmT")))]
979 ""
980 "*
981 {
982 if (!REG_P (operands[0]) || !CONST_INT_P (operands[2])
983 || !CONST_INT_P (operands[3])
984 || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16)
985 || INTVAL (operands[2]) + INTVAL (operands[3]) > 32
986 || side_effects_p (operands[1])
987 || (MEM_P (operands[1])
988 && mode_dependent_address_p (XEXP (operands[1], 0))))
989 return \"extv %3,%2,%1,%0\";
990 if (INTVAL (operands[2]) == 8)
991 return \"rotl %R3,%1,%0\;cvtbl %0,%0\";
992 return \"rotl %R3,%1,%0\;cvtwl %0,%0\";
993 }")
995 (define_expand "extzv"
996 [(set (match_operand:SI 0 "general_operand" "")
997 (zero_extract:SI (match_operand:SI 1 "general_operand" "")
998 (match_operand:QI 2 "general_operand" "")
999 (match_operand:SI 3 "general_operand" "")))]
1000 ""
1001 "")
1003 (define_insn ""
1004 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1005 (zero_extract:SI (match_operand:QI 1 "memory_operand" "m")
1006 (match_operand:QI 2 "general_operand" "g")
1007 (match_operand:SI 3 "general_operand" "nrmT")))]
1008 ""
1009 "*
1010 {
1011 if (!REG_P (operands[0]) || !CONST_INT_P (operands[2])
1012 || !CONST_INT_P (operands[3])
1013 || INTVAL (operands[2]) + INTVAL (operands[3]) > 32
1014 || side_effects_p (operands[1])
1015 || (MEM_P (operands[1])
1016 && mode_dependent_address_p (XEXP (operands[1], 0))))
1017 return \"extzv %3,%2,%1,%0\";
1018 if (INTVAL (operands[2]) == 8)
1019 return \"rotl %R3,%1,%0\;movzbl %0,%0\";
1020 if (INTVAL (operands[2]) == 16)
1021 return \"rotl %R3,%1,%0\;movzwl %0,%0\";
1022 if (MEM_P (operands[1])
1023 && GET_CODE (XEXP (operands[1], 0)) == PLUS
1024 && REG_P (XEXP (XEXP (operands[1], 0), 0))
1025 && CONST_INT_P (XEXP (XEXP (operands[1], 0), 1))
1026 && CONST_INT_P (operands[2])
1027 && CONST_INT_P (operands[3]))
1028 {
1029 HOST_WIDE_INT o = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1030 HOST_WIDE_INT l = INTVAL (operands[2]);
1031 HOST_WIDE_INT v = INTVAL (operands[3]);
1032 if ((o & 3) && (o & 3) * 8 + v + l <= 32)
1033 {
1034 rtx tmp;
1035 tmp = XEXP (XEXP (operands[1], 0), 0);
1036 if (o & ~3)
1037 tmp = gen_rtx_PLUS (SImode, tmp, GEN_INT (o & ~3));
1038 operands[1] = gen_rtx_MEM (QImode, tmp);
1039 operands[3] = GEN_INT (v + (o & 3) * 8);
1040 }
1041 if (optimize_size)
1042 return \"extzv %3,%2,%1,%0\";
1043 }
1044 return \"rotl %R3,%1,%0\;bicl2 %M2,%0\";
1045 }")
1047 (define_expand "insv"
1048 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
1049 (match_operand:QI 1 "general_operand" "")
1050 (match_operand:SI 2 "general_operand" ""))
1051 (match_operand:SI 3 "general_operand" ""))]
1052 ""
1053 "")
1055 (define_insn ""
1056 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+g")
1057 (match_operand:QI 1 "general_operand" "g")
1058 (match_operand:SI 2 "general_operand" "nrmT"))
1059 (match_operand:SI 3 "general_operand" "nrmT"))]
1060 ""
1061 "*
1062 {
1063 if (MEM_P (operands[0])
1064 && GET_CODE (XEXP (operands[0], 0)) == PLUS
1065 && REG_P (XEXP (XEXP (operands[0], 0), 0))
1066 && CONST_INT_P (XEXP (XEXP (operands[0], 0), 1))
1067 && CONST_INT_P (operands[1])
1068 && CONST_INT_P (operands[2]))
1069 {
1070 HOST_WIDE_INT o = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1071 HOST_WIDE_INT v = INTVAL (operands[2]);
1072 HOST_WIDE_INT l = INTVAL (operands[1]);
1073 if ((o & 3) && (o & 3) * 8 + v + l <= 32)
1074 {
1075 rtx tmp;
1076 tmp = XEXP (XEXP (operands[0], 0), 0);
1077 if (o & ~3)
1078 tmp = gen_rtx_PLUS (SImode, tmp, GEN_INT (o & ~3));
1079 operands[0] = gen_rtx_MEM (QImode, tmp);
1080 operands[2] = GEN_INT (v + (o & 3) * 8);
1081 }
1082 }
1083 return \"insv %3,%2,%1,%0\";
1084 }")
1086 (define_insn ""
1087 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
1088 (match_operand:QI 1 "general_operand" "g")
1089 (match_operand:SI 2 "general_operand" "nrmT"))
1090 (match_operand:SI 3 "general_operand" "nrmT"))]
1091 ""
1092 "insv %3,%2,%1,%0")
1093 \f
1094 ;; Unconditional jump
1095 (define_insn "jump"
1096 [(set (pc)
1097 (label_ref (match_operand 0 "" "")))]
1098 ""
1099 "jbr %l0")
1101 ;; Conditional jumps
1102 (define_code_macro any_cond [eq ne gt lt gtu ltu ge le geu leu])
1104 (define_insn "b<code>"
1105 [(set (pc)
1106 (if_then_else (any_cond (cc0)
1107 (const_int 0))
1108 (label_ref (match_operand 0 "" ""))
1109 (pc)))]
1110 ""
1111 "* return vax_output_conditional_branch (<CODE>);")
1113 ;; Recognize reversed jumps.
1114 (define_insn ""
1115 [(set (pc)
1116 (if_then_else (match_operator 0 "comparison_operator"
1117 [(cc0)
1118 (const_int 0)])
1119 (pc)
1120 (label_ref (match_operand 1 "" ""))))]
1121 ""
1122 "j%C0 %l1") ; %C0 negates condition
1123 \f
1124 ;; Recognize jbs, jlbs, jbc and jlbc instructions. Note that the operand
1125 ;; of jlbs and jlbc insns are SImode in the hardware. However, if it is
1126 ;; memory, we use QImode in the insn. So we can't use those instructions
1127 ;; for mode-dependent addresses.
1129 (define_insn ""
1130 [(set (pc)
1131 (if_then_else
1132 (ne (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g")
1133 (const_int 1)
1134 (match_operand:SI 1 "general_operand" "I,nrmT"))
1135 (const_int 0))
1136 (label_ref (match_operand 2 "" ""))
1137 (pc)))]
1138 ""
1139 "@
1140 jlbs %0,%l2
1141 jbs %1,%0,%l2")
1143 (define_insn ""
1144 [(set (pc)
1145 (if_then_else
1146 (eq (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g")
1147 (const_int 1)
1148 (match_operand:SI 1 "general_operand" "I,nrmT"))
1149 (const_int 0))
1150 (label_ref (match_operand 2 "" ""))
1151 (pc)))]
1152 ""
1153 "@
1154 jlbc %0,%l2
1155 jbc %1,%0,%l2")
1157 (define_insn ""
1158 [(set (pc)
1159 (if_then_else
1160 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r")
1161 (const_int 1)
1162 (match_operand:SI 1 "general_operand" "I,nrmT"))
1163 (const_int 0))
1164 (label_ref (match_operand 2 "" ""))
1165 (pc)))]
1166 ""
1167 "@
1168 jlbs %0,%l2
1169 jbs %1,%0,%l2")
1171 (define_insn ""
1172 [(set (pc)
1173 (if_then_else
1174 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r")
1175 (const_int 1)
1176 (match_operand:SI 1 "general_operand" "I,nrmT"))
1177 (const_int 0))
1178 (label_ref (match_operand 2 "" ""))
1179 (pc)))]
1180 ""
1181 "@
1182 jlbc %0,%l2
1183 jbc %1,%0,%l2")
1184 \f
1185 ;; Subtract-and-jump and Add-and-jump insns.
1186 ;; These are not used when output is for the Unix assembler
1187 ;; because it does not know how to modify them to reach far.
1189 ;; Normal sob insns.
1191 (define_insn ""
1192 [(set (pc)
1193 (if_then_else
1194 (gt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1195 (const_int -1))
1196 (const_int 0))
1197 (label_ref (match_operand 1 "" ""))
1198 (pc)))
1199 (set (match_dup 0)
1200 (plus:SI (match_dup 0)
1201 (const_int -1)))]
1202 "!TARGET_UNIX_ASM"
1203 "jsobgtr %0,%l1")
1205 (define_insn ""
1206 [(set (pc)
1207 (if_then_else
1208 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1209 (const_int -1))
1210 (const_int 0))
1211 (label_ref (match_operand 1 "" ""))
1212 (pc)))
1213 (set (match_dup 0)
1214 (plus:SI (match_dup 0)
1215 (const_int -1)))]
1216 "!TARGET_UNIX_ASM"
1217 "jsobgeq %0,%l1")
1219 ;; Normal aob insns. Define a version for when operands[1] is a constant.
1220 (define_insn ""
1221 [(set (pc)
1222 (if_then_else
1223 (lt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1224 (const_int 1))
1225 (match_operand:SI 1 "general_operand" "nrmT"))
1226 (label_ref (match_operand 2 "" ""))
1227 (pc)))
1228 (set (match_dup 0)
1229 (plus:SI (match_dup 0)
1230 (const_int 1)))]
1231 "!TARGET_UNIX_ASM"
1232 "jaoblss %1,%0,%l2")
1234 (define_insn ""
1235 [(set (pc)
1236 (if_then_else
1237 (lt (match_operand:SI 0 "nonimmediate_operand" "+g")
1238 (match_operand:SI 1 "general_operand" "nrmT"))
1239 (label_ref (match_operand 2 "" ""))
1240 (pc)))
1241 (set (match_dup 0)
1242 (plus:SI (match_dup 0)
1243 (const_int 1)))]
1244 "!TARGET_UNIX_ASM && GET_CODE (operands[1]) == CONST_INT"
1245 "jaoblss %P1,%0,%l2")
1247 (define_insn ""
1248 [(set (pc)
1249 (if_then_else
1250 (le (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1251 (const_int 1))
1252 (match_operand:SI 1 "general_operand" "nrmT"))
1253 (label_ref (match_operand 2 "" ""))
1254 (pc)))
1255 (set (match_dup 0)
1256 (plus:SI (match_dup 0)
1257 (const_int 1)))]
1258 "!TARGET_UNIX_ASM"
1259 "jaobleq %1,%0,%l2")
1261 (define_insn ""
1262 [(set (pc)
1263 (if_then_else
1264 (le (match_operand:SI 0 "nonimmediate_operand" "+g")
1265 (match_operand:SI 1 "general_operand" "nrmT"))
1266 (label_ref (match_operand 2 "" ""))
1267 (pc)))
1268 (set (match_dup 0)
1269 (plus:SI (match_dup 0)
1270 (const_int 1)))]
1271 "!TARGET_UNIX_ASM && GET_CODE (operands[1]) == CONST_INT"
1272 "jaobleq %P1,%0,%l2")
1274 ;; Something like a sob insn, but compares against -1.
1275 ;; This finds `while (foo--)' which was changed to `while (--foo != -1)'.
1277 (define_insn ""
1278 [(set (pc)
1279 (if_then_else
1280 (ne (match_operand:SI 0 "nonimmediate_operand" "+g")
1281 (const_int 0))
1282 (label_ref (match_operand 1 "" ""))
1283 (pc)))
1284 (set (match_dup 0)
1285 (plus:SI (match_dup 0)
1286 (const_int -1)))]
1287 ""
1288 "decl %0\;jgequ %l1")
1289 \f
1290 (define_expand "call_pop"
1291 [(parallel [(call (match_operand:QI 0 "memory_operand" "")
1292 (match_operand:SI 1 "const_int_operand" ""))
1293 (set (reg:SI VAX_SP_REGNUM)
1294 (plus:SI (reg:SI VAX_SP_REGNUM)
1295 (match_operand:SI 3 "immediate_operand" "")))])]
1296 ""
1297 {
1298 gcc_assert (INTVAL (operands[3]) <= 255 * 4 && INTVAL (operands[3]) % 4 == 0);
1300 /* Operand 1 is the number of bytes to be popped by DW_CFA_GNU_args_size
1301 during EH unwinding. We must include the argument count pushed by
1302 the calls instruction. */
1303 operands[1] = GEN_INT (INTVAL (operands[3]) + 4);
1304 })
1306 (define_insn "*call_pop"
1307 [(call (match_operand:QI 0 "memory_operand" "m")
1308 (match_operand:SI 1 "const_int_operand" "n"))
1309 (set (reg:SI VAX_SP_REGNUM) (plus:SI (reg:SI VAX_SP_REGNUM)
1310 (match_operand:SI 2 "immediate_operand" "i")))]
1311 ""
1312 {
1313 operands[1] = GEN_INT ((INTVAL (operands[1]) - 4) / 4);
1314 return "calls %1,%0";
1315 })
1317 (define_expand "call_value_pop"
1318 [(parallel [(set (match_operand 0 "" "")
1319 (call (match_operand:QI 1 "memory_operand" "")
1320 (match_operand:SI 2 "const_int_operand" "")))
1321 (set (reg:SI VAX_SP_REGNUM)
1322 (plus:SI (reg:SI VAX_SP_REGNUM)
1323 (match_operand:SI 4 "immediate_operand" "")))])]
1324 ""
1325 {
1326 gcc_assert (INTVAL (operands[4]) <= 255 * 4 && INTVAL (operands[4]) % 4 == 0);
1328 /* Operand 2 is the number of bytes to be popped by DW_CFA_GNU_args_size
1329 during EH unwinding. We must include the argument count pushed by
1330 the calls instruction. */
1331 operands[2] = GEN_INT (INTVAL (operands[4]) + 4);
1332 })
1334 (define_insn "*call_value_pop"
1335 [(set (match_operand 0 "" "")
1336 (call (match_operand:QI 1 "memory_operand" "m")
1337 (match_operand:SI 2 "const_int_operand" "n")))
1338 (set (reg:SI VAX_SP_REGNUM) (plus:SI (reg:SI VAX_SP_REGNUM)
1339 (match_operand:SI 3 "immediate_operand" "i")))]
1340 ""
1341 "*
1342 {
1343 operands[2] = GEN_INT ((INTVAL (operands[2]) - 4) / 4);
1344 return \"calls %2,%1\";
1345 }")
1347 (define_expand "call"
1348 [(call (match_operand:QI 0 "memory_operand" "")
1349 (match_operand:SI 1 "const_int_operand" ""))]
1350 ""
1351 "
1352 {
1353 /* Operand 1 is the number of bytes to be popped by DW_CFA_GNU_args_size
1354 during EH unwinding. We must include the argument count pushed by
1355 the calls instruction. */
1356 operands[1] = GEN_INT (INTVAL (operands[1]) + 4);
1357 }")
1359 (define_insn "*call"
1360 [(call (match_operand:QI 0 "memory_operand" "m")
1361 (match_operand:SI 1 "const_int_operand" ""))]
1362 ""
1363 "calls $0,%0")
1365 (define_expand "call_value"
1366 [(set (match_operand 0 "" "")
1367 (call (match_operand:QI 1 "memory_operand" "")
1368 (match_operand:SI 2 "const_int_operand" "")))]
1369 ""
1370 "
1371 {
1372 /* Operand 2 is the number of bytes to be popped by DW_CFA_GNU_args_size
1373 during EH unwinding. We must include the argument count pushed by
1374 the calls instruction. */
1375 operands[2] = GEN_INT (INTVAL (operands[2]) + 4);
1376 }")
1378 (define_insn "*call_value"
1379 [(set (match_operand 0 "" "")
1380 (call (match_operand:QI 1 "memory_operand" "m")
1381 (match_operand:SI 2 "const_int_operand" "")))]
1382 ""
1383 "calls $0,%1")
1385 ;; Call subroutine returning any type.
1387 (define_expand "untyped_call"
1388 [(parallel [(call (match_operand 0 "" "")
1389 (const_int 0))
1390 (match_operand 1 "" "")
1391 (match_operand 2 "" "")])]
1392 ""
1393 "
1394 {
1395 int i;
1397 emit_call_insn (gen_call_pop (operands[0], const0_rtx, NULL, const0_rtx));
1399 for (i = 0; i < XVECLEN (operands[2], 0); i++)
1400 {
1401 rtx set = XVECEXP (operands[2], 0, i);
1402 emit_move_insn (SET_DEST (set), SET_SRC (set));
1403 }
1405 /* The optimizer does not know that the call sets the function value
1406 registers we stored in the result block. We avoid problems by
1407 claiming that all hard registers are used and clobbered at this
1408 point. */
1409 emit_insn (gen_blockage ());
1411 DONE;
1412 }")
1414 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
1415 ;; all of memory. This blocks insns from being moved across this point.
1417 (define_insn "blockage"
1418 [(unspec_volatile [(const_int 0)] VUNSPEC_BLOCKAGE)]
1419 ""
1420 "")
1422 (define_insn "return"
1423 [(return)]
1424 ""
1425 "ret")
1427 (define_expand "epilogue"
1428 [(return)]
1429 ""
1430 "
1431 {
1432 emit_jump_insn (gen_return ());
1433 DONE;
1434 }")
1436 (define_insn "nop"
1437 [(const_int 0)]
1438 ""
1439 "nop")
1441 ;; This had a wider constraint once, and it had trouble.
1442 ;; If you are tempted to try `g', please don't--it's not worth
1443 ;; the risk we will reopen the same bug.
1444 (define_insn "indirect_jump"
1445 [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
1446 ""
1447 "jmp (%0)")
1449 ;; This is here to accept 5 arguments (as passed by expand_end_case)
1450 ;; and pass the first 4 along to the casesi1 pattern that really does
1451 ;; the actual casesi work. We emit a jump here to the default label
1452 ;; _before_ the casesi so that we can be sure that the casesi never
1453 ;; drops through.
1454 ;; This is suboptimal perhaps, but so is much of the rest of this
1455 ;; machine description. For what it's worth, HPPA uses the same trick.
1456 ;;
1457 ;; operand 0 is index
1458 ;; operand 1 is the minimum bound (a const_int)
1459 ;; operand 2 is the maximum bound - minimum bound + 1 (also a const_int)
1460 ;; operand 3 is CODE_LABEL for the table;
1461 ;; operand 4 is the CODE_LABEL to go to if index out of range (ie. default).
1462 ;;
1463 ;; We emit:
1464 ;; i = index - minimum_bound
1465 ;; if (i > (maximum_bound - minimum_bound + 1) goto default;
1466 ;; casesi (i, 0, table);
1467 ;;
1468 (define_expand "casesi"
1469 [(match_operand:SI 0 "general_operand" "")
1470 (match_operand:SI 1 "general_operand" "")
1471 (match_operand:SI 2 "general_operand" "")
1472 (match_operand 3 "" "")
1473 (match_operand 4 "" "")]
1474 ""
1475 {
1476 /* i = index - minimum_bound;
1477 But only if the lower bound is not already zero. */
1478 if (operands[1] != const0_rtx)
1479 {
1480 rtx index = gen_reg_rtx (SImode);
1481 emit_insn (gen_addsi3 (index,
1482 operands[0],
1483 GEN_INT (-INTVAL (operands[1]))));
1484 operands[0] = index;
1485 }
1487 /* if (i > (maximum_bound - minimum_bound + 1) goto default; */
1488 emit_insn (gen_cmpsi (operands[0], operands[2]));
1489 emit_jump_insn (gen_bgtu (operands[4]));
1491 /* casesi (i, 0, table); */
1492 emit_jump_insn (gen_casesi1 (operands[0], operands[2], operands[3]));
1493 DONE;
1494 })
1496 ;; This insn is a bit of a lier. It actually falls through if no case
1497 ;; matches. But, we prevent that from ever happening by emitting a jump
1498 ;; before this, see the define_expand above.
1499 (define_insn "casesi1"
1500 [(match_operand:SI 1 "const_int_operand" "n")
1501 (set (pc)
1502 (plus:SI (sign_extend:SI
1503 (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "general_operand" "nrmT")
1504 (const_int 2))
1505 (pc))))
1506 (label_ref:SI (match_operand 2 "" ""))))]
1507 ""
1508 "casel %0,$0,%1")
1509 \f
1510 (define_insn "pushextsym"
1511 [(set (match_operand:SI 0 "push_operand" "=g")
1512 (match_operand:SI 1 "external_symbolic_operand" "i"))]
1513 ""
1514 "pushab %a1")
1516 (define_insn "movextsym"
1517 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1518 (match_operand:SI 1 "external_symbolic_operand" "i"))]
1519 ""
1520 "movab %a1,%0")
1522 (define_insn "pushlclsym"
1523 [(set (match_operand:SI 0 "push_operand" "=g")
1524 (match_operand:SI 1 "local_symbolic_operand" "i"))]
1525 ""
1526 "pushab %a1")
1528 (define_insn "movlclsym"
1529 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1530 (match_operand:SI 1 "local_symbolic_operand" "i"))]
1531 ""
1532 "movab %a1,%0")
1533 \f
1534 ;;- load or push effective address
1535 ;; These come after the move and add/sub patterns
1536 ;; because we don't want pushl $1 turned into pushad 1.
1537 ;; or addl3 r1,r2,r3 turned into movab 0(r1)[r2],r3.
1539 ;; It does not work to use constraints to distinguish pushes from moves,
1540 ;; because < matches any autodecrement, not just a push.
1542 (define_insn "pushaddr<mode>"
1543 [(set (match_operand:SI 0 "push_operand" "=g")
1544 (match_operand:VAXintQHSD 1 "address_operand" "p"))]
1545 ""
1546 "pusha<VAXintQHSD:isfx> %a1")
1548 (define_insn "movaddr<mode>"
1549 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1550 (match_operand:VAXintQHSD 1 "address_operand" "p"))]
1551 ""
1552 "mova<VAXintQHSD:isfx> %a1,%0")
1554 (define_insn "pushaddr<mode>"
1555 [(set (match_operand:SI 0 "push_operand" "=g")
1556 (match_operand:VAXfp 1 "address_operand" "p"))]
1557 ""
1558 "pusha<VAXfp:fsfx> %a1")
1560 (define_insn "movaddr<mode>"
1561 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1562 (match_operand:VAXfp 1 "address_operand" "p"))]
1563 ""
1564 "mova<VAXfp:fsfx> %a1,%0")
1565 \f
1566 ;; These used to be peepholes, but it is more straightforward to do them
1567 ;; as single insns. However, we must force the output to be a register
1568 ;; if it is not an offsettable address so that we know that we can assign
1569 ;; to it twice.
1571 ;; If we had a good way of evaluating the relative costs, these could be
1572 ;; machine-independent.
1574 ;; Optimize extzv ...,z; andl2 ...,z
1575 ;; or ashl ...,z; andl2 ...,z
1576 ;; with other operands constant. This is what the combiner converts the
1577 ;; above sequences to before attempting to recognize the new insn.
1579 (define_insn ""
1580 [(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
1581 (and:SI (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT")
1582 (match_operand:QI 2 "const_int_operand" "n"))
1583 (match_operand:SI 3 "const_int_operand" "n")))]
1584 "(INTVAL (operands[3]) & ~((1 << (32 - INTVAL (operands[2]))) - 1)) == 0"
1585 "*
1586 {
1587 unsigned long mask1 = INTVAL (operands[3]);
1588 unsigned long mask2 = (1 << (32 - INTVAL (operands[2]))) - 1;
1590 if ((mask1 & mask2) != mask1)
1591 operands[3] = GEN_INT (mask1 & mask2);
1593 return \"rotl %R2,%1,%0\;bicl2 %N3,%0\";
1594 }")
1596 ;; left-shift and mask
1597 ;; The only case where `ashl' is better is if the mask only turns off
1598 ;; bits that the ashl would anyways, in which case it should have been
1599 ;; optimized away.
1601 (define_insn ""
1602 [(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
1603 (and:SI (ashift:SI (match_operand:SI 1 "general_operand" "nrmT")
1604 (match_operand:QI 2 "const_int_operand" "n"))
1605 (match_operand:SI 3 "const_int_operand" "n")))]
1606 ""
1607 "*
1608 {
1609 operands[3]
1610 = GEN_INT (INTVAL (operands[3]) & ~((1 << INTVAL (operands[2])) - 1));
1611 return \"rotl %2,%1,%0\;bicl2 %N3,%0\";
1612 }")
1614 ;; Instruction sequence to sync the VAX instruction stream.
1615 (define_insn "sync_istream"
1616 [(unspec_volatile [(const_int 0)] VUNSPEC_SYNC_ISTREAM)]
1617 ""
1618 "movpsl -(%|sp)\;pushal 1(%|pc)\;rei")
1620 (include "builtins.md")