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1 .\" $NetBSD: cpu.4,v 1.1 2004/09/22 16:38:26 jkunz Exp $
2 .\"
3 .\" $OpenBSD: cpu.4tbl,v 1.19 2004/04/08 16:17:09 mickey Exp $
4 .\"
5 .\" Copyright (c) 2002 Michael Shalayeff
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29 .Dd April 4, 2002
30 .Dt CPU 4 hp700
31 .Os
32 .Sh NAME
33 .Nm cpu
34 .Nd HP PA-RISC CPU
35 .Sh SYNOPSIS
36 .Cd "cpu* at mainbus0 irq 31"
37 .Sh DESCRIPTION
38 The following table lists the
39 .Tn PA-RISC
40 CPU types and their characteristics, such as TLB, maximum
41 cache sizes and
42 .Tn HP 9000/700
43 machines they were used in (see also
44 .Xr intro 4
45 for the reverse list).
46 .Pp
47 .in +\n(dIu
48 .TS
49 .\" tab (:) ;
50 l l l l l l l
51 l l l l l l l
52 l l l l l l l
53 _ _ _ _ _ _ _
54 l l l l l l l .
55 CPU:PA:Clock:Caches:TLB:BTLB:Models
56 : :(max):(max) : : :
57 : : MHz : KB : : :
58 7000:1.1a:66 : 256 L1I:96I:4 I:705,710,720
59 : : : 256 L1D:96D:4 D:730,750
60 7100:1.1b:100:1024 L1I:120:16:715/33/50/75
61 : : :2048 L1D: : :725/50/75
62 : : : : : :{735,755}/100
63 : : : : : :742i, 745i, 747i
64 7150:1.1b:125:1024 L1I:120:16:{735,755}/125
65 : : :2048 L1D: : :
66 7100LC:1.1c:100: 1 L1I:64:8:712/60/80/100
67 : : :1024 L2I: : :715/64/80/100
68 : : :1024 L2D: : :715/100XC
69 : : : : : :725/64/100
70 : : : : : :743i, 748i
71 : : : : : :SAIC
72 7200:1.1d:140: 2 L1 :120:16:C100,C110
73 : : :1024 L2I: : :J200,J210
74 : : :1024 L2D: : :
75 7300LC:1.1e:180: 64 L1I:96:8:A180,A180C
76 : : : 64 L1D: : :B132,B160,B180
77 : : :8192 L2: : :C132L,C160L
78 : : : : : :744, 745, 748
79 : : : : : :RDI PrecisioBook
80 .TE
81 .in -\n(dIu
82 .Sh FLOATING-POINT COPROCESSOR
83 The following table summarizes available floating-point coprocessor
84 models for the 32-bit
85 .Tn PA-RISC
86 processors.
87 .Pp
88 .in +\n(dIu
89 .TS
90 tab (:) ;
91 l l
92 _ _
93 l l .
94 FPU:Model
95 Indigo:
96 Sterling I MIU (TYCO):
97 Sterling I MIU (ROC w/Weitek):
98 FPC (w/Weitek):
99 FPC (w/Bit):
100 Timex-II:
101 Rolex:725/50, 745i
102 HARP-I:
103 Tornado:J2x0,C1x0
104 PA-50 (Hitachi):
105 PCXL:712/60/80/100
106 .TE
107 .in -\n(dIu
108 .Sh SUPERSCALAR EXECUTION
109 The following table summarizes the superscalar execution capabilities
110 of 32-bit
111 .Tn PA-RISC
112 processors.
113 .Pp
114 .in +\n(dIu
115 .TS
116 nokeep tab (:) ;
117 l l l
118 _ _ _
119 l l l .
120 CPU:Units:Bundles
121 7100:1 integer ALU:load-store/fp
122 :1 FP :int/fp
123 : :branch/*
124 7100LC:2 integer ALU:load-store/int
125 :1 FP :load-store/fp
126 : :int/fp
127 : :branch/*
128 7200:2 integer ALU:load-store/int
129 :1 FP :load-store/fp
130 : :int/int
131 : :int/fp
132 : :branch/*
133 7300LC:2 integer ALU:load-store/int
134 :1 FP :load-store/fp
135 : :int/fp
136 : :branch/*
137 .TE
138 .in -\n(dIu
139 .Pp
140 In conclusion, all of the above CPUs are dual-issue, or 2-way superscalar,
141 with the exception that on CPUs with two integer ALUs only one of these
142 units is capable of doing shift, load/store, and test operations.
143 Additionally, there are several kinds of restrictions placed upon the
144 superscalar execution:
145 .Pp
146 For the purpose of showing which instructions are allowed to proceed
147 together through the pipeline, they are divided into classes:
148 .Pp
149 .in +\n(dIu
150 .TS
151 tab (:) ;
152 l l
153 _ _
154 l l .
155 Class:Description
156 flop:floating point operation
157 ldst:loads and stores
158 flex:integer ALU
159 mm:shifts, extracts and deposits
160 nul:might nullify successor
161 bv:BV, BE
162 br:other branches
163 fsys:FTEST and FP status/exception
164 sys:system control instructions
165 .TE
166 .in -\n(dIu
167 .Pp
168 For CPUs with two integer ALUs (7100LC, 7200, 7300LC), the following
169 table lists the instructions which are allowed to be executed
170 concurrently:
171 .Pp
172 .in +\n(dIu
173 .TS
174 tab (:) ;
175 l l
176 _ _
177 l l .
178 First:Second instruction
179 flop: + ldst/flex/mm/nul/bv/br
180 ldst: + flop/flex/mm/nul/br
181 flex: + flop/ldst/flex/mm/nul/br/fsys
182 mm: + flop/ldst/flex/fsys
183 nul: + flop
184 sys: never bundled
185 .TE
186 .in -\n(dIu
187 .Pp
188 ldst + ldst is also possible under certain circumstances, which is then
189 called "double word load/store".
190 .Pp
191 The following restrictions are placed upon the superscalar execution:
192 .Pp
193 .Bl -bullet -compact
194 .It
195 An instruction that modifies a register will not be bundled with another
196 instruction that takes this register as operand.
197 Exception: a flop can be bundled with an FP store of the flop's result register.
198 .It
199 An FP load to one word of a doubleword register will not be bundled with
200 a flop that uses the other doubleword of this register.
201 .It
202 A flop will not be bundled with an FP load if both instructions have the
203 same target register.
204 .It
205 An instruction that could set the carry/borrow bits will not be bundled
206 with an instruction that uses
207 carry/borrow bits.
208 .It
209 An instruction which is in the delay slot of a branch is never bundled
210 with other instructions.
211 .It
212 An instruction which is at an odd word address and executed as a target
213 of a taken branch is never bundled.
214 .It
215 An instruction which might nullify its successor is never bundled with
216 this successor.
217 Only if the successor is a flop instruction is this bundle allowed.
218 .El
219 .Sh PERFORMANCE MONITOR COPROCESSOR
220 The performance monitor coprocessor is an optional,
221 implementation-dependent coprocessor which provides a minimal common
222 software interface to implementation-dependent performance monitor hardware.
223 .Sh DEBUG SPECIAL UNIT
224 The debug special function unit is an optional,
225 architected SFU which provides hardware assistance for software debugging
226 using breakpoints.
227 The debug SFU is currently defined only for Level 0 processors.
228 .Sh SEE ALSO
229 .Xr asp 4 ,
230 .Xr intro 4 ,
231 .Xr lasi 4 ,
232 .Xr mem 4 ,
233 .Xr wax 4 ,
234 .Pa http://www.openpa.net/
235 .Rs
236 .%T PA-RISC 1.1 Architecture and Instruction Set Reference Manual
237 .%A Hewlett-Packard
238 .%D May 15, 1996
239 .Re
240 .Rs
241 .%T PA7100LC ERS
242 .%A Hewlett-Packard
243 .%D March 30 1999
244 .%N Public version 1.0
245 .Re
246 .Rs
247 .%T Design of the PA7200 CPU
248 .%A Hewlett-Packard Journal
249 .%D February 1996
250 .Re
251 .Rs
252 .%T PA7300LC ERS
253 .%A Hewlett-Packard
254 .%D March 18 1996
255 .%N Version 1.0
256 .Re
257 .Sh HISTORY
258 The
259 .Nm
260 driver was written by
261 .An Michael Shalayeff Aq mickey@openbsd.org
262 for the HPPA port for
263 .Ox 2.5 .
264 It was ported to
265 .Nx 1.6
266 by Matthew Fredette.