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1 .\" $NetBSD: pdc.4,v 1.5 2009/03/22 14:29:34 perry Exp $
2 .\"
3 .\" $OpenBSD: pdc.4,v 1.6 2007/06/01 19:54:10 aanriot Exp $
4 .\"
5 .\" Copyright (c) 2004 Michael Shalayeff
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29 .Dd June 1, 2007
30 .Dt PDC 4 hp700
31 .Os
32 .Sh NAME
33 .Nm pdc
34 .Nd Processor-Dependent Code firmware driver
35 .Sh SYNOPSIS
36 .Cd "pdc0 at mainbus?"
37 .Sh DESCRIPTION
38 The
39 .Nm
40 driver provides system console services through the PDC
41 and also a means for calling PDC procedures, described later.
42 The PDC console is used early in the kernel startup before enough kernel
43 subsystems have been initialized to directly use the hardware
44 i.e. serial ports, keyboard, and video.
45 .Pp
46 The PDC version displayed at system boot is relevant to the particular
47 system model and is not necessarily comparable to PDC versions
48 on other systems.
49 .\" TODO page0 description and entry points
50 .Sh PDC PROCEDURES
51 PDC procedure calls are all made through a single entry point
52 and assume normal C language calling conventions, with option
53 number in the first argument and the return data address in the
54 second, unless indicated otherwise.
55 Each call requires at most 7KB of the available stack.
56 Here is the list of procedures and options descriptions:
57 .Bl -tag -width pdc
58 .It Fn pdc "PDC_ADD_VALID" "PDC_ADD_VALID_DFLT" "paddr"
59 Perform a read operation attempt at the physical address
60 .Ar paddr
61 without causing a HPMC, in order to verify that the address is valid
62 and there is a device to respond to it.
63 The implementation may choose to call the caller's HPMC handler and
64 raise error conditions on the bus convertors.
65 .It Fn pdc "PDC_ALLOC" "PDC_ALLOC_DFLT" "ptr" "size"
66 Allocate static storage for IODC use of
67 .Ar size
68 bytes and return the address in a word pointed to by the
69 .Ar ptr
70 argument.
71 There is no way of freeing the storage allocated and thus
72 care shall be taken to not exhaust the total allocation limit of 32KB.
73 .It Fn pdc "PDC_BLOCK_TLB" "PDC_BTLB_DEFAULT" "ptr"
74 Get block TLB parameters into the data area pointed to by the
75 .Ar ptr
76 argument.
77 This includes minimal and maximal entry size and number of fixed and
78 variable sized entries in the block TLB.
79 Fixed entries have size of power of two and are aligned to the size
80 where variable entries can have any size and base address both
81 aligned to a page.
82 .It Fn pdc PDC_BLOCK_TLB PDC_BTLB_INSERT sp va pa len acc slot
83 Insert block TLB entry specified by the space ID
84 .Ar sp ,
85 virtual address
86 .Ar va ,
87 physical address
88 .Ar pa ,
89 region length
90 .Ar len ,
91 access rights
92 .Ar acc ,
93 into the slot number
94 .Ar slot .
95 .It Fn pdc "PDC_BLOCK_TLB" "PDC_BTLB_PURGE" "sp" "va" "slot" "len"
96 Purge one entry from the block TLB specified by the space ID
97 .Ar sp ,
98 virtual address
99 .Ar va ,
100 region length
101 .Ar len ,
102 from slot number
103 .Ar slot .
104 .It Fn pdc "PDC_BLOCK_TLB" "PDC_BTLB_PURGE_ALL"
105 Purge all entries from the block TLB.
106 .\" TODO .It Fn pdc "PDC_BUS_BAD" "PDC_BUS_BAD_DLFT"
107 .It Fn pdc "PDC_CACHE" "PDC_CACHE_DFLT" "ptr"
108 Retrieve cache and TLB configuration parameters into the data area
109 pointed to by the
110 .Ar ptr
111 argument.
112 The format of the data stores is as follows:
113 .Bl -column "0x00" -offset left
114 .It Sy "addr" Ta Sy "contents"
115 .It "0x00" Ta "I-cache size in bytes"
116 .It "0x04" Ta "I-cache configuration"
117 .It "0x08" Ta "I-cache base for flushing"
118 .It "0x0c" Ta "I-cache stride for flushing"
119 .It "0x10" Ta "I-cache count for flushing"
120 .It "0x14" Ta "I-cache loop size for flushing"
121 .It "0x18" Ta "D-cache size in bytes"
122 .It "0x1c" Ta "D-cache configuration"
123 .It "0x20" Ta "D-cache base for flushing"
124 .It "0x24" Ta "D-cache stride for flushing"
125 .It "0x28" Ta "D-cache count for flushing"
126 .It "0x2c" Ta "D-cache loop size for flushing"
127 .It "0x30" Ta "ITLB size"
128 .It "0x34" Ta "ITLB configuration"
129 .It "0x38" Ta "ITLB space base for flushing"
130 .It "0x3c" Ta "ITLB space stride for flushing"
131 .It "0x40" Ta "ITLB space count for flushing"
132 .It "0x44" Ta "ITLB address base for flushing"
133 .It "0x48" Ta "ITLB address stride for flushing"
134 .It "0x4c" Ta "ITLB address count for flushing"
135 .It "0x50" Ta "ITLB loop size for flushing"
136 .It "0x54" Ta "DTLB size"
137 .It "0x58" Ta "DTLB configuration"
138 .It "0x5c" Ta "DTLB space base for flushing"
139 .It "0x60" Ta "DTLB space stride for flushing"
140 .It "0x64" Ta "DTLB space count for flushing"
141 .It "0x68" Ta "DTLB address base for flushing"
142 .It "0x6c" Ta "DTLB address stride for flushing"
143 .It "0x70" Ta "DTLB address count for flushing"
144 .It "0x74" Ta "DTLB loop size for flushing"
145 .El
146 .Pp
147 The cache configuration word is formatted as follows:
148 .Bl -column "bit" "len" -offset left
149 .It Sy "bit" Ta Sy "len" Ta Sy "contents"
150 .It "0" Ta "12" Ta "reserved"
151 .It "13" Ta "3" Ta "set 1 if coherent operation supported"
152 .It "16" Ta "2" Ta "flush mode: 0 -- fdc \*[Am] fic; 1 -- fdc; 2 -- fic; 3 -- either"
153 .It "18" Ta "1" Ta "write-thru D-cache if set"
154 .It "19" Ta "2" Ta "reserved"
155 .It "21" Ta "3" Ta "cache line size"
156 .It "24" Ta "4" Ta "associativity"
157 .It "28" Ta "4" Ta "virtual address alias boundary"
158 .El
159 .Pp
160 .It Fn pdc "PDC_CACHE" "PDC_CACHE_SETCS" "ptr" "i_cst" "d_cst" "it_cst" "dt_cst"
161 The second word in each of the
162 .Ar i_cst ,
163 .Ar d_cst ,
164 .Ar it_cst ,
165 and
166 .Ar dt_cst
167 arguments specifies the desired coherency operation for the instructions cache,
168 data cache, instructions TLB, and data TLB, respectively.
169 The data area pointed to by the
170 .Ar ptr
171 argument receives the actual coherent operation state
172 after an attempted change.
173 The CPU does not support the requested operation change
174 should the corresponding words not match the arguments upon return.
175 The currently supported values are zero for incoherent operation,
176 and one for coherent operation.
177 .It Fn pdc "PDC_CACHE" "PDC_CACHE_GETSPIDB" "ptr"
178 The word pointed to by the
179 .Ar ptr
180 argument receives a mask of space ID used in hashing for cache tag.
181 .It Fn pdc "PDC_CHASSIS" "PDC_CHASSIS_DISP" "display"
182 Update the chassis display with data given in the
183 .Ar display
184 argument.
185 The bitfields in the word are as follows:
186 .Pp
187 .Bl -tag -width 0xfffff -compact
188 .It 0xe0000
189 Specifies the system state.
190 .Bl -tag -width 0xfffff -compact
191 .It 0x00000
192 off
193 .It 0x20000
194 fault
195 .It 0x40000
196 test
197 .It 0x60000
198 initialize
199 .It 0x80000
200 shutdown
201 .It 0xa0000
202 warning
203 .It 0xc0000
204 run
205 .It 0xe0000
206 all on
207 .El
208 .It 0x10000
209 Blank the chassis display.
210 .It 0x0f000
211 This and the other lower three nibbles specify the four hex digits
212 to be displayed on the chassis display.
213 .El
214 .It Fn pdc "PDC_CHASSIS" "PDC_CHASSIS_WARN" "ptr"
215 Return the warnings from the chassis fans, temperature sensors,
216 batteries and power supplies.
217 A word of data is returned in the area pointed by the
218 .Ar ptr
219 argument and is described with bitfields:
220 .Pp
221 .Bl -tag -width 0xff -compact
222 .It 0xff000000
223 Zero means none of the redundant chassis components has indicated any failures.
224 A non-zero value specifies the failing component.
225 .It 0x4
226 Indicates the chassis battery charge is low.
227 .It 0x2
228 The chassis temperature has exceeded the low threshold.
229 .It 0x1
230 The chassis temperature has exceeded the middle threshold.
231 .El
232 .It Fn pdc "PDC_CHASSIS" "PDC_CHASSIS_ALL" "ptr" "display"
233 Both retrieves the chassis warnings into the word pointed by the
234 .Ar ptr
235 argument and sets the chassis display using data in the
236 .Ar display
237 argument.
238 .\" TODO .It Fn pdc "PDC_CONF" "PDC_CONFIG_DECONF" "ptr" "hpa"
239 .\" TODO .It Fn pdc "PDC_CONF" "PDC_CONFIG_RECONF" "ptr" "hpa"
240 .\" TODO .It Fn pdc "PDC_CONF" "PDC_CONFIG_INFO" "ptr" "hpa"
241 .It Fn pdc "PDC_COPROC" "PDC_COPROC_DFLT" "ptr"
242 Identify the coprocessors attached to the CPU.
243 The
244 .Ar ptr
245 points to a memory location where data is to be stored.
246 The first word provides a mask for functional coprocessors and
247 the second word is the mask for all present coprocessors.
248 .It Fn pdc "PDC_DEBUG" "PDC_DEBUG_DFLT" "ptr"
249 Retrieve address of the PDC debugger placed in to the word
250 pointed to by the
251 .Ar ptr
252 argument.
253 .\" TODO .It Fn pdc "PDC_INSTR" "PDC_INSTR_DFLT"
254 .It Fn pdc "PDC_IODC" "PDC_IODC_READ" "ptr" "hpa" "entry" "addr" "count"
255 Given a module
256 .Ar hpa ,
257 retrieve the specified
258 .Ar entry
259 from the module's IODC into a memory area at
260 .Ar adr
261 of
262 .Ar count
263 bytes long at most.
264 The
265 .Ar entry
266 index is a one-byte index, with a value of zero being a special case.
267 For the 0th entry, an IODC header of 16 bytes is returned instead
268 of an actual code.
269 .It Fn pdc "PDC_IODC" "PDC_IODC_NINIT" "ptr" "hpa" "spa"
270 Non-destructively initialize the memory module specified by the
271 .Ar hpa
272 and
273 .Ar spa
274 arguments and return the module status after the init in the first word
275 pointed to by the
276 .Ar ptr
277 argument, followed by the SPA space size and an amount of
278 available memory bytes in the subsequent two words.
279 .It Fn pdc "PDC_IODC" "PDC_IODC_DINIT" "ptr" "hpa" "spa"
280 Same as
281 .Nm PDC_IODC_NINIT
282 except a destructive memory test is performed.
283 .It Fn pdc "PDC_IODC" "PDC_IODC_MEMERR" "ptr" "hpa" "spa"
284 For the memory module that is specified by
285 .Ar hpa
286 and
287 .Ar spa ,
288 return the last most severe error information comprised of copies of
289 IO_STATUS, IO_ERR_RESP, IO_ERR_INFO, and IO_ERR_REQ registers placed
290 into the data area pointed to by the
291 .Ar ptr
292 argument, and clear the error status.
293 .It Fn pdc "PDC_IODC" "PDC_IODC_IMEMMASTER" "ptr" "hpa"
294 HPA for the primary memory module is returned in a word pointed to by the
295 .Ar ptr
296 argument for a memory module specified by
297 .Ar hpa
298 if it's configured as a slave module in an interleave group.
299 .It Fn pdc "PDC_LAN_STATION_ID" "PDC_LAN_STATION_ID_READ" "macptr" "hpa"
300 Retrieve the MAC address for the device at
301 .Ar hpa
302 into the data area pointed to by the
303 .Ar macptr
304 argument.
305 .\" TODO .It Fn pdc "PDC_MEM" "PDC_MEM_INFO" "ptr"
306 .\" TODO .It Fn pdc "PDC_MEM" "PDC_MEM_ADD" "ptr" "PDT"
307 .\" TODO .It Fn pdc "PDC_MEM" "PDC_MEM_CLR" "ptr"
308 .\" TODO .It Fn pdc "PDC_MEM" "PDC_MEM_READ" "ptr" "PDT"
309 .\" TODO .It Fn pdc "PDC_MEM" "PDC_MEM_RSTCLR" "ptr"
310 .\" TODO .It Fn pdc "PDC_MEM" "PDC_MEM_SETGOOD" "ptr" "good"
311 .It Fn pdc "PDC_MEMMAP" "PDC_MEMMAP_HPA." "ptr" "path"
312 Returns device HPA in the word pointed to by the
313 .Ar ptr
314 argument given the device
315 .Ar path
316 pointer.
317 .It Fn pdc "PDC_MODEL" "PDC_MODEL_INFO" "ptr"
318 Returns the System model numbers.
319 .It Fn pdc "PDC_MODEL" "PDC_MODEL_BOOTID" "boot_id"
320 Set BOOT_ID of the processor module (used during boot
321 process of monarch selection) to a word given in the
322 .Ar boot_id
323 argument.
324 .It Fn pdc "PDC_MODEL" "PDC_MODEL_COMP" "ptr" "index"
325 Retrieve processor component versions by issuing this procedure with
326 subsequent indexes in the
327 .Ar index
328 argument starting at zero.
329 The component version number is stored in the word pointed to by
330 the
331 .Ar ptr
332 argument.
333 .It Fn pdc "PDC_MODEL" "PDC_MODEL_MODEL" "ptr" "os_id" "mod_addr"
334 Return a string of 80 chars maximum stored at address
335 .Ar mod_addr
336 and conforming to the OS specified by the
337 .Ar os_id
338 16-bit integer (see
339 .Nm PDC_STABLE
340 for more information on OS ID).
341 A word at the
342 .Ar ptr
343 address receives the result string length.
344 .\" TODO .It Fn pdc "PDC_MODEL" "PDC_MODEL_ENSPEC" "ptr"
345 .\" TODO .It Fn pdc "PDC_MODEL" "PDC_MODEL_DISPEC" "ptr"
346 .It Fn pdc "PDC_MODEL" "PDC_MODEL_CPUID" "ptr"
347 Retrieve CPU model information.
348 A word stored at the address given by the
349 .Ar ptr
350 argument specifies the CPU revision in the lower 5 bits followed by 7 bits
351 of CPU model number.
352 .It Fn pdc "PDC_MODEL" "PDC_MODEL_CPBALITIES" "ptr"
353 Retrieve platform capabilities into the word pointed by the
354 .Ar ptr
355 argument.
356 Bit 0 and 1 specify that a 64- or 32-bit OS is supported, respectively.
357 .It Fn pdc "PDC_MODEL" "PDC_MODEL_GETBOOTOPTS" "ptr"
358 Retrieve the currently enabled, overall supported, and enabled by default
359 boot test masks respectively stored at location pointed to by
360 the
361 .Ar ptr
362 argument.
363 .It Fn pdc "PDC_MODEL" "PDC_MODEL_SETBOOTOPTS" "ptr" "disable" "enable"
364 Disable boot tests specified by mask in the
365 .Ar disable
366 argument and enable
367 boot tests specified by the mask given in the
368 .Ar enable
369 argument.
370 The memory location pointed to by
371 .Ar ptr
372 will contain the resulting masks as returned
373 by the PDC_MODEL_GETBOOTOPTS function.
374 If an attempt is made to enable and disable the same test in one
375 call a PDC_ERR_INVAL will be returned.
376 .It Fn pdc "PDC_NVM" "PDC_NVM_READ" "offset" "ptr" "count"
377 Read contents of the NVM at
378 .Ar offset
379 into the memory area pointed to by the
380 .Ar ptr
381 argument of no more than
382 .Ar count
383 bytes.
384 .Pp
385 The format of the NVM is as follows:
386 .Bl -column "0x0000" "size" "contents" -offset left
387 .It Sy "offset" Ta Sy "size" Ta Sy "contents"
388 .It "0x00" Ta "0x24" Ta "HV dependent"
389 .It "0x24" Ta "0x20" Ta "bootpath"
390 .It "0x44" Ta "0x04" Ta "ISL revision"
391 .It "0x48" Ta "0x04" Ta "timestamp"
392 .It "0x4c" Ta "0x30" Ta "LIF utility entries"
393 .It "0x7c" Ta "0x04" Ta "entry point"
394 .It "0x80" Ta "0x80" Ta "OS panic information"
395 .El
396 .It Fn pdc "PDC_NVM" "PDC_NVM_WRITE" "offset" "ptr" "count"
397 Write data pointed to by the
398 .Ar ptr
399 argument of
400 .Ar count
401 bytes at
402 .Ar address
403 in the NVM.
404 .It Fn pdc "PDC_NVM" "PDC_NVM_SIZE" "ptr"
405 Put the size of Non-Volatile Memory into the word pointed to by the
406 .Ar ptr
407 argument.
408 .It Fn pdc "PDC_NVM" "PDC_NVM_VRFY"
409 Verify that the contents of NVM are valid.
410 .It Fn pdc "PDC_NVM" "PDC_NVM_INIT"
411 Reset the contents of NVM to zeroes without any arguments.
412 .It Fn pdc "PDC_HPA" "PDC_HPA_DFLT" "ptr"
413 The data returned provides the monarch CPUs HPA in the word pointed to by
414 .Ar ptr .
415 .It Fn pdc "PDC_HPA" "PDC_HPA_MODULES" "ptr"
416 Retrieve the bit mask for devices on the CPU bus into the data location
417 pointed to by
418 .Ar ptr .
419 The first word is a bitmask for devices 0-31, and the second is
420 a bitmask for devices 32-63, where bits set to one specify that
421 the corresponding device number is on the same bus as the CPU.
422 .\" TODO .It Fn pdc "PDC_PAT_IO" "PDC_PAT_IO_GET_PCI_RTSZ"
423 .\" TODO .It Fn pdc "PDC_PAT_IO" "PDC_PAT_IO_GET_PCI_RT"
424 .It Fn pdc "PDC_PIM" "PDC_PIM_HPMC" "offset" "ptr" "count"
425 Get HPMC data from
426 .Ar offset
427 in Processor Internal Memory (PIM) into a
428 .Ar ptr
429 memory area of no more than
430 .Ar count
431 bytes in size.
432 Data provided includes (in the order it is copied into the buffer):
433 general registers (r0-r31), control registers (cr0-cr31), space
434 registers (sr0-sr7), IIA space tail, IIA offset tail, check type,
435 CPU state, cache check, TLB check, bus check, assist check, assist
436 state, path info, system responder address, system requestor address,
437 FPU registers (fpr0-fpr31).
438 .It Fn pdc "PDC_PIM" "PDC_PIM_SIZE" "ptr"
439 Return the amount of data available in bytes in the word pointed to by
440 .Ar ptr .
441 .It Fn pdc "PDC_PIM" "PDC_PIM_LPMC" "offset" "ptr" "count"
442 Get LPMC data from
443 .Ar offset
444 in PIM into a
445 .Ar ptr
446 memory area of no more than
447 .Ar count
448 bytes in size.
449 Data provided includes: HV dependent 0x4a words, check type, HV dependent
450 word, cache check, TLB check, bus check, assist check, assist state,
451 path info, system responder address, system requestor address,
452 FPU registers (fpr0-fpr31).
453 .It Fn pdc "PDC_PIM" "PDC_PIM_SBD" "offset" "ptr" "count"
454 Get Soft Boot Data from
455 .Ar offset
456 in PIM into a
457 .Ar ptr
458 memory area of no more than
459 .Ar count
460 bytes in size.
461 Data provided includes: general registers (r0-r31), control registers
462 (cr0-cr31), space registers (sr0-sr7), IIA space tail, IIA offset tail,
463 HV dependent word, CPU state.
464 .It Fn pdc "PDC_PIM" "PDC_PIM_TOC" "offset" "ptr" "count"
465 Get TOC (Transfer Of Control) data from
466 .Ar offset
467 in PIM into a
468 .Ar ptr
469 memory area of no more than
470 .Ar count
471 bytes in size.
472 Data provided includes: general registers (r0-r31), control registers
473 (cr0-cr31), space registers (sr0-sr7), IIA space tail, IIA offset tail,
474 HV dependent word, CPU state.
475 .It Fn pdc "PDC_POW_FAIL" "PDC_POW_FAIL_DFLT"
476 Prepare for power fail.
477 On the machines that provide power failure interrupts, this function is
478 to be called after the operating system has completed
479 .Xr shutdown 8
480 to finish system-dependent tasks and power down.
481 This function only requires 512 bytes of stack.
482 .It Fn pdc "PDC_PROC" "PDC_PROC_STOP"
483 Stop the currently executing processor and also disable bus requestorship,
484 disable interrupts, and exclude the processor from cache coherency protocols.
485 The caller must flush any necessary data from the cache before calling this
486 function.
487 .It Fn pdc "PDC_PROC" "PDC_PROC_RENDEZVOUS"
488 Enter the reset rendezvous code on the current processor.
489 This function is only implemented on category B processors and
490 implementation is optional on category A processors.
491 .It Fn pdc "PDC_PSW" "PDC_PSW_GETMASK" "ptr"
492 Get the mask of default bits implemented into a word pointed to by the
493 .Ar ptr
494 argument.
495 The following mask values are possible:
496 .Pp
497 .Bl -tag -width 100 -compact
498 .It 1
499 Default endianness bit is available.
500 .It 2
501 Default word width bit is available.
502 .El
503 .It Fn pdc "PDC_PSW" "PDC_PSW_DEFAULTS" "ptr"
504 Retrieve the default PSW bits into the word pointed to by the
505 .Ar ptr
506 argument.
507 .It Fn pdc "PDC_PSW" "PDC_PSW_SETDEFAULTS" "bits"
508 Set the default PSW
509 .Ar bits .
510 .It Fn pdc "PDC_SOFT_POWER" "PDC_SOFT_POWER_INFO" "ptr"
511 Retrieve
512 .Dq power
513 register address into the word pointed to by the
514 .Ar ptr
515 argument.
516 Bit-0 in the
517 .Dq power
518 register address being set specifies the power button being depressed.
519 No dampening is required, unlike with the
520 .Xr lasi 4
521 power circuit.
522 .It Fn pdc "PDC_SOFT_POWER" "PDC_SOFT_POWER_ENABLE" "ptr" "stat"
523 Enable (zero
524 .Ar stat )
525 or disable (non-zero
526 .Ar stat )
527 the soft power function,
528 where disable means the machine will turn immediately off
529 should the power get depressed.
530 The
531 .Ar ptr
532 argument still points to the data provided previously
533 by the PDC_SOFT_POWER_INFO call.
534 .It Fn pdc "PDC_STABLE" "PDC_STABLE_READ" "offset" "ptr" "count"
535 Read contents of the
536 .Dq Stable Storage
537 at
538 .Ar offset
539 into the memory area pointed to by the
540 .Ar ptr
541 argument of no more than
542 .Ar count
543 bytes.
544 .Pp
545 The format of the stable storage is as follows:
546 .Bl -column "offset" "0x00" "contents" -offset left
547 .It Sy "offset" Ta Sy "size" Ta Sy "contents"
548 .It "0x0000" Ta "0x20" Ta "primary bootpath"
549 .It "0x0020" Ta "0x20" Ta "reserved"
550 .It "0x0040" Ta "0x02" Ta "OS ID"
551 .It "0x0042" Ta "0x16" Ta "OS dependent"
552 .It "0x0058" Ta "0x02" Ta "diagnostic"
553 .It "0x005a" Ta "0x03" Ta "reserved"
554 .It "0x005d" Ta "0x02" Ta "OS dependent"
555 .It "0x005f" Ta "0x01" Ta "fast size"
556 .It "0x0060" Ta "0x20" Ta "console path"
557 .It "0x0080" Ta "0x20" Ta "alternative boot path"
558 .It "0x00a0" Ta "0x20" Ta "keyboard path"
559 .It "0x00c0" Ta "0x20" Ta "reserved"
560 .It "0x00e0" Ta "size" Ta "OS dependent"
561 .El
562 .Pp
563 The
564 .Dq OS ID
565 field may have the following values:
566 .Bl -column "value" "OS" -offset left
567 .It Sy "value" Ta Sy "OS"
568 .It "0x000" Ta "No OS-dependent info"
569 .It "0x001" Ta "HP-UX"
570 .It "0x002" Ta "MPE-iX"
571 .It "0x003" Ta "OSF"
572 .It "0x004" Ta "HP-RT"
573 .It "0x005" Ta "Novell Netware"
574 .El
575 .Pp
576 The
577 .Dq fast size
578 field is the amount of memory to be tested upon system boot
579 and is a power of two multiplier for 256KB.
580 Values of 0xe and 0xf are reserved.
581 .It Fn pdc "PDC_STABLE" "PDC_STABLE_WRITE" "address" "ptr" "count"
582 Write data pointed to by the
583 .Ar ptr
584 argument of
585 .Ar count
586 bytes at
587 .Ar address
588 in the
589 .Dq Stable Storage .
590 .It Fn pdc "PDC_STABLE" "PDC_STABLE_SIZE" "ptr"
591 Put the size of the
592 .Dq Stable Storage
593 into the word pointed to by the
594 .Ar ptr
595 argument.
596 .It Fn pdc "PDC_STABLE" "PDC_STABLE_VRFY" "ptr"
597 Verify that the contents of the
598 .Dq Stable Storage
599 are valid.
600 .It Fn pdc "PDC_STABLE" "PDC_STABLE_INIT" "ptr"
601 Reset the contents of the
602 .Dq Stable Storage
603 to zeroes.
604 .It Fn pdc "PDC_SYSMAP" "PDC_SYSMAP_FIND" "ptr" "path" "number"
605 Map module
606 .Ar number
607 into HPA and also provide an area size starting at HPA and a number of
608 additional addresses placed into the data area pointed to by the
609 .Ar ptr
610 argument words one, two, and three, respectively.
611 The device path is placed into the data area pointed to by the
612 .Ar path
613 argument.
614 .It Fn pdc "PDC_SYSMAP" "PDC_SYSMAP_ADDR" "ptr" "im" "ia"
615 Retrieve a list of additional addresses for the module number
616 .Ar im
617 for the address index
618 .Ar ia .
619 The result is placed into the data area pointed to by
620 .Ar ptr ,
621 where the first word gives the address and the second the size of the area.
622 .It Fn pdc "PDC_SYSMAP" "PDC_SYSMAP_HPA" "ptr" "path_ptr"
623 Map device
624 .Ar path_ptr
625 into device's HPA placed into a word pointed to by the
626 .Ar ptr
627 argument.
628 .It Fn pdc "PDC_TLB" "PDC_TLB_INFO" "ptr"
629 Retrieve the hardware TLB handler parameters.
630 This includes a minimal and maximal size for the page table, in bytes,
631 stored into words zero and one, respectively,
632 in the data area pointed to by the
633 .Ar ptr
634 argument.
635 .It Fn pdc "PDC_TLB" "PDC_TLB_CONFIG" "ptr" "base" "size" "param"
636 Configure the hardware TLB miss handler given the same parameters fetched
637 previously with PDC_TLB_INFO into data area pointed to by the
638 .Ar ptr
639 and page table
640 .Ar base
641 address, page table
642 .Ar size ,
643 and handler parameters
644 .Ar param .
645 The hardware TLB handler parameter bits are as follows:
646 .Pp
647 .Bl -tag -width 0xff -compact
648 .It 1
649 Enable the hardware TLB miss handler.
650 The default is to load cr28 with the faulted page table entry address.
651 .It 4
652 Pointer to the next page table entry is put into cr28.
653 .It 6
654 Next pointer field of the page table entry is put into cr28.
655 .El
656 .Pp
657 Resetting the page table address and/or size without disabling
658 the hardware TLB miss handler is allowed.
659 Any changes made are immediate upon Code or Data virtual
660 address translation bits are set in PSW.
661 .It Fn pdc "PDC_TOD" "PDC_TOD_READ" "ptr"
662 Read the TOD, which is a UNIX Epoch time, into the data area
663 pointed to by the
664 .Ar ptr
665 argument.
666 That includes seconds in the first word and microseconds in
667 the second.
668 .It Fn pdc "PDC_TOD" "PDC_TOD_WRITE" "sec" "usec"
669 Write TOD with UNIX Epoch time with
670 .Ar sec
671 seconds and
672 .Ar usec
673 microseconds.
674 .It Fn pdc "PDC_TOD" "PDC_TOD_ITIMER" "ptr"
675 Get TOD and CPU timer accuracy into the data location pointed to by the
676 .Ar ptr
677 argument.
678 The first two words specify a double floating-point value giving
679 CPU timer frequency.
680 The next two words provide accuracy in parts per billion for the TOD and
681 CPU timer, respectively.
682 .El
683 .Sh FILES
684 .Bl -tag -width /sys/arch/hp700/dev/cpudevs -compact
685 .It machine/pdc.h
686 C header file with relevant definitions.
687 .It /sys/arch/hp700/dev/cpudevs
688 System components' version numbers.
689 .It /dev/console
690 System console device.
691 .El
692 .Sh DIAGNOSTICS
693 Upon successful completion all procedures return zero.
694 The following error codes are returned in case of failures:
695 .Pp
696 .Bl -tag -width PDC_ERR_NOPROC -compact
697 .It PDC_ERR_NOPROC
698 No such procedure
699 .It PDC_ERR_NOPT
700 No such option
701 .It PDC_ERR_COMPL
702 Unable to complete without error
703 .It PDC_ERR_EOD
704 No such device
705 .It PDC_ERR_INVAL
706 Invalid argument
707 .It PDC_ERR_PFAIL
708 Aborted by powerfail
709 .El
710 .Sh SEE ALSO
711 .Xr intro 4 ,
712 .Xr io 4 ,
713 .Xr lasi 4
714 .Rs
715 .%T PA-RISC 1.1 Firmware Architecture Reference Specification
716 .%A Hewlett-Packard
717 .%D March 8, 1999
718 .Re
719 .Rs
720 .%T PA-RISC 2.0 Firmware Architecture Reference Specification
721 .%A Hewlett-Packard
722 .%D March 7, 1999
723 .Re