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30 .Dd April 17, 2009
31 .Dt PCI 9
32 .Os
33 .Sh NAME
34 .Nm PCI ,
35 .Nm pci_activate ,
36 .Nm pci_conf_read ,
37 .Nm pci_conf_write ,
38 .Nm pci_conf_print ,
39 .Nm pci_conf_capture ,
40 .Nm pci_conf_restore ,
41 .Nm pci_find_device ,
42 .Nm pci_get_capability ,
43 .Nm pci_mapreg_type ,
44 .Nm pci_mapreg_map ,
45 .Nm pci_mapreg_info ,
46 .Nm pci_intr_map ,
47 .Nm pci_intr_string ,
48 .Nm pci_intr_evcnt ,
49 .Nm pci_intr_establish ,
50 .Nm pci_intr_disestablish ,
51 .Nm pci_get_powerstate ,
52 .Nm pci_set_powerstate ,
53 .Nm pci_vpd_read ,
54 .Nm pci_vpd_write ,
55 .Nm pci_make_tag ,
56 .Nm pci_decompose_tag ,
57 .Nm pci_findvendor ,
58 .Nm pci_devinfo ,
59 .Nm PCI_VENDOR ,
60 .Nm PCI_PRODUCT ,
61 .Nm PCI_REVISION
62 .Nd Peripheral Component Interconnect
63 .Sh SYNOPSIS
64 .In machine/bus.h
65 .In dev/pci/pcivar.h
66 .In dev/pci/pcireg.h
67 .In dev/pci/pcidevs.h
68 .Ft int
69 .Fn pci_activate "pci_chipset_tag_t pc" "pcitag_t tag" "device_t dev" \
70 "int (*wakeup)(pci_chipset_tag_t pc, pcitag_t tag" \
71 "\t\tdevice_t dev, pcireg_t reg)"
72 .Ft pcireg_t
73 .Fn pci_conf_read "pci_chipset_tag_t pc" "pcitag_t tag" "int reg"
74 .Ft void
75 .Fn pci_conf_write "pci_chipset_tag_t pc" "pcitag_t tag" "int reg" \
76 "pcireg_t val"
77 .Ft void
78 .Fn pci_conf_print "pci_chipset_tag_t pc" "pcitag_t tag" \
79 "void (*func)(pci_chipset_tag_t, pcitag_t, const pcireg_t *)"
80 .Ft void
81 .Fn pci_conf_capture "pci_chipset_tag_t pc" "pcitag_t tag" \
82 "struct pci_conf_state *"
83 .Ft void
84 .Fn pci_conf_restore "pci_chipset_tag_t pc" "pcitag_t tag" \
85 "struct pci_conf_state *"
86 .Ft int
87 .Fn pci_find_device "struct pci_attach_args *pa" \
88 "int (*func)(struct pci_attach_args *)"
89 .Ft int
90 .Fn pci_get_capability "pci_chipset_tag_t pc" "pcitag_t tag" \
91 "int capid" "int *offsetp" "pcireg_t *valuep"
92 .Ft pcireg_t
93 .Fn pci_mapreg_type "pci_chipset_tag_t pc" "pcitag_t tag" "int reg"
94 .Ft int
95 .Fn pci_mapreg_map "struct pci_attach_args *pa" "int reg" \
96 "pcireg_t type" "int busflags" "bus_space_tag_t *tagp" \
97 "bus_space_handle_t *handlep" "bus_addr_t *basep" "bus_size_t *sizep"
98 .Ft int
99 .Fn pci_mapreg_info "pci_chipset_tag_t pc" "pcitag_t tag" "int reg" \
100 "pcireg_t type" "bus_addr_t *basep" "bus_size_t *sizep" "int *flagsp"
101 .Ft int
102 .Fn pci_find_rom "struct pci_attach_args *pa" \
103 "bus_space_tag_t bst" "bus_space_handle_t bsh" "int code" \
104 "bus_space_handle_t *handlep" "bus_space_size_t *sizep"
105 .Ft int
106 .Fn pci_intr_map "struct pci_attach_args *pa" "pci_intr_handle_t *ih"
107 .Ft const char *
108 .Fn pci_intr_string "pci_chipset_tag_t pc" "pci_intr_handle_t ih"
109 .Ft const struct evcnt *
110 .Fn pci_intr_evcnt "pci_chipset_tag_t pc" "pci_intr_handle_t ih"
111 .Ft void *
112 .Fn pci_intr_establish "pci_chipset_tag_t pc" "pci_intr_handle_t ih" \
113 "int level" "int (*handler)(void *)" "void *arg"
114 .Ft void
115 .Fn pci_intr_disestablish "pci_chipset_tag_t pc" "void *ih"
116 .Ft int
117 .Fn pci_set_powerstate "pci_chipset_tag_t pc" "pcitag_t tag" \
118 "pcireg_t newstate"
119 .Ft int
120 .Fn pci_get_powerstate "pci_chipset_tag_t pc" "pcitag_t tag" "pcireg_t *state"
121 .Ft int
122 .Fn pci_vpd_read "pci_chipset_tag_t pc" "pcitag_t tag" "int offset" \
123 "int count" "pcireg_t *data"
124 .Ft int
125 .Fn pci_vpd_write "pci_chipset_tag_t pc" "pcitag_t tag" "int offset" \
126 "int count" "pcireg_t *data"
127 .Ft pcitag_t
128 .Fn pci_make_tag "pci_chipset_tag_t pc" "int bus" "int device" \
129 "int function"
130 .Ft void
131 .Fn pci_decompose_tag "pci_chipset_tag_t pc" "pcitag_t tag" \
132 "int *busp" "int *devicep" "int *functionp"
133 .Ft char *
134 .Fn pci_findvendor "pcireg_t id"
135 .Ft void
136 .Fn pci_devinfo "pcireg_t id" "pcireg_t class" "int show" "char *cp" "size_t len"
137 .Ft int
138 .Fn PCI_VENDOR "pcireg_t id"
139 .Ft int
140 .Fn PCI_PRODUCT "pcireg_t id"
141 .Ft int
142 .Fn PCI_REVISION "pcireg_t id"
143 .Sh DESCRIPTION
144 The machine-independent
145 .Nm
146 subsystem provides support for PCI devices.
147 .Pp
148 The PCI bus was initially developed by Intel in the early 1990's to
149 replace the ISA bus for interfacing with their Pentium processor.
150 The PCI specification is widely regarded as well designed, and the
151 PCI bus has found widespread acceptance in machines ranging from
152 Apple's PowerPC-based systems to Sun's UltraSPARC-based machines.
153 .Pp
154 The PCI bus is a multiplexed bus, allowing addresses and data on the same
155 pins for a reduced number of pins.
156 Data transfers can be 8-bit, 16-bit or 32-bit.
157 A 64-bit extended PCI bus is also defined.
158 Multi-byte transfers are little-endian.
159 The PCI bus operates up to 33MHz and any device on the bus can be
160 the bus master.
161 .Pp
162 AGP is a version of PCI optimised for high-throughput data rates,
163 particularly for accelerated frame buffers.
164 .Pp
165 The PCI bus is a "plug and play" bus, in the sense that devices can be
166 configured dynamically by software.
167 The PCI interface chip on a PCI device bus presents a small window
168 of registers into the PCI configuration space.
169 These registers contain information about the device such as the vendor
170 and a product ID.
171 The configuration registers can also be written to by software to alter
172 how the device interfaces to the PCI bus.
173 An important register in the configuration space is the Base Address
174 Register (BAR).
175 The BAR is written to by software to map the device registers into a
176 window of processor address space.
177 Once this mapping is done, the device registers can be accessed relative
178 to the base address.
179 .Sh DATA TYPES
180 Drivers for devices attached to the
181 .Nm
182 will make use of the following data types:
183 .Bl -tag -width compact
184 .It Fa pcireg_t
185 Configuration space register.
186 .It Fa pci_chipset_tag_t
187 Chipset tag for the PCI bus.
188 .It Fa pcitag_t
189 Configuration tag describing the location and function of the PCI
190 device.
191 It contains the tuple
192 .Ao
193 bus, device, function
194 .Ac .
195 .It Fa pci_intr_handle_t
196 The opaque handle describing an established interrupt handler.
197 .It Fa struct pci_attach_args
198 Devices have their identity recorded in this structure.
199 It contains the following members:
200 .Bd -literal
201 bus_space_tag_t pa_iot; /* pci i/o space tag */
202 bus_space_tag_t pa_memt; /* pci mem space tag */
203 bus_dma_tag_t pa_dmat; /* DMA tag */
204 pci_chipset_tag_t pa_pc;
205 int pa_flags; /* flags */
206 pcitag_t pa_tag;
207 pcireg_t pa_id;
208 pcireg_t pa_class;
209 .Ed
210 .It Fa struct pci_conf_state
211 Stores the PCI configuration state of a device.
212 It contains the following member:
213 .Bd -literal
214 pcireg_t reg[16]; /* pci conf register */
215 .Ed
216 .El
217 .Sh FUNCTIONS
218 .Bl -tag -width compact
219 .It Fn pci_activate "pc" "tag" "dev" "fun"
220 Attempt to bring the device to state D0.
221 If the device is not in the D0 state call
222 .Fa fun
223 to restore its state.
224 If
225 .Fa fun
226 is
227 .Dv NULL
228 then restoring from state D3 is going to fail.
229 .It Fn pci_conf_read "pc" "tag" "reg"
230 Read from register
231 .Fa reg
232 in PCI configuration space.
233 The argument
234 .Fa tag
235 is the PCI tag for the current device attached to PCI chipset
236 .Fa pc .
237 .It Fn pci_conf_write "pc" "tag" "reg" "val"
238 Write to register
239 .Fa reg
240 in PCI configuration space.
241 The argument
242 .Fa tag
243 is the PCI tag for the current device attached to PCI chipset
244 .Fa pc .
245 .It Fn pci_conf_print "pc" "tag" "func"
246 Print out most of the registers in the PCI configuration for the
247 device.
248 The argument
249 .Fa tag
250 is the PCI tag for the current device attached to PCI chipset
251 .Fa pc .
252 The argument
253 .Fa func
254 is a function called by
255 .Fn pci_conf_print
256 to print the device-dependent registers.
257 This function is only useful for driver development and is usually
258 wrapped in pre-processor declarations.
259 .It Fn pci_conf_capture "pc" "tag" "pcs"
260 Capture PCI configuration space into structure
261 .Fa pcs .
262 The argument
263 .Fa tag
264 is the PCI tag for the current device attached to the PCI
265 chipset
266 .Fa pc .
267 .It Fn pci_conf_restore "pc" "tag" "pcs"
268 Restores PCI configuration space from structure
269 .Fa pcs .
270 The argument
271 .Fa tag
272 is the PCI tag for the current device attached to the PCI
273 chipset
274 .Fa pc .
275 .It Fn pci_find_device "pa" "func"
276 Find a device using a match function on all probed busses.
277 The argument
278 .Fa func
279 is called by
280 .Fn pci_find_device
281 to match a device.
282 The argument
283 .Fa pa
284 is filled in if the device is matched.
285 .Fn pci_find_device
286 returns 1 if the device is matched, and zero otherwise.
287 This function is specifically for use by kernel modules
288 and its use otherwise is strongly discouraged.
289 .It Fn pci_get_capability "pc" "tag" "capid" "offsetp" "valuep"
290 Parse the device capability list in configuration space looking for
291 capability
292 .Fa capid .
293 If
294 .Fa offsetp
295 is not NULL, the register offset in configuration space is returned in
296 .Fa offsetp .
297 If
298 .Fa valuep
299 is not NULL, the value of the capability is returned in
300 .Fa valuep .
301 The argument
302 .Fa tag
303 is the PCI tag for the current device attached to PCI chipset
304 .Fa pc .
305 This function returns 1 if the capability was found.
306 If the capability was not found, it returns zero, and
307 .Fa offsetp
308 and
309 .Fa valuep
310 remain unchanged.
311 .It Fn pci_mapreg_type "pc" "tag" "reg"
312 Interrogates the Base Address Register (BAR) in configuration space
313 specified by
314 .Fa reg
315 and returns the default (or current) mapping type.
316 Valid returns values are:
317 .Bl -tag -width compact
318 .It Dv PCI_MAPREG_TYPE_IO
319 The mapping is to I/O address space.
320 .It Dv PCI_MAPREG_TYPE_MEM
321 The mapping is to memory address space.
322 .It Dv PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT
323 The mapping is to 64-bit memory address space.
324 .It Dv PCI_MAPREG_TYPE_ROM
325 The mapping is to ROM.
326 Note that in the current implementation,
327 .Dv PCI_MAPREG_TYPE_ROM
328 has the same numeric value as
329 .Dv PCI_MAPREG_TYPE_MEM .
330 .El
331 .Pp
332 The argument
333 .Fa tag
334 is the PCI tag for the current device attached to PCI chipset
335 .Fa pc .
336 .It Fn pci_mapreg_map "pa" "reg" "type" "busflags" "tagp" "handlep" "basep" "sizep"
337 Maps the register windows for the device into kernel virtual address
338 space.
339 This function is generally only called during the driver attach step
340 and takes a pointer to the
341 .Em struct pci_attach_args
342 in
343 .Fa pa .
344 The physical address of the mapping is in the Base Address Register
345 (BAR) in configuration space specified by
346 .Fa reg .
347 Valid values for the type of mapping
348 .Fa type
349 are:
350 .Bl -tag -width compact
351 .It Dv PCI_MAPREG_TYPE_IO
352 The mapping should be to I/O address space.
353 .It Dv PCI_MAPREG_TYPE_MEM
354 The mapping should be to memory address space.
355 .It Dv PCI_MAPREG_TYPE_ROM
356 The mapping is to access ROM.
357 This type of mapping is only permitted when the value for
358 .Fa reg
359 is
360 .Dv PCI_MAPREG_ROM .
361 .El
362 .Pp
363 The argument
364 .Fa busflags
365 are bus-space flags passed to
366 .Fn bus_space_map
367 to perform the mapping (see
368 .Xr bus_space 9 ) .
369 The bus-space tag and handle for the mapped register window are
370 returned in
371 .Fa tagp
372 and
373 .Fa handlep
374 respectively.
375 The bus-address and size of the mapping are returned in
376 .Fa basep
377 and
378 .Fa sizep
379 respectively.
380 If any of
381 .Fa tagp ,
382 .Fa handlep ,
383 .Fa basep ,
384 or
385 .Fa sizep
386 are NULL then
387 .Fn pci_mapreg_map
388 does not define their return value.
389 This function returns zero on success and non-zero on error.
390 .It Fn pci_mapreg_info "pc" "tag" "reg" "type" "basep" "sizep" "flagsp"
391 Performs the same operations as
392 .Fn pci_mapreg_map
393 but doesn't actually map the register window into kernel virtual
394 address space.
395 Returns the bus-address, size and bus flags in
396 .Fa basep ,
397 .Fa sizep
398 and
399 .Fa flagsp
400 respectively.
401 These return values can be used by
402 .Fn bus_space_map
403 to actually map the register window into kernel virtual address space.
404 This function is useful for setting up the registers in configuration
405 space and deferring the mapping to a later time, such as in a
406 bus-independent attachment routine.
407 .Fa pci_mapreg_info
408 returns zero on success and non-zero on failure.
409 .It Fn pci_find_rom "pa" "bst" "bsh" "code" "handlep" "sizep"
410 Locates a suitable ROM image within a PCI expansion ROM previously mapped with
411 .Fn pci_mapreg_map
412 and creates a subregion for it with
413 .Fn bus_space_subregion .
414 The
415 .Fa bst
416 and
417 .Fa bsh
418 arguments are the bus tag and handle obtained with the prior call to
419 .Fn pci_mapreg_map .
420 Valid values for the image type
421 .Fa code
422 are:
423 .Bl -tag -width compact
424 .It Dv PCI_ROM_CODE_TYPE_X86
425 Find a ROM image containing i386 executable code for use by PC BIOS.
426 .It Dv PCI_ROM_CODE_TYPE_OFW
427 Find a ROM image containing Forth code for use by Open Firmware.
428 .It Dv PCI_ROM_CODE_TYPE_HPPA
429 Find a ROM image containing HP PA/RISC executable code.
430 .El
431 .Pp
432 The created subregion will cover the entire selected ROM image, including
433 header data.
434 The handle to this subregion is returned in
435 .Fa handlep .
436 The size of the image (and the corresponding subregion) is returned in
437 .Fa sizep .
438 This function can only be used with expansion ROMs located at the
439 .Dv PCI_MAPREG_ROM
440 base address register (BAR).
441 .It Fn pci_intr_map "pa" "ih"
442 See
443 .Xr pci_intr 9 .
444 .It Fn pci_intr_string "pc" "ih"
445 See
446 .Xr pci_intr 9 .
447 .It Fn pci_intr_evcnt "pc" "ih"
448 See
449 .Xr pci_intr 9 .
450 .It Fn pci_intr_establish "pc" "ih" "level" "handler" "arg"
451 See
452 .Xr pci_intr 9 .
453 .It Fn pci_intr_disestablish "pc" "ih"
454 See
455 .Xr pci_intr 9 .
456 .It Fn pci_set_powerstate "pc" "tag" "newstate"
457 Set power state of the device to newstate.
458 Valid values for
459 .Fa newstate
460 are:
461 .Pp
462 .Bl -tag -width PCI_PMCSR_STATE_D0 -compact
463 .It Dv PCI_PMCSR_STATE_D0
464 .It Dv PCI_PMCSR_STATE_D1
465 .It Dv PCI_PMCSR_STATE_D2
466 .It Dv PCI_PMCSR_STATE_D3
467 .El
468 .It Fn pci_get_powerstate "pc" "tag" "state"
469 Get current power state of the device.
470 .It Fn pci_vpd_read "pc" "tag" "offset" "count" "data"
471 Read
472 .Fa count
473 32-bit words of Vital Product Data for the device starting at offset
474 .Fa offset
475 into the buffer pointed to by
476 .Fa data .
477 Returns 0 on success or non-zero if the device has no Vital Product Data
478 capability or if reading the Vital Product Data fails.
479 .It Fn pci_vpd_write "pc" "tag" "offset" "count" "data"
480 Write
481 .Fa count
482 32-bit words of Vital Product Data for the device starting at offset
483 .Fa offset
484 from the buffer pointed to by
485 .Fa data .
486 Returns 0 on success or non-zero if the device has no Vital Product Data
487 capability of if writing the Vital Product Data fails.
488 .It Fn pci_make_tag "pc" "bus" "device" "function"
489 Create a new PCI tag for the PCI device specified by the tuple
490 .Ao
491 bus, device, function
492 .Ac .
493 This function is not useful to the usual PCI device driver.
494 It is generally used by drivers of multi-function devices when
495 attaching other PCI device drivers to each function.
496 .It Fn pci_decompose_tag "pc" "tag" "busp" "devicep" "fnp"
497 Decompose the PCI tag
498 .Fa tag
499 generated by
500 .Fn pci_make_tag
501 into its
502 .Ao
503 bus, device, function
504 .Ac
505 tuple.
506 .It Fn pci_findvendor "id"
507 Return the string of the vendor name for the device specified by
508 .Fa id .
509 .It Fn pci_devinfo "id" "class" "show" "cp" "len"
510 Returns the description string from the in-kernel PCI database for the
511 device described by
512 .Fa id
513 and
514 .Fa class .
515 The description string is returned in
516 .Fa cp ;
517 the size of that storage is given in
518 .Fa len .
519 The argument
520 .Fa show
521 specifies whether the PCI subsystem should report the string to the
522 console.
523 .It Fn PCI_VENDOR "id"
524 Return the PCI vendor id for device
525 .Fa id .
526 .It Fn PCI_PRODUCT "id"
527 Return the PCI product id for device
528 .Fa id .
529 .It Fn PCI_REVISION "id"
530 Return the PCI product revision for device
531 .Fa id .
532 .El
533 .Sh AUTOCONFIGURATION
534 During autoconfiguration, a
535 .Nm
536 driver will receive a pointer to
537 .Fa struct pci_attach_args
538 describing the device attaches to the PCI bus.
539 Drivers match the device using the
540 .Fa pa_id
541 member using
542 .Fn PCI_VENDOR .
543 .Fn PCI_PRODUCT
544 and
545 .Fn PCI_REVISION .
546 .Pp
547 During the driver attach step, drivers can read the device
548 configuration space using
549 .Fn pci_conf_read .
550 The meaning attached to registers in the PCI configuration space are
551 device-dependent, but will usually contain physical addresses of the
552 device register windows.
553 Device options can also be stored into the PCI configuration space using
554 .Fn pci_conf_write .
555 For example, the driver can request support for bus-mastering DMA by
556 writing the option to the PCI configuration space.
557 .Pp
558 Device capabilities can be queried using
559 .Fn pci_get_capability ,
560 and returns device-specific information which can be found in the PCI
561 configuration space to alter device operation.
562 .Pp
563 After reading the physical addresses of the device register windows
564 from configuration space, these windows must be mapped into kernel
565 virtual address space using
566 .Fn pci_mapreg_map .
567 Device registers can now be accessed using the standard bus-space API
568 (see
569 .Xr bus_space 9 ) .
570 .Pp
571 Details of using PCI interrupts is described in
572 .Xr pci_intr 9 .
573 .Sh DMA SUPPORT
574 The PCI bus supports bus-mastering operations from any device on the bus.
575 The DMA facilities are accessed through the standard
576 .Xr bus_dma 9
577 interface.
578 To support DMA transfers from the device to the host, it is necessary
579 to enable bus-mastering in the PCI configuration space for the device.
580 .Pp
581 During system shutdown, it is necessary to abort any DMA transfers in
582 progress by registering a shutdown hook (see
583 .Xr shutdownhook_establish 9 ) .
584 .Sh CODE REFERENCES
585 This section describes places within the
586 .Nx
587 source tree where actual code implementing or using the
588 machine-independent PCI subsystem can be found.
589 All pathnames are relative to
590 .Pa /usr/src .
591 .Pp
592 The PCI subsystem itself is implemented within the files
593 .Pa sys/dev/pci/pci.c ,
594 .Pa sys/dev/pci/pci_subr.c ,
595 .Pa sys/dev/pci/pci_map.c ,
596 .Pa sys/dev/pci/pci_quirks.c ,
597 and
598 .Pa sys/dev/pci/pciconf.c .
599 Machine-dependent portions are implemented within the file
600 .Pa sys/arch/\*[Lt]arch\*[Gt]/pci/pci_machdep.c .
601 .Pp
602 The database of known devices exists within the file
603 .Pa sys/dev/pci/pcidevs_data.h
604 and is generated automatically from the file
605 .Pa sys/dev/pci/pcidevs .
606 New vendor and product identifiers should be added to this file.
607 The database can be regenerated using the Makefile
608 .Pa sys/dev/pci/Makefile.pcidevs .
609 .Sh SEE ALSO
610 .Xr pci 4 ,
611 .Xr autoconf 9 ,
612 .Xr bus_dma 9 ,
613 .Xr bus_space 9 ,
614 .Xr driver 9 ,
615 .Xr pci_configure_bus 9 ,
616 .Xr pci_intr 9 ,
617 .Xr shutdownhook_establish 9
618 .Sh HISTORY
619 The machine-independent PCI subsystem appeared in
620 .Nx 1.2 .