sys/arch/acorn26/iobus/iocreg.h

   1 /* $NetBSD: iocreg.h,v 1.2 2002/03/07 23:16:44 bjh21 Exp $ */
   2
   3 /*
   4  * Copyright (c) 1997 Ben Harris.
   5  * Copyright (c) 1994 Mark Brinicombe.
   6  * Copyright (c) 1994 Brini.
   7  * All rights reserved.
   8  *
   9  * This code is derived from software written for Brini by Mark Brinicombe
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  * 1. Redistributions of source code must retain the above copyright
  15  *    notice, this list of conditions and the following disclaimer.
  16  * 2. Redistributions in binary form must reproduce the above copyright
  17  *    notice, this list of conditions and the following disclaimer in the
  18  *    documentation and/or other materials provided with the distribution.
  19  * 3. All advertising materials mentioning features or use of this software
  20  *    must display the following acknowledgement:
  21  *      This product includes software developed by Brini.
  22  * 4. The name of the company nor the name of the author may be used to
  23  *    endorse or promote products derived from this software without specific
  24  *    prior written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
  27  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  28  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  29  * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
  30  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  31  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  32  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  36  * SUCH DAMAGE.
  37  */
  38
  39 /*
  40  * iocreg.h - Acorn IOC (Albion/VC2311) registers
  41  *
  42  * Based on arch/arm32/include/iomd.h 1.7:
  43  * Created      : 18/09/94
  44  * Based on kate/display/iomd.h
  45  */
  46
  47 #ifndef _ARM26_IOCREG_H
  48 #define _ARM26_IOCREG_H
  49
  50 /*
  51  * These addresses are intended to be inputs to bus_space functions,
  52  * and as such bits 0-4 here map to A[2:6] on the IOC.
  53  */
  54
  55 /*                              Read            Write           */
  56 #define IOC_CTL         0x00 /* Control         Control         */
  57 #define IOC_KBDDAT      0x01 /* Kbd receive     Kbd send        */
  58
  59 #define IOC_IRQSTA      0x04 /* IRQ status A    -               */
  60 #define IOC_IRQRQA      0x05 /* IRQ request A   IRQ clear       */
  61 #define IOC_IRQMSKA     0x06 /* IRQ mask A      IRQ mask A      */
  62
  63 #define IOC_IRQSTB      0x08 /* IRQ status B    -               */
  64 #define IOC_IRQRQB      0x09 /* IRQ request B   -               */
  65 #define IOC_IRQMSKB     0x0a /* IRQ mask B      IRQ mask B      */
  66
  67 #define IOC_FIQST       0x0c /* FIQ status      -               */
  68 #define IOC_FIQRQ       0x0d /* FIQ request     -               */
  69 #define IOC_FIQMSK      0x0e /* FIQ mask        FIQ mask        */
  70
  71 #define IOC_T0LOW       0x10 /* T0 count low    T0 latch low    */
  72 #define IOC_T0HIGH      0x11 /* T0 count high   T0 latch high   */
  73 #define IOC_T0GO        0x12 /* -               T0 go command   */
  74 #define IOC_T0LATCH     0x13 /* -               T0 latch command */
  75
  76 #define IOC_T1LOW       0x14 /* T1 count low    T1 latch low    */
  77 #define IOC_T1HIGH      0x15 /* T1 count high   T1 latch high   */
  78 #define IOC_T1GO        0x16 /* -               T1 go command   */
  79 #define IOC_T1LATCH     0x17 /* -               T1 latch command */
  80
  81 #define IOC_T2LOW       0x18 /* T2 count low    T2 latch low    */
  82 #define IOC_T2HIGH      0x19 /* T2 count high   T2 latch high   */
  83 #define IOC_T2GO        0x1a /* -               T2 go command   */
  84 #define IOC_T2LATCH     0x1b /* -               T2 latch command */
  85
  86 #define IOC_T3LOW       0x1c /* T3 count low    T3 latch low    */
  87 #define IOC_T3HIGH      0x1d /* T3 count high   T3 latch high   */
  88 #define IOC_T3GO        0x1e /* -               T3 go command   */
  89 #define IOC_T3LATCH     0x1f /* -               T3 latch command */
  90
  91 #define IOC_SIZE        0x20 /* Total amount of bus space used by the IOC */
  92
  93 /* Control register bits (should most of these be defined here?) */
  94 #define IOC_CTL_SDA             0x01    /* IIC serial data      */
  95 #define IOC_CTL_SCL             0x02    /* IIC serial clock     */
  96 #define IOC_CTL_FLYBACK         0x80    /* Video flyback        */
  97
  98 /* Archimdes machines only */
  99 #define IOC_CTL_FDREADY         0x04    /* Floppy disc ready    */
 100 #define IOC_CTL_SMUTE           0x20    /* Speaker mute         */
 101 #define IOC_CTL_LPTACK          0x40    /* Printer acknowledge  */
 102
 103 /* IOEB machines only */
 104 #define IOC_CTL_FDDEN           0x04    /* Floppy disc media density */
 105 #define IOC_CTL_SSN             0x08    /* Electronic machine number */
 106 #define IOC_CTL_NINDEX          0x40    /* Floppy disc INDEX* signal */
 107
 108 /* Internal control register bits */
 109 /* These give the current state of the edge-sensitive IRQ lines */
 110 #define IOC_CTL_NIF     0x40    /* Set if IF* is high (IRQ 2) */
 111 #define IOC_CTL_IR      0x80    /* Set if IR  is high (IRQ 3) */
 112
 113 /* IOC definitions of interrupt sources (independent of machine) */
 114 /* Hmm Interrupt numbers or masks?  Numbers for now. */
 115 #define IOC_IRQ_IL6     0  /* Active low input */
 116 #define IOC_IRQ_IL7     1  /* Active low input */
 117 #define IOC_IRQ_IF      2  /* Falling edge-triggered */
 118 #define IOC_IRQ_IR      3  /* Rising edge-triggered */
 119 #define IOC_IRQ_POR     4  /* Power-on reset */
 120 #define IOC_IRQ_TM0     5  /* Timer 0 reloaded */
 121 #define IOC_IRQ_TM1     6  /* Timer 1 reloaded */
 122 #define IOC_IRQ_1       7  /* Always interrupt */
 123 #define IOC_IRQ_IL0     8  /* Active low input */
 124 #define IOC_IRQ_IL1     9  /* Active low input */
 125 #define IOC_IRQ_IL2     10 /* Active low input */
 126 #define IOC_IRQ_IL3     11 /* Active low input */
 127 #define IOC_IRQ_IL4     12 /* Active low input */
 128 #define IOC_IRQ_IL5     13 /* Active low input */
 129 #define IOC_IRQ_STX     14 /* KART transmit finished */
 130 #define IOC_IRQ_SRX     15 /* KART receive finished */
 131 #define IOC_IRQA_BIT(n) ((n) < 8 ? 1 << (n) : 0)
 132 #define IOC_IRQB_BIT(n) ((n) < 8 ? 0 : 1 << ((n) - 8))
 133
 134 #define IOC_IRQ_CLEARABLE_MASK 0x7c
 135
 136 /* FIQ sources */
 137 #define IOC_FIQ_FH0     0  /* Active high input */
 138 #define IOC_FIQ_FH1     1  /* Active high input */
 139 #define IOC_FIQ_FL      2  /* Active low input */
 140 #define IOC_FIQ_C3      3  /* Active low input (also ctl reg) */
 141 #define IOC_FIQ_C4      4  /* Active low input (also ctl reg) */
 142 #define IOC_FIQ_C5      5  /* Active low input (also ctl reg) */
 143 #define IOC_FIQ_IL0     6  /* Active low input (also IRQ) */
 144 #define IOC_FIQ_1       7  /* Always interrupt */
 145 #define IOC_FIQ_BIT(n)  (1 << (n))
 146
 147 /* Cycle types */
 148 #define IOC_TYPE_SLOW   0
 149 #define IOC_TYPE_MEDIUM 1
 150 #define IOC_TYPE_FAST   2
 151 #define IOC_TYPE_SYNC   3
 152
 153 /* Counter decrement rate */
 154 #define IOC_TIMER_RATE  2000000 /* 2 MHz */
 155
 156 /* Archimedes-specific defines */
 157 #define IOC_TYPE_SHIFT (19 - 2) /* A[20:19] -> T[1:0] */
 158 #define IOC_BANK_SHIFT (16 - 2) /* A[18:16] -> B[2:0] */
 159
 160 #endif