sys/arch/acorn26/ioc/ioebreg.h

   1 /* $NetBSD: ioebreg.h,v 1.1 2000/05/09 21:56:02 bjh21 Exp $ */
   2
   3 /*
   4  * This file is in the public domain.
   5  *
   6  * Derived from:
   7  * RISC OS 3 Programmer's Reference Manual
   8  * A3010/A3020/A4000 Technical Reference Manual
   9  */
  10
  11 /* Acorn IOEB (Input/Output Extension Block) registers */
  12
  13 #ifndef _IOEBREG_H_
  14 #define _IOEBREG_H_
  15
  16 /*
  17  * IOEB starts at a rather high offset because it avoids the ranges
  18  * used on older machines.
  19  */
  20
  21 #define IOEB_REG_VIDCTL         18 /* Video control latch */
  22 #define IOEB_REG_ID             20 /* Device ID */
  23 #define IOEB_REG_SPEED          21 /* Clock speed (A4?) */
  24 #define IOEB_REG_INTRCLR        22 /* Printer interrupt clear */
  25 #define IOEB_REG_MONID          28 /* Monitor ID */
  26 #define IOEB_REG_VGATEST        29 /* VGA test pin/SCART sound ??? */
  27 #define IOEB_REG_JOY1           30 /* Joystick 1 */
  28 #define IOEB_REG_JOY2           31 /* Joystick 2 */
  29
  30 /* The IOEB is connected to D[3:0], so its internal registers are 4-bit */
  31 #define IOEB_VIDCTL_HSINV       0x1 /* Invert horizontal sync */
  32 #define IOEB_VIDCTL_VSINV       0x2 /* Invert vertical sync */
  33 #define IOEB_VIDCTL_CLK_MASK    0xc /* VIDCLK select */
  34 #define IOEB_VIDCTL_CLK_24MHZ   0x0 /* 24 MHz */
  35 #define IOEB_VIDCTL_CLK_25MHZ   0x4 /* 25.175 MHz */
  36 #define IOEB_VIDCTL_CLK_36MHZ   0x8 /* 36 MHz */
  37
  38 #define IOEB_ID_IOEB            0x5
  39
  40 #endif