sys/arch/alpha/a12/a12dcreg.h

   1 /* $NetBSD: a12dcreg.h,v 1.1 1998/09/23 21:14:02 ross Exp $ */
   2
   3 /* [Notice revision 2.2]
   4  * Copyright (c) 1997, 1998 Avalon Computer Systems, Inc.
   5  * All rights reserved.
   6  *
   7  * Author: Ross Harvey
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright and
  13  *    author notice, this list of conditions, and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. Neither the name of Avalon Computer Systems, Inc. nor the names of
  18  *    its contributors may be used to endorse or promote products derived
  19  *    from this software without specific prior written permission.
  20  * 4. This copyright will be assigned to The NetBSD Foundation on
  21  *    1/1/2000 unless these terms (including possibly the assignment
  22  *    date) are updated in writing by Avalon prior to the latest specified
  23  *    assignment date.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY AVALON COMPUTER SYSTEMS, INC. AND CONTRIBUTORS
  26  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL AVALON OR THE CONTRIBUTORS
  29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  35  * POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #define A12DCREG()      /* Generate ctags(1) key */
  39
  40 /* Id: a12backdriver.h,v 1.1.1.1 1997/12/04 04:33:31 ross Exp  */
  41
  42 #define A12C_TXRDY      0x8000
  43 #define A12C_TXACK      0x4000
  44 #define CHMASK          0x3f00
  45
  46 #define MCQ_SLOTNO      0x81
  47
  48 #define MSP(n) (a12_mstate+(n))
  49
  50 #define CHANNEL_KDATA   1
  51 #define CHANNEL_KMARK   2
  52 #define CHANNEL_MULTI   3
  53 #define CHANNEL_MONITOR 4
  54 #define CHANNEL_SROM_A  5
  55 #define CHANNEL_SROM_D  6
  56 #define CHANNEL_CONSOLE 7
  57
  58 /* detached console commands       >  to detached console               */
  59 /*                                 <  to A12 CPU                        */
  60 #define CPX_GEO         129     /* >return geographical address (card #)*/
  61 #define CPX_LOGMC       130     /* >return multi channel log level      */
  62 #define CPX_PANIC       131     /* >process has entered panic()         */
  63 #define CPX_READY       132     /* >fw kernel can accept CPX_GO command */
  64 #define CPX_GO          133     /* <fw kernel should proceed with boot  */
  65
  66 #define MAX_EVENTS      1000
  67 #ifndef MAX_MODULES
  68 #define MAX_MODULES     1
  69 #endif
  70
  71 #define mcgetput(mn,chan,byte) msgetput(&a12_mstate[mn],(chan),(byte))
  72
  73 typedef unsigned char a12uchar;
  74
  75 enum tx_state {
  76         tx_idle,        /* transmitter idle */
  77         tx_braaw        /* transmitter byte ready assert ack wait */
  78 };
  79
  80 enum rx_state {
  81         rx_idle,        /* receiver idle */
  82         rx_busy         /* receiver byte is ready */
  83 };
  84
  85 typedef volatile long mmreg_t;
  86
  87 typedef struct mstate_struct {
  88         mmreg_t *xcdr;                  /* address of CDR */
  89         unsigned short  cbvsr,          /* software copy */
  90                         cdr;            /* software copy */
  91         unsigned short  txsv, rxsv;     /* transmitter and receiver states */
  92         a12uchar        b2c_char,
  93                         b2c_channel,
  94                         c2b_char,
  95                         c2b_channel;
  96         char    up,
  97                 inuse,
  98                 reset_scanner,
  99                 reset_loader;
 100         int     panicexit;
 101         int     txrdy_out, txrdy_in,    /* current polarity of interlocks */
 102                 txack_out, txack_in;
 103         char    lastr, lastrc,          /* last received char. and channel */
 104                 lastt, lasttc;          /* last transmitted char. and channel */
 105         unsigned int    rx_busy_wait,   /* receive busy ticks */
 106                         rx_busy_cnt,    /* receive busy start count */
 107                         tx_busy_wait,   /* transmit busy ticks */
 108                         tx_busy_cnt;    /* transmit busy start count */
 109         unsigned int    tbytes,         /* bytes not in block send */
 110                         tblkbytes,      /* bytes in block send */
 111                         tblks;          /* total blocks */
 112         unsigned int    blwobe,         /* blocks sent without retry */
 113                         blwbe;          /* blocks sent with retry */
 114         unsigned int    max_blkretry;   /* max. retries to send block */
 115         unsigned int    max_blktime,    /* max. time to send block */
 116                         max_blktimesz;  /* size of max. time block */
 117         unsigned int    avg_blksz,      /* avg. size block */
 118                         avg_blktime;    /* avg. time to send block */
 119         unsigned int    retry_time;     /* time spent sending re-try blocks */
 120 } mstate_type;
 121
 122 /* EVENT TRACKING */
 123
 124 typedef enum {
 125 BS,BE,BL,READ0,READ1,WRITE0,WRITE1,R360,W360,CL1,CL2,IDL1,IDL2
 126 } ET;
 127
 128 typedef struct {
 129         ET      type;
 130         int     time;
 131         char    m;      /* module # */
 132         char    chnl;
 133         char    rsv1;
 134         char    rsv2;
 135         int     data;
 136 } ESTRUCT;
 137
 138 /* EVENT TRACKING END */
 139
 140 mstate_type a12_mstate[MAX_MODULES];
 141
 142 int a12console_last_unexpected_error;
 143
 144 int a12dccnattach(void);