sys/arch/alpha/pci/a12creg.h

   1 /* $NetBSD: a12creg.h,v 1.1 1998/01/29 21:42:52 ross Exp $ */
   2
   3 /* [Notice revision 2.0]
   4  * Copyright (c) 1997 Avalon Computer Systems, Inc.
   5  * All rights reserved.
   6  *
   7  * Author: Ross Harvey
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright and
  13  *    author notice, this list of conditions, and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. Neither the name of Avalon Computer Systems, Inc. nor the names of
  18  *    its contributors may be used to endorse or promote products derived
  19  *    from this software without specific prior written permission.
  20  * 4. This copyright will be assigned to The NetBSD Foundation on
  21  *    1/1/2000 unless these terms (including possibly the assignment
  22  *    date) are updated in writing by Avalon prior to the latest specified
  23  *    assignment date.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY AVALON COMPUTER SYSTEMS, INC. AND CONTRIBUTORS
  26  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  35  * POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #ifndef _ALPHA_PCI_A12CREG_H_
  39 #define _ALPHA_PCI_A12CREG_H_
  40
  41 #define A12CREG()       /* generate ctags(1) key */
  42
  43 #define REGADDR(r)      ((volatile long *)ALPHA_PHYS_TO_K0SEG(r))
  44 #define REGVAL(r)       (*REGADDR(r))
  45 /*
  46  *                         --   A  d  d  r  e  s  s     L  i  n  e  --
  47  *
  48  *                         39 36      29 28  27-13 12 .11 10  9 8-6 5 4 3
  49  *
  50  * IMALR                   1   1       a  a   a-a   a . a  a  a a-a 0 0
  51  * IMALR_LB                1   1       a  a   a-a   a . a  a  a a-a 0 1
  52  * OMALR                   1   1       a  a   a-a   a . a  a  a a-a 1 0
  53  * OMALR_LB                1   1       a  a   a-a   a . a  a  a a-a 1 1
  54  * MCRP                    1   0       0            0 . 0  0  0 a-a a a a
  55  * MCRP_LWE                1   0       0            0 . 0  0  1       0 1
  56  * MCRP_LWO                1   0       0            0 . 0  1  0       1 1
  57  * MCSR                    1   0       0            1 . 0  0  1       1
  58  * OMR                     1   0       0            1 . 0  1  0       1
  59  * GSR                     1   0       0            1 . 0  1  1       1
  60  * IETCR                   1   0       0            1 . 1  0  0       1
  61  * CDR                     1   0       0            1 . 1  0  1       1
  62  * PMEM                    1   0       0            1 . 1  1  0       1
  63  * SOR                     1   0       0            1 . 1  1  1       1
  64  * PCI Buffer              1   0       1  0   a-a   a . a  a  a     a a a
  65  * PCI Target              1   0       1  1   a-a   a . a  a  a     a a a
  66  * Main Memory             0   0       a  a   a-a   a . a  a  a     a a a
  67  *
  68  *
  69  */
  70
  71 #define _A12_IO         0x8000000000L
  72
  73 #define A12_OFFS_FIFO         0x0000
  74 #define A12_OFFS_FIFO_LWE     0x0200
  75 #define A12_OFFS_FIFO_LWO     0x0400
  76 #define A12_OFFS_VERS         0x1010
  77 #define A12_OFFS_MCSR         0x1210
  78 #define A12_OFFS_OMR          0x1410
  79 #define A12_OFFS_GSR          0x1610
  80 #define A12_OFFS_IETCR        0x1810
  81 #define A12_OFFS_CDR          0x1a10
  82 #define A12_OFFS_PMEM         0x1c10
  83 #define A12_OFFS_SOR          0x1e10
  84
  85 #define A12_FIFO        (_A12_IO|A12_OFFS_FIFO)
  86 #define A12_FIFO_LWE    (_A12_IO|A12_OFFS_FIFO_LWE)
  87 #define A12_FIFO_LWO    (_A12_IO|A12_OFFS_FIFO_LWO)
  88 #define A12_VERS        (_A12_IO|A12_OFFS_VERS)
  89 #define A12_MCSR        (_A12_IO|A12_OFFS_MCSR)
  90 #define A12_OMR         (_A12_IO|A12_OFFS_OMR)
  91 #define A12_GSR         (_A12_IO|A12_OFFS_GSR)
  92 #define A12_IETCR       (_A12_IO|A12_OFFS_IETCR)
  93 #define A12_CDR         (_A12_IO|A12_OFFS_CDR)
  94 #define A12_PMEM        (_A12_IO|A12_OFFS_PMEM)
  95 #define A12_SOR         (_A12_IO|A12_OFFS_SOR)
  96
  97 #define A12_PCIBuffer   0x8020000000L
  98 #define A12_PCITarget   0x8030000000L
  99
 100 #define A12_PCIMasterAbort      0x8000          /* GSR */
 101
 102 #define A12_OMR_PCIAddr2        0x1000L         /* OMR */
 103 #define A12_OMR_PCIConfigCycle  0x0800L         /* OMR */
 104 #define A12_OMR_ICW_ENABLE      0x0400L         /* OMR */
 105 #define A12_OMR_IEI_ENABLE      0x0200L         /* OMR */
 106 #define A12_OMR_TEI_ENABLE      0x0100L         /* OMR */
 107 #define A12_OMR_PCI_ENABLE      0x0080L         /* OMR */
 108 #define A12_OMR_OMF_ENABLE      0x0040L         /* OMR */
 109
 110 #define A12_MCSR_DMAOUT         0x4000  /* Outgoing DMA channel armed */
 111 #define A12_MCSR_DMAIN          0x2000  /* Incoming DMA channel armed */
 112 #define A12_MCSR_OMFE           0x1000  /* Outgoing message fifo empty */
 113 #define A12_MCSR_OMFF           0x0800  /* Outgoing message fifo full */
 114 #define A12_MCSR_OMFAF          0x0400  /* Outgoing message fifo almost full */
 115 #define A12_MCSR_IMFAE          0x0200  /* Incoming message fifo almost empty */
 116 #define A12_MCSR_IMP            0x0100  /* Incoming message pending */
 117 #define A12_MCSR_TBC            0x0080  /* Transmit Block Complete */
 118 #define A12_MCSR_RBC            0x0040  /* Receive Block Complete */
 119
 120 #define A12_GSR_PDI             0x0040  /* PCI device interrupt asserted */
 121 #define A12_GSR_PEI             0x0080  /* PCI SERR# pulse received */
 122 #define A12_GSR_MCE             0x0100  /* Missing Close Error Flag */
 123 #define A12_GSR_ECE             0x0200  /* Embedded Close Error Flag */
 124 #define A12_GSR_TEI             0x0400  /* Timer event interrupt pending */
 125 #define A12_GSR_IEI             0x0800  /* Interval event interrupt pending */
 126 #define A12_GSR_FORUN           0x1000  /* FIFO Overrun Error */
 127 #define A12_GSR_FURUN           0x2000  /* FIFO Underrun Error */
 128 #define A12_GSR_ICW             0x4000  /* Incoming Control Word */
 129 #define A12_GSR_ABORT           0x8000  /* PCI Master or Target Abort */
 130
 131 #define A12_ALL_WIRED           0xffc0  /* Core logic wires these bits */
 132 #define A12_ALL_FIRST                6  /* ...starting at this one */
 133 #define A12_ALL_EXTRACT(r)      (((r) & A12_ALL_WIRED) >> A12_ALL_FIRST)
 134
 135 #define A12_CBMAOFFSET          0x0100
 136
 137 #define A12_XBAR_CHANNEL_MAX    14
 138 #define A12_TMP_PID_COUNT       12
 139
 140 #define A12CONS_CPU_LOCAL       0x40    /* our switch channel */
 141 #define A12CONS_CPU_ETHER       0x41    /* route to outside world */
 142 #define A12CONS_CPU_GLOBAL      0x42    /* location in the big picture */
 143
 144 #define DIE()           NICETRY()
 145 #define NICETRY()       panic("Nice try @ %s:%d\n", __FILE__, __LINE__)
 146 #define What()          printf("%s:%d. What?\n",    __FILE__, __LINE__)
 147
 148 #endif