sys/arch/alpha/pci/a12cvar.h

   1 /* $NetBSD: a12cvar.h,v 1.4 2005/12/11 12:16:17 christos Exp $ */
   2
   3 /* [Notice revision 2.0]
   4  * Copyright (c) 1997 Avalon Computer Systems, Inc.
   5  * All rights reserved.
   6  *
   7  * Author: Ross Harvey
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright and
  13  *    author notice, this list of conditions, and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. Neither the name of Avalon Computer Systems, Inc. nor the names of
  18  *    its contributors may be used to endorse or promote products derived
  19  *    from this software without specific prior written permission.
  20  * 4. This copyright will be assigned to The NetBSD Foundation on
  21  *    1/1/2000 unless these terms (including possibly the assignment
  22  *    date) are updated in writing by Avalon prior to the latest specified
  23  *    assignment date.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY AVALON COMPUTER SYSTEMS, INC. AND CONTRIBUTORS
  26  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  35  * POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #ifndef _ALPHA_PCI_A12CVAR_H_
  39 #define _ALPHA_PCI_A12CVAR_H_
  40
  41 #define A12CVAR()       /* generate ctags(1) key */
  42
  43 #include <dev/isa/isavar.h>
  44 #include <dev/pci/pcivar.h>
  45 #include <alpha/pci/pci_sgmap_pte64.h>
  46 /*
  47  * A12 Core Logic -a12c- configuration.
  48  */
  49 struct a12c_config {
  50         int     ac_initted;
  51
  52         bus_space_tag_t ac_iot, ac_memt;
  53         struct alpha_pci_chipset ac_pc;
  54
  55         struct alpha_bus_dma_tag ac_dmat_direct;
  56         struct alpha_bus_dma_tag ac_dmat_sgmap;
  57
  58         struct alpha_sgmap ac_sgmap;
  59
  60         u_int32_t ac_hae_mem;
  61         u_int32_t ac_hae_io;
  62
  63         struct extent *ac_io_ex, *ac_d_mem_ex, *ac_s_mem_ex;
  64         int     ac_mallocsafe;
  65 };
  66
  67 struct a12c_softc {
  68         struct  device sc_dev;
  69
  70         struct  a12c_config *sc_ccp;
  71 };
  72
  73 void    a12c_init(struct a12c_config *, int);
  74 void    a12c_pci_init(pci_chipset_tag_t, void *);
  75 void    a12c_dma_init(struct a12c_config *);
  76
  77 bus_space_tag_t a12c_bus_io_init(void *);
  78 bus_space_tag_t a12c_bus_mem_init(void *);
  79 /*
  80  * The following two CPU numbers are relative to the local switch;
  81  * in a multistage system these numbers will not be unique. a12_ethercpu
  82  * is used to route bootp packets and to mount the root FS.
  83  */
  84 int     a12_cpu_local;  /* our CPU number relative to the local switch */
  85 int     a12_cpu_ether;  /* relative CPU number with outside world access */
  86 int     a12_cpu_global; /* XXX used to construct MSN routing tables XXX */
  87
  88 void    a12_intr_register_xb(int (*)(void *));
  89 void    a12_intr_register_icw(int (*)(void *));
  90 void    configure_xb(void);
  91 void    configure_a12dc(void);
  92
  93 #endif