sys/arch/alpha/pci/cia.c

   1 /* $NetBSD: cia.c,v 1.68 2009/03/14 15:35:59 dsl Exp $ */
   2
   3 /*-
   4  * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
   9  * NASA Ames Research Center.
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  * 1. Redistributions of source code must retain the above copyright
  15  *    notice, this list of conditions and the following disclaimer.
  16  * 2. Redistributions in binary form must reproduce the above copyright
  17  *    notice, this list of conditions and the following disclaimer in the
  18  *    documentation and/or other materials provided with the distribution.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  21  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  22  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  23  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30  * POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 /*
  34  * Copyright (c) 1995, 1996 Carnegie-Mellon University.
  35  * All rights reserved.
  36  *
  37  * Author: Chris G. Demetriou
  38  *
  39  * Permission to use, copy, modify and distribute this software and
  40  * its documentation is hereby granted, provided that both the copyright
  41  * notice and this permission notice appear in all copies of the
  42  * software, derivative works or modified versions, and any portions
  43  * thereof, and that both notices appear in supporting documentation.
  44  *
  45  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
  46  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
  47  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
  48  *
  49  * Carnegie Mellon requests users of this software to return to
  50  *
  51  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
  52  *  School of Computer Science
  53  *  Carnegie Mellon University
  54  *  Pittsburgh PA 15213-3890
  55  *
  56  * any improvements or extensions that they make and grant Carnegie the
  57  * rights to redistribute these changes.
  58  */
  59
  60 #include "opt_dec_eb164.h"
  61 #include "opt_dec_kn20aa.h"
  62 #include "opt_dec_550.h"
  63 #include "opt_dec_1000a.h"
  64 #include "opt_dec_1000.h"
  65
  66 #include <sys/cdefs.h>                  /* RCS ID & Copyright macro defns */
  67
  68 __KERNEL_RCSID(0, "$NetBSD: cia.c,v 1.68 2009/03/14 15:35:59 dsl Exp $");
  69
  70 #include <sys/param.h>
  71 #include <sys/systm.h>
  72 #include <sys/kernel.h>
  73 #include <sys/malloc.h>
  74 #include <sys/device.h>
  75
  76 #include <uvm/uvm_extern.h>
  77
  78 #include <machine/autoconf.h>
  79 #include <machine/rpb.h>
  80 #include <machine/sysarch.h>
  81 #include <machine/alpha.h>
  82
  83 #include <dev/isa/isareg.h>
  84 #include <dev/isa/isavar.h>
  85
  86 #include <dev/pci/pcireg.h>
  87 #include <dev/pci/pcivar.h>
  88 #include <alpha/pci/ciareg.h>
  89 #include <alpha/pci/ciavar.h>
  90
  91 #ifdef DEC_KN20AA
  92 #include <alpha/pci/pci_kn20aa.h>
  93 #endif
  94 #ifdef DEC_EB164
  95 #include <alpha/pci/pci_eb164.h>
  96 #endif
  97 #ifdef DEC_550
  98 #include <alpha/pci/pci_550.h>
  99 #endif
 100 #ifdef DEC_1000A
 101 #include <alpha/pci/pci_1000a.h>
 102 #endif
 103 #ifdef DEC_1000
 104 #include <alpha/pci/pci_1000.h>
 105 #endif
 106
 107 int     ciamatch(struct device *, struct cfdata *, void *);
 108 void    ciaattach(struct device *, struct device *, void *);
 109
 110 CFATTACH_DECL(cia, sizeof(struct cia_softc),
 111     ciamatch, ciaattach, NULL, NULL);
 112
 113 extern struct cfdriver cia_cd;
 114
 115 int     cia_bus_get_window(int, int,
 116             struct alpha_bus_space_translation *);
 117
 118 /* There can be only one. */
 119 int ciafound;
 120 struct cia_config cia_configuration;
 121
 122 /*
 123  * This determines if we attempt to use BWX for PCI bus and config space
 124  * access.  Some systems, notably with Pyxis, don't fare so well unless
 125  * BWX is used.
 126  *
 127  * EXCEPT!  Some devices have a really hard time if BWX is used (WHY?!).
 128  * So, we decouple the uses for PCI config space and PCI bus space.
 129  *
 130  * FURTHERMORE!  The Pyxis, most notably earlier revs, really don't
 131  * do so well if you don't use BWX for bus access.  So we default to
 132  * forcing BWX on those chips.
 133  *
 134  * Geez.
 135  */
 136
 137 #ifndef CIA_PCI_USE_BWX
 138 #define CIA_PCI_USE_BWX 1
 139 #endif
 140
 141 #ifndef CIA_BUS_USE_BWX
 142 #define CIA_BUS_USE_BWX 0
 143 #endif
 144
 145 #ifndef CIA_PYXIS_FORCE_BWX
 146 #define CIA_PYXIS_FORCE_BWX 0
 147 #endif
 148
 149 int     cia_pci_use_bwx = CIA_PCI_USE_BWX;
 150 int     cia_bus_use_bwx = CIA_BUS_USE_BWX;
 151 int     cia_pyxis_force_bwx = CIA_PYXIS_FORCE_BWX;
 152
 153 int
 154 ciamatch(struct device *parent, struct cfdata *match, void *aux)
 155 {
 156         struct mainbus_attach_args *ma = aux;
 157
 158         /* Make sure that we're looking for a CIA. */
 159         if (strcmp(ma->ma_name, cia_cd.cd_name) != 0)
 160                 return (0);
 161
 162         if (ciafound)
 163                 return (0);
 164
 165         return (1);
 166 }
 167
 168 /*
 169  * Set up the chipset's function pointers.
 170  */
 171 void
 172 cia_init(struct cia_config *ccp, int mallocsafe)
 173 {
 174         int pci_use_bwx = cia_pci_use_bwx;
 175         int bus_use_bwx = cia_bus_use_bwx;
 176
 177         ccp->cc_hae_mem = REGVAL(CIA_CSR_HAE_MEM);
 178         ccp->cc_hae_io = REGVAL(CIA_CSR_HAE_IO);
 179         ccp->cc_rev = REGVAL(CIA_CSR_REV) & REV_MASK;
 180
 181         /*
 182          * Determine if we have a Pyxis.  Only two systypes can
 183          * have this: the EB164 systype (AlphaPC164LX and AlphaPC164SX)
 184          * and the DEC_550 systype (Miata).
 185          */
 186         if ((cputype == ST_EB164 &&
 187              (hwrpb->rpb_variation & SV_ST_MASK) >= SV_ST_ALPHAPC164LX_400) ||
 188             cputype == ST_DEC_550) {
 189                 ccp->cc_flags |= CCF_ISPYXIS;
 190                 if (cia_pyxis_force_bwx)
 191                         pci_use_bwx = bus_use_bwx = 1;
 192         }
 193
 194         /*
 195          * ALCOR/ALCOR2 Revisions >= 2 and Pyxis have the CNFG register.
 196          */
 197         if (ccp->cc_rev >= 2 || (ccp->cc_flags & CCF_ISPYXIS) != 0)
 198                 ccp->cc_cnfg = REGVAL(CIA_CSR_CNFG);
 199         else
 200                 ccp->cc_cnfg = 0;
 201
 202         /*
 203          * Use BWX iff:
 204          *
 205          *      - It hasn't been disbled by the user,
 206          *      - it's enabled in CNFG,
 207          *      - we're implementation version ev5,
 208          *      - BWX is enabled in the CPU's capabilities mask
 209          */
 210         if ((pci_use_bwx || bus_use_bwx) &&
 211             (ccp->cc_cnfg & CNFG_BWEN) != 0 &&
 212             (cpu_amask & ALPHA_AMASK_BWX) != 0) {
 213                 u_int32_t ctrl;
 214
 215                 if (pci_use_bwx)
 216                         ccp->cc_flags |= CCF_PCI_USE_BWX;
 217                 if (bus_use_bwx)
 218                         ccp->cc_flags |= CCF_BUS_USE_BWX;
 219
 220                 /*
 221                  * For whatever reason, the firmware seems to enable PCI
 222                  * loopback mode if it also enables BWX.  Make sure it's
 223                  * enabled if we have an old, buggy firmware rev.
 224                  */
 225                 alpha_mb();
 226                 ctrl = REGVAL(CIA_CSR_CTRL);
 227                 if ((ctrl & CTRL_PCI_LOOP_EN) == 0) {
 228                         REGVAL(CIA_CSR_CTRL) = ctrl | CTRL_PCI_LOOP_EN;
 229                         alpha_mb();
 230                 }
 231         }
 232
 233         if (!ccp->cc_initted) {
 234                 /* don't do these twice since they set up extents */
 235                 if (ccp->cc_flags & CCF_BUS_USE_BWX) {
 236                         cia_bwx_bus_io_init(&ccp->cc_iot, ccp);
 237                         cia_bwx_bus_mem_init(&ccp->cc_memt, ccp);
 238
 239                         /*
 240                          * We have one window for both PCI I/O and MEM
 241                          * in BWX mode.
 242                          */
 243                         alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_IO] = 1;
 244                         alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_MEM] = 1;
 245                 } else {
 246                         cia_swiz_bus_io_init(&ccp->cc_iot, ccp);
 247                         cia_swiz_bus_mem_init(&ccp->cc_memt, ccp);
 248
 249                         /*
 250                          * We have two I/O windows and 4 MEM windows in
 251                          * SWIZ mode.
 252                          */
 253                         alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_IO] = 2;
 254                         alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_MEM] = 4;
 255                 }
 256                 alpha_bus_get_window = cia_bus_get_window;
 257         }
 258         ccp->cc_mallocsafe = mallocsafe;
 259
 260         cia_pci_init(&ccp->cc_pc, ccp);
 261         alpha_pci_chipset = &ccp->cc_pc;
 262
 263         ccp->cc_initted = 1;
 264 }
 265
 266 void
 267 ciaattach(struct device *parent, struct device *self, void *aux)
 268 {
 269         struct cia_softc *sc = (struct cia_softc *)self;
 270         struct cia_config *ccp;
 271         struct pcibus_attach_args pba;
 272         char bits[64];
 273         const char *name;
 274         int pass;
 275
 276         /* note that we've attached the chipset; can't have 2 CIAs. */
 277         ciafound = 1;
 278
 279         /*
 280          * set up the chipset's info; done once at console init time
 281          * (maybe), but we must do it here as well to take care of things
 282          * that need to use memory allocation.
 283          */
 284         ccp = sc->sc_ccp = &cia_configuration;
 285         cia_init(ccp, 1);
 286
 287         if (ccp->cc_flags & CCF_ISPYXIS) {
 288                 name = "Pyxis";
 289                 pass = ccp->cc_rev;
 290         } else {
 291                 name = "ALCOR/ALCOR2";
 292                 pass = ccp->cc_rev + 1;
 293         }
 294
 295         printf(": DECchip 2117x Core Logic Chipset (%s), pass %d\n",
 296             name, pass);
 297         if (ccp->cc_cnfg) {
 298                 snprintb(bits, sizeof(bits), CIA_CSR_CNFG_BITS, ccp->cc_cnfg);
 299                 printf("%s: extended capabilities: %s\n", self->dv_xname, bits);
 300         }
 301
 302         switch (ccp->cc_flags & (CCF_PCI_USE_BWX|CCF_BUS_USE_BWX)) {
 303         case CCF_PCI_USE_BWX|CCF_BUS_USE_BWX:
 304                 name = "PCI config and bus";
 305                 break;
 306         case CCF_PCI_USE_BWX:
 307                 name = "PCI config";
 308                 break;
 309         case CCF_BUS_USE_BWX:
 310                 name = "bus";
 311                 break;
 312         default:
 313                 name = NULL;
 314                 break;
 315         }
 316         if (name != NULL)
 317                 printf("%s: using BWX for %s access\n", self->dv_xname, name);
 318
 319 #ifdef DEC_550
 320         if (cputype == ST_DEC_550 &&
 321             (hwrpb->rpb_variation & SV_ST_MASK) < SV_ST_MIATA_1_5) {
 322                 /*
 323                  * Miata 1 systems have a bug: DMA cannot cross
 324                  * an 8k boundary!  Make sure PCI read prefetching
 325                  * is disabled on these chips.  Note that secondary
 326                  * PCI busses don't have this problem, because of
 327                  * the way PPBs handle PCI read requests.
 328                  *
 329                  * In the 21174 Technical Reference Manual, this is
 330                  * actually documented as "Pyxis Pass 1", but apparently
 331                  * there are chips that report themselves as "Pass 1"
 332                  * which do not have the bug!  Miatas with the Cypress
 333                  * PCI-ISA bridge (i.e. Miata 1.5 and Miata 2) do not
 334                  * have the bug, so we use this check.
 335                  *
 336                  * NOTE: This bug is actually worked around in cia_dma.c,
 337                  * when direct-mapped DMA maps are created.
 338                  *
 339                  * XXX WE NEED TO THINK ABOUT HOW TO HANDLE THIS FOR
 340                  * XXX SGMAP DMA MAPPINGS!
 341                  */
 342                 u_int32_t ctrl;
 343
 344                 /* XXX no bets... */
 345                 printf("%s: WARNING: Pyxis pass 1 DMA bug; no bets...\n",
 346                     self->dv_xname);
 347
 348                 ccp->cc_flags |= CCF_PYXISBUG;
 349
 350                 alpha_mb();
 351                 ctrl = REGVAL(CIA_CSR_CTRL);
 352                 ctrl &= ~(CTRL_RD_TYPE|CTRL_RL_TYPE|CTRL_RM_TYPE);
 353                 REGVAL(CIA_CSR_CTRL) = ctrl;
 354                 alpha_mb();
 355         }
 356 #endif /* DEC_550 */
 357
 358         cia_dma_init(ccp);
 359
 360         switch (cputype) {
 361 #ifdef DEC_KN20AA
 362         case ST_DEC_KN20AA:
 363                 pci_kn20aa_pickintr(ccp);
 364                 break;
 365 #endif
 366
 367 #ifdef DEC_EB164
 368         case ST_EB164:
 369                 pci_eb164_pickintr(ccp);
 370                 break;
 371 #endif
 372
 373 #ifdef DEC_550
 374         case ST_DEC_550:
 375                 pci_550_pickintr(ccp);
 376                 break;
 377 #endif
 378
 379 #ifdef DEC_1000A
 380         case ST_DEC_1000A:
 381                 pci_1000a_pickintr(ccp, &ccp->cc_iot, &ccp->cc_memt,
 382                         &ccp->cc_pc);
 383                 break;
 384 #endif
 385
 386 #ifdef DEC_1000
 387         case ST_DEC_1000:
 388                 pci_1000_pickintr(ccp, &ccp->cc_iot, &ccp->cc_memt,
 389                         &ccp->cc_pc);
 390                 break;
 391 #endif
 392
 393         default:
 394                 panic("ciaattach: shouldn't be here, really...");
 395         }
 396
 397         pba.pba_iot = &ccp->cc_iot;
 398         pba.pba_memt = &ccp->cc_memt;
 399         pba.pba_dmat =
 400             alphabus_dma_get_tag(&ccp->cc_dmat_direct, ALPHA_BUS_PCI);
 401         pba.pba_dmat64 = NULL;
 402         pba.pba_pc = &ccp->cc_pc;
 403         pba.pba_bus = 0;
 404         pba.pba_bridgetag = NULL;
 405         pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED;
 406         if ((ccp->cc_flags & CCF_PYXISBUG) == 0)
 407                 pba.pba_flags |= PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY |
 408                     PCI_FLAGS_MWI_OKAY;
 409         config_found_ia(self, "pcibus", &pba, pcibusprint);
 410 }
 411
 412 int
 413 cia_bus_get_window(int type, int window, struct alpha_bus_space_translation *abst)
 414 {
 415         struct cia_config *ccp = &cia_configuration;
 416         bus_space_tag_t st;
 417
 418         switch (type) {
 419         case ALPHA_BUS_TYPE_PCI_IO:
 420                 st = &ccp->cc_iot;
 421                 break;
 422
 423         case ALPHA_BUS_TYPE_PCI_MEM:
 424                 st = &ccp->cc_memt;
 425                 break;
 426
 427         default:
 428                 panic("cia_bus_get_window");
 429         }
 430
 431         return (alpha_bus_space_get_window(st, window, abst));
 432 }
 433
 434 void
 435 cia_pyxis_intr_enable(int irq, int onoff)
 436 {
 437         u_int64_t imask;
 438         int s;
 439
 440 #if 0
 441         printf("cia_pyxis_intr_enable: %s %d\n",
 442             onoff ? "enabling" : "disabling", irq);
 443 #endif
 444
 445         s = splhigh();
 446         alpha_mb();
 447         imask = REGVAL64(PYXIS_INT_MASK);
 448         if (onoff)
 449                 imask |= (1UL << irq);
 450         else
 451                 imask &= ~(1UL << irq);
 452         REGVAL64(PYXIS_INT_MASK) = imask;
 453         alpha_mb();
 454         splx(s);
 455 }