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[netbsd-mini2440.git] / sys / arch / alpha / pci / cia_swiz_bus_mem.c
blobb165924e5fa05189a8ccb36002439166323419fe
1 /* $NetBSD: cia_swiz_bus_mem.c,v 1.15 1997/09/02 13:19:22 thorpej Exp $ */
3 /*
4 * Copyright (c) 1996 Carnegie-Mellon University.
5 * All rights reserved.
7 * Author: Chris G. Demetriou
9 * Permission to use, copy, modify and distribute this software and
10 * its documentation is hereby granted, provided that both the copyright
11 * notice and this permission notice appear in all copies of the
12 * software, derivative works or modified versions, and any portions
13 * thereof, and that both notices appear in supporting documentation.
15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
19 * Carnegie Mellon requests users of this software to return to
21 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
22 * School of Computer Science
23 * Carnegie Mellon University
24 * Pittsburgh PA 15213-3890
26 * any improvements or extensions that they make and grant Carnegie the
27 * rights to redistribute these changes.
30 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
32 __KERNEL_RCSID(1, "$NetBSD: cia_swiz_bus_mem.c,v 1.15 1997/09/02 13:19:22 thorpej Exp $");
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/malloc.h>
37 #include <sys/syslog.h>
38 #include <sys/device.h>
40 #include <uvm/uvm_extern.h>
42 #include <machine/bus.h>
44 #include <alpha/pci/ciareg.h>
45 #include <alpha/pci/ciavar.h>
47 #define CHIP cia_swiz
49 #define CHIP_EX_MALLOC_SAFE(v) (((struct cia_config *)(v))->cc_mallocsafe)
50 #define CHIP_D_MEM_EXTENT(v) (((struct cia_config *)(v))->cc_d_mem_ex)
51 #define CHIP_S_MEM_EXTENT(v) (((struct cia_config *)(v))->cc_s_mem_ex)
53 /* Dense region 1 */
54 #define CHIP_D_MEM_W1_BUS_START(v) 0x00000000UL
55 #define CHIP_D_MEM_W1_BUS_END(v) 0xffffffffUL
56 #define CHIP_D_MEM_W1_SYS_START(v) CIA_PCI_DENSE
57 #define CHIP_D_MEM_W1_SYS_END(v) (CIA_PCI_DENSE + 0xffffffffUL)
59 /* Sparse region 1 */
60 #define CHIP_S_MEM_W1_BUS_START(v) \
61 HAE_MEM_REG1_START(((struct cia_config *)(v))->cc_hae_mem)
62 #define CHIP_S_MEM_W1_BUS_END(v) \
63 (CHIP_S_MEM_W1_BUS_START(v) + HAE_MEM_REG1_MASK)
64 #define CHIP_S_MEM_W1_SYS_START(v) \
65 CIA_PCI_SMEM1
66 #define CHIP_S_MEM_W1_SYS_END(v) \
67 (CIA_PCI_SMEM1 + ((HAE_MEM_REG1_MASK + 1) << 5) - 1)
69 /* Sparse region 2 */
70 #define CHIP_S_MEM_W2_BUS_START(v) \
71 HAE_MEM_REG2_START(((struct cia_config *)(v))->cc_hae_mem)
72 #define CHIP_S_MEM_W2_BUS_END(v) \
73 (CHIP_S_MEM_W2_BUS_START(v) + HAE_MEM_REG2_MASK)
74 #define CHIP_S_MEM_W2_SYS_START(v) \
75 CIA_PCI_SMEM2
76 #define CHIP_S_MEM_W2_SYS_END(v) \
77 (CIA_PCI_SMEM2 + ((HAE_MEM_REG2_MASK + 1) << 5) - 1)
79 /* Sparse region 3 */
80 #define CHIP_S_MEM_W3_BUS_START(v) \
81 HAE_MEM_REG3_START(((struct cia_config *)(v))->cc_hae_mem)
82 #define CHIP_S_MEM_W3_BUS_END(v) \
83 (CHIP_S_MEM_W3_BUS_START(v) + HAE_MEM_REG3_MASK)
84 #define CHIP_S_MEM_W3_SYS_START(v) \
85 CIA_PCI_SMEM3
86 #define CHIP_S_MEM_W3_SYS_END(v) \
87 (CIA_PCI_SMEM3 + ((HAE_MEM_REG3_MASK + 1) << 5) - 1)
89 #include <alpha/pci/pci_swiz_bus_mem_chipdep.c>