sys/arch/alpha/pci/dwlpx.c

   1 /* $NetBSD: dwlpx.c,v 1.33 2009/03/14 14:45:53 dsl Exp $ */
   2
   3 /*
   4  * Copyright (c) 1997 by Matthew Jacob
   5  * NASA AMES Research Center.
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice immediately at the beginning of the file, without modification,
  13  *    this list of conditions, and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. The name of the author may not be used to endorse or promote products
  18  *    derived from this software without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
  24  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  30  * SUCH DAMAGE.
  31  */
  32
  33 #include <sys/cdefs.h>                  /* RCS ID & Copyright macro defns */
  34
  35 __KERNEL_RCSID(0, "$NetBSD: dwlpx.c,v 1.33 2009/03/14 14:45:53 dsl Exp $");
  36
  37 #include <sys/param.h>
  38 #include <sys/systm.h>
  39 #include <sys/kernel.h>
  40 #include <sys/device.h>
  41
  42 #include <uvm/uvm_extern.h>
  43
  44 #include <machine/autoconf.h>
  45
  46 #include <dev/pci/pcireg.h>
  47 #include <dev/pci/pcivar.h>
  48
  49 #include <alpha/tlsb/tlsbreg.h>
  50 #include <alpha/tlsb/kftxxvar.h>
  51 #include <alpha/tlsb/kftxxreg.h>
  52 #include <alpha/pci/dwlpxreg.h>
  53 #include <alpha/pci/dwlpxvar.h>
  54 #include <alpha/pci/pci_kn8ae.h>
  55
  56 #define KV(_addr)       ((void *)ALPHA_PHYS_TO_K0SEG((_addr)))
  57 #define DWLPX_SYSBASE(sc)       \
  58             ((((unsigned long)((sc)->dwlpx_node - 4))   << 36) |        \
  59              (((unsigned long) (sc)->dwlpx_hosenum)     << 34) |        \
  60              (1LL                                       << 39))
  61 #define DWLPX_SYSBASE1(node, hosenum)   \
  62             ((((unsigned long)(node - 4))       << 36) |        \
  63              (((unsigned long) hosenum)         << 34) |        \
  64              (1LL                                       << 39))
  65
  66
  67 static int      dwlpxmatch(struct device *, struct cfdata *, void *);
  68 static void     dwlpxattach(struct device *, struct device *, void *);
  69 CFATTACH_DECL(dwlpx, sizeof(struct dwlpx_softc),
  70     dwlpxmatch, dwlpxattach, NULL, NULL);
  71
  72 extern struct cfdriver dwlpx_cd;
  73
  74 void    dwlpx_errintr(void *, u_long vec);
  75
  76 static int
  77 dwlpxmatch(struct device *parent, struct cfdata *cf, void *aux)
  78 {
  79         struct kft_dev_attach_args *ka = aux;
  80         unsigned long ls;
  81         u_int32_t ctl;
  82
  83         if (strcmp(ka->ka_name, dwlpx_cd.cd_name) != 0)
  84                 return (0);
  85
  86         ls = DWLPX_SYSBASE1(ka->ka_node, ka->ka_hosenum);
  87
  88         /*
  89          * Probe the first HPC to make sure this really is a dwlpx and
  90          * nothing else.
  91          */
  92         if (badaddr(KV(PCIA_CTL(1) + ls), sizeof (ctl)) != 0) {
  93                 /*
  94                  * If we are here something went wrong. One reason
  95                  * could be that this is a dwlma and not a dwlpx.
  96                  *
  97                  * We can not clear potential illegal CSR errors here
  98                  * since it is unknown hardware.
  99                  */
 100                 return (0);
 101         }
 102
 103         return (1);
 104 }
 105
 106 static void
 107 dwlpxattach(struct device *parent, struct device *self, void *aux)
 108 {
 109         static int once = 0;
 110         struct dwlpx_softc *sc = (struct dwlpx_softc *)self;
 111         struct dwlpx_config *ccp = &sc->dwlpx_cc;
 112         struct kft_dev_attach_args *ka = aux;
 113         struct pcibus_attach_args pba;
 114         u_int32_t pcia_present;
 115
 116         sc->dwlpx_node = ka->ka_node;
 117         sc->dwlpx_dtype = ka->ka_dtype;
 118         sc->dwlpx_hosenum = ka->ka_hosenum;
 119
 120         dwlpx_init(sc);
 121         dwlpx_dma_init(ccp);
 122
 123         pcia_present = REGVAL(PCIA_PRESENT + ccp->cc_sysbase);
 124         printf(": PCIA rev. %d, STD I/O %spresent, %dK S/G entries\n",
 125             (pcia_present >> PCIA_PRESENT_REVSHIFT) & PCIA_PRESENT_REVMASK,
 126             (pcia_present & PCIA_PRESENT_STDIO) == 0 ? "not " : "",
 127             sc->dwlpx_sgmapsz == DWLPX_SG128K ? 128 : 32);
 128
 129 #if 0
 130         {
 131                 int hpc, slot, slotval;
 132                 const char *str;
 133                 for (hpc = 0; hpc < sc->dwlpx_nhpc; hpc++) {
 134                         for (slot = 0; slot < 4; slot++) {
 135                                 slotval = (pcia_present >>
 136                                     PCIA_PRESENT_SLOTSHIFT(hpc, slot)) &
 137                                     PCIA_PRESENT_SLOT_MASK;
 138                                 if (slotval == PCIA_PRESENT_SLOT_NONE)
 139                                         continue;
 140                                 switch (slotval) {
 141                                 case PCIA_PRESENT_SLOT_25W:
 142                                         str = "25";
 143                                         break;
 144                                 case PCIA_PRESENT_SLOT_15W:
 145                                         str = "15";
 146                                         break;
 147                                 case PCIA_PRESENT_SLOW_7W:
 148                                 default:                /* XXX gcc */
 149                                         str = "7.5";
 150                                         break;
 151                                 }
 152                                 printf("%s: hpc %d slot %d: %s watt module\n",
 153                                     sc->dwlpx_dev.dv_xname, hpc, slot, str);
 154                         }
 155                 }
 156         }
 157 #endif
 158
 159         if (once == 0) {
 160                 /*
 161                  * Set up interrupts
 162                  */
 163                 pci_kn8ae_pickintr(&sc->dwlpx_cc, 1);
 164                 once++;
 165         } else {
 166                 pci_kn8ae_pickintr(&sc->dwlpx_cc, 0);
 167         }
 168
 169         /*
 170          * Attach PCI bus
 171          */
 172         pba.pba_iot = &sc->dwlpx_cc.cc_iot;
 173         pba.pba_memt = &sc->dwlpx_cc.cc_memt;
 174         pba.pba_dmat =  /* start with direct, may change... */
 175             alphabus_dma_get_tag(&sc->dwlpx_cc.cc_dmat_direct, ALPHA_BUS_PCI);
 176         pba.pba_dmat64 = NULL;
 177         pba.pba_pc = &sc->dwlpx_cc.cc_pc;
 178         pba.pba_bus = 0;
 179         pba.pba_bridgetag = NULL;
 180         pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED |
 181             PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY;
 182         config_found_ia(self, "pcibus", &pba, pcibusprint);
 183 }
 184
 185 void
 186 dwlpx_init(struct dwlpx_softc *sc)
 187 {
 188         u_int32_t ctl;
 189         struct dwlpx_config *ccp = &sc->dwlpx_cc;
 190         unsigned long vec, ls = DWLPX_SYSBASE(sc);
 191         int i;
 192
 193         if (ccp->cc_initted == 0) {
 194                 /*
 195                  * On reads, you get a fault if you read a nonexisted HPC.
 196                  * We know the internal KFTIA hose (hose 0) has only 2 HPCs,
 197                  * but we can also actually probe for HPCs.
 198                  * Assume at least one.
 199                  */
 200                 for (sc->dwlpx_nhpc = 1; sc->dwlpx_nhpc < NHPC;
 201                     sc->dwlpx_nhpc++) {
 202                         if (badaddr(KV(PCIA_CTL(sc->dwlpx_nhpc) + ls),
 203                             sizeof (ctl)) != 0) {
 204                                 break;
 205                         }
 206                 }
 207                 if (sc->dwlpx_nhpc != NHPC) {
 208                         /* clear (potential) Illegal CSR Address Error */
 209                         REGVAL(PCIA_ERR(0) + DWLPX_SYSBASE(sc)) =
 210                                 PCIA_ERR_ALLERR;
 211                 }
 212
 213                 dwlpx_bus_io_init(&ccp->cc_iot, ccp);
 214                 dwlpx_bus_mem_init(&ccp->cc_memt, ccp);
 215         }
 216         dwlpx_pci_init(&ccp->cc_pc, ccp);
 217         ccp->cc_sc = sc;
 218
 219         /*
 220          * Establish a precalculated base for convenience's sake.
 221          */
 222         ccp->cc_sysbase = ls;
 223
 224         /*
 225          * If there are only 2 HPCs, then the 'present' register is not
 226          * implemented, so there will only ever be 32K SG entries. Otherwise
 227          * any revision greater than zero will have 128K entries.
 228          */
 229         ctl = REGVAL(PCIA_PRESENT + ccp->cc_sysbase);
 230         if (sc->dwlpx_nhpc == 2) {
 231                 sc->dwlpx_sgmapsz = DWLPX_SG32K;
 232 #if 0
 233         /*
 234          * As of 2/25/98- When I enable SG128K, and then have to flip
 235          * TBIT below, I get bad SGRAM errors. We'll fix this later
 236          * if this gets important.
 237          */
 238         } else if ((ctl >> PCIA_PRESENT_REVSHIFT) & PCIA_PRESENT_REVMASK) {
 239                 sc->dwlpx_sgmapsz = DWLPX_SG128K;
 240 #endif
 241         } else {
 242                 sc->dwlpx_sgmapsz = DWLPX_SG32K;
 243         }
 244
 245         /*
 246          * Set up interrupt stuff for this DWLPX.
 247          *
 248          * Note that all PCI interrupt pins are disabled at this time.
 249          *
 250          * Do this even for all HPCs- even for the nonexistent
 251          * one on hose zero of a KFTIA.
 252          */
 253         vec = scb_alloc(dwlpx_errintr, sc);
 254         if (vec == SCB_ALLOC_FAILED)
 255                 panic("%s: unable to allocate error vector",
 256                     sc->dwlpx_dev.dv_xname);
 257         printf("%s: error interrupt at vector 0x%lx\n",
 258             sc->dwlpx_dev.dv_xname, vec);
 259         for (i = 0; i < NHPC; i++) {
 260                 REGVAL(PCIA_IMASK(i) + ccp->cc_sysbase) = DWLPX_IMASK_DFLT;
 261                 REGVAL(PCIA_ERRVEC(i) + ccp->cc_sysbase) = vec;
 262         }
 263
 264         /*
 265          * Establish HAE values, as well as make sure of sanity elsewhere.
 266          */
 267         for (i = 0; i < sc->dwlpx_nhpc; i++) {
 268                 ctl = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase);
 269                 ctl &= 0x0fffffff;
 270                 ctl &= ~(PCIA_CTL_MHAE(0x1f) | PCIA_CTL_IHAE(0x1f));
 271                 /*
 272                  * I originally also had it or'ing in 3, which makes no sense.
 273                  */
 274
 275                 ctl |= PCIA_CTL_RMMENA | PCIA_CTL_RMMARB;
 276
 277                 /*
 278                  * Only valid if we're attached to a KFTIA or a KTHA.
 279                  */
 280                 ctl |= PCIA_CTL_3UP;
 281
 282                 ctl |= PCIA_CTL_CUTENA;
 283
 284                 /*
 285                  * Fit in appropriate S/G Map Ram size.
 286                  */
 287                 if (sc->dwlpx_sgmapsz == DWLPX_SG32K)
 288                         ctl |= PCIA_CTL_SG32K;
 289                 else if (sc->dwlpx_sgmapsz == DWLPX_SG128K)
 290                         ctl |= PCIA_CTL_SG128K;
 291                 else
 292                         ctl |= PCIA_CTL_SG32K;
 293
 294                 REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = ctl;
 295         }
 296         /*
 297          * Enable TBIT if required
 298          */
 299         if (sc->dwlpx_sgmapsz == DWLPX_SG128K)
 300                 REGVAL(PCIA_TBIT + ccp->cc_sysbase) = 1;
 301         alpha_mb();
 302         ccp->cc_initted = 1;
 303 }
 304
 305 void
 306 dwlpx_errintr(void *arg, unsigned long vec)
 307 {
 308         struct dwlpx_softc *sc = arg;
 309         struct dwlpx_config *ccp = &sc->dwlpx_cc;
 310         int i;
 311         struct {
 312                 u_int32_t err;
 313                 u_int32_t addr;
 314         } hpcs[NHPC];
 315
 316         for (i = 0; i < sc->dwlpx_nhpc; i++) {
 317                 hpcs[i].err = REGVAL(PCIA_ERR(i) + ccp->cc_sysbase);
 318                 hpcs[i].addr = REGVAL(PCIA_FADR(i) + ccp->cc_sysbase);
 319         }
 320         printf("%s: node %d hose %d error interrupt\n",
 321             sc->dwlpx_dev.dv_xname, sc->dwlpx_node, sc->dwlpx_hosenum);
 322
 323         for (i = 0; i < sc->dwlpx_nhpc; i++) {
 324                 if ((hpcs[i].err & PCIA_ERR_ERROR) == 0)
 325                         continue;
 326                 printf("\tHPC %d: ERR=0x%08x; DMA %s Memory, "
 327                         "Failing Address 0x%x\n",
 328                         i, hpcs[i].err, hpcs[i].addr & 0x1? "write to" :
 329                         "read from", hpcs[i].addr & ~3);
 330                 if (hpcs[i].err & PCIA_ERR_SERR_L)
 331                         printf("\t       PCI device asserted SERR_L\n");
 332                 if (hpcs[i].err & PCIA_ERR_ILAT)
 333                         printf("\t       Incremental Latency Exceeded\n");
 334                 if (hpcs[i].err & PCIA_ERR_SGPRTY)
 335                         printf("\t       CPU access of SG RAM Parity Error\n");
 336                 if (hpcs[i].err & PCIA_ERR_ILLCSR)
 337                         printf("\t       Illegal CSR Address Error\n");
 338                 if (hpcs[i].err & PCIA_ERR_PCINXM)
 339                         printf("\t       Nonexistent PCI Address Error\n");
 340                 if (hpcs[i].err & PCIA_ERR_DSCERR)
 341                         printf("\t       PCI Target Disconnect Error\n");
 342                 if (hpcs[i].err & PCIA_ERR_ABRT)
 343                         printf("\t       PCI Target Abort Error\n");
 344                 if (hpcs[i].err & PCIA_ERR_WPRTY)
 345                         printf("\t       PCI Write Parity Error\n");
 346                 if (hpcs[i].err & PCIA_ERR_DPERR)
 347                         printf("\t       PCI Data Parity Error\n");
 348                 if (hpcs[i].err & PCIA_ERR_APERR)
 349                         printf("\t       PCI Address Parity Error\n");
 350                 if (hpcs[i].err & PCIA_ERR_DFLT)
 351                         printf("\t       SG Map RAM Invalid Entry Error\n");
 352                 if (hpcs[i].err & PCIA_ERR_DPRTY)
 353                         printf("\t       DMA access of SG RAM Parity Error\n");
 354                 if (hpcs[i].err & PCIA_ERR_DRPERR)
 355                         printf("\t       DMA Read Return Parity Error\n");
 356                 if (hpcs[i].err & PCIA_ERR_MABRT)
 357                         printf("\t       PCI Master Abort Error\n");
 358                 if (hpcs[i].err & PCIA_ERR_CPRTY)
 359                         printf("\t       CSR Parity Error\n");
 360                 if (hpcs[i].err & PCIA_ERR_COVR)
 361                         printf("\t       CSR Overrun Error\n");
 362                 if (hpcs[i].err & PCIA_ERR_MBPERR)
 363                         printf("\t       Mailbox Parity Error\n");
 364                 if (hpcs[i].err & PCIA_ERR_MBILI)
 365                         printf("\t       Mailbox Illegal Length Error\n");
 366                 REGVAL(PCIA_ERR(i) + ccp->cc_sysbase) = hpcs[i].err;
 367         }
 368 }