sys/arch/alpha/pci/dwlpxreg.h

   1 /* $NetBSD: dwlpxreg.h,v 1.9 1998/03/21 22:02:42 mjacob Exp $ */
   2
   3 /*
   4  * Copyright (c) 1997 by Matthew Jacob
   5  * NASA AMES Research Center.
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice immediately at the beginning of the file, without modification,
  13  *    this list of conditions, and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. The name of the author may not be used to endorse or promote products
  18  *    derived from this software without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
  24  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  30  * SUCH DAMAGE.
  31  */
  32
  33 /*
  34  * Taken from combinations of:
  35  *
  36  *      ``DWLPA and DWLPB PCI Adapter Technical Manual,
  37  *        Order Number: EK-DWLPX-TM.A01''
  38  *
  39  *  and
  40  *
  41  *      ``AlphaServer 8200/8400 System Technical Manual,
  42  *        Order Number EK-T8030-TM. A01''
  43  */
  44
  45 #define REGVAL(r)       (*(volatile int32_t *)ALPHA_PHYS_TO_K0SEG(r))
  46
  47 /*
  48  * There are (potentially) 4 I/O hoses, and there are three
  49  * (electrically distinct) PCI busses per DWLPX (which appear
  50  * as one logical PCI bus).
  51  *
  52  * A CPU to PCI Address Mapping looks (roughly) like this:
  53  *
  54  *  39 38........36 35.34 33.....32 31....................5 4.........3 2...0
  55  *  --------------------------------------------------------------------------
  56  *  |1| I/O NodeID |Hose#|PCI Space|Byte Aligned I/O <26:0>|Byte Length|0 0 0|
  57  *  --------------------------------------------------------------------------
  58  *
  59  * I/O Node is the TLSB Node ID minus 4. Don't ask.
  60  */
  61
  62 #define NHPC    3
  63
  64 /*
  65  * Address Space Cookies
  66  *
  67  * (lacking I/O Node ID and Hose Numbers)
  68  */
  69
  70 #define DWLPX_PCI_DENSE         0x000000000UL
  71 #define DWLPX_PCI_SPARSE        0x100000000UL
  72 #define DWLPX_PCI_IOSPACE       0x200000000UL
  73 #define DWLPX_PCI_CONF          0x300000000UL
  74
  75 /*
  76  * PCIA Interface Adapter Register Addresses (Offsets from Node Address)
  77  *
  78  *
  79  * Addresses are for Hose #0, PCI bus #0. Macros below will offset
  80  * per bus. I/O Hose and TLSB Node I/D offsets must be added separately.
  81  */
  82
  83 #define _PCIA_CTL       0x380000000UL   /* PCI 0 Bus Control */
  84 #define _PCIA_MRETRY    0x380000080UL   /* PCI 0 Master Retry Limit */
  85 #define _PCIA_GPR       0x380000100UL   /* PCI 0 General Purpose */
  86 #define _PCIA_ERR       0x380000180UL   /* PCI 0 Error Summary */
  87 #define _PCIA_FADR      0x380000200UL   /* PCI 0 Failing Address */
  88 #define _PCIA_IMASK     0x380000280UL   /* PCI 0 Interrupt Mask */
  89 #define _PCIA_DIAG      0x380000300UL   /* PCI 0 Diagnostic  */
  90 #define _PCIA_IPEND     0x380000380UL   /* PCI 0 Interrupt Pending */
  91 #define _PCIA_IPROG     0x380000400UL   /* PCI 0 Interrupt in Progress */
  92 #define _PCIA_WMASK_A   0x380000480UL   /* PCI 0 Window Mask A */
  93 #define _PCIA_WBASE_A   0x380000500UL   /* PCI 0 Window Base A */
  94 #define _PCIA_TBASE_A   0x380000580UL   /* PCI 0 Window Translated Base A */
  95 #define _PCIA_WMASK_B   0x380000600UL   /* PCI 0 Window Mask B */
  96 #define _PCIA_WBASE_B   0x380000680UL   /* PCI 0 Window Base B */
  97 #define _PCIA_TBASE_B   0x380000700UL   /* PCI 0 Window Translated Base B */
  98 #define _PCIA_WMASK_C   0x380000780UL   /* PCI 0 Window Mask C */
  99 #define _PCIA_WBASE_C   0x380000800UL   /* PCI 0 Window Base C */
 100 #define _PCIA_TBASE_C   0x380000880UL   /* PCI 0 Window Translated Base C */
 101 #define _PCIA_ERRVEC    0x380000900UL   /* PCI 0 Error Interrupt Vector */
 102 #define _PCIA_DEVVEC    0x380001000UL   /* PCI 0 Device Interrupt Vector */
 103
 104
 105 #define PCIA_CTL(hpc)           (_PCIA_CTL      + (0x200000 * (hpc)))
 106 #define PCIA_MRETRY(hpc)        (_PCIA_MRETRY   + (0x200000 * (hpc)))
 107 #define PCIA_GPR(hpc)           (_PCIA_GPR      + (0x200000 * (hpc)))
 108 #define PCIA_ERR(hpc)           (_PCIA_ERR      + (0x200000 * (hpc)))
 109 #define PCIA_FADR(hpc)          (_PCIA_FADR     + (0x200000 * (hpc)))
 110 #define PCIA_IMASK(hpc)         (_PCIA_IMASK    + (0x200000 * (hpc)))
 111 #define PCIA_DIAG(hpc)          (_PCIA_DIAG     + (0x200000 * (hpc)))
 112 #define PCIA_IPEND(hpc)         (_PCIA_IPEND    + (0x200000 * (hpc)))
 113 #define PCIA_IPROG(hpc)         (_PCIA_IPROG    + (0x200000 * (hpc)))
 114 #define PCIA_WMASK_A(hpc)       (_PCIA_WMASK_A  + (0x200000 * (hpc)))
 115 #define PCIA_WBASE_A(hpc)       (_PCIA_WBASE_A  + (0x200000 * (hpc)))
 116 #define PCIA_TBASE_A(hpc)       (_PCIA_TBASE_A  + (0x200000 * (hpc)))
 117 #define PCIA_WMASK_B(hpc)       (_PCIA_WMASK_B  + (0x200000 * (hpc)))
 118 #define PCIA_WBASE_B(hpc)       (_PCIA_WBASE_B  + (0x200000 * (hpc)))
 119 #define PCIA_TBASE_B(hpc)       (_PCIA_TBASE_B  + (0x200000 * (hpc)))
 120 #define PCIA_WMASK_C(hpc)       (_PCIA_WMASK_C  + (0x200000 * (hpc)))
 121 #define PCIA_WBASE_C(hpc)       (_PCIA_WBASE_C  + (0x200000 * (hpc)))
 122 #define PCIA_TBASE_C(hpc)       (_PCIA_TBASE_C  + (0x200000 * (hpc)))
 123 #define PCIA_ERRVEC(hpc)        (_PCIA_ERRVEC   + (0x200000 * (hpc)))
 124
 125 #define PCIA_DEVVEC(hpc, subslot, ipin) \
 126  (_PCIA_DEVVEC + (0x200000 * (hpc)) + ((subslot) * 0x200) + ((ipin-1) * 0x80))
 127
 128 #define PCIA_SCYCLE     0x380002000UL   /* PCI Special Cycle */
 129 #define PCIA_IACK       0x380002080UL   /* PCI Interrupt Acknowledge */
 130
 131 #define PCIA_PRESENT    0x380800000UL   /* PCI Slot Present */
 132 #define PCIA_TBIT       0x380A00000UL   /* PCI TBIT */
 133 #define PCIA_MCTL       0x380C00000UL   /* PCI Module Control */
 134 #define PCIA_IBR        0x380E00000UL   /* PCI Information Base Repair */
 135
 136 /*
 137  * Bits in PCIA_CTL register
 138  */
 139 #define PCIA_CTL_SG32K  (0<<25)         /* 32K SGMAP entries */
 140 #define PCIA_CTL_SG64K  (1<<25)         /* 64K SGMAP entries */
 141 #define PCIA_CTL_SG128K (3<<25)         /* 128K SGMAP entries */
 142 #define PCIA_CTL_SG0K   (2<<25)         /* disable SGMAP in HPC */
 143 #define PCIA_CTL_4UP    (0<<23)         /* 4 Up Hose buffers */
 144 #define PCIA_CTL_1UP    (1<<23)         /* 1 "" */
 145 #define PCIA_CTL_2UP    (2<<23)         /* 2 "" */
 146 #define PCIA_CTL_3UP    (3<<23)         /* 3 "" (normal) */
 147 #define PCIA_CTL_RMM4X  (1<<22)         /* Read Multiple 2X -> 4X */
 148 #define PCIA_CTL_RMMENA (1<<21)         /* Read Multiple Enable */
 149 #define PCIA_CTL_RMMARB (1<<20)         /* RMM Multiple Arb */
 150 #define PCIA_CTL_HAEDIS (1<<19)         /* Hardware Address Ext. Disable */
 151 #define PCIA_CTL_MHAE(x) ((x&0x1f)<<14) /* Memory Hardware Address Extension */
 152 #define PCIA_CTL_IHAE(x) ((x&0x1f)<<9)  /* I/O Hardware Address Extension */
 153 #define PCIA_CTL_CUTENA (1<<8)          /* PCI Cut Through */
 154 #define PCIA_CTL_CUT(x) ((x&0x7)<<4)    /* PCI Cut Through Size */
 155 #define PCIA_CTL_PRESET (1<<3)          /* PCI Reset */
 156 #define PCIA_CTL_DTHROT (1<<2)          /* DMA downthrottle */
 157 #define PCIA_CTL_T1CYC  (1<<0)          /* Type 1 Configuration Cycle */
 158
 159 /*
 160  * Bits in PCIA_ERR. All are "Write 1 to clear".
 161  */
 162 #define PCIA_ERR_SERR_L (1<<18)         /* PCI device asserted SERR_L */
 163 #define PCIA_ERR_ILAT   (1<<17)         /* Incremental Latency Exceeded */
 164 #define PCIA_ERR_SGPRTY (1<<16)         /* CPU access of SG RAM Parity Error */
 165 #define PCIA_ERR_ILLCSR (1<<15)         /* Illegal CSR Address Error */
 166 #define PCIA_ERR_PCINXM (1<<14)         /* Nonexistent PCI Address Error */
 167 #define PCIA_ERR_DSCERR (1<<13)         /* PCI Target Disconnect Error */
 168 #define PCIA_ERR_ABRT   (1<<12)         /* PCI Target Abort Error */
 169 #define PCIA_ERR_WPRTY  (1<<11)         /* PCI Write Parity Error */
 170 #define PCIA_ERR_DPERR  (1<<10)         /* PCI Data Parity Error */
 171 #define PCIA_ERR_APERR  (1<<9)          /* PCI Address Parity Error */
 172 #define PCIA_ERR_DFLT   (1<<8)          /* SG Map RAM Invalid Entry Error */
 173 #define PCIA_ERR_DPRTY  (1<<7)          /* DMA access of SG RAM Parity Error */
 174 #define PCIA_ERR_DRPERR (1<<6)          /* DMA Read Return Parity Error */
 175 #define PCIA_ERR_MABRT  (1<<5)          /* PCI Master Abort Error */
 176 #define PCIA_ERR_CPRTY  (1<<4)          /* CSR Parity Error */
 177 #define PCIA_ERR_COVR   (1<<3)          /* CSR Overrun Error */
 178 #define PCIA_ERR_MBPERR (1<<2)          /* Mailbox Parity Error */
 179 #define PCIA_ERR_MBILI  (1<<1)          /* Mailbox Illegal Length Error */
 180 #define PCIA_ERR_ERROR  (1<<0)          /* Summary Error */
 181 #define PCIA_ERR_ALLERR ((1<<19) - 1)
 182
 183 /*
 184  * Bits in PCIA_PRESENT.
 185  */
 186 #define PCIA_PRESENT_REVSHIFT   25      /* shift by this to get revision */
 187 #define PCIA_PRESENT_REVMASK    0xf
 188 #define PCIA_PRESENT_STDIO      0x01000000 /* STD I/O bridge present */
 189 #define PCIA_PRESENT_SLOTSHIFT(hpc, slot) \
 190                 (((hpc) << 3) + ((slot) << 1))
 191 #define PCIA_PRESENT_SLOT_MASK  0x3
 192 #define PCIA_PRESENT_SLOT_NONE  0x0
 193 #define PCIA_PRESENT_SLOT_25W   0x1
 194 #define PCIA_PRESENT_SLOT_15W   0x2
 195 #define PCIA_PRESENT_SLOW_7W    0x3
 196
 197 /*
 198  * Location of the DWLPx SGMAP page table SRAM.
 199  */
 200 #define PCIA_SGMAP_PT   0x381000000UL
 201
 202 /*
 203  * Values for PCIA_WMASK_x
 204  */
 205 #define PCIA_WMASK_MASK 0xffff0000      /* mask of valid bits */
 206 #define PCIA_WMASK_64K  0x00000000
 207 #define PCIA_WMASK_128K 0x00010000
 208 #define PCIA_WMASK_256K 0x00030000
 209 #define PCIA_WMASK_512K 0x00070000
 210 #define PCIA_WMASK_1M   0x000f0000
 211 #define PCIA_WMASK_2M   0x001f0000
 212 #define PCIA_WMASK_4M   0x003f0000
 213 #define PCIA_WMASK_8M   0x007f0000
 214 #define PCIA_WMASK_16M  0x00ff0000
 215 #define PCIA_WMASK_32M  0x01ff0000
 216 #define PCIA_WMASK_64M  0x03ff0000
 217 #define PCIA_WMASK_128M 0x07ff0000
 218 #define PCIA_WMASK_256M 0x0fff0000
 219 #define PCIA_WMASK_512M 0x1fff0000
 220 #define PCIA_WMASK_1G   0x3fff0000
 221 #define PCIA_WMASK_2G   0x7fff0000
 222 #define PCIA_WMASK_4G   0xffff0000
 223
 224 /*
 225  * Values for PCIA_WBASE_x
 226  */
 227 #define PCIA_WBASE_MASK  0xffff0000     /* mask of valid bits in address */
 228 #define PCIA_WBASE_W_EN  0x00000002     /* window enable */
 229 #define PCIA_WBASE_SG_EN 0x00000001     /* SGMAP enable */
 230
 231 /*
 232  * Values for PCIA_TBASE_x
 233  *
 234  * NOTE: Translated Base is only used on direct-mapped DMA on the DWLPx!!
 235  */
 236 #define PCIA_TBASE_MASK  0x00fffffe
 237 #define PCIA_TBASE_SHIFT 15