sys/arch/alpha/pci/dwlpxvar.h

   1 /* $NetBSD: dwlpxvar.h,v 1.8 2001/07/27 00:25:20 thorpej Exp $ */
   2
   3 /*
   4  * Copyright (c) 1997 by Matthew Jacob
   5  * NASA AMES Research Center.
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice immediately at the beginning of the file, without modification,
  13  *    this list of conditions, and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. The name of the author may not be used to endorse or promote products
  18  *    derived from this software without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
  24  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  30  * SUCH DAMAGE.
  31  */
  32
  33 #include <dev/pci/pcivar.h>
  34 #include <sys/extent.h>
  35
  36 #include <alpha/pci/pci_sgmap_pte32.h>
  37
  38 #define _FSTORE (EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long))
  39
  40 /*
  41  * DWLPX configuration.
  42  */
  43 struct dwlpx_config {
  44         int                             cc_initted;
  45         struct alpha_bus_space          cc_iot;
  46         struct alpha_bus_space          cc_memt;
  47         struct extent *                 cc_io_ex;
  48         struct extent *                 cc_d_mem_ex;
  49         struct extent *                 cc_s_mem_ex;
  50         struct alpha_pci_chipset        cc_pc;
  51         struct dwlpx_softc *            cc_sc;  /* back pointer */
  52         long                            cc_io_exstorage[_FSTORE];
  53         long                            cc_dmem_exstorage[_FSTORE];
  54         long                            cc_smem_exstorage[_FSTORE];
  55         unsigned long                   cc_sysbase;     /* shorthand */
  56         struct alpha_bus_dma_tag        cc_dmat_direct;
  57         struct alpha_bus_dma_tag        cc_dmat_sgmap;
  58         struct alpha_sgmap              cc_sgmap;
  59 };
  60
  61 struct dwlpx_softc {
  62         struct device           dwlpx_dev;
  63         struct dwlpx_config     dwlpx_cc;       /* config info */
  64         u_int16_t               dwlpx_dtype;    /* Node Type */
  65         u_int8_t                dwlpx_node;     /* TurboLaser Node */
  66         u_int8_t                dwlpx_hosenum;  /* Hose Number */
  67         u_int8_t                dwlpx_nhpc;     /* # of hpcs */
  68         u_int8_t                dwlpx_sgmapsz;  /* size of SGMAP */
  69 };
  70 #define DWLPX_NONE      0
  71 #define DWLPX_SG32K     1
  72 #define DWLPX_SG64K     2
  73 #define DWLPX_SG128K    3
  74
  75 void    dwlpx_init(struct dwlpx_softc *);
  76 void    dwlpx_pci_init(pci_chipset_tag_t, void *);
  77 void    dwlpx_dma_init(struct dwlpx_config *);
  78
  79 void    dwlpx_bus_io_init(bus_space_tag_t, void *);
  80 void    dwlpx_bus_mem_init(bus_space_tag_t, void *);
  81
  82 /*
  83  * Each DWLPX supports up to 15 devices, 12 of which are PCI slots.
  84  *
  85  * Since the STD I/O modules in slots 12-14 are really a PCI-EISA
  86  * bridge, we'll punt on those for the moment.
  87  */
  88 #define DWLPX_MAXDEV    12
  89
  90 #define DWLPX_NIONODE   5
  91 #define DWLPX_NHOSE     4
  92
  93 /*
  94  * Default values to put into DWLPX IMASK register(s)
  95  */
  96 #define DWLPX_IMASK_DFLT        \
  97         (1 << 24) |     /* IPL 17 for error interrupts */ \
  98         (1 << 17) |     /* IPL 14 for device interrupts */ \
  99         (1 << 16)       /* Enable Error Interrupts */