sys/arch/alpha/pci/lcareg.h

   1 /* $NetBSD: lcareg.h,v 1.7 1997/06/06 23:54:31 thorpej Exp $ */
   2
   3 /*
   4  * Copyright (c) 1995 Carnegie-Mellon University.
   5  * All rights reserved.
   6  *
   7  * Authors: Jeffrey Hsu, Jason R. Thorpe
   8  *
   9  * Permission to use, copy, modify and distribute this software and
  10  * its documentation is hereby granted, provided that both the copyright
  11  * notice and this permission notice appear in all copies of the
  12  * software, derivative works or modified versions, and any portions
  13  * thereof, and that both notices appear in supporting documentation.
  14  *
  15  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
  16  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
  17  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
  18  *
  19  * Carnegie Mellon requests users of this software to return to
  20  *
  21  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
  22  *  School of Computer Science
  23  *  Carnegie Mellon University
  24  *  Pittsburgh PA 15213-3890
  25  *
  26  * any improvements or extensions that they make and grant Carnegie the
  27  * rights to redistribute these changes.
  28  */
  29
  30 /*
  31  * 21066 chip registers
  32  */
  33
  34 #define REGVAL(r)       (*(volatile int32_t *)ALPHA_PHYS_TO_K0SEG(r))
  35 #define REGVAL64(r)     (*(volatile int64_t *)ALPHA_PHYS_TO_K0SEG(r))
  36
  37 /*
  38  * Base addresses
  39  */
  40 #define LCA_IOC_BASE    0x180000000L            /* LCA IOC Regs */
  41 #define LCA_PCI_SIO     0x1c0000000L            /* PCI Sp. I/O Space */
  42 #define LCA_PCI_CONF    0x1e0000000L            /* PCI Conf. Space */
  43 #define LCA_PCI_SPARSE  0x200000000L            /* PCI Sparse Space */
  44 #define LCA_PCI_DENSE   0x300000000L            /* PCI Dense Space */
  45
  46 #define LCA_IOC_HAE     LCA_IOC_BASE            /* Host Address Ext. (64) */
  47 #define IOC_HAE_ADDREXT 0x00000000f8000000UL
  48 #define IOC_HAE_RSVSD   0xffffffff07ffffffUL
  49
  50 #define LCA_IOC_CONF    (LCA_IOC_BASE + 0x020)  /* Configuration Cycle Type */
  51
  52 #define LCA_IOC_STAT0   (LCA_IOC_BASE + 0x040)  /* Status 0 */
  53 #define IOC_STAT0_CMD   0x000000000000000fUL    /* PCI command mask */
  54 #define IOC_STAT0_ERR   0x0000000000000010UL    /* IOC error indicator R/W1C */
  55 #define IOC_STAT0_LOST  0x0000000000000020UL    /* IOC lose error info R/W1C */
  56 #define IOC_STAT0_THIT  0x0000000000000040UL    /* test hit */
  57 #define IOC_STAT0_TREF  0x0000000000000080UL    /* test reference */
  58 #define IOC_STAT0_CODE  0x0000000000000700UL    /* code mask */
  59 #define IOC_STAT0_CODESHIFT 8
  60 #define IOC_STAT0_P_NBR 0x00000000ffffe000UL    /* page number mask */
  61
  62 #define LCA_IOC_STAT1   (LCA_IOC_BASE + 0x060)  /* Status 1 */
  63 #define IOC_STAT1_ADDR  0x00000000ffffffffUL    /* PCI address mask */
  64
  65 #define LCA_IOC_TBIA    (LCA_IOC_BASE + 0x080)  /* TLB Invalidate All */
  66 #define LCA_IOC_TB_ENA  (LCA_IOC_BASE + 0x0a0)  /* TLB Enable */
  67 #define IOC_TB_ENA_TEN  0x0000000000000080UL
  68
  69 #define LCA_IOC_W_BASE0 (LCA_IOC_BASE + 0x100)  /* Window Base */
  70 #define LCA_IOC_W_MASK0 (LCA_IOC_BASE + 0x140)  /* Window Mask */
  71 #define LCA_IOC_W_T_BASE0 (LCA_IOC_BASE + 0x180) /* Translated Base */
  72
  73 #define LCA_IOC_W_BASE1 (LCA_IOC_BASE + 0x120)  /* Window Base */
  74 #define LCA_IOC_W_MASK1 (LCA_IOC_BASE + 0x160)  /* Window Mask */
  75 #define LCA_IOC_W_T_BASE1 (LCA_IOC_BASE + 0x1a0) /* Translated Base */
  76
  77 #define IOC_W_BASE_W_BASE 0x00000000fff00000UL  /* Window base value */
  78 #define IOC_W_BASE_SG     0x0000000100000000UL  /* Window uses SGMAPs */
  79 #define IOC_W_BASE_WEN    0x0000000200000000UL  /* Window enable */
  80
  81 #define IOC_W_MASK_1M   0x0000000000000000UL    /* 1MB window */
  82 #define IOC_W_MASK_2M   0x0000000000100000UL    /* 2MB window */
  83 #define IOC_W_MASK_4M   0x0000000000300000UL    /* 4MB window */
  84 #define IOC_W_MASK_8M   0x0000000000700000UL    /* 8MB window */
  85 #define IOC_W_MASK_16M  0x0000000000f00000UL    /* 16MB window */
  86 #define IOC_W_MASK_32M  0x0000000001f00000UL    /* 32MB window */
  87 #define IOC_W_MASK_64M  0x0000000003f00000UL    /* 64MB window */
  88 #define IOC_W_MASK_128M 0x0000000007f00000UL    /* 128M window */
  89 #define IOC_W_MASK_256M 0x000000000ff00000UL    /* 256M window */
  90 #define IOC_W_MASK_512M 0x000000001ff00000UL    /* 512M window */
  91 #define IOC_W_MASK_1G   0x000000003ff00000UL    /* 1GB window */
  92 #define IOC_W_MASK_2G   0x000000007ff00000UL    /* 2GB window */
  93 #define IOC_W_MASK_4G   0x00000000fff00000UL    /* 4GB window */
  94
  95 #define IOC_W_T_BASE    0x00000000fffffc00UL    /* page table base */