sys/arch/alpha/pci/mcpciareg.h

   1 /* $NetBSD: mcpciareg.h,v 1.6 2005/12/11 12:16:17 christos Exp $ */
   2
   3 /*
   4  * Copyright (c) 1998 by Matthew Jacob
   5  * NASA AMES Research Center.
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice immediately at the beginning of the file, without modification,
  13  *    this list of conditions, and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. The name of the author may not be used to endorse or promote products
  18  *    derived from this software without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
  24  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  30  * SUCH DAMAGE.
  31  */
  32
  33 /*
  34  * Taken from:
  35  *
  36  *      ``RAWHIDE Systems Programmer's Manual, Revision 1.4''
  37  */
  38
  39 #define REGVAL(r)       (*(volatile int32_t *)ALPHA_PHYS_TO_K0SEG(r))
  40
  41 /*
  42  * There are 4 possible PCI busses per MCBUS.
  43  *
  44  * (from mcpcia.h, Digital Unix 4.0E):
  45  *
  46  * I/O Space Per PCI Node (8GBytes per)
  47  * ------------------------------------
  48  * (8+x)8 0000 0000 - (8+x)9 FFFF FFFF  - I/O Space for PCI0
  49  * (8+x)A 0000 0000 - (8+x)B FFFF FFFF  - I/O Space for PCI1
  50  * (8+x)C 0000 0000 - (8+x)D FFFF FFFF  - I/O Space for PCI2
  51  * (8+x)E 0000 0000 - (8+x)F FFFF FFFF  - I/O Space for PCI3
  52  *
  53  * CPU to PCI Address Mapping:
  54  * ---------------------------
  55  *
  56  * +---+-------+-------+--+--+--+--+--+--+---------------+----------+-----+
  57  * | 1 |  GID  |  MID  |  |  |  |  |  |  | Byte Aligned  | Byte Len | Zero|
  58  * |   |       |       |  |  |  |  |  |  | I/O Address   |   Field  |     |
  59  * +---+-------+-------+--+--+--+--+--+--+---------------+----------+-----+
  60  *  39  38   36 35   33 32 31 30 29 28 27 26            5 4        3  2  0
  61  *
  62  * <39> - I/O Select (Always 1 for direct I/O access)
  63  *
  64  * <38-36> - Global Bus slot # (MCBUS #)
  65  *      GID slot #0->7 (MCBUS #0->7)
  66  *
  67  * <35-33> - MCBUS Slot #
  68  *      MCBUS slot 0->7
  69  *
  70  * <32-27> - PCI Address Space
  71  *      0.xxxxx = Sparse Memory Space   (  4GB on MCBUS; 128MB on PCI)
  72  *      1.0xxxx = Dense Memory Space    (  2GB on MCBUS;   2GB on PCI)
  73  *      1.10xxx = Sparse IO Space       (  1GB on MCBUS;  32MB on PCI)
  74  *      1.110xx = Sparse Config Space   (512MB on MCBUS;  16MB on PCI)
  75  *      1.1110x = PCI Bridge CSR Space  (256MB on MCBUS) -- Sparse-mapped!
  76  *      1.11110 = Interrupt Acknowledge (128MB on MCBUS)
  77  *      1.11111 = Unused                (128MB on MCBUS)
  78  *
  79  * ------------------------------------------------------------
  80  * CPU to PCI Address Mapping for MCBUS-PCIy Bridge on MCBUS x:
  81  * ------------------------------------------------------------
  82  *
  83  * CPU Address Range            PCI Address Range       PCI Address Space
  84  * ------------------------     ---------------------   ------------------------
  85  * (8+x)(8+y*2).0000.0000       0000.0000 - 00FF.FFFF   PCIy Sparse Memory Space
  86  * - (8+x)(8+y*2).1FFF.FFFF                              (fixed, lower 16MB)
  87  *
  88  * (8+x)(8+y*2).2000.0000       0100.0000 - 07FF.FFFF   PCIy Sparse Memory Space
  89  * - (8+x)(8+y*2).FFFF.FFFF                              (variable, offset = 0)
  90  *
  91  * (8+x)(9+y*2).0000.0000       0000.0000 - 7FFF.FFFF   PCIy Dense Memory Space
  92  * - (8+x)(9+y*2).7FFF.FFFF  or 8000.0000 - FFFF.FFFF      if HAE_DENSE_MEM = 1
  93  *
  94  * (8+x)(9+y*2).8000.0000       0000.0000 - 0000.FFFF   PCIy Sparse IO Space
  95  * - (8+x)(9+y*2).801F.FFFF                              (fixed, lower 64K)
  96  *
  97  * (8+x)(9+y*2).8020.0000       0001.0000 - 01FF.FFFF   PCIy Sparse IO Space
  98  * - (8+x)(9+y*2).BFFF.FFFF                              (variable, offset = 0)
  99  *
 100  * (8+x)(9+y*2).C000.0000       0000.0000 - 0FFF.FFFF   PCIy Config Space (16MB)
 101  * - (8+x)(9+y*2).DFFF.FFFF
 102  *
 103  * (8+x)(9+y*2).E000.0000               N/A             PCIy-Bridge CSR Space
 104  *                                                      (8MB)
 105  * - (8+x)(9+y*2).EFFF.FFFF
 106  *
 107  * (8+x)(9+y*2).F000.0000               N/A             Unused
 108  * - (8+x)(9+y*2).F000.3EFF
 109  *
 110  * (8+x)(9+y*2).F000.3F00,              N/A             PCIy Interrupt ACK0
 111  * (8+x)(9+y*2).F000.3F40                               PCIy INteruppt ACK1
 112  *
 113  * (8+x)(9+y*2).F000.3F80               N/A             Unused
 114  * - (8+x)(9+y*2).FFFF.FFFF
 115  *
 116  */
 117
 118 /*
 119  * MC-PCI Bus Bridge CSRs
 120  *
 121  * Address Map Overview:
 122  *
 123  * Offset                Selected Space
 124  * ----------------      -------------------------------------------------
 125  * 0x00000000            General config, control, diag, error logging regs.
 126  * 0x00001000            PCI Error Status
 127  * 0x00001300            PCI Scatter/Gather Regs.
 128  * 0x00001800            Scatter/Gather TLB Regs.
 129  * 0x00004000            MDPA Error Status & Diagnostic Control
 130  * 0x00008000            MDPB Error Status & Diagnostic Control
 131  * 0x000E0000 -          Flash Rom Space --
 132  * 0x000FFFFF            offset address into PCI Dense Mem Space
 133  * 0x10003F00            Interrupt Acknowledge
 134  *
 135  */
 136
 137
 138 /*
 139  * Address Space Cookies
 140  */
 141
 142 #define MCPCIA_PCI_SPARSE       0x000000000UL
 143 #define MCPCIA_PCI_DENSE        0x100000000UL
 144 #define MCPCIA_PCI_IOSPACE      0x180000000UL
 145 #define MCPCIA_PCI_CONF         0x1C0000000UL
 146 #define MCPCIA_PCI_BRIDGE       0x1E0000000UL
 147 #define MCPCIA_PCI_IACK         0x1F0000000UL
 148
 149 /*
 150  * MCPCIA Bus Bridge Registers
 151  *
 152  * These are offsets that don't include GBUS, MID, or address space offsets.
 153  */
 154
 155 #define _MCPCIA_PCI_REV         0x000000000     /* PCI Revision Register (R) */
 156 #define _MCPCIA_WHOAMI          0x000000040     /* PCI Who Am I (R) */
 157 #define _MCPCIA_PCI_LAT         0x000000080     /* PCI Latency Timer (RW) */
 158 #define _MCPCIA_CAP_CTRL        0x000000100     /* PCI Bridge Control (RW) */
 159 #define _MCPCIA_HAE_MEM         0x000000400     /* PCI HAE Sparse Memory (RW) */
 160 #define _MCPCIA_HAE_IO          0x000000440     /* PCI HAE Sparse I/O (RW) */
 161 #define _MCPCIA_IACK_SC         0x000000480     /* PCI Special Cycle Ack */
 162 #define _MCPCIA_HAE_DENSE       0x0000004C0     /* PCI HAE Dense Memory (RW) */
 163
 164 #define _MCPCIA_INT_CTL         0x000000500     /* PCI Interrupt Control */
 165 #define _MCPCIA_INT_REQ         0x000000540     /* PCI Interrupt Request */
 166 #define _MCPCIA_INT_TARG        0x000000580     /* PCI Int Tgt Devices */
 167 #define _MCPCIA_INT_ADR         0x0000005C0     /* PCI Int Tgt Address */
 168 #define _MCPCIA_INT_ADR_EXT     0x000000600     /* PCI Int Tgt Addr Ext */
 169 #define _MCPCIA_INT_MASK0       0x000000640     /* PCI Int Mask 0 */
 170 #define _MCPCIA_INT_MASK1       0x000000680     /* PCI Int Mask 1 */
 171
 172 #define _MCPCIA_INT_ACK0        0x100003F00     /* PCI Int Ack 0 */
 173 #define _MCPCIA_INT_ACK1        0x100003F40     /* PCI Int Ack 1 */
 174
 175 #define _MCPCIA_PERF_MON        0x000000300     /* PCI Perf Monitor */
 176 #define _MCPCIA_PERF_CONT       0x000000340     /* PCI Perf Monitor Control */
 177
 178 #define _MCPCIA_CAP_DIAG        0x000000700     /* MC-PCI Diagnostic Control */
 179 #define _MCPCIA_SCRATCH0        0x000000740     /* Diag General */
 180 #define _MCPCIA_SCRATCH1        0x000000780     /* Diag General */
 181 #define _MCPCIA_TOM             0x0000007C0     /* Top Of Memory */
 182 #define _MCPCIA_MC_ERR0         0x000000800     /* MC Err Info 0 */
 183 #define _MCPCIA_MC_ERR1         0x000000840     /* MC Err Info 1 */
 184 #define _MCPCIA_CAP_ERR         0x000000880     /* CAP Error Register */
 185
 186 #define _MCPCIA_PCI_ERR1        0x000001040     /* PCI Error Status */
 187
 188 #define _MCPCIA_MDPA_STAT       0x000004000     /* MDPA Status */
 189 #define _MCPCIA_MDPA_SYN        0x000004040     /* MDPA Syndrome */
 190 #define _MCPCIA_MDPA_DIAG       0x000004080     /* Diag Check MDPA */
 191
 192 #define _MCPCIA_MDPB_STAT       0x000008000     /* MDPB Status */
 193 #define _MCPCIA_MDPB_SYN        0x000008040     /* MDPB Syndrome */
 194 #define _MCPCIA_MDPB_DIAG       0x000008080     /* Diag Check MDPB */
 195
 196 #define _MCPCIA_SG_TBIA         0x000001300     /* Scatter/Gather TBIA */
 197 #define _MCPCIA_HBASE           0x000001340     /* PC "Hole" Compatibility */
 198 #define _MCPCIA_W0_BASE         0x000001400     /* Window Base 0 */
 199 #define _MCPCIA_W0_MASK         0x000001440     /* Window Mask 0 */
 200 #define _MCPCIA_T0_BASE         0x000001480     /* Translated Base 0 */
 201 #define _MCPCIA_W1_BASE         0x000001500     /* Window Base 1 */
 202 #define _MCPCIA_W1_MASK         0x000001540     /* Window Mask 1 */
 203 #define _MCPCIA_T1_BASE         0x000001580     /* Translated Base 1 */
 204 #define _MCPCIA_W2_BASE         0x000001600     /* Window Base 2 */
 205 #define _MCPCIA_W2_MASK         0x000001640     /* Window Mask 2 */
 206 #define _MCPCIA_T2_BASE         0x000001680     /* Translated Base 2 */
 207 #define _MCPCIA_W3_BASE         0x000001700     /* Window Base 3 */
 208 #define _MCPCIA_W3_MASK         0x000001740     /* Window Mask 3 */
 209 #define _MCPCIA_T3_BASE         0x000001780     /* Translated Base 3 */
 210 #define _MCPCIA_W_DAC           0x0000017C0     /* Window DAC Base */
 211
 212
 213 /*
 214  * Handier defines- uses precalculated offset in softc.
 215  */
 216 #define _SYBRIDGE(ccp)  ((ccp)->cc_sysbase | MCPCIA_PCI_BRIDGE)
 217
 218 #define MCPCIA_PCI_REV(ccp)     (_SYBRIDGE(ccp) | _MCPCIA_PCI_REV)
 219 #define MCPCIA_WHOAMI(ccp)      (_SYBRIDGE(ccp) | _MCPCIA_WHOAMI)
 220 #define MCPCIA_PCI_LAT(ccp)     (_SYBRIDGE(ccp) | _MCPCIA_PCI_LAT)
 221 #define MCPCIA_CAP_CTRL(ccp)    (_SYBRIDGE(ccp) | _MCPCIA_CAP_CTRL)
 222 #define MCPCIA_HAE_MEM(ccp)     (_SYBRIDGE(ccp) | _MCPCIA_HAE_MEM)
 223 #define MCPCIA_HAE_IO(ccp)      (_SYBRIDGE(ccp) | _MCPCIA_HAE_IO)
 224 #define MCPCIA_IACK_SC(ccp)     (_SYBRIDGE(ccp) | _MCPCIA_IACK_SC)
 225 #define MCPCIA_HAE_DENSE(ccp)   (_SYBRIDGE(ccp) | _MCPCIA_HAE_DENSE)
 226 #define MCPCIA_INT_CTL(ccp)     (_SYBRIDGE(ccp) | _MCPCIA_INT_CTL)
 227 #define MCPCIA_INT_REQ(ccp)     (_SYBRIDGE(ccp) | _MCPCIA_INT_REQ)
 228 #define MCPCIA_INT_TARG(ccp)    (_SYBRIDGE(ccp) | _MCPCIA_INT_TARG)
 229 #define MCPCIA_INT_ADR(ccp)     (_SYBRIDGE(ccp) | _MCPCIA_INT_ADR)
 230 #define MCPCIA_INT_ADR_EXT(ccp) (_SYBRIDGE(ccp) | _MCPCIA_INT_ADR_EXT)
 231 #define MCPCIA_INT_MASK0(ccp)   (_SYBRIDGE(ccp) | _MCPCIA_INT_MASK0)
 232 #define MCPCIA_INT_MASK1(ccp)   (_SYBRIDGE(ccp) | _MCPCIA_INT_MASK1)
 233 #define MCPCIA_INT_ACK0(ccp)    (_SYBRIDGE(ccp) | _MCPCIA_INT_ACK0)
 234 #define MCPCIA_INT_ACK1(ccp)    (_SYBRIDGE(ccp) | _MCPCIA_INT_ACK1)
 235 #define MCPCIA_PERF_MON(ccp)    (_SYBRIDGE(ccp) | _MCPCIA_PERF_MON)
 236 #define MCPCIA_PERF_CONT(ccp)   (_SYBRIDGE(ccp) | _MCPCIA_PERF_CONT)
 237 #define MCPCIA_CAP_DIAG(ccp)    (_SYBRIDGE(ccp) | _MCPCIA_CAP_DIAG)
 238 #define MCPCIA_SCRATCH0(ccp)    (_SYBRIDGE(ccp) | _MCPCIA_SCRATCH0)
 239 #define MCPCIA_SCRATCH1(ccp)    (_SYBRIDGE(ccp) | _MCPCIA_SCRATCH1)
 240 #define MCPCIA_TOM(ccp)         (_SYBRIDGE(ccp) | _MCPCIA_TOM)
 241 #define MCPCIA_MC_ERR0(ccp)     (_SYBRIDGE(ccp) | _MCPCIA_MC_ERR0)
 242 #define MCPCIA_MC_ERR1(ccp)     (_SYBRIDGE(ccp) | _MCPCIA_MC_ERR1)
 243 #define MCPCIA_CAP_ERR(ccp)     (_SYBRIDGE(ccp) | _MCPCIA_CAP_ERR)
 244 #define MCPCIA_PCI_ERR1(ccp)    (_SYBRIDGE(ccp) | _MCPCIA_PCI_ERR1)
 245 #define MCPCIA_MDPA_STAT(ccp)   (_SYBRIDGE(ccp) | _MCPCIA_MDPA_STAT)
 246 #define MCPCIA_MDPA_SYN(ccp)    (_SYBRIDGE(ccp) | _MCPCIA_MDPA_SYN)
 247 #define MCPCIA_MDPA_DIAG(ccp)   (_SYBRIDGE(ccp) | _MCPCIA_MDPA_DIAG)
 248 #define MCPCIA_MDPB_STAT(ccp)   (_SYBRIDGE(ccp) | _MCPCIA_MDPB_STAT)
 249 #define MCPCIA_MDPB_SYN(ccp)    (_SYBRIDGE(ccp) | _MCPCIA_MDPB_SYN)
 250 #define MCPCIA_MDPB_DIAG(ccp)   (_SYBRIDGE(ccp) | _MCPCIA_MDPB_DIAG)
 251 #define MCPCIA_SG_TBIA(ccp)     (_SYBRIDGE(ccp) | _MCPCIA_SG_TBIA)
 252 #define MCPCIA_HBASE(ccp)       (_SYBRIDGE(ccp) | _MCPCIA_HBASE)
 253 #define MCPCIA_W0_BASE(ccp)     (_SYBRIDGE(ccp) | _MCPCIA_W0_BASE)
 254 #define MCPCIA_W0_MASK(ccp)     (_SYBRIDGE(ccp) | _MCPCIA_W0_MASK)
 255 #define MCPCIA_T0_BASE(ccp)     (_SYBRIDGE(ccp) | _MCPCIA_T0_BASE)
 256 #define MCPCIA_W1_BASE(ccp)     (_SYBRIDGE(ccp) | _MCPCIA_W1_BASE)
 257 #define MCPCIA_W1_MASK(ccp)     (_SYBRIDGE(ccp) | _MCPCIA_W1_MASK)
 258 #define MCPCIA_T1_BASE(ccp)     (_SYBRIDGE(ccp) | _MCPCIA_T1_BASE)
 259 #define MCPCIA_W2_BASE(ccp)     (_SYBRIDGE(ccp) | _MCPCIA_W2_BASE)
 260 #define MCPCIA_W2_MASK(ccp)     (_SYBRIDGE(ccp) | _MCPCIA_W2_MASK)
 261 #define MCPCIA_T2_BASE(ccp)     (_SYBRIDGE(ccp) | _MCPCIA_T2_BASE)
 262 #define MCPCIA_W3_BASE(ccp)     (_SYBRIDGE(ccp) | _MCPCIA_W3_BASE)
 263 #define MCPCIA_W3_MASK(ccp)     (_SYBRIDGE(ccp) | _MCPCIA_W3_MASK)
 264 #define MCPCIA_T3_BASE(ccp)     (_SYBRIDGE(ccp) | _MCPCIA_T3_BASE)
 265 #define MCPCIA_W_DAC(ccp)       (_SYBRIDGE(ccp) | _MCPCIA_W_DAC)
 266
 267 /*
 268  * This is here for what error handling will get as a collected subpacket.
 269  */
 270
 271 struct mcpcia_iodsnap {
 272         u_int64_t       base_addr;
 273         u_int32_t       whami;
 274         u_int32_t       rsvd0;
 275         u_int32_t       pci_rev;
 276         u_int32_t       cap_ctrl;
 277         u_int32_t       hae_mem;
 278         u_int32_t       hae_io;
 279         u_int32_t       int_ctl;
 280         u_int32_t       int_reg;
 281         u_int32_t       int_mask0;
 282         u_int32_t       int_mask1;
 283         u_int32_t       mc_err0;
 284         u_int32_t       mc_err1;
 285         u_int32_t       cap_err;
 286         u_int32_t       sys_env;
 287         u_int32_t       pci_err1;
 288         u_int32_t       mdpa_stat;
 289         u_int32_t       mdpa_syn;
 290         u_int32_t       mdpb_stat;
 291         u_int32_t       mdpb_syn;
 292         u_int32_t       rsvd2;
 293         u_int32_t       rsvd3;
 294         u_int32_t       rsvd4;
 295 };
 296
 297 /*
 298  * PCI_REV Register definitions
 299  */
 300 #define CAP_REV(reg)            ((reg) & 0xf)
 301 #define HORSE_REV(reg)          (((reg) >> 4) & 0xf)
 302 #define SADDLE_REV(reg)         (((reg) >> 8) & 0xf)
 303 #define SADDLE_TYPE(reg)        (((reg) >> 12) & 0x3)
 304 #define EISA_PRESENT(reg)       ((reg) & (1 << 15))
 305 #define IS_MCPCIA_MAGIC(reg)    (((reg) & 0xffff0000) == 0x6000000)
 306
 307
 308 /*
 309  * WHOAMI Register definitions
 310  *
 311  * The Device ID is an echo of the MID of the CPU reading this register-
 312  * cheezy way to figure out who you are (ask someone else!).
 313  */
 314 #define MCBUS_CPU_MID(x)                ((x) & 0x7)
 315 #define MCBUS_CPU_INFO(x)               (((x) >> 6) & 0xff)
 316 #define         CPU_Fill_Err    0x80
 317 #define         CPU_DTAG_Perr   0x40
 318 #define         CPU_RevMask     0x38
 319 #define         CPU_RevShift    3
 320 #define         CPU_BCacheMask  0x3
 321 #define                 CPU_BCache_0MB  0
 322 #define                 CPU_BCache_1MB  1
 323 #define                 CPU_BCache_2MB  2
 324 #define                 CPU_BCache_4MB  3
 325
 326 /*
 327  * PCI Latency Register Definitions
 328  */
 329 #define PCI_LAT_SHIFT   8       /* it's in the 2nd byte. */
 330
 331 /*
 332  * CAP Control Register Definitions
 333  */
 334 #define CAP_LED_ON      0x00000001      /* Selftest LED passed */
 335 #define CAP_EV56_BW_EN  0x00000002      /* BW Enables (EV56, EV6 only) */
 336 #define CAP_DLY_RD_EN   0x00000010      /* PCI Delayed Reads Enabled */
 337 #define CAP_MEM_EN      0x00000020      /* Respond to PCI transactions */
 338 #define CAP_REQ64_EN    0x00000040      /* Request 64 bit data transactions */
 339 #define CAP_ACK64_EN    0x00000080      /* Respond to 64 bit data "" */
 340 #define CAP_ADR_PAR_EN  0x00000100      /* Check PCI address Parity */
 341 #define CAP_MC_CA_PAR   0x00000200      /* Check MC bus CMD/Address Parity */
 342 #define CAP_MC_NXM_EN   0x00000400      /* Check for MC NXM */
 343 #define CAP_BUS_MON     0x00000800      /* Check for PCI errs (as bystander) */
 344 /* bits 19:16 control number of pending write transactions */
 345 #define         SHORT   0
 346 #define         MED     1
 347 #define         LONG    2
 348 #define CAP_MEMRD_PREFETCH_SHIFT        20
 349 #define CAP_MEMRDLN_PREFETCH_SHIFT      22
 350 #define CAP_MEMRDMULT_PREFETCH_SHIFT    24
 351 #define CAP_PARTIAL_WRITE       (1 << 26)
 352
 353 #define CAP_ARB_BPRI    0x00000000      /* Bridge Priority Arb */
 354 #define CAP_ARB_RROBIN  0x40000000      /* "" Round Robin */
 355 #define CAP_ARB_RROBIN1 0x80000000      /* "" Round Robin #1 */
 356
 357 /*
 358  * Diagnostic Register Bits
 359  */
 360 /* CAP_DIAG register */
 361 #define CAP_DIAG_PCIRESET       0x1     /*
 362                                          * WriteOnly. Assert 1 for 100usec min.,
 363                                          * then write zero. NOTE: deadlocks
 364                                          * exist in h/w if anything but this
 365                                          * register is accessed while reset
 366                                          * is asserted.
 367                                          */
 368 #define CAP_DIAG_MC_ADRPE       (1<<30) /* Invert MC Bus Address/Parity */
 369 #define CAP_DIAG_PCI_ADRPE      (1<<31) /* Force bad PCI parity (low 32) */
 370
 371 /* MDPA_DIAG or MDPB_DIAG registers */
 372 #define MDPX_ECC_ENA            (1<<28) /* Enable ECC on MC Bus (default 1) */
 373 #define MDPX_PAR_ENA            (1<<29) /* Enable Parity on PCI (default 0) */
 374 #define MDPX_DIAG_FPE_PCI       (1<<30) /* Force PCI parity error */
 375 #define MDPX_DIAG_USE_CHK       (1<<31) /*
 376                                          * When set, DMA write cycles use the
 377                                          * value in the low 8 bits of this
 378                                          * register (MDPA or MDPB) as ECC
 379                                          * sent onto main memory.
 380                                          */
 381
 382 /*
 383  * Interrupt Specific bits...
 384  *
 385  * Mostly we don't have to mess with any of the interrupt specific registers
 386  * as the SRM has set most of this pretty complex stuff up for us.
 387  *
 388  * However, to enable specific interrupts, we need to set some bits
 389  * in imask0 if we want to have them vectored to PALcode for appropriate
 390  * dispatch.
 391  */
 392
 393 /*
 394  * bits 0-15 correspond to 4 slots (time 4 buspins) for each PCI bus.
 395  * bit 16 is the NCR810 onboard SCSI interrupt.
 396  * bits 19-20 are reserved.
 397  */
 398
 399 #define MCPCIA_I2C_CTRL_INTR            (1<<17)
 400 #define MCPCIA_I2C_CTRL_BUS_ERR         (1<<18)
 401
 402 #define MCPCIA_8259_NMI_INTR            (1<<21)
 403 #define MCPCIA_SOFT_ERR_INTR            (1<<22)
 404 #define MCPCIA_HARD_ERR_INTR            (1<<23)
 405
 406 #ifdef  YET
 407 #define MCPCIA_GEN_IENABL       \
 408         (MCPCIA_I2C_CTRL_BUS_ERR|MCPCIA_SOFT_ERR_INTR|MCPCIA_HARD_ERR_INTR)
 409 #else
 410 #define MCPCIA_GEN_IENABL       \
 411         (MCPCIA_SOFT_ERR_INTR|MCPCIA_HARD_ERR_INTR)
 412 #endif
 413
 414 /*
 415  * DMA Address Specific bits...
 416  */
 417
 418 #define MCPCIA_WBASE_EN                 0x1
 419 #define MCPCIA_WBASE_SG                 0x2
 420 #define MCPCIA_WBASE_DAC                0x8
 421 #define MCPCIA_WBASE_BSHIFT             20
 422
 423 #define MCPCIA_WMASK_1M                 0x00000000
 424 #define MCPCIA_WMASK_2M                 0x00100000
 425 #define MCPCIA_WMASK_4M                 0x00300000
 426 #define MCPCIA_WMASK_8M                 0x00700000
 427 #define MCPCIA_WMASK_16M                0x00f00000
 428 #define MCPCIA_WMASK_32M                0x01f00000
 429 #define MCPCIA_WMASK_64M                0x03f00000
 430 #define MCPCIA_WMASK_128M               0x07f00000
 431 #define MCPCIA_WMASK_256M               0x0ff00000
 432 #define MCPCIA_WMASK_512M               0x1ff00000
 433 #define MCPCIA_WMASK_1G                 0x3ff00000
 434 #define MCPCIA_WMASK_2G                 0x7ff00000
 435 #define MCPCIA_WMASK_4G                 0xfff00000
 436
 437 /*
 438  * The WBASEX register contains bits 39:10 of a physical address
 439  * shifted to bits 31:2 of this 32 bit register. Namely, shifted
 440  * right by 8 bits.
 441  */
 442 #define MCPCIA_TBASEX_SHIFT             8