sys/arch/alpha/pci/pci_2100_a500.c

   1 /* $NetBSD: pci_2100_a500.c,v 1.8 2007/12/03 15:33:06 ad Exp $ */
   2
   3 /*-
   4  * Copyright (c) 1999 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by Jason R. Thorpe.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 #include <sys/cdefs.h>                  /* RCS ID & Copyright macro defns */
  33
  34 __KERNEL_RCSID(0, "$NetBSD: pci_2100_a500.c,v 1.8 2007/12/03 15:33:06 ad Exp $");
  35
  36 #include <sys/types.h>
  37 #include <sys/param.h>
  38 #include <sys/time.h>
  39 #include <sys/systm.h>
  40 #include <sys/errno.h>
  41 #include <sys/malloc.h>
  42 #include <sys/device.h>
  43 #include <sys/syslog.h>
  44
  45 #include <machine/autoconf.h>
  46
  47 #include <dev/eisa/eisavar.h>
  48
  49 #include <dev/pci/pcireg.h>
  50 #include <dev/pci/pcivar.h>
  51
  52 #include <alpha/pci/ttwogareg.h>
  53 #include <alpha/pci/ttwogavar.h>
  54 #include <alpha/pci/pci_2100_a500.h>
  55
  56 static bus_space_tag_t pic_iot;
  57 static bus_space_handle_t pic_master_ioh;
  58 static bus_space_handle_t pic_slave_ioh[4];
  59 static bus_space_handle_t pic_elcr_ioh;
  60
  61 static const int pic_slave_to_master[4] = { 1, 3, 4, 5 };
  62
  63 int     dec_2100_a500_pic_intr_map(struct pci_attach_args *,
  64             pci_intr_handle_t *);
  65
  66 int     dec_2100_a500_icic_intr_map(struct pci_attach_args *,
  67             pci_intr_handle_t *);
  68
  69 const char *dec_2100_a500_intr_string(void *, pci_intr_handle_t);
  70 const struct evcnt *dec_2100_a500_intr_evcnt(void *, pci_intr_handle_t);
  71 void    *dec_2100_a500_intr_establish(void *, pci_intr_handle_t,
  72             int, int (*)(void *), void *);
  73 void    dec_2100_a500_intr_disestablish(void *, void *);
  74
  75 int     dec_2100_a500_eisa_intr_map(void *, u_int, eisa_intr_handle_t *);
  76 const char *dec_2100_a500_eisa_intr_string(void *, int);
  77 const struct evcnt *dec_2100_a500_eisa_intr_evcnt(void *, int);
  78 void    *dec_2100_a500_eisa_intr_establish(void *, int, int, int,
  79             int (*)(void *), void *);
  80 void    dec_2100_a500_eisa_intr_disestablish(void *, void *);
  81 int     dec_2100_a500_eisa_intr_alloc(void *, int, int, int *);
  82
  83 #define PCI_STRAY_MAX   5
  84
  85 /*
  86  * On systems with cascaded 8259s, it's actually 32.  Systems which
  87  * use the ICIC interrupt logic have 64, however.
  88  */
  89 #define SABLE_MAX_IRQ           64
  90 #define SABLE_8259_MAX_IRQ      32
  91
  92 void    dec_2100_a500_iointr(void *, u_long);
  93
  94 void    dec_2100_a500_pic_enable_intr(struct ttwoga_config *, int, int);
  95 void    dec_2100_a500_pic_init_intr(struct ttwoga_config *);
  96 void    dec_2100_a500_pic_setlevel(struct ttwoga_config *, int, int);
  97 void    dec_2100_a500_pic_eoi(struct ttwoga_config *, int);
  98
  99 void    dec_2100_a500_icic_enable_intr(struct ttwoga_config *, int, int);
 100 void    dec_2100_a500_icic_init_intr(struct ttwoga_config *);
 101 void    dec_2100_a500_icic_setlevel(struct ttwoga_config *, int, int);
 102 void    dec_2100_a500_icic_eoi(struct ttwoga_config *, int);
 103
 104 #define T2_IRQ_EISA_START       7
 105 #define T2_IRQ_EISA_COUNT       16
 106
 107 #define T2_IRQ_IS_EISA(irq)                                             \
 108         ((irq) >= T2_IRQ_EISA_START &&                                  \
 109          (irq) < (T2_IRQ_EISA_START + T2_IRQ_EISA_COUNT))
 110
 111 const int dec_2100_a500_intr_deftype[SABLE_MAX_IRQ] = {
 112         IST_LEVEL,              /* PCI slot 0 A */
 113         IST_LEVEL,              /* on-board SCSI */
 114         IST_LEVEL,              /* on-board Ethernet */
 115         IST_EDGE,               /* mouse */
 116         IST_LEVEL,              /* PCI slot 1 A */
 117         IST_LEVEL,              /* PCI slot 2 A */
 118         IST_EDGE,               /* keyboard */
 119         IST_EDGE,               /* floppy (EISA IRQ 0) */
 120         IST_EDGE,               /* serial port 1 (EISA IRQ 1) */
 121         IST_EDGE,               /* parallel port (EISA IRQ 2) */
 122         IST_NONE,               /* EISA IRQ 3 (edge/level) */
 123         IST_NONE,               /* EISA IRQ 4 (edge/level) */
 124         IST_NONE,               /* EISA IRQ 5 (edge/level) */
 125         IST_NONE,               /* EISA IRQ 6 (edge/level) */
 126         IST_NONE,               /* EISA IRQ 7 (edge/level) */
 127         IST_EDGE,               /* serial port 0 (EISA IRQ 8) */
 128         IST_NONE,               /* EISA IRQ 9 (edge/level) */
 129         IST_NONE,               /* EISA IRQ 10 (edge/level) */
 130         IST_NONE,               /* EISA IRQ 11 (edge/level) */
 131         IST_NONE,               /* EISA IRQ 12 (edge/level) */
 132         IST_LEVEL,              /* PCI slot 2 B (EISA IRQ 13 n/c) */
 133         IST_NONE,               /* EISA IRQ 14 (edge/level) */
 134         IST_NONE,               /* EISA IRQ 15 (edge/level) */
 135         IST_LEVEL,              /* I2C (XXX double-check this) */
 136         IST_LEVEL,              /* PCI slot 0 B */
 137         IST_LEVEL,              /* PCI slot 1 B */
 138         IST_LEVEL,              /* PCI slot 0 C */
 139         IST_LEVEL,              /* PCI slot 1 C */
 140         IST_LEVEL,              /* PCI slot 2 C */
 141         IST_LEVEL,              /* PCI slot 0 D */
 142         IST_LEVEL,              /* PCI slot 1 D */
 143         IST_LEVEL,              /* PCI slot 2 D */
 144
 145         /*
 146          * These are the PCI interrupts on the T3/T4 systems.  See
 147          * dec_2100_a500_icic_intr_map() for the mapping.
 148          */
 149         IST_LEVEL,
 150         IST_LEVEL,
 151         IST_LEVEL,
 152         IST_LEVEL,
 153         IST_LEVEL,
 154         IST_LEVEL,
 155         IST_LEVEL,
 156         IST_LEVEL,
 157         IST_LEVEL,
 158         IST_LEVEL,
 159         IST_LEVEL,
 160         IST_LEVEL,
 161         IST_LEVEL,
 162         IST_LEVEL,
 163         IST_LEVEL,
 164         IST_LEVEL,
 165         IST_LEVEL,
 166         IST_LEVEL,
 167         IST_LEVEL,
 168         IST_LEVEL,
 169         IST_LEVEL,
 170         IST_LEVEL,
 171         IST_LEVEL,
 172         IST_LEVEL,
 173         IST_LEVEL,
 174         IST_LEVEL,
 175         IST_LEVEL,
 176         IST_LEVEL,
 177         IST_LEVEL,
 178         IST_LEVEL,
 179         IST_LEVEL,
 180         IST_LEVEL,
 181 };
 182
 183 void
 184 pci_2100_a500_pickintr(struct ttwoga_config *tcp)
 185 {
 186         pci_chipset_tag_t pc = &tcp->tc_pc;
 187         char *cp;
 188         int i;
 189
 190         pic_iot = &tcp->tc_iot;
 191
 192         pc->pc_intr_v = tcp;
 193         pc->pc_intr_string = dec_2100_a500_intr_string;
 194         pc->pc_intr_evcnt = dec_2100_a500_intr_evcnt;
 195         pc->pc_intr_establish = dec_2100_a500_intr_establish;
 196         pc->pc_intr_disestablish = dec_2100_a500_intr_disestablish;
 197
 198         /* Not supported on T2. */
 199         pc->pc_pciide_compat_intr_establish = NULL;
 200
 201         tcp->tc_intrtab = alpha_shared_intr_alloc(SABLE_MAX_IRQ, 8);
 202         for (i = 0; i < SABLE_MAX_IRQ; i++) {
 203                 alpha_shared_intr_set_dfltsharetype(tcp->tc_intrtab,
 204                     i, tcp->tc_hose == 0 ?
 205                     dec_2100_a500_intr_deftype[i] : IST_LEVEL);
 206                 alpha_shared_intr_set_maxstrays(tcp->tc_intrtab,
 207                     i, PCI_STRAY_MAX);
 208
 209                 cp = alpha_shared_intr_string(tcp->tc_intrtab, i);
 210                 sprintf(cp, "irq %d", T2_IRQ_IS_EISA(i) ?
 211                     i - T2_IRQ_EISA_START : i);
 212                 evcnt_attach_dynamic(alpha_shared_intr_evcnt(
 213                     tcp->tc_intrtab, i), EVCNT_TYPE_INTR, NULL,
 214                     T2_IRQ_IS_EISA(i) ? "eisa" : "T2", cp);
 215         }
 216
 217         /* 64 16-byte vectors per hose. */
 218         tcp->tc_vecbase = 0x800 + ((64 * 16) * tcp->tc_hose);
 219
 220         /*
 221          * T2 uses a custom layout of cascaded 8259 PICs for interrupt
 222          * control.  T3 and T4 use a built-in interrupt controller.
 223          *
 224          * Note that the external PCI bus (Hose 1) always uses
 225          * the new interrupt controller.
 226          */
 227         if (tcp->tc_rev < TRN_T3 && tcp->tc_hose == 0) {
 228                 pc->pc_intr_map = dec_2100_a500_pic_intr_map;
 229                 tcp->tc_enable_intr = dec_2100_a500_pic_enable_intr;
 230                 tcp->tc_setlevel = dec_2100_a500_pic_setlevel;
 231                 tcp->tc_eoi = dec_2100_a500_pic_eoi;
 232                 dec_2100_a500_pic_init_intr(tcp);
 233         } else {
 234                 pc->pc_intr_map = dec_2100_a500_icic_intr_map;
 235                 tcp->tc_enable_intr = dec_2100_a500_icic_enable_intr;
 236                 tcp->tc_setlevel = dec_2100_a500_icic_setlevel;
 237                 tcp->tc_eoi = dec_2100_a500_icic_eoi;
 238                 dec_2100_a500_icic_init_intr(tcp);
 239         }
 240 }
 241
 242 void
 243 pci_2100_a500_eisa_pickintr(pci_chipset_tag_t pc, eisa_chipset_tag_t ec)
 244 {
 245
 246         ec->ec_v = pc->pc_intr_v;
 247         ec->ec_intr_map = dec_2100_a500_eisa_intr_map;
 248         ec->ec_intr_string = dec_2100_a500_eisa_intr_string;
 249         ec->ec_intr_evcnt = dec_2100_a500_eisa_intr_evcnt;
 250         ec->ec_intr_establish = dec_2100_a500_eisa_intr_establish;
 251         ec->ec_intr_disestablish = dec_2100_a500_eisa_intr_disestablish;
 252 }
 253
 254 void
 255 pci_2100_a500_isa_pickintr(pci_chipset_tag_t pc, isa_chipset_tag_t ic)
 256 {
 257
 258         ic->ic_v = pc->pc_intr_v;
 259         ic->ic_intr_evcnt = dec_2100_a500_eisa_intr_evcnt;
 260         ic->ic_intr_establish = dec_2100_a500_eisa_intr_establish;
 261         ic->ic_intr_disestablish = dec_2100_a500_eisa_intr_disestablish;
 262         ic->ic_intr_alloc = dec_2100_a500_eisa_intr_alloc;
 263 }
 264
 265 /*****************************************************************************
 266  * PCI interrupt support.
 267  *****************************************************************************/
 268
 269 int
 270 dec_2100_a500_pic_intr_map(struct pci_attach_args *pa,
 271     pci_intr_handle_t *ihp)
 272 {
 273         /*
 274          * Interrupts in the Sable are even more of a pain than other
 275          * Alpha systems.  The interrupt logic is made up of 5 8259
 276          * PICs, arranged as follows:
 277          *
 278          *      Slave 0 --------------------------------+
 279          *      0 PCI slot 0 A                          |
 280          *      1 on-board SCSI                         |
 281          *      2 on-board Ethernet                     |
 282          *      3 mouse                                 |
 283          *      4 PCI slot 1 A                          |
 284          *      5 PCI slot 2 A                          |
 285          *      6 keyboard                              |
 286          *      7 floppy (EISA IRQ 0)                   |
 287          *                                              |
 288          *      Slave 1 ------------------------+       |   Master
 289          *      0 serial port 1 (EISA IRQ 1)    |       |   0 ESC interrupt
 290          *      1 parallel port (EISA IRQ 2)    |       +-- 1 Slave 0
 291          *      2 EISA IRQ 3                    |           2 reserved
 292          *      3 EISA IRQ 4                    +---------- 3 Slave 1
 293          *      4 EISA IRQ 5                    +---------- 4 Slave 2
 294          *      5 EISA IRQ 6                    |       +-- 5 Slave 3
 295          *      6 EISA IRQ 7                    |       |   6 reserved
 296          *      7 serial port 0 (EISA IRQ 8)    |       |   7 n/c
 297          *                                      |       |
 298          *      Slave 2 ------------------------+       |
 299          *      0 EISA IRQ 9                            |
 300          *      1 EISA IRQ 10                           |
 301          *      2 EISA IRQ 11                           |
 302          *      3 EISA IRQ 12                           |
 303          *      4 PCI slot 2 B (EISA IRQ 13 n/c)        |
 304          *      5 EISA IRQ 14                           |
 305          *      6 EISA IRQ 15                           |
 306          *      7 I2C                                   |
 307          *                                              |
 308          *      Slave 3 --------------------------------+
 309          *      0 PCI slot 0 B
 310          *      1 PCI slot 1 B
 311          *      2 PCI slot 0 C
 312          *      3 PCI slot 1 C
 313          *      4 PCI slot 2 C
 314          *      5 PCI slot 0 D
 315          *      6 PCI slot 1 D
 316          *      7 PCI slot 2 D
 317          *
 318          * Careful readers will note that the PCEB does not handle ISA
 319          * interrupts at all; when ISA interrupts are established, they
 320          * must be mapped to Sable interrupts.  Thankfully, this is easy
 321          * to do.
 322          *
 323          * The T3 and T4, generally found on Lynx, use a totally different
 324          * scheme because they have more PCI interrupts to handle; see below.
 325          */
 326         static const int irqmap[9/*device*/][4/*pin*/] = {
 327                 { 0x02, -1, -1, -1 },           /* 0: on-board Ethernet */
 328                 { 0x01, -1, -1, -1 },           /* 1: on-board SCSI */
 329                 { -1, -1, -1, -1 },             /* 2: invalid */
 330                 { -1, -1, -1, -1 },             /* 3: invalid */
 331                 { -1, -1, -1, -1 },             /* 4: invalid */
 332                 { -1, -1, -1, -1 },             /* 5: invalid */
 333                 { 0x00, 0x18, 0x1a, 0x1d },     /* 6: PCI slot 0 */
 334                 { 0x04, 0x19, 0x1b, 0x1e },     /* 7: PCI slot 1 */
 335                 { 0x05, 0x14, 0x1c, 0x1f },     /* 8: PCI slot 2 */
 336         };
 337         pcitag_t bustag = pa->pa_intrtag;
 338         int buspin = pa->pa_intrpin;
 339         pci_chipset_tag_t pc = pa->pa_pc;
 340         int device, irq;
 341
 342         if (buspin == 0) {
 343                 /* No IRQ used. */
 344                 return (1);
 345         }
 346
 347         if (buspin > 4) {
 348                 printf("dec_2100_a500_pic_intr_map: bad interrupt pin %d\n",
 349                     buspin);
 350                 return (1);
 351         }
 352
 353         pci_decompose_tag(pc, bustag, NULL, &device, NULL);
 354         if (device > 8) {
 355                 printf("dec_2100_a500_pic_intr_map: bad device %d\n",
 356                     device);
 357                 return (1);
 358         }
 359
 360         irq = irqmap[device][buspin - 1];
 361         if (irq == -1) {
 362                 printf("dec_2100_a500_pic_intr_map: no mapping for "
 363                     "device %d pin %d\n", device, buspin);
 364                 return (1);
 365         }
 366         *ihp = irq;
 367         return (0);
 368 }
 369
 370 int
 371 dec_2100_a500_icic_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
 372 {
 373         pcitag_t bustag = pa->pa_intrtag;
 374         int buspin = pa->pa_intrpin;
 375         pci_chipset_tag_t pc = pa->pa_pc;
 376         int device, irq;
 377
 378         if (buspin == 0) {
 379                 /* No IRQ used. */
 380                 return (1);
 381         }
 382
 383         if (buspin > 4) {
 384                 printf("dec_2100_a500_icic_intr_map: bad interrupt in %d\n",
 385                     buspin);
 386                 return (1);
 387         }
 388
 389         pci_decompose_tag(pc, bustag, NULL, &device, NULL);
 390         switch (device) {
 391         case 0:         /* on-board Ethernet */
 392                 irq = 24;
 393                 break;
 394
 395         case 1:         /* on-board SCSI */
 396                 irq = 28;
 397                 break;
 398
 399         case 6:         /* PCI slots */
 400         case 7:
 401         case 8:
 402                 irq = (32 + (4 * (device - 6))) + (buspin - 1);
 403                 break;
 404
 405         default:
 406                 printf("dec_2100_a500_icic_intr_map: bad device %d\n",
 407                     device);
 408                 return (1);
 409         }
 410
 411         *ihp = irq;
 412         return (0);
 413 }
 414
 415 const char *
 416 dec_2100_a500_intr_string(void *v, pci_intr_handle_t ih)
 417 {
 418         static char irqstr[15];         /* 11 + 2 + NULL + sanity */
 419
 420         if (ih >= SABLE_MAX_IRQ)
 421                 panic("dec_2100_a500_intr_string: bogus T2 IRQ 0x%lx", ih);
 422
 423         sprintf(irqstr, "T2 irq %ld", ih);
 424         return (irqstr);
 425 }
 426
 427 const struct evcnt *
 428 dec_2100_a500_intr_evcnt(void *v, pci_intr_handle_t ih)
 429 {
 430         struct ttwoga_config *tcp = v;
 431
 432         if (ih >= SABLE_MAX_IRQ)
 433                 panic("dec_2100_a500_intr_evcnt: bogus T2 IRQ 0x%lx", ih);
 434
 435         return (alpha_shared_intr_evcnt(tcp->tc_intrtab, ih));
 436 }
 437
 438 void *
 439 dec_2100_a500_intr_establish(void *v, pci_intr_handle_t ih, int level,
 440     int (*func)(void *), void *arg)
 441 {
 442         struct ttwoga_config *tcp = v;
 443         void *cookie;
 444
 445         if (ih >= SABLE_MAX_IRQ)
 446                 panic("dec_2100_a500_intr_establish: bogus IRQ 0x%lx",
 447                     ih);
 448
 449         cookie = alpha_shared_intr_establish(tcp->tc_intrtab, ih,
 450             dec_2100_a500_intr_deftype[ih], level, func, arg, "T2 irq");
 451
 452         if (cookie != NULL &&
 453             alpha_shared_intr_firstactive(tcp->tc_intrtab, ih)) {
 454                 scb_set(tcp->tc_vecbase + SCB_IDXTOVEC(ih),
 455                     dec_2100_a500_iointr, tcp, level);
 456                 (*tcp->tc_enable_intr)(tcp, ih, 1);
 457         }
 458
 459         return (cookie);
 460 }
 461
 462 void
 463 dec_2100_a500_intr_disestablish(void *v, void *cookie)
 464 {
 465         struct ttwoga_config *tcp = v;
 466         struct alpha_shared_intrhand *ih = cookie;
 467         unsigned int irq = ih->ih_num;
 468         int s;
 469
 470         s = splhigh();
 471
 472         alpha_shared_intr_disestablish(tcp->tc_intrtab, cookie,
 473             "T2 irq");
 474         if (alpha_shared_intr_isactive(tcp->tc_intrtab, irq) == 0) {
 475                 (*tcp->tc_enable_intr)(tcp, irq, 0);
 476                 alpha_shared_intr_set_dfltsharetype(tcp->tc_intrtab,
 477                     irq, dec_2100_a500_intr_deftype[irq]);
 478                 scb_free(tcp->tc_vecbase + SCB_IDXTOVEC(irq));
 479         }
 480
 481         splx(s);
 482 }
 483
 484 /*****************************************************************************
 485  * EISA interrupt support.
 486  *****************************************************************************/
 487
 488 int
 489 dec_2100_a500_eisa_intr_map(void *v, u_int eirq, eisa_intr_handle_t *ihp)
 490 {
 491
 492         if (eirq > 15) {
 493                 printf("dec_2100_a500_eisa_intr_map: bad EISA IRQ %d\n",
 494                     eirq);
 495                 *ihp = -1;
 496                 return (1);
 497         }
 498
 499         /*
 500          * EISA IRQ 13 is not connected.
 501          */
 502         if (eirq == 13) {
 503                 printf("dec_2100_a500_eisa_intr_map: EISA IRQ 13 not "
 504                     "connected\n");
 505                 *ihp = -1;
 506                 return (1);
 507         }
 508
 509         /*
 510          * Don't map to a T2 IRQ here; we must do this when we hook the
 511          * interrupt up, since ISA interrupts aren't explicitly translated.
 512          */
 513
 514         *ihp = eirq;
 515         return (0);
 516 }
 517
 518 const char *
 519 dec_2100_a500_eisa_intr_string(void *v, int eirq)
 520 {
 521         static char irqstr[32];
 522
 523         if (eirq > 15 || eirq == 13)
 524                 panic("dec_2100_a500_eisa_intr_string: bogus EISA IRQ 0x%x",
 525                     eirq);
 526
 527         sprintf(irqstr, "eisa irq %d (T2 irq %d)", eirq,
 528             eirq + T2_IRQ_EISA_START);
 529         return (irqstr);
 530 }
 531
 532 const struct evcnt *
 533 dec_2100_a500_eisa_intr_evcnt(void *v, int eirq)
 534 {
 535         struct ttwoga_config *tcp = v;
 536
 537         if (eirq > 15 || eirq == 13)
 538                 panic("dec_2100_a500_eisa_intr_evcnt: bogus EISA IRQ 0x%x",
 539                     eirq);
 540
 541         return (alpha_shared_intr_evcnt(tcp->tc_intrtab,
 542             eirq + T2_IRQ_EISA_START));
 543 }
 544
 545 void *
 546 dec_2100_a500_eisa_intr_establish(void *v, int eirq, int type, int level,
 547     int (*fn)(void *), void *arg)
 548 {
 549         struct ttwoga_config *tcp = v;
 550         void *cookie;
 551         int irq;
 552
 553         if (eirq > 15 || type == IST_NONE)
 554                 panic("dec_2100_a500_eisa_intr_establish: bogus irq or type");
 555
 556         if (eirq == 13) {
 557                 printf("dec_2100_a500_eisa_intr_establish: EISA IRQ 13 not "
 558                     "connected\n");
 559                 return (NULL);
 560         }
 561
 562         irq = eirq + T2_IRQ_EISA_START;
 563
 564         /*
 565          * We can't change the trigger type of some interrupts.  Don't allow
 566          * level triggers to be hooked up to non-changeable edge triggers.
 567          */
 568         if (dec_2100_a500_intr_deftype[irq] == IST_EDGE && type == IST_LEVEL) {
 569                 printf("dec_2100_a500_eisa_intr_establish: non-EDGE on EDGE\n");
 570                 return (NULL);
 571         }
 572
 573         cookie = alpha_shared_intr_establish(tcp->tc_intrtab, irq,
 574             type, level, fn, arg, "T2 irq");
 575
 576         if (cookie != NULL &&
 577             alpha_shared_intr_firstactive(tcp->tc_intrtab, irq)) {
 578                 scb_set(tcp->tc_vecbase + SCB_IDXTOVEC(irq),
 579                     dec_2100_a500_iointr, tcp, level);
 580                 (*tcp->tc_setlevel)(tcp, eirq,
 581                     alpha_shared_intr_get_sharetype(tcp->tc_intrtab,
 582                                                     irq) == IST_LEVEL);
 583                 (*tcp->tc_enable_intr)(tcp, irq, 1);
 584         }
 585
 586         return (cookie);
 587 }
 588
 589 void
 590 dec_2100_a500_eisa_intr_disestablish(void *v, void *cookie)
 591 {
 592         struct ttwoga_config *tcp = v;
 593         struct alpha_shared_intrhand *ih = cookie;
 594         int s, irq = ih->ih_num;
 595
 596         s = splhigh();
 597
 598         /* Remove it from the link. */
 599         alpha_shared_intr_disestablish(tcp->tc_intrtab, cookie,
 600             "T2 irq");
 601
 602         if (alpha_shared_intr_isactive(tcp->tc_intrtab, irq) == 0) {
 603                 (*tcp->tc_enable_intr)(tcp, irq, 0);
 604                 alpha_shared_intr_set_dfltsharetype(tcp->tc_intrtab,
 605                     irq, dec_2100_a500_intr_deftype[irq]);
 606                 scb_free(tcp->tc_vecbase + SCB_IDXTOVEC(irq));
 607         }
 608
 609         splx(s);
 610 }
 611
 612 int
 613 dec_2100_a500_eisa_intr_alloc(void *v, int mask, int type, int *eirqp)
 614 {
 615
 616         /* XXX Not supported right now. */
 617         return (1);
 618 }
 619
 620 /*****************************************************************************
 621  * Interrupt support routines.
 622  *****************************************************************************/
 623
 624 #define ICIC_ADDR(tcp, addr)                                            \
 625 do {                                                                    \
 626         alpha_mb();                                                     \
 627         T2GA((tcp), T2_AIR) = (addr);                                   \
 628         alpha_mb();                                                     \
 629         alpha_mb();                                                     \
 630         (void) T2GA((tcp), T2_AIR);                                     \
 631         alpha_mb();                                                     \
 632         alpha_mb();                                                     \
 633 } while (0)
 634
 635 #define ICIC_READ(tcp)  T2GA((tcp), T2_DIR)
 636 #define ICIC_WRITE(tcp, val)                                            \
 637 do {                                                                    \
 638         alpha_mb();                                                     \
 639         T2GA((tcp), T2_DIR) = (val);                                    \
 640         alpha_mb();                                                     \
 641         alpha_mb();                                                     \
 642 } while (0)
 643
 644 void
 645 dec_2100_a500_iointr(void *arg, u_long vec)
 646 {
 647         struct ttwoga_config *tcp = arg;
 648         int irq, rv;
 649
 650         irq = SCB_VECTOIDX(vec - tcp->tc_vecbase);
 651
 652         rv = alpha_shared_intr_dispatch(tcp->tc_intrtab, irq);
 653         (*tcp->tc_eoi)(tcp, irq);
 654         if (rv == 0) {
 655                 alpha_shared_intr_stray(tcp->tc_intrtab, irq, "T2 irq");
 656                 if (ALPHA_SHARED_INTR_DISABLE(tcp->tc_intrtab, irq))
 657                         (*tcp->tc_enable_intr)(tcp, irq, 0);
 658         } else
 659                 alpha_shared_intr_reset_strays(tcp->tc_intrtab, irq);
 660 }
 661
 662 void
 663 dec_2100_a500_pic_enable_intr(struct ttwoga_config *tcp, int irq, int onoff)
 664 {
 665         int pic;
 666         u_int8_t bit, mask;
 667
 668         pic = irq >> 3;
 669         bit = 1 << (irq & 0x7);
 670
 671         mask = bus_space_read_1(pic_iot, pic_slave_ioh[pic], 1);
 672         if (onoff)
 673                 mask &= ~bit;
 674         else
 675                 mask |= bit;
 676         bus_space_write_1(pic_iot, pic_slave_ioh[pic], 1, mask);
 677 }
 678
 679 void
 680 dec_2100_a500_icic_enable_intr(struct ttwoga_config *tcp, int irq, int onoff)
 681 {
 682         u_int64_t bit, mask;
 683
 684         bit = 1UL << irq;
 685
 686         ICIC_ADDR(tcp, 0x40);
 687
 688         mask = ICIC_READ(tcp);
 689         if (onoff)
 690                 mask &= ~bit;
 691         else
 692                 mask |= bit;
 693         ICIC_WRITE(tcp, mask);
 694 }
 695
 696 void
 697 dec_2100_a500_pic_init_intr(struct ttwoga_config *tcp)
 698 {
 699         static const int picaddr[4] = {
 700                 0x536, 0x53a, 0x53c, 0x53e
 701         };
 702         int pic;
 703
 704         /*
 705          * Map the master PIC.
 706          */
 707         if (bus_space_map(pic_iot, 0x534, 2, 0, &pic_master_ioh))
 708                 panic("dec_2100_a500_pic_init_intr: unable to map master PIC");
 709
 710         /*
 711          * Map all slave PICs and mask off the interrupts on them.
 712          */
 713         for (pic = 0; pic < 4; pic++) {
 714                 if (bus_space_map(pic_iot, picaddr[pic], 2, 0,
 715                     &pic_slave_ioh[pic]))
 716                         panic("dec_2100_a500_pic_init_intr: unable to map "
 717                             "slave PIC %d", pic);
 718                 bus_space_write_1(pic_iot, pic_slave_ioh[pic], 1, 0xff);
 719         }
 720
 721         /*
 722          * Map the ELCR registers.
 723          */
 724         if (bus_space_map(pic_iot, 0x26, 2, 0, &pic_elcr_ioh))
 725                 panic("dec_2100_a500_pic_init_intr: unable to map ELCR "
 726                     "registers");
 727 }
 728
 729 void
 730 dec_2100_a500_icic_init_intr(struct ttwoga_config *tcp)
 731 {
 732
 733         ICIC_ADDR(tcp, 0x40);
 734         ICIC_WRITE(tcp, 0xffffffffffffffffUL);
 735 }
 736
 737 void
 738 dec_2100_a500_pic_setlevel(struct ttwoga_config *tcp, int eirq, int level)
 739 {
 740         int elcr;
 741         u_int8_t bit, mask;
 742
 743         switch (eirq) {         /* EISA IRQ */
 744         case 3:
 745         case 4:
 746         case 5:
 747         case 6:
 748         case 7:
 749                 elcr = 0;
 750                 bit = 1 << (eirq - 3);
 751                 break;
 752
 753         case 9:
 754         case 10:
 755         case 11:
 756                 elcr = 0;
 757                 bit = 1 << (eirq - 4);
 758                 break;
 759
 760         case 12:
 761                 elcr = 1;
 762                 bit = 1 << (eirq - 12);
 763                 break;
 764
 765         case 14:
 766         case 15:
 767                 elcr = 1;
 768                 bit = 1 << (eirq - 13);
 769                 break;
 770
 771         default:
 772                 panic("dec_2100_a500_pic_setlevel: bogus EISA IRQ %d", eirq);
 773         }
 774
 775         mask = bus_space_read_1(pic_iot, pic_elcr_ioh, elcr);
 776         if (level)
 777                 mask |= bit;
 778         else
 779                 mask &= ~bit;
 780         bus_space_write_1(pic_iot, pic_elcr_ioh, elcr, mask);
 781 }
 782
 783 void
 784 dec_2100_a500_icic_setlevel(struct ttwoga_config *tcp, int eirq, int level)
 785 {
 786         u_int64_t bit, mask;
 787
 788         switch (eirq) {
 789         case 3:
 790         case 4:
 791         case 5:
 792         case 6:
 793         case 7:
 794         case 9:
 795         case 10:
 796         case 11:
 797         case 12:
 798         case 14:
 799         case 15:
 800                 bit = 1UL << (eirq + T2_IRQ_EISA_START);
 801
 802                 ICIC_ADDR(tcp, 0x50);
 803                 mask = ICIC_READ(tcp);
 804                 if (level)
 805                         mask |= bit;
 806                 else
 807                         mask &= ~bit;
 808                 ICIC_WRITE(tcp, mask);
 809                 break;
 810
 811         default:
 812                 panic("dec_2100_a500_icic_setlevel: bogus EISA IRQ %d", eirq);
 813         }
 814 }
 815
 816 void
 817 dec_2100_a500_pic_eoi(struct ttwoga_config *tcp, int irq)
 818 {
 819         int pic;
 820
 821         if (irq >= 0 && irq <= 7)
 822                 pic = 0;
 823         else if (irq >= 8 && irq <= 15)
 824                 pic = 1;
 825         else if (irq >= 16 && irq <= 23)
 826                 pic = 2;
 827         else
 828                 pic = 3;
 829
 830         bus_space_write_1(pic_iot, pic_slave_ioh[pic], 0,
 831             0xe0 | (irq - (8 * pic)));
 832         bus_space_write_1(pic_iot, pic_master_ioh, 0,
 833             0xe0 | pic_slave_to_master[pic]);
 834 }
 835
 836 void
 837 dec_2100_a500_icic_eoi(struct ttwoga_config *tcp, int irq)
 838 {
 839
 840         T2GA(tcp, T2_VAR) = irq;
 841         alpha_mb();
 842         alpha_mb();     /* MAGIC */
 843 }