sys/arch/alpha/pci/pci_550.c

   1 /* $NetBSD: pci_550.c,v 1.31 2009/03/14 21:04:02 dsl Exp $ */
   2
   3 /*-
   4  * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
   9  * NASA Ames Research Center, and by Andrew Gallatin.
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  * 1. Redistributions of source code must retain the above copyright
  15  *    notice, this list of conditions and the following disclaimer.
  16  * 2. Redistributions in binary form must reproduce the above copyright
  17  *    notice, this list of conditions and the following disclaimer in the
  18  *    documentation and/or other materials provided with the distribution.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  21  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  22  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  23  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30  * POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 /*
  34  * Copyright (c) 1995, 1996 Carnegie-Mellon University.
  35  * All rights reserved.
  36  *
  37  * Author: Chris G. Demetriou
  38  *
  39  * Permission to use, copy, modify and distribute this software and
  40  * its documentation is hereby granted, provided that both the copyright
  41  * notice and this permission notice appear in all copies of the
  42  * software, derivative works or modified versions, and any portions
  43  * thereof, and that both notices appear in supporting documentation.
  44  *
  45  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
  46  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
  47  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
  48  *
  49  * Carnegie Mellon requests users of this software to return to
  50  *
  51  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
  52  *  School of Computer Science
  53  *  Carnegie Mellon University
  54  *  Pittsburgh PA 15213-3890
  55  *
  56  * any improvements or extensions that they make and grant Carnegie the
  57  * rights to redistribute these changes.
  58  */
  59
  60 #include <sys/cdefs.h>                  /* RCS ID & Copyright macro defns */
  61
  62 __KERNEL_RCSID(0, "$NetBSD: pci_550.c,v 1.31 2009/03/14 21:04:02 dsl Exp $");
  63
  64 #include <sys/types.h>
  65 #include <sys/param.h>
  66 #include <sys/time.h>
  67 #include <sys/systm.h>
  68 #include <sys/errno.h>
  69 #include <sys/malloc.h>
  70 #include <sys/device.h>
  71 #include <sys/syslog.h>
  72
  73 #include <uvm/uvm_extern.h>
  74
  75 #include <machine/autoconf.h>
  76 #include <machine/rpb.h>
  77
  78 #include <dev/pci/pcireg.h>
  79 #include <dev/pci/pcivar.h>
  80 #include <dev/pci/pciidereg.h>
  81 #include <dev/pci/pciidevar.h>
  82
  83 #include <alpha/pci/ciareg.h>
  84 #include <alpha/pci/ciavar.h>
  85
  86 #include <alpha/pci/pci_550.h>
  87
  88 #include "sio.h"
  89 #if NSIO
  90 #include <alpha/pci/siovar.h>
  91 #endif
  92
  93 int     dec_550_intr_map(struct pci_attach_args *,
  94             pci_intr_handle_t *);
  95 const char *dec_550_intr_string(void *, pci_intr_handle_t);
  96 const struct evcnt *dec_550_intr_evcnt(void *, pci_intr_handle_t);
  97 void    *dec_550_intr_establish(void *, pci_intr_handle_t,
  98             int, int (*func)(void *), void *);
  99 void    dec_550_intr_disestablish(void *, void *);
 100
 101 void    *dec_550_pciide_compat_intr_establish(void *, struct device *,
 102             struct pci_attach_args *, int, int (*)(void *), void *);
 103
 104 #define DEC_550_PCI_IRQ_BEGIN   8
 105 #define DEC_550_MAX_IRQ         (64 - DEC_550_PCI_IRQ_BEGIN)
 106
 107 /*
 108  * The Miata has a Pyxis, which seems to have problems with stray
 109  * interrupts.  Work around this by just ignoring strays.
 110  */
 111 #define PCI_STRAY_MAX           0
 112
 113 /*
 114  * Some Miata models, notably models with a Cypress PCI-ISA bridge, have
 115  * a PCI device (the OHCI USB controller) with interrupts tied to ISA IRQ
 116  * lines.  This IRQ is encoded as: line = FLAG | isa_irq. Usually FLAG
 117  * is 0xe0, however, it can be 0xf0.  We don't allow 0xf0 | irq15.
 118  */
 119 #define DEC_550_LINE_IS_ISA(line)       ((line) >= 0xe0 && (line) <= 0xfe)
 120 #define DEC_550_LINE_ISA_IRQ(line)      ((line) & 0x0f)
 121
 122 struct alpha_shared_intr *dec_550_pci_intr;
 123
 124 void    dec_550_iointr(void *arg, unsigned long vec);
 125 void    dec_550_intr_enable(int irq);
 126 void    dec_550_intr_disable(int irq);
 127
 128 void
 129 pci_550_pickintr(struct cia_config *ccp)
 130 {
 131         bus_space_tag_t iot = &ccp->cc_iot;
 132         pci_chipset_tag_t pc = &ccp->cc_pc;
 133         char *cp;
 134         int i;
 135
 136         pc->pc_intr_v = ccp;
 137         pc->pc_intr_map = dec_550_intr_map;
 138         pc->pc_intr_string = dec_550_intr_string;
 139         pc->pc_intr_evcnt = dec_550_intr_evcnt;
 140         pc->pc_intr_establish = dec_550_intr_establish;
 141         pc->pc_intr_disestablish = dec_550_intr_disestablish;
 142
 143         pc->pc_pciide_compat_intr_establish =
 144             dec_550_pciide_compat_intr_establish;
 145
 146         /*
 147          * DEC 550's interrupts are enabled via the Pyxis interrupt
 148          * mask register.  Nothing to map.
 149          */
 150
 151         for (i = 0; i < DEC_550_MAX_IRQ; i++)
 152                 dec_550_intr_disable(i);
 153
 154         dec_550_pci_intr = alpha_shared_intr_alloc(DEC_550_MAX_IRQ, 8);
 155         for (i = 0; i < DEC_550_MAX_IRQ; i++) {
 156                 alpha_shared_intr_set_maxstrays(dec_550_pci_intr, i,
 157                     PCI_STRAY_MAX);
 158                 alpha_shared_intr_set_private(dec_550_pci_intr, i, ccp);
 159
 160                 cp = alpha_shared_intr_string(dec_550_pci_intr, i);
 161                 sprintf(cp, "irq %d", i);
 162                 evcnt_attach_dynamic(alpha_shared_intr_evcnt(
 163                     dec_550_pci_intr, i), EVCNT_TYPE_INTR, NULL,
 164                     "dec_550", cp);
 165         }
 166
 167 #if NSIO
 168         sio_intr_setup(pc, iot);
 169 #endif
 170 }
 171
 172 int
 173 dec_550_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
 174 {
 175         pcitag_t bustag = pa->pa_intrtag;
 176         int buspin = pa->pa_intrpin, line = pa->pa_intrline;
 177         pci_chipset_tag_t pc = pa->pa_pc;
 178         int bus, device, function;
 179
 180         if (buspin == 0) {
 181                 /* No IRQ used. */
 182                 return 1;
 183         }
 184         if (buspin > 4) {
 185                 printf("dec_550_intr_map: bad interrupt pin %d\n", buspin);
 186                 return 1;
 187         }
 188
 189         pci_decompose_tag(pc, bustag, &bus, &device, &function);
 190
 191         /*
 192          * There are two main variants of Miata: Miata 1 (Intel SIO)
 193          * and Miata {1.5,2} (Cypress).
 194          *
 195          * The Miata 1 has a CMD PCI IDE wired to compatibility mode at
 196          * device 4 of bus 0.  This variant apparently also has the
 197          * Pyxis DMA bug.
 198          *
 199          * On the Miata 1.5 and Miata 2, the Cypress PCI-ISA bridge lives
 200          * on device 7 of bus 0.  This device has PCI IDE wired to
 201          * compatibility mode on functions 1 and 2.
 202          *
 203          * There will be no interrupt mapping for these devices, so just
 204          * bail out now.
 205          */
 206         if (bus == 0) {
 207                 if ((hwrpb->rpb_variation & SV_ST_MASK) < SV_ST_MIATA_1_5) {
 208                         /* Miata 1 */
 209                         if (device == 7)
 210                                 panic("dec_550_intr_map: SIO device");
 211                         else if (device == 4)
 212                                 return (1);
 213                 } else {
 214                         /* Miata 1.5 or Miata 2 */
 215                         if (device == 7) {
 216                                 if (function == 0)
 217                                         panic("dec_550_intr_map: SIO device");
 218                                 if (function == 1 || function == 2)
 219                                         return (1);
 220                         }
 221                 }
 222         }
 223
 224         /*
 225          * The console places the interrupt mapping in the "line" value.
 226          * A value of (char)-1 indicates there is no mapping.
 227          */
 228         if (line == 0xff) {
 229                 printf("dec_550_intr_map: no mapping for %d/%d/%d\n",
 230                     bus, device, function);
 231                 return (1);
 232         }
 233
 234 #if NSIO == 0
 235         if (DEC_550_LINE_IS_ISA(line)) {
 236                 printf("dec_550_intr_map: ISA IRQ %d for %d/%d/%d\n",
 237                     DEC_550_LINE_ISA_IRQ(line), bus, device, function);
 238                 return (1);
 239         }
 240 #endif
 241
 242         if (DEC_550_LINE_IS_ISA(line) == 0 && line >= DEC_550_MAX_IRQ) {
 243                 printf("dec_550_intr_map: irq %d out of range %d/%d/%d\n",
 244                     line, bus, device, function);
 245                 return (1);
 246         }
 247         *ihp = line;
 248         return (0);
 249 }
 250
 251 const char *
 252 dec_550_intr_string(void *ccv, pci_intr_handle_t ih)
 253 {
 254 #if 0
 255         struct cia_config *ccp = ccv;
 256 #endif
 257         static char irqstr[16];         /* 12 + 2 + NULL + sanity */
 258
 259 #if NSIO
 260         if (DEC_550_LINE_IS_ISA(ih))
 261                 return (sio_intr_string(NULL /*XXX*/,
 262                     DEC_550_LINE_ISA_IRQ(ih)));
 263 #endif
 264
 265         if (ih >= DEC_550_MAX_IRQ)
 266                 panic("dec_550_intr_string: bogus 550 IRQ 0x%lx", ih);
 267         sprintf(irqstr, "dec 550 irq %ld", ih);
 268         return (irqstr);
 269 }
 270
 271 const struct evcnt *
 272 dec_550_intr_evcnt(void *ccv, pci_intr_handle_t ih)
 273 {
 274 #if 0
 275         struct cia_config *ccp = ccv;
 276 #endif
 277
 278 #if NSIO
 279         if (DEC_550_LINE_IS_ISA(ih))
 280                 return (sio_intr_evcnt(NULL /*XXX*/,
 281                     DEC_550_LINE_ISA_IRQ(ih)));
 282 #endif
 283
 284         if (ih >= DEC_550_MAX_IRQ)
 285                 panic("dec_550_intr_evcnt: bogus 550 IRQ 0x%lx", ih);
 286
 287         return (alpha_shared_intr_evcnt(dec_550_pci_intr, ih));
 288 }
 289
 290 void *
 291 dec_550_intr_establish(void *ccv, pci_intr_handle_t ih, int level, int (*func)(void *), void *arg)
 292 {
 293 #if 0
 294         struct cia_config *ccp = ccv;
 295 #endif
 296         void *cookie;
 297
 298 #if NSIO
 299         if (DEC_550_LINE_IS_ISA(ih))
 300                 return (sio_intr_establish(NULL /*XXX*/,
 301                     DEC_550_LINE_ISA_IRQ(ih), IST_LEVEL, level, func, arg));
 302 #endif
 303
 304         if (ih >= DEC_550_MAX_IRQ)
 305                 panic("dec_550_intr_establish: bogus dec 550 IRQ 0x%lx", ih);
 306
 307         cookie = alpha_shared_intr_establish(dec_550_pci_intr, ih, IST_LEVEL,
 308             level, func, arg, "dec 550 irq");
 309
 310         if (cookie != NULL &&
 311             alpha_shared_intr_firstactive(dec_550_pci_intr, ih)) {
 312                 scb_set(0x900 + SCB_IDXTOVEC(ih), dec_550_iointr, NULL,
 313                     level);
 314                 dec_550_intr_enable(ih);
 315         }
 316         return (cookie);
 317 }
 318
 319 void
 320 dec_550_intr_disestablish(void *ccv, void *cookie)
 321 {
 322         struct cia_config *ccp = ccv;
 323         struct alpha_shared_intrhand *ih = cookie;
 324         unsigned int irq = ih->ih_num;
 325         int s;
 326
 327 #if NSIO
 328         /*
 329          * We have to determine if this is an ISA IRQ or not!  We do this
 330          * by checking to see if the intrhand points back to an intrhead
 331          * that points to our cia_config.  If not, it's an ISA IRQ.  Pretty
 332          * disgusting, eh?
 333          */
 334         if (ih->ih_intrhead->intr_private != ccp) {
 335                 sio_intr_disestablish(NULL /*XXX*/, cookie);
 336                 return;
 337         }
 338 #endif
 339
 340         s = splhigh();
 341
 342         alpha_shared_intr_disestablish(dec_550_pci_intr, cookie,
 343             "dec 550 irq");
 344         if (alpha_shared_intr_isactive(dec_550_pci_intr, irq) == 0) {
 345                 dec_550_intr_disable(irq);
 346                 alpha_shared_intr_set_dfltsharetype(dec_550_pci_intr, irq,
 347                     IST_NONE);
 348                 scb_free(0x900 + SCB_IDXTOVEC(irq));
 349         }
 350
 351         splx(s);
 352 }
 353
 354 void *
 355 dec_550_pciide_compat_intr_establish(void *v, struct device *dev, struct pci_attach_args *pa, int chan, int (*func)(void *), void *arg)
 356 {
 357         pci_chipset_tag_t pc = pa->pa_pc;
 358         void *cookie = NULL;
 359         int bus, irq;
 360
 361         pci_decompose_tag(pc, pa->pa_tag, &bus, NULL, NULL);
 362
 363         /*
 364          * If this isn't PCI bus #0, all bets are off.
 365          */
 366         if (bus != 0)
 367                 return (NULL);
 368
 369         irq = PCIIDE_COMPAT_IRQ(chan);
 370 #if NSIO
 371         cookie = sio_intr_establish(NULL /*XXX*/, irq, IST_EDGE, IPL_BIO,
 372             func, arg);
 373         if (cookie == NULL)
 374                 return (NULL);
 375         printf("%s: %s channel interrupting at %s\n", dev->dv_xname,
 376             PCIIDE_CHANNEL_NAME(chan), sio_intr_string(NULL /*XXX*/, irq));
 377 #endif
 378         return (cookie);
 379 }
 380
 381 void
 382 dec_550_iointr(void *arg, unsigned long vec)
 383 {
 384         int irq;
 385
 386         irq = SCB_VECTOIDX(vec - 0x900);
 387
 388         if (irq >= DEC_550_MAX_IRQ)
 389                 panic("550_iointr: vec 0x%lx out of range", vec);
 390
 391         if (!alpha_shared_intr_dispatch(dec_550_pci_intr, irq)) {
 392                 alpha_shared_intr_stray(dec_550_pci_intr, irq,
 393                     "dec 550 irq");
 394                 if (ALPHA_SHARED_INTR_DISABLE(dec_550_pci_intr, irq))
 395                         dec_550_intr_disable(irq);
 396         } else
 397                 alpha_shared_intr_reset_strays(dec_550_pci_intr, irq);
 398 }
 399
 400 void
 401 dec_550_intr_enable(int irq)
 402 {
 403
 404         cia_pyxis_intr_enable(irq + DEC_550_PCI_IRQ_BEGIN, 1);
 405 }
 406
 407 void
 408 dec_550_intr_disable(int irq)
 409 {
 410
 411         cia_pyxis_intr_enable(irq + DEC_550_PCI_IRQ_BEGIN, 0);
 412 }