Sync usage with man page.
[netbsd-mini2440.git] / sys / arch / alpha / pci / pci_6600.c
blobac5cbd88fcf2e0d929361f40dac58de74e3f6d5b
1 /* $NetBSD: pci_6600.c,v 1.18 2009/03/14 21:04:02 dsl Exp $ */
3 /*-
4 * Copyright (c) 1999 by Ross Harvey. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Ross Harvey.
17 * 4. The name of Ross Harvey may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY ROSS HARVEY ``AS IS'' AND ANY EXPRESS
21 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP0SE
23 * ARE DISCLAIMED. IN NO EVENT SHALL ROSS HARVEY BE LIABLE FOR ANY
24 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
34 #include <sys/cdefs.h>
36 __KERNEL_RCSID(0, "$NetBSD: pci_6600.c,v 1.18 2009/03/14 21:04:02 dsl Exp $");
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/kernel.h>
41 #include <sys/device.h>
42 #include <sys/malloc.h>
44 #include <uvm/uvm_extern.h>
46 #include <machine/autoconf.h>
47 #define _ALPHA_BUS_DMA_PRIVATE
48 #include <machine/bus.h>
49 #include <machine/rpb.h>
50 #include <machine/alpha.h>
52 #include <dev/pci/pcireg.h>
53 #include <dev/pci/pcivar.h>
54 #include <dev/pci/pciidereg.h>
55 #include <dev/pci/pciidevar.h>
57 #include <alpha/pci/tsreg.h>
58 #include <alpha/pci/tsvar.h>
59 #include <alpha/pci/pci_6600.h>
61 #define pci_6600() { Generate ctags(1) key. }
63 #include "sio.h"
64 #if NSIO
65 #include <alpha/pci/siovar.h>
66 #endif
68 #define PCI_NIRQ 64
69 #define PCI_STRAY_MAX 5
72 * Some Tsunami models have a PCI device (the USB controller) with interrupts
73 * tied to ISA IRQ lines. The IRQ is encoded as:
75 * line = 0xe0 | isa_irq;
77 #define DEC_6600_LINE_IS_ISA(line) ((line) >= 0xe0 && (line) <= 0xef)
78 #define DEC_6600_LINE_ISA_IRQ(line) ((line) & 0x0f)
80 static const char *irqtype = "6600 irq";
81 static struct tsp_config *sioprimary;
83 void dec_6600_intr_disestablish(void *, void *);
84 void *dec_6600_intr_establish(
85 void *, pci_intr_handle_t, int, int (*func)(void *), void *);
86 const char *dec_6600_intr_string(void *, pci_intr_handle_t);
87 const struct evcnt *dec_6600_intr_evcnt(void *, pci_intr_handle_t);
88 int dec_6600_intr_map(struct pci_attach_args *, pci_intr_handle_t *);
89 void *dec_6600_pciide_compat_intr_establish(void *, struct device *,
90 struct pci_attach_args *, int, int (*)(void *), void *);
92 struct alpha_shared_intr *dec_6600_pci_intr;
94 void dec_6600_iointr(void *arg, unsigned long vec);
95 extern void dec_6600_intr_enable(int irq);
96 extern void dec_6600_intr_disable(int irq);
98 void
99 pci_6600_pickintr(struct tsp_config *pcp)
101 bus_space_tag_t iot = &pcp->pc_iot;
102 pci_chipset_tag_t pc = &pcp->pc_pc;
103 char *cp;
104 int i;
106 pc->pc_intr_v = pcp;
107 pc->pc_intr_map = dec_6600_intr_map;
108 pc->pc_intr_string = dec_6600_intr_string;
109 pc->pc_intr_evcnt = dec_6600_intr_evcnt;
110 pc->pc_intr_establish = dec_6600_intr_establish;
111 pc->pc_intr_disestablish = dec_6600_intr_disestablish;
112 pc->pc_pciide_compat_intr_establish = NULL;
115 * System-wide and Pchip-0-only logic...
117 if (dec_6600_pci_intr == NULL) {
118 sioprimary = pcp;
119 pc->pc_pciide_compat_intr_establish =
120 dec_6600_pciide_compat_intr_establish;
121 dec_6600_pci_intr = alpha_shared_intr_alloc(PCI_NIRQ, 8);
122 for (i = 0; i < PCI_NIRQ; i++) {
123 alpha_shared_intr_set_maxstrays(dec_6600_pci_intr, i,
124 PCI_STRAY_MAX);
125 alpha_shared_intr_set_private(dec_6600_pci_intr, i,
126 sioprimary);
128 cp = alpha_shared_intr_string(dec_6600_pci_intr, i);
129 sprintf(cp, "irq %d", i);
130 evcnt_attach_dynamic(alpha_shared_intr_evcnt(
131 dec_6600_pci_intr, i), EVCNT_TYPE_INTR, NULL,
132 "dec_6600", cp);
134 #if NSIO
135 sio_intr_setup(pc, iot);
136 dec_6600_intr_enable(55); /* irq line for sio */
137 #endif
141 int
142 dec_6600_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
144 pcitag_t bustag = pa->pa_intrtag;
145 int buspin = pa->pa_intrpin, line = pa->pa_intrline;
146 pci_chipset_tag_t pc = pa->pa_pc;
147 int bus, device, function;
149 if (buspin == 0) {
150 /* No IRQ used. */
151 return 1;
153 if (buspin > 4) {
154 printf("intr_map: bad interrupt pin %d\n", buspin);
155 return 1;
158 pci_decompose_tag(pc, bustag, &bus, &device, &function);
161 * The console places the interrupt mapping in the "line" value.
162 * A value of (char)-1 indicates there is no mapping.
164 if (line == 0xff) {
165 printf("dec_6600_intr_map: no mapping for %d/%d/%d\n",
166 bus, device, function);
167 return (1);
170 #if NSIO == 0
171 if (DEC_6600_LINE_IS_ISA(line)) {
172 printf("dec_6600_intr_map: ISA IRQ %d for %d/%d/%d\n",
173 DEC_6600_LINE_ISA_IRQ(line), bus, device, function);
174 return (1);
176 #endif
178 if (DEC_6600_LINE_IS_ISA(line) == 0 && line >= PCI_NIRQ)
179 panic("dec_6600_intr_map: dec 6600 irq too large (%d)",
180 line);
182 *ihp = line;
183 return (0);
186 const char *
187 dec_6600_intr_string(void *acv, pci_intr_handle_t ih)
190 static const char irqfmt[] = "dec 6600 irq %ld";
191 static char irqstr[sizeof irqfmt];
193 #if NSIO
194 if (DEC_6600_LINE_IS_ISA(ih))
195 return (sio_intr_string(NULL /*XXX*/,
196 DEC_6600_LINE_ISA_IRQ(ih)));
197 #endif
199 snprintf(irqstr, sizeof irqstr, irqfmt, ih);
200 return (irqstr);
203 const struct evcnt *
204 dec_6600_intr_evcnt(void *acv, pci_intr_handle_t ih)
207 #if NSIO
208 if (DEC_6600_LINE_IS_ISA(ih))
209 return (sio_intr_evcnt(NULL /*XXX*/,
210 DEC_6600_LINE_ISA_IRQ(ih)));
211 #endif
213 return (alpha_shared_intr_evcnt(dec_6600_pci_intr, ih));
216 void *
217 dec_6600_intr_establish(void *acv, pci_intr_handle_t ih, int level, int (*func)(void *), void *arg)
219 void *cookie;
221 #if NSIO
222 if (DEC_6600_LINE_IS_ISA(ih))
223 return (sio_intr_establish(NULL /*XXX*/,
224 DEC_6600_LINE_ISA_IRQ(ih), IST_LEVEL, level, func, arg));
225 #endif
227 if (ih >= PCI_NIRQ)
228 panic("dec_6600_intr_establish: bogus dec 6600 IRQ 0x%lx",
229 ih);
231 cookie = alpha_shared_intr_establish(dec_6600_pci_intr, ih, IST_LEVEL,
232 level, func, arg, irqtype);
234 if (cookie != NULL &&
235 alpha_shared_intr_firstactive(dec_6600_pci_intr, ih)) {
236 scb_set(0x900 + SCB_IDXTOVEC(ih), dec_6600_iointr, NULL,
237 level);
238 dec_6600_intr_enable(ih);
240 return (cookie);
243 void
244 dec_6600_intr_disestablish(void *acv, void *cookie)
246 struct alpha_shared_intrhand *ih = cookie;
247 unsigned int irq = ih->ih_num;
248 int s;
250 #if NSIO
252 * We have to determine if this is an ISA IRQ or not! We do this
253 * by checking to see if the intrhand points back to an intrhead
254 * that points to the sioprimary TSP. If not, it's an ISA IRQ.
255 * Pretty disgusting, eh?
257 if (ih->ih_intrhead->intr_private != sioprimary) {
258 sio_intr_disestablish(NULL /*XXX*/, cookie);
259 return;
261 #endif
263 s = splhigh();
265 alpha_shared_intr_disestablish(dec_6600_pci_intr, cookie, irqtype);
266 if (alpha_shared_intr_isactive(dec_6600_pci_intr, irq) == 0) {
267 dec_6600_intr_disable(irq);
268 alpha_shared_intr_set_dfltsharetype(dec_6600_pci_intr, irq,
269 IST_NONE);
270 scb_free(0x900 + SCB_IDXTOVEC(irq));
273 splx(s);
276 void
277 dec_6600_iointr(void *arg, unsigned long vec)
279 int irq;
281 irq = SCB_VECTOIDX(vec - 0x900);
283 if (irq >= PCI_NIRQ)
284 panic("iointr: irq %d is too high", irq);
286 if (!alpha_shared_intr_dispatch(dec_6600_pci_intr, irq)) {
287 alpha_shared_intr_stray(dec_6600_pci_intr, irq,
288 irqtype);
289 if (ALPHA_SHARED_INTR_DISABLE(dec_6600_pci_intr, irq))
290 dec_6600_intr_disable(irq);
291 } else
292 alpha_shared_intr_reset_strays(dec_6600_pci_intr, irq);
295 void
296 dec_6600_intr_enable(int irq)
298 alpha_mb();
299 STQP(TS_C_DIM0) |= 1UL << irq;
300 alpha_mb();
303 void
304 dec_6600_intr_disable(int irq)
306 alpha_mb();
307 STQP(TS_C_DIM0) &= ~(1UL << irq);
308 alpha_mb();
311 void *
312 dec_6600_pciide_compat_intr_establish(void *v, struct device *dev, struct pci_attach_args *pa, int chan, int (*func)(void *), void *arg)
314 pci_chipset_tag_t pc = pa->pa_pc;
315 void *cookie = NULL;
316 int bus, irq;
318 pci_decompose_tag(pc, pa->pa_tag, &bus, NULL, NULL);
321 * If this isn't PCI bus #0 on the TSP that holds the PCI-ISA
322 * bridge, all bets are off.
324 if (bus != 0 || pc->pc_intr_v != sioprimary)
325 return (NULL);
327 irq = PCIIDE_COMPAT_IRQ(chan);
328 #if NSIO
329 cookie = sio_intr_establish(NULL /*XXX*/, irq, IST_EDGE, IPL_BIO,
330 func, arg);
331 if (cookie == NULL)
332 return (NULL);
333 printf("%s: %s channel interrupting at %s\n", dev->dv_xname,
334 PCIIDE_CHANNEL_NAME(chan), sio_intr_string(NULL /*XXX*/, irq));
335 #endif
336 return (cookie);