sys/arch/alpha/pci/sio_pic.c

   1 /* $NetBSD: sio_pic.c,v 1.39 2009/03/14 21:04:02 dsl Exp $ */
   2
   3 /*-
   4  * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
   9  * NASA Ames Research Center.
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  * 1. Redistributions of source code must retain the above copyright
  15  *    notice, this list of conditions and the following disclaimer.
  16  * 2. Redistributions in binary form must reproduce the above copyright
  17  *    notice, this list of conditions and the following disclaimer in the
  18  *    documentation and/or other materials provided with the distribution.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  21  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  22  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  23  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30  * POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 /*
  34  * Copyright (c) 1995, 1996 Carnegie-Mellon University.
  35  * All rights reserved.
  36  *
  37  * Author: Chris G. Demetriou
  38  *
  39  * Permission to use, copy, modify and distribute this software and
  40  * its documentation is hereby granted, provided that both the copyright
  41  * notice and this permission notice appear in all copies of the
  42  * software, derivative works or modified versions, and any portions
  43  * thereof, and that both notices appear in supporting documentation.
  44  *
  45  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
  46  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
  47  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
  48  *
  49  * Carnegie Mellon requests users of this software to return to
  50  *
  51  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
  52  *  School of Computer Science
  53  *  Carnegie Mellon University
  54  *  Pittsburgh PA 15213-3890
  55  *
  56  * any improvements or extensions that they make and grant Carnegie the
  57  * rights to redistribute these changes.
  58  */
  59
  60 #include <sys/cdefs.h>                  /* RCS ID & Copyright macro defns */
  61
  62 __KERNEL_RCSID(0, "$NetBSD: sio_pic.c,v 1.39 2009/03/14 21:04:02 dsl Exp $");
  63
  64 #include <sys/param.h>
  65 #include <sys/systm.h>
  66 #include <sys/device.h>
  67 #include <sys/malloc.h>
  68 #include <sys/syslog.h>
  69
  70 #include <machine/intr.h>
  71 #include <machine/bus.h>
  72
  73 #include <dev/pci/pcireg.h>
  74 #include <dev/pci/pcivar.h>
  75 #include <dev/pci/pcidevs.h>
  76
  77 #include <dev/pci/cy82c693reg.h>
  78 #include <dev/pci/cy82c693var.h>
  79
  80 #include <dev/isa/isareg.h>
  81 #include <dev/isa/isavar.h>
  82 #include <alpha/pci/siovar.h>
  83
  84 #include "sio.h"
  85
  86 /*
  87  * To add to the long history of wonderful PROM console traits,
  88  * AlphaStation PROMs don't reset themselves completely on boot!
  89  * Therefore, if an interrupt was turned on when the kernel was
  90  * started, we're not going to EVER turn it off...  I don't know
  91  * what will happen if new interrupts (that the PROM console doesn't
  92  * want) are turned on.  I'll burn that bridge when I come to it.
  93  */
  94 #define BROKEN_PROM_CONSOLE
  95
  96 /*
  97  * Private functions and variables.
  98  */
  99
 100 bus_space_tag_t sio_iot;
 101 pci_chipset_tag_t sio_pc;
 102 bus_space_handle_t sio_ioh_icu1, sio_ioh_icu2;
 103
 104 #define ICU_LEN         16              /* number of ISA IRQs */
 105
 106 static struct alpha_shared_intr *sio_intr;
 107
 108 #ifndef STRAY_MAX
 109 #define STRAY_MAX       5
 110 #endif
 111
 112 #ifdef BROKEN_PROM_CONSOLE
 113 /*
 114  * If prom console is broken, must remember the initial interrupt
 115  * settings and enforce them.  WHEE!
 116  */
 117 u_int8_t initial_ocw1[2];
 118 u_int8_t initial_elcr[2];
 119 #endif
 120
 121 void            sio_setirqstat(int, int, int);
 122
 123 u_int8_t        (*sio_read_elcr)(int);
 124 void            (*sio_write_elcr)(int, u_int8_t);
 125 static void     specific_eoi(int);
 126 #ifdef BROKEN_PROM_CONSOLE
 127 void            sio_intr_shutdown(void *);
 128 #endif
 129
 130 /******************** i82378 SIO ELCR functions ********************/
 131
 132 int             i82378_setup_elcr(void);
 133 u_int8_t        i82378_read_elcr(int);
 134 void            i82378_write_elcr(int, u_int8_t);
 135
 136 bus_space_handle_t sio_ioh_elcr;
 137
 138 int
 139 i82378_setup_elcr()
 140 {
 141         int rv;
 142
 143         /*
 144          * We could probe configuration space to see that there's
 145          * actually an SIO present, but we are using this as a
 146          * fall-back in case nothing else matches.
 147          */
 148
 149         rv = bus_space_map(sio_iot, 0x4d0, 2, 0, &sio_ioh_elcr);
 150
 151         if (rv == 0) {
 152                 sio_read_elcr = i82378_read_elcr;
 153                 sio_write_elcr = i82378_write_elcr;
 154         }
 155
 156         return (rv);
 157 }
 158
 159 u_int8_t
 160 i82378_read_elcr(int elcr)
 161 {
 162
 163         return (bus_space_read_1(sio_iot, sio_ioh_elcr, elcr));
 164 }
 165
 166 void
 167 i82378_write_elcr(int elcr, u_int8_t val)
 168 {
 169
 170         bus_space_write_1(sio_iot, sio_ioh_elcr, elcr, val);
 171 }
 172
 173 /******************** Cypress CY82C693 ELCR functions ********************/
 174
 175 int             cy82c693_setup_elcr(void);
 176 u_int8_t        cy82c693_read_elcr(int);
 177 void            cy82c693_write_elcr(int, u_int8_t);
 178
 179 const struct cy82c693_handle *sio_cy82c693_handle;
 180
 181 int
 182 cy82c693_setup_elcr()
 183 {
 184         int device, maxndevs;
 185         pcitag_t tag;
 186         pcireg_t id;
 187
 188         /*
 189          * Search PCI configuration space for a Cypress CY82C693.
 190          *
 191          * Note we can make some assumptions about our bus number
 192          * here, because:
 193          *
 194          *      (1) there can be at most one ISA/EISA bridge per PCI bus, and
 195          *
 196          *      (2) any ISA/EISA bridges must be attached to primary PCI
 197          *          busses (i.e. bus zero).
 198          */
 199
 200         maxndevs = pci_bus_maxdevs(sio_pc, 0);
 201
 202         for (device = 0; device < maxndevs; device++) {
 203                 tag = pci_make_tag(sio_pc, 0, device, 0);
 204                 id = pci_conf_read(sio_pc, tag, PCI_ID_REG);
 205
 206                 /* Invalid vendor ID value? */
 207                 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID)
 208                         continue;
 209                 /* XXX Not invalid, but we've done this ~forever. */
 210                 if (PCI_VENDOR(id) == 0)
 211                         continue;
 212
 213                 if (PCI_VENDOR(id) != PCI_VENDOR_CONTAQ ||
 214                     PCI_PRODUCT(id) != PCI_PRODUCT_CONTAQ_82C693)
 215                         continue;
 216
 217                 /*
 218                  * Found one!
 219                  */
 220
 221 #if 0
 222                 printf("cy82c693_setup_elcr: found 82C693 at device %d\n",
 223                     device);
 224 #endif
 225
 226                 sio_cy82c693_handle = cy82c693_init(sio_iot);
 227                 sio_read_elcr = cy82c693_read_elcr;
 228                 sio_write_elcr = cy82c693_write_elcr;
 229
 230                 return (0);
 231         }
 232
 233         /*
 234          * Didn't find a CY82C693.
 235          */
 236         return (ENODEV);
 237 }
 238
 239 u_int8_t
 240 cy82c693_read_elcr(int elcr)
 241 {
 242
 243         return (cy82c693_read(sio_cy82c693_handle, CONFIG_ELCR1 + elcr));
 244 }
 245
 246 void
 247 cy82c693_write_elcr(int elcr, u_int8_t val)
 248 {
 249
 250         cy82c693_write(sio_cy82c693_handle, CONFIG_ELCR1 + elcr, val);
 251 }
 252
 253 /******************** ELCR access function configuration ********************/
 254
 255 /*
 256  * Put the Intel SIO at the end, so we fall back on it if we don't
 257  * find anything else.  If any of the non-Intel functions find a
 258  * matching device, but are unable to map it for whatever reason,
 259  * they should panic.
 260  */
 261
 262 int (*sio_elcr_setup_funcs[])(void) = {
 263         cy82c693_setup_elcr,
 264         i82378_setup_elcr,
 265         NULL,
 266 };
 267
 268 /******************** Shared SIO/Cypress functions ********************/
 269
 270 void
 271 sio_setirqstat(int irq, int enabled, int type)
 272 {
 273         u_int8_t ocw1[2], elcr[2];
 274         int icu, bit;
 275
 276 #if 0
 277         printf("sio_setirqstat: irq %d: %s, %s\n", irq,
 278             enabled ? "enabled" : "disabled", isa_intr_typename(type));
 279 #endif
 280
 281         icu = irq / 8;
 282         bit = irq % 8;
 283
 284         ocw1[0] = bus_space_read_1(sio_iot, sio_ioh_icu1, 1);
 285         ocw1[1] = bus_space_read_1(sio_iot, sio_ioh_icu2, 1);
 286         elcr[0] = (*sio_read_elcr)(0);                          /* XXX */
 287         elcr[1] = (*sio_read_elcr)(1);                          /* XXX */
 288
 289         /*
 290          * interrupt enable: set bit to mask (disable) interrupt.
 291          */
 292         if (enabled)
 293                 ocw1[icu] &= ~(1 << bit);
 294         else
 295                 ocw1[icu] |= 1 << bit;
 296
 297         /*
 298          * interrupt type select: set bit to get level-triggered.
 299          */
 300         if (type == IST_LEVEL)
 301                 elcr[icu] |= 1 << bit;
 302         else
 303                 elcr[icu] &= ~(1 << bit);
 304
 305 #ifdef not_here
 306         /* see the init function... */
 307         ocw1[0] &= ~0x04;               /* always enable IRQ2 on first PIC */
 308         elcr[0] &= ~0x07;               /* IRQ[0-2] must be edge-triggered */
 309         elcr[1] &= ~0x21;               /* IRQ[13,8] must be edge-triggered */
 310 #endif
 311
 312         bus_space_write_1(sio_iot, sio_ioh_icu1, 1, ocw1[0]);
 313         bus_space_write_1(sio_iot, sio_ioh_icu2, 1, ocw1[1]);
 314         (*sio_write_elcr)(0, elcr[0]);                          /* XXX */
 315         (*sio_write_elcr)(1, elcr[1]);                          /* XXX */
 316 }
 317
 318 void
 319 sio_intr_setup(pci_chipset_tag_t pc, bus_space_tag_t iot)
 320 {
 321         char *cp;
 322         int i;
 323
 324         sio_iot = iot;
 325         sio_pc = pc;
 326
 327         if (bus_space_map(sio_iot, IO_ICU1, 2, 0, &sio_ioh_icu1) ||
 328             bus_space_map(sio_iot, IO_ICU2, 2, 0, &sio_ioh_icu2))
 329                 panic("sio_intr_setup: can't map ICU I/O ports");
 330
 331         for (i = 0; sio_elcr_setup_funcs[i] != NULL; i++)
 332                 if ((*sio_elcr_setup_funcs[i])() == 0)
 333                         break;
 334         if (sio_elcr_setup_funcs[i] == NULL)
 335                 panic("sio_intr_setup: can't map ELCR");
 336
 337 #ifdef BROKEN_PROM_CONSOLE
 338         /*
 339          * Remember the initial values, so we can restore them later.
 340          */
 341         initial_ocw1[0] = bus_space_read_1(sio_iot, sio_ioh_icu1, 1);
 342         initial_ocw1[1] = bus_space_read_1(sio_iot, sio_ioh_icu2, 1);
 343         initial_elcr[0] = (*sio_read_elcr)(0);                  /* XXX */
 344         initial_elcr[1] = (*sio_read_elcr)(1);                  /* XXX */
 345         shutdownhook_establish(sio_intr_shutdown, 0);
 346 #endif
 347
 348         sio_intr = alpha_shared_intr_alloc(ICU_LEN, 8);
 349
 350         /*
 351          * set up initial values for interrupt enables.
 352          */
 353         for (i = 0; i < ICU_LEN; i++) {
 354                 alpha_shared_intr_set_maxstrays(sio_intr, i, STRAY_MAX);
 355
 356                 cp = alpha_shared_intr_string(sio_intr, i);
 357                 sprintf(cp, "irq %d", i);
 358                 evcnt_attach_dynamic(alpha_shared_intr_evcnt(sio_intr, i),
 359                     EVCNT_TYPE_INTR, NULL, "isa", cp);
 360
 361                 switch (i) {
 362                 case 0:
 363                 case 1:
 364                 case 8:
 365                 case 13:
 366                         /*
 367                          * IRQs 0, 1, 8, and 13 must always be
 368                          * edge-triggered.
 369                          */
 370                         sio_setirqstat(i, 0, IST_EDGE);
 371                         alpha_shared_intr_set_dfltsharetype(sio_intr, i,
 372                             IST_EDGE);
 373                         specific_eoi(i);
 374                         break;
 375
 376                 case 2:
 377                         /*
 378                          * IRQ 2 must be edge-triggered, and should be
 379                          * enabled (otherwise IRQs 8-15 are ignored).
 380                          */
 381                         sio_setirqstat(i, 1, IST_EDGE);
 382                         alpha_shared_intr_set_dfltsharetype(sio_intr, i,
 383                             IST_UNUSABLE);
 384                         break;
 385
 386                 default:
 387                         /*
 388                          * Otherwise, disable the IRQ and set its
 389                          * type to (effectively) "unknown."
 390                          */
 391                         sio_setirqstat(i, 0, IST_NONE);
 392                         alpha_shared_intr_set_dfltsharetype(sio_intr, i,
 393                             IST_NONE);
 394                         specific_eoi(i);
 395                         break;
 396                 }
 397         }
 398 }
 399
 400 #ifdef BROKEN_PROM_CONSOLE
 401 void
 402 sio_intr_shutdown(void *arg)
 403 {
 404         /*
 405          * Restore the initial values, to make the PROM happy.
 406          */
 407         bus_space_write_1(sio_iot, sio_ioh_icu1, 1, initial_ocw1[0]);
 408         bus_space_write_1(sio_iot, sio_ioh_icu2, 1, initial_ocw1[1]);
 409         (*sio_write_elcr)(0, initial_elcr[0]);                  /* XXX */
 410         (*sio_write_elcr)(1, initial_elcr[1]);                  /* XXX */
 411 }
 412 #endif
 413
 414 const char *
 415 sio_intr_string(void *v, int irq)
 416 {
 417         static char irqstr[12];         /* 8 + 2 + NULL + sanity */
 418
 419         if (irq == 0 || irq >= ICU_LEN || irq == 2)
 420                 panic("sio_intr_string: bogus isa irq 0x%x", irq);
 421
 422         sprintf(irqstr, "isa irq %d", irq);
 423         return (irqstr);
 424 }
 425
 426 const struct evcnt *
 427 sio_intr_evcnt(void *v, int irq)
 428 {
 429
 430         if (irq == 0 || irq >= ICU_LEN || irq == 2)
 431                 panic("sio_intr_evcnt: bogus isa irq 0x%x", irq);
 432
 433         return (alpha_shared_intr_evcnt(sio_intr, irq));
 434 }
 435
 436 void *
 437 sio_intr_establish(void *v, int irq, int type, int level, int (*fn)(void *), void *arg)
 438 {
 439         void *cookie;
 440
 441         if (irq > ICU_LEN || type == IST_NONE)
 442                 panic("sio_intr_establish: bogus irq or type");
 443
 444         cookie = alpha_shared_intr_establish(sio_intr, irq, type, level, fn,
 445             arg, "isa irq");
 446
 447         if (cookie != NULL &&
 448             alpha_shared_intr_firstactive(sio_intr, irq)) {
 449                 scb_set(0x800 + SCB_IDXTOVEC(irq), sio_iointr, NULL,
 450                     level);
 451                 sio_setirqstat(irq, 1,
 452                     alpha_shared_intr_get_sharetype(sio_intr, irq));
 453         }
 454
 455         return (cookie);
 456 }
 457
 458 void
 459 sio_intr_disestablish(void *v, void *cookie)
 460 {
 461         struct alpha_shared_intrhand *ih = cookie;
 462         int s, ist, irq = ih->ih_num;
 463
 464         s = splhigh();
 465
 466         /* Remove it from the link. */
 467         alpha_shared_intr_disestablish(sio_intr, cookie, "isa irq");
 468
 469         /*
 470          * Decide if we should disable the interrupt.  We must ensure
 471          * that:
 472          *
 473          *      - An initially-enabled interrupt is never disabled.
 474          *      - An initially-LT interrupt is never untyped.
 475          */
 476         if (alpha_shared_intr_isactive(sio_intr, irq) == 0) {
 477                 /*
 478                  * IRQs 0, 1, 8, and 13 must always be edge-triggered
 479                  * (see setup).
 480                  */
 481                 switch (irq) {
 482                 case 0:
 483                 case 1:
 484                 case 8:
 485                 case 13:
 486                         /*
 487                          * If the interrupt was initially level-triggered
 488                          * a warning was printed in setup.
 489                          */
 490                         ist = IST_EDGE;
 491                         break;
 492
 493                 default:
 494                         ist = IST_NONE;
 495                         break;
 496                 }
 497                 sio_setirqstat(irq, 0, ist);
 498                 alpha_shared_intr_set_dfltsharetype(sio_intr, irq, ist);
 499
 500                 /* Release our SCB vector. */
 501                 scb_free(0x800 + SCB_IDXTOVEC(irq));
 502         }
 503
 504         splx(s);
 505 }
 506
 507 void
 508 sio_iointr(void *arg, unsigned long vec)
 509 {
 510         int irq;
 511
 512         irq = SCB_VECTOIDX(vec - 0x800);
 513
 514 #ifdef DIAGNOSTIC
 515         if (irq > ICU_LEN || irq < 0)
 516                 panic("sio_iointr: irq out of range (%d)", irq);
 517 #endif
 518
 519         if (!alpha_shared_intr_dispatch(sio_intr, irq))
 520                 alpha_shared_intr_stray(sio_intr, irq, "isa irq");
 521         else
 522                 alpha_shared_intr_reset_strays(sio_intr, irq);
 523
 524         /*
 525          * Some versions of the machines which use the SIO
 526          * (or is it some PALcode revisions on those machines?)
 527          * require the non-specific EOI to be fed to the PIC(s)
 528          * by the interrupt handler.
 529          */
 530         specific_eoi(irq);
 531 }
 532
 533 #define LEGAL_IRQ(x)    ((x) >= 0 && (x) < ICU_LEN && (x) != 2)
 534
 535 int
 536 sio_intr_alloc(void *v, int mask, int type, int *irq)
 537 {
 538         int i, tmp, bestirq, count;
 539         struct alpha_shared_intrhand **p, *q;
 540
 541         if (type == IST_NONE)
 542                 panic("intr_alloc: bogus type");
 543
 544         bestirq = -1;
 545         count = -1;
 546
 547         /* some interrupts should never be dynamically allocated */
 548         mask &= 0xdef8;
 549
 550         /*
 551          * XXX some interrupts will be used later (6 for fdc, 12 for pms).
 552          * the right answer is to do "breadth-first" searching of devices.
 553          */
 554         mask &= 0xefbf;
 555
 556         for (i = 0; i < ICU_LEN; i++) {
 557                 if (LEGAL_IRQ(i) == 0 || (mask & (1<<i)) == 0)
 558                         continue;
 559
 560                 switch(sio_intr[i].intr_sharetype) {
 561                 case IST_NONE:
 562                         /*
 563                          * if nothing's using the irq, just return it
 564                          */
 565                         *irq = i;
 566                         return (0);
 567
 568                 case IST_EDGE:
 569                 case IST_LEVEL:
 570                         if (type != sio_intr[i].intr_sharetype)
 571                                 continue;
 572                         /*
 573                          * if the irq is shareable, count the number of other
 574                          * handlers, and if it's smaller than the last irq like
 575                          * this, remember it
 576                          *
 577                          * XXX We should probably also consider the
 578                          * interrupt level and stick IPL_TTY with other
 579                          * IPL_TTY, etc.
 580                          */
 581                         for (p = &TAILQ_FIRST(&sio_intr[i].intr_q), tmp = 0;
 582                              (q = *p) != NULL; p = &TAILQ_NEXT(q, ih_q), tmp++)
 583                                 ;
 584                         if ((bestirq == -1) || (count > tmp)) {
 585                                 bestirq = i;
 586                                 count = tmp;
 587                         }
 588                         break;
 589
 590                 case IST_PULSE:
 591                         /* this just isn't shareable */
 592                         continue;
 593                 }
 594         }
 595
 596         if (bestirq == -1)
 597                 return (1);
 598
 599         *irq = bestirq;
 600
 601         return (0);
 602 }
 603
 604 static void
 605 specific_eoi(int irq)
 606 {
 607         if (irq > 7)
 608                 bus_space_write_1(sio_iot,
 609                     sio_ioh_icu2, 0, 0x60 | (irq & 0x07));      /* XXX */
 610         bus_space_write_1(sio_iot, sio_ioh_icu1, 0, 0x60 | (irq > 7 ? 2 : irq));
 611 }