sys/arch/alpha/pci/tsreg.h

   1 /* $NetBSD: tsreg.h,v 1.2 2000/06/26 02:42:11 thorpej Exp $ */
   2
   3 /*-
   4  * Copyright (c) 1999 by Ross Harvey.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Ross Harvey.
  17  * 4. The name of Ross Harvey may not be used to endorse or promote products
  18  *    derived from this software without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY ROSS HARVEY ``AS IS'' AND ANY EXPRESS
  21  * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  22  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP0SE
  23  * ARE DISCLAIMED.  IN NO EVENT SHALL ROSS HARVEY BE LIABLE FOR ANY
  24  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  30  * SUCH DAMAGE.
  31  *
  32  */
  33
  34 /*
  35  * 21272 Core Logic registers and constants.
  36  */
  37
  38 #define tsreg() { Generate ctags(1) key. }
  39
  40 /*
  41  * Superpage pointer from physical address.
  42  */
  43 #define S_PAGE(phys) ((void *)ALPHA_PHYS_TO_K0SEG(phys))
  44
  45 /*
  46  * {LD,ST}QP: LoaD and STore Quad Physical
  47  */
  48 #define LDQP(a) (*(volatile long *)ALPHA_PHYS_TO_K0SEG(a))
  49 #define STQP(a) LDQP(a)
  50
  51 /*
  52  * Define extraction functions for bit fields via length and left,right bitno
  53  */
  54 #define TSFIELD(r,offs,len) (((r) >> (offs)) & (~0UL >> (64 - (len))))
  55 #define TSFIELDBB(r,lb,rb) TSFIELD((r), (rb), (lb) - (rb) + 1)
  56
  57 /*
  58  * EV6 has a new superpage which can pass through 44 address bits.  (Umm, a
  59  * superduperpage?) But, the firmware doesn't turn it on, so we use the old
  60  * one and let the HW sign extend va/pa<40> to get us the pa<43> that makes
  61  * the needed I/O space access. This is just as well; it means we don't have
  62  * to worry about which GENERIC code might get called on other CPU models.
  63  *
  64  *      E.g., we want this:           0x0801##a000##0000
  65  *      We use this:                  0x0101##a000##0000
  66  *      ...mix in the old SP:   0xffff##fc00##0000##0000
  67  *      ...after PA sign ext:   0xffff##ff00##a000##0000
  68  *      (PA<42:41> ignored)
  69  */
  70
  71 /*
  72  * This hack allows us to map the I/O address space without using
  73  * the KSEG sign extension hack.
  74  */
  75 #define TS_PHYSADDR(x)                                                  \
  76         (((x) & ~0x0100##0000##0000) | 0x0800##0000##0000)
  77
  78 /*
  79  * Cchip CSR Map
  80  */
  81
  82 #define TS_C_CSC        0x101##a000##0000UL     /* Cchip System Configuration */
  83
  84 #       define  CSC_P1P         (1L << 14)
  85 #       define  CSC_BC(r)       TSFIELD((r), 0, 2)
  86 #       define  CSC_AW          (1L << 8)
  87
  88 #define TS_C_MTR        0x101##a000##0040UL
  89
  90 #define TS_C_MISC       0x101##a000##0080UL     /* Miscellaneous Register */
  91
  92 #       define  MISC_REV(r)     TSFIELD((r), 39, 8)
  93
  94 #define TS_C_MPD        0x101##a000##00c0UL
  95
  96 #define TS_C_AAR0       0x101##a000##0100UL
  97 #define TS_C_AAR1       0x101##a000##0140UL
  98 #define TS_C_AAR2       0x101##a000##0180UL
  99 #define TS_C_AAR3       0x101##a000##01c0UL
 100
 101 #       define  AAR_ASIZ(r)     TSFIELD((r), 12, 4)
 102 #       define  AAR_SPLIT       (1L << 8)
 103
 104 #define TS_C_DIM0       0x101##a000##0200UL
 105 #define TS_C_DIM1       0x101##a000##0240UL
 106 #define TS_C_DIR0       0x101##a000##0280UL
 107 #define TS_C_DIR1       0x101##a000##02c0UL
 108 #define TS_C_DRIR       0x101##a000##0300UL
 109 #define TS_C_PRBEN      0x101##a000##0340UL
 110 #define TS_C_IIC0       0x101##a000##0380UL
 111 #define TS_C_IIC1       0x101##a000##03c0UL
 112 #define TS_C_MPR0       0x101##a000##0400UL
 113 #define TS_C_MPR1       0x101##a000##0440UL
 114 #define TS_C_MPR2       0x101##a000##0480UL
 115 #define TS_C_MPR3       0x101##a000##04c0UL
 116 #define TS_C_MCTL       0x101##a000##0500UL
 117
 118 #define TS_C_TTR        0x101##a000##0580UL
 119 #define TS_C_TDR        0x101##a000##05c0UL
 120
 121 /*
 122  * Dchip CSR Map
 123  */
 124
 125 #define TS_D_DSC        0x101##b000##0800UL
 126 #define TS_D_STR        0x101##b000##0840UL
 127 #define TS_D_DREV       0x101##b000##0880UL
 128 #define TS_D_DSC2       0x101##b000##08c0UL
 129
 130 /*
 131  * Pchip CSR Offsets
 132  */
 133
 134 #define P_WSBA0         0x0000
 135 #define P_WSBA1         0x0040
 136 #define P_WSBA2         0x0080
 137 #define P_WSBA3         0x00c0
 138
 139 #       define  WSBA_ADDR(r) (TSFIELDBB((r), 31, 20) << 20)
 140 #       define  WSBA_SG      2
 141 #       define  WSBA_ENA     1
 142
 143 #define P_WSM0          0x0100
 144 #define P_WSM1          0x0140
 145 #define P_WSM2          0x0180
 146 #define P_WSM3          0x01c0
 147
 148 #       define  WSM_AM(r)    TSFIELDBB((r), 31, 20)
 149 #       define  WSM_LEN(r)   ((WSM_AM(r) + 1) << 20)
 150
 151 #define P_TBA0          0x0200
 152 #define P_TBA1          0x0240
 153 #define P_TBA2          0x0280
 154 #define P_TBA3          0x02c0
 155
 156 #define P_PCTL          0x0300
 157 #define P_PLAT          0x0340
 158         /* reserved     0x0380 */
 159 #define P_PERROR        0x03c0
 160
 161 #define P_PERRMASK      0x0400
 162 #define P_PERRSET       0x0440
 163 #define P_TLBIV         0x0480
 164 #define P_TLBIA         0x04c0
 165
 166 #define P_PMONCTL       0x0500
 167 #define P_PMONCNT       0x0540
 168
 169 #define P_SPRST         0x0800
 170
 171 #define TS_STEP         0x40
 172
 173 /*
 174  * Pchip I/O offsets
 175  */
 176
 177 #define P_CSRBASE        0x001##8000##0000UL
 178 #define P_PCI_MEM        0
 179 #define P_PCI_IO         0x001##fc00##0000UL
 180 #define P_PCI_CONFIG     0x001##fe00##0000UL
 181
 182 /*
 183  * Construct EV6 I/O Space Address for Pchip 0 and Pchip 1.
 184  */
 185
 186 #define TS_P0(offs)     (0x100##0000##0000UL + (offs))
 187 #define TS_P1(offs)     (0x102##0000##0000UL + (offs))
 188 #define TS_Pn(n, offs)  (0x100##0000##0000UL + 0x2##0000##0000UL * (n) + (offs))
 189
 190 /*
 191  * Tsunami Generic Register Type
 192  */
 193 typedef struct _ts_gr {
 194         volatile u_int64_t tsg_r;
 195         long    tsg_deadspace[7];
 196 } TS_GR;
 197
 198 /*
 199  * Tsunami Pchip
 200  */
 201 struct  ts_pchip {
 202         TS_GR   tsp_wsba[4];    /* Window Space Base Address */
 203
 204         TS_GR   tsp_wsm[4];     /* Window Space Mask */
 205
 206         TS_GR   tsp_tba[4];     /* Translated Base Address */
 207
 208         TS_GR   tsp_pctl;       /* Pchip Control */
 209         TS_GR   tsp_plat;       /* Pchip Latency */
 210         TS_GR   tsp_resA;
 211         TS_GR   tsp_error;      /* Pchip Error */
 212
 213         TS_GR   tsp_perrmask;   /* Pchip Error Mask */
 214         TS_GR   tsp_perrset;    /* Pchip Error Set */
 215         TS_GR   tsp_tlbiv;      /* Translation Buffer Invalidate Virtual */
 216         TS_GR   tsp_tlbia;      /* Translation Buffer Invalidate All */
 217
 218         TS_GR   tsp_pmonctl;    /* PChip Monitor Control */
 219         TS_GR   tsp_pmoncnt;    /* PChip Monitor Counters */
 220         TS_GR   tsp_resB;
 221         TS_GR   tsp_resC;
 222
 223         TS_GR   tsp_resD_K[8];
 224
 225         TS_GR   tsp_sprts;      /* ??? */
 226 };