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[netbsd-mini2440.git] / sys / arch / alpha / tc / tc_bus_mem.c
blob8c6d60d222b99eeef55dbb533649a6c47c915678
1 /* $NetBSD: tc_bus_mem.c,v 1.29 2009/03/14 15:36:00 dsl Exp $ */
2
3 /*
4 * Copyright (c) 1996 Carnegie-Mellon University.
5 * All rights reserved.
6 *
7 * Author: Chris G. Demetriou
8 *
9 * Permission to use, copy, modify and distribute this software and
10 * its documentation is hereby granted, provided that both the copyright
11 * notice and this permission notice appear in all copies of the
12 * software, derivative works or modified versions, and any portions
13 * thereof, and that both notices appear in supporting documentation.
14 *
15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
18 *
19 * Carnegie Mellon requests users of this software to return to
20 *
21 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
22 * School of Computer Science
23 * Carnegie Mellon University
24 * Pittsburgh PA 15213-3890
25 *
26 * any improvements or extensions that they make and grant Carnegie the
27 * rights to redistribute these changes.
28 */
29
30 /*
31 * Common TurboChannel Chipset "bus memory" functions.
32 */
33
34 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
35
36 __KERNEL_RCSID(0, "$NetBSD: tc_bus_mem.c,v 1.29 2009/03/14 15:36:00 dsl Exp $");
37
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/malloc.h>
41 #include <sys/syslog.h>
42 #include <sys/device.h>
43
44 #include <uvm/uvm_extern.h>
45
46 #include <machine/bus.h>
47 #include <dev/tc/tcvar.h>
48
49 #define __C(A,B) __CONCAT(A,B)
50
51 /* mapping/unmapping */
52 int tc_mem_map(void *, bus_addr_t, bus_size_t, int,
53 bus_space_handle_t *, int);
54 void tc_mem_unmap(void *, bus_space_handle_t, bus_size_t, int);
55 int tc_mem_subregion(void *, bus_space_handle_t, bus_size_t,
56 bus_size_t, bus_space_handle_t *);
57
58 int tc_mem_translate(void *, bus_addr_t, bus_size_t,
59 int, struct alpha_bus_space_translation *);
60 int tc_mem_get_window(void *, int,
61 struct alpha_bus_space_translation *);
62
63 /* allocation/deallocation */
64 int tc_mem_alloc(void *, bus_addr_t, bus_addr_t, bus_size_t,
65 bus_size_t, bus_addr_t, int, bus_addr_t *,
66 bus_space_handle_t *);
67 void tc_mem_free(void *, bus_space_handle_t, bus_size_t);
68
69 /* get kernel virtual address */
70 void * tc_mem_vaddr(void *, bus_space_handle_t);
71
72 /* mmap for user */
73 paddr_t tc_mem_mmap(void *, bus_addr_t, off_t, int, int);
74
75 /* barrier */
76 inline void tc_mem_barrier(void *, bus_space_handle_t,
77 bus_size_t, bus_size_t, int);
78
79 /* read (single) */
80 inline u_int8_t tc_mem_read_1(void *, bus_space_handle_t, bus_size_t);
81 inline u_int16_t tc_mem_read_2(void *, bus_space_handle_t, bus_size_t);
82 inline u_int32_t tc_mem_read_4(void *, bus_space_handle_t, bus_size_t);
83 inline u_int64_t tc_mem_read_8(void *, bus_space_handle_t, bus_size_t);
84
85 /* read multiple */
86 void tc_mem_read_multi_1(void *, bus_space_handle_t,
87 bus_size_t, u_int8_t *, bus_size_t);
88 void tc_mem_read_multi_2(void *, bus_space_handle_t,
89 bus_size_t, u_int16_t *, bus_size_t);
90 void tc_mem_read_multi_4(void *, bus_space_handle_t,
91 bus_size_t, u_int32_t *, bus_size_t);
92 void tc_mem_read_multi_8(void *, bus_space_handle_t,
93 bus_size_t, u_int64_t *, bus_size_t);
94
95 /* read region */
96 void tc_mem_read_region_1(void *, bus_space_handle_t,
97 bus_size_t, u_int8_t *, bus_size_t);
98 void tc_mem_read_region_2(void *, bus_space_handle_t,
99 bus_size_t, u_int16_t *, bus_size_t);
100 void tc_mem_read_region_4(void *, bus_space_handle_t,
101 bus_size_t, u_int32_t *, bus_size_t);
102 void tc_mem_read_region_8(void *, bus_space_handle_t,
103 bus_size_t, u_int64_t *, bus_size_t);
104
105 /* write (single) */
106 inline void tc_mem_write_1(void *, bus_space_handle_t, bus_size_t,
107 u_int8_t);
108 inline void tc_mem_write_2(void *, bus_space_handle_t, bus_size_t,
109 u_int16_t);
110 inline void tc_mem_write_4(void *, bus_space_handle_t, bus_size_t,
111 u_int32_t);
112 inline void tc_mem_write_8(void *, bus_space_handle_t, bus_size_t,
113 u_int64_t);
114
115 /* write multiple */
116 void tc_mem_write_multi_1(void *, bus_space_handle_t,
117 bus_size_t, const u_int8_t *, bus_size_t);
118 void tc_mem_write_multi_2(void *, bus_space_handle_t,
119 bus_size_t, const u_int16_t *, bus_size_t);
120 void tc_mem_write_multi_4(void *, bus_space_handle_t,
121 bus_size_t, const u_int32_t *, bus_size_t);
122 void tc_mem_write_multi_8(void *, bus_space_handle_t,
123 bus_size_t, const u_int64_t *, bus_size_t);
124
125 /* write region */
126 void tc_mem_write_region_1(void *, bus_space_handle_t,
127 bus_size_t, const u_int8_t *, bus_size_t);
128 void tc_mem_write_region_2(void *, bus_space_handle_t,
129 bus_size_t, const u_int16_t *, bus_size_t);
130 void tc_mem_write_region_4(void *, bus_space_handle_t,
131 bus_size_t, const u_int32_t *, bus_size_t);
132 void tc_mem_write_region_8(void *, bus_space_handle_t,
133 bus_size_t, const u_int64_t *, bus_size_t);
134
135 /* set multiple */
136 void tc_mem_set_multi_1(void *, bus_space_handle_t,
137 bus_size_t, u_int8_t, bus_size_t);
138 void tc_mem_set_multi_2(void *, bus_space_handle_t,
139 bus_size_t, u_int16_t, bus_size_t);
140 void tc_mem_set_multi_4(void *, bus_space_handle_t,
141 bus_size_t, u_int32_t, bus_size_t);
142 void tc_mem_set_multi_8(void *, bus_space_handle_t,
143 bus_size_t, u_int64_t, bus_size_t);
144
145 /* set region */
146 void tc_mem_set_region_1(void *, bus_space_handle_t,
147 bus_size_t, u_int8_t, bus_size_t);
148 void tc_mem_set_region_2(void *, bus_space_handle_t,
149 bus_size_t, u_int16_t, bus_size_t);
150 void tc_mem_set_region_4(void *, bus_space_handle_t,
151 bus_size_t, u_int32_t, bus_size_t);
152 void tc_mem_set_region_8(void *, bus_space_handle_t,
153 bus_size_t, u_int64_t, bus_size_t);
154
155 /* copy */
156 void tc_mem_copy_region_1(void *, bus_space_handle_t,
157 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t);
158 void tc_mem_copy_region_2(void *, bus_space_handle_t,
159 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t);
160 void tc_mem_copy_region_4(void *, bus_space_handle_t,
161 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t);
162 void tc_mem_copy_region_8(void *, bus_space_handle_t,
163 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t);
164
165 static struct alpha_bus_space tc_mem_space = {
166 /* cookie */
167 NULL,
168
169 /* mapping/unmapping */
170 tc_mem_map,
171 tc_mem_unmap,
172 tc_mem_subregion,
173
174 tc_mem_translate,
175 tc_mem_get_window,
176
177 /* allocation/deallocation */
178 tc_mem_alloc,
179 tc_mem_free,
180
181 /* get kernel virtual address */
182 tc_mem_vaddr,
183
184 /* mmap for user */
185 tc_mem_mmap,
186
187 /* barrier */
188 tc_mem_barrier,
189
190 /* read (single) */
191 tc_mem_read_1,
192 tc_mem_read_2,
193 tc_mem_read_4,
194 tc_mem_read_8,
195
196 /* read multiple */
197 tc_mem_read_multi_1,
198 tc_mem_read_multi_2,
199 tc_mem_read_multi_4,
200 tc_mem_read_multi_8,
201
202 /* read region */
203 tc_mem_read_region_1,
204 tc_mem_read_region_2,
205 tc_mem_read_region_4,
206 tc_mem_read_region_8,
207
208 /* write (single) */
209 tc_mem_write_1,
210 tc_mem_write_2,
211 tc_mem_write_4,
212 tc_mem_write_8,
213
214 /* write multiple */
215 tc_mem_write_multi_1,
216 tc_mem_write_multi_2,
217 tc_mem_write_multi_4,
218 tc_mem_write_multi_8,
219
220 /* write region */
221 tc_mem_write_region_1,
222 tc_mem_write_region_2,
223 tc_mem_write_region_4,
224 tc_mem_write_region_8,
225
226 /* set multiple */
227 tc_mem_set_multi_1,
228 tc_mem_set_multi_2,
229 tc_mem_set_multi_4,
230 tc_mem_set_multi_8,
231
232 /* set region */
233 tc_mem_set_region_1,
234 tc_mem_set_region_2,
235 tc_mem_set_region_4,
236 tc_mem_set_region_8,
237
238 /* copy */
239 tc_mem_copy_region_1,
240 tc_mem_copy_region_2,
241 tc_mem_copy_region_4,
242 tc_mem_copy_region_8,
243 };
244
245 bus_space_tag_t
246 tc_bus_mem_init(void *memv)
247 {
248 bus_space_tag_t h = &tc_mem_space;
249
250 h->abs_cookie = memv;
251 return (h);
252 }
253
254 /* ARGSUSED */
255 int
256 tc_mem_translate(void *v, bus_addr_t memaddr, bus_size_t memlen, int flags, struct alpha_bus_space_translation *abst)
257 {
258
259 return (EOPNOTSUPP);
260 }
261
262 /* ARGSUSED */
263 int
264 tc_mem_get_window(void *v, int window, struct alpha_bus_space_translation *abst)
265 {
266
267 return (EOPNOTSUPP);
268 }
269
270 /* ARGSUSED */
271 int
272 tc_mem_map(void *v, bus_addr_t memaddr, bus_size_t memsize, int flags, bus_space_handle_t *memhp, int acct)
273 {
274 int cacheable = flags & BUS_SPACE_MAP_CACHEABLE;
275 int linear = flags & BUS_SPACE_MAP_LINEAR;
276
277 /* Requests for linear uncacheable space can't be satisfied. */
278 if (linear && !cacheable)
279 return (EOPNOTSUPP);
280
281 if (memaddr & 0x7)
282 panic("tc_mem_map needs 8 byte alignment");
283 if (cacheable)
284 *memhp = ALPHA_PHYS_TO_K0SEG(memaddr);
285 else
286 *memhp = ALPHA_PHYS_TO_K0SEG(TC_DENSE_TO_SPARSE(memaddr));
287 return (0);
288 }
289
290 /* ARGSUSED */
291 void
292 tc_mem_unmap(void *v, bus_space_handle_t memh, bus_size_t memsize, int acct)
293 {
294
295 /* XXX XX XXX nothing to do. */
296 }
297
298 int
299 tc_mem_subregion(void *v, bus_space_handle_t memh, bus_size_t offset, bus_size_t size, bus_space_handle_t *nmemh)
300 {
301
302 /* Disallow subregioning that would make the handle unaligned. */
303 if ((offset & 0x7) != 0)
304 return (1);
305
306 if ((memh & TC_SPACE_SPARSE) != 0)
307 *nmemh = memh + (offset << 1);
308 else
309 *nmemh = memh + offset;
310
311 return (0);
312 }
313
314 int
315 tc_mem_alloc(void *v, bus_addr_t rstart, bus_addr_t rend, bus_size_t size, bus_size_t align, bus_size_t boundary, int flags, bus_addr_t *addrp, bus_space_handle_t *bshp)
316 {
317
318 /* XXX XXX XXX XXX XXX XXX */
319 panic("tc_mem_alloc unimplemented");
320 }
321
322 void
323 tc_mem_free(void *v, bus_space_handle_t bsh, bus_size_t size)
324 {
325
326 /* XXX XXX XXX XXX XXX XXX */
327 panic("tc_mem_free unimplemented");
328 }
329
330 void *
331 tc_mem_vaddr(void *v, bus_space_handle_t bsh)
332 {
333 #ifdef DIAGNOSTIC
334 if ((bsh & TC_SPACE_SPARSE) != 0) {
335 /*
336 * tc_mem_map() catches linear && !cacheable,
337 * so we shouldn't come here
338 */
339 panic("tc_mem_vaddr");
340 }
341 #endif
342 return ((void *)bsh);
343 }
344
345 paddr_t
346 tc_mem_mmap(void *v, bus_addr_t addr, off_t off, int prot, int flags)
347 {
348 int linear = flags & BUS_SPACE_MAP_LINEAR;
349 bus_addr_t rv;
350
351 if (linear)
352 rv = addr + off;
353 else
354 rv = TC_DENSE_TO_SPARSE(addr + off);
355
356 return (alpha_btop(rv));
357 }
358
359 inline void
360 tc_mem_barrier(void *v, bus_space_handle_t h, bus_size_t o, bus_size_t l, int f)
361 {
362
363 if ((f & BUS_SPACE_BARRIER_READ) != 0)
364 alpha_mb();
365 else if ((f & BUS_SPACE_BARRIER_WRITE) != 0)
366 alpha_wmb();
367 }
368
369 inline u_int8_t
370 tc_mem_read_1(void *v, bus_space_handle_t memh, bus_size_t off)
371 {
372 volatile u_int8_t *p;
373
374 alpha_mb(); /* XXX XXX XXX */
375
376 if ((memh & TC_SPACE_SPARSE) != 0)
377 panic("tc_mem_read_1 not implemented for sparse space");
378
379 p = (u_int8_t *)(memh + off);
380 return (*p);
381 }
382
383 inline u_int16_t
384 tc_mem_read_2(void *v, bus_space_handle_t memh, bus_size_t off)
385 {
386 volatile u_int16_t *p;
387
388 alpha_mb(); /* XXX XXX XXX */
389
390 if ((memh & TC_SPACE_SPARSE) != 0)
391 panic("tc_mem_read_2 not implemented for sparse space");
392
393 p = (u_int16_t *)(memh + off);
394 return (*p);
395 }
396
397 inline u_int32_t
398 tc_mem_read_4(void *v, bus_space_handle_t memh, bus_size_t off)
399 {
400 volatile u_int32_t *p;
401
402 alpha_mb(); /* XXX XXX XXX */
403
404 if ((memh & TC_SPACE_SPARSE) != 0)
405 /* Nothing special to do for 4-byte sparse space accesses */
406 p = (u_int32_t *)(memh + (off << 1));
407 else
408 p = (u_int32_t *)(memh + off);
409 return (*p);
410 }
411
412 inline u_int64_t
413 tc_mem_read_8(void *v, bus_space_handle_t memh, bus_size_t off)
414 {
415 volatile u_int64_t *p;
416
417 alpha_mb(); /* XXX XXX XXX */
418
419 if ((memh & TC_SPACE_SPARSE) != 0)
420 panic("tc_mem_read_8 not implemented for sparse space");
421
422 p = (u_int64_t *)(memh + off);
423 return (*p);
424 }
425
426 #define tc_mem_read_multi_N(BYTES,TYPE) \
427 void \
428 __C(tc_mem_read_multi_,BYTES)(v, h, o, a, c) \
429 void *v; \
430 bus_space_handle_t h; \
431 bus_size_t o, c; \
432 TYPE *a; \
433 { \
434 \
435 while (c-- > 0) { \
436 tc_mem_barrier(v, h, o, sizeof *a, BUS_SPACE_BARRIER_READ); \
437 *a++ = __C(tc_mem_read_,BYTES)(v, h, o); \
438 } \
439 }
440 tc_mem_read_multi_N(1,u_int8_t)
441 tc_mem_read_multi_N(2,u_int16_t)
442 tc_mem_read_multi_N(4,u_int32_t)
443 tc_mem_read_multi_N(8,u_int64_t)
444
445 #define tc_mem_read_region_N(BYTES,TYPE) \
446 void \
447 __C(tc_mem_read_region_,BYTES)(v, h, o, a, c) \
448 void *v; \
449 bus_space_handle_t h; \
450 bus_size_t o, c; \
451 TYPE *a; \
452 { \
453 \
454 while (c-- > 0) { \
455 *a++ = __C(tc_mem_read_,BYTES)(v, h, o); \
456 o += sizeof *a; \
457 } \
458 }
459 tc_mem_read_region_N(1,u_int8_t)
460 tc_mem_read_region_N(2,u_int16_t)
461 tc_mem_read_region_N(4,u_int32_t)
462 tc_mem_read_region_N(8,u_int64_t)
463
464 inline void
465 tc_mem_write_1(void *v, bus_space_handle_t memh, bus_size_t off, u_int8_t val)
466 {
467
468 if ((memh & TC_SPACE_SPARSE) != 0) {
469 volatile u_int64_t *p, vl;
470 u_int64_t shift, msk;
471
472 shift = off & 0x3;
473 off &= 0x3;
474
475 p = (u_int64_t *)(memh + (off << 1));
476
477 msk = ~(0x1 << shift) & 0xf;
478 vl = (msk << 32) | (((u_int64_t)val) << (shift * 8));
479
480 *p = val;
481 } else {
482 volatile u_int8_t *p;
483
484 p = (u_int8_t *)(memh + off);
485 *p = val;
486 }
487 alpha_mb(); /* XXX XXX XXX */
488 }
489
490 inline void
491 tc_mem_write_2(void *v, bus_space_handle_t memh, bus_size_t off, u_int16_t val)
492 {
493
494 if ((memh & TC_SPACE_SPARSE) != 0) {
495 volatile u_int64_t *p, vl;
496 u_int64_t shift, msk;
497
498 shift = off & 0x2;
499 off &= 0x3;
500
501 p = (u_int64_t *)(memh + (off << 1));
502
503 msk = ~(0x3 << shift) & 0xf;
504 vl = (msk << 32) | (((u_int64_t)val) << (shift * 8));
505
506 *p = val;
507 } else {
508 volatile u_int16_t *p;
509
510 p = (u_int16_t *)(memh + off);
511 *p = val;
512 }
513 alpha_mb(); /* XXX XXX XXX */
514 }
515
516 inline void
517 tc_mem_write_4(void *v, bus_space_handle_t memh, bus_size_t off, u_int32_t val)
518 {
519 volatile u_int32_t *p;
520
521 if ((memh & TC_SPACE_SPARSE) != 0)
522 /* Nothing special to do for 4-byte sparse space accesses */
523 p = (u_int32_t *)(memh + (off << 1));
524 else
525 p = (u_int32_t *)(memh + off);
526 *p = val;
527 alpha_mb(); /* XXX XXX XXX */
528 }
529
530 inline void
531 tc_mem_write_8(void *v, bus_space_handle_t memh, bus_size_t off, u_int64_t val)
532 {
533 volatile u_int64_t *p;
534
535 if ((memh & TC_SPACE_SPARSE) != 0)
536 panic("tc_mem_read_8 not implemented for sparse space");
537
538 p = (u_int64_t *)(memh + off);
539 *p = val;
540 alpha_mb(); /* XXX XXX XXX */
541 }
542
543 #define tc_mem_write_multi_N(BYTES,TYPE) \
544 void \
545 __C(tc_mem_write_multi_,BYTES)(v, h, o, a, c) \
546 void *v; \
547 bus_space_handle_t h; \
548 bus_size_t o, c; \
549 const TYPE *a; \
550 { \
551 \
552 while (c-- > 0) { \
553 __C(tc_mem_write_,BYTES)(v, h, o, *a++); \
554 tc_mem_barrier(v, h, o, sizeof *a, BUS_SPACE_BARRIER_WRITE); \
555 } \
556 }
557 tc_mem_write_multi_N(1,u_int8_t)
558 tc_mem_write_multi_N(2,u_int16_t)
559 tc_mem_write_multi_N(4,u_int32_t)
560 tc_mem_write_multi_N(8,u_int64_t)
561
562 #define tc_mem_write_region_N(BYTES,TYPE) \
563 void \
564 __C(tc_mem_write_region_,BYTES)(v, h, o, a, c) \
565 void *v; \
566 bus_space_handle_t h; \
567 bus_size_t o, c; \
568 const TYPE *a; \
569 { \
570 \
571 while (c-- > 0) { \
572 __C(tc_mem_write_,BYTES)(v, h, o, *a++); \
573 o += sizeof *a; \
574 } \
575 }
576 tc_mem_write_region_N(1,u_int8_t)
577 tc_mem_write_region_N(2,u_int16_t)
578 tc_mem_write_region_N(4,u_int32_t)
579 tc_mem_write_region_N(8,u_int64_t)
580
581 #define tc_mem_set_multi_N(BYTES,TYPE) \
582 void \
583 __C(tc_mem_set_multi_,BYTES)(v, h, o, val, c) \
584 void *v; \
585 bus_space_handle_t h; \
586 bus_size_t o, c; \
587 TYPE val; \
588 { \
589 \
590 while (c-- > 0) { \
591 __C(tc_mem_write_,BYTES)(v, h, o, val); \
592 tc_mem_barrier(v, h, o, sizeof val, BUS_SPACE_BARRIER_WRITE); \
593 } \
594 }
595 tc_mem_set_multi_N(1,u_int8_t)
596 tc_mem_set_multi_N(2,u_int16_t)
597 tc_mem_set_multi_N(4,u_int32_t)
598 tc_mem_set_multi_N(8,u_int64_t)
599
600 #define tc_mem_set_region_N(BYTES,TYPE) \
601 void \
602 __C(tc_mem_set_region_,BYTES)(v, h, o, val, c) \
603 void *v; \
604 bus_space_handle_t h; \
605 bus_size_t o, c; \
606 TYPE val; \
607 { \
608 \
609 while (c-- > 0) { \
610 __C(tc_mem_write_,BYTES)(v, h, o, val); \
611 o += sizeof val; \
612 } \
613 }
614 tc_mem_set_region_N(1,u_int8_t)
615 tc_mem_set_region_N(2,u_int16_t)
616 tc_mem_set_region_N(4,u_int32_t)
617 tc_mem_set_region_N(8,u_int64_t)
618
619 #define tc_mem_copy_region_N(BYTES) \
620 void \
621 __C(tc_mem_copy_region_,BYTES)(v, h1, o1, h2, o2, c) \
622 void *v; \
623 bus_space_handle_t h1, h2; \
624 bus_size_t o1, o2, c; \
625 { \
626 bus_size_t o; \
627 \
628 if ((h1 & TC_SPACE_SPARSE) != 0 && \
629 (h2 & TC_SPACE_SPARSE) != 0) { \
630 memmove((void *)(h2 + o2), (void *)(h1 + o1), c * BYTES); \
631 return; \
632 } \
633 \
634 if (h1 + o1 >= h2 + o2) \
635 /* src after dest: copy forward */ \
636 for (o = 0; c > 0; c--, o += BYTES) \
637 __C(tc_mem_write_,BYTES)(v, h2, o2 + o, \
638 __C(tc_mem_read_,BYTES)(v, h1, o1 + o)); \
639 else \
640 /* dest after src: copy backwards */ \
641 for (o = (c - 1) * BYTES; c > 0; c--, o -= BYTES) \
642 __C(tc_mem_write_,BYTES)(v, h2, o2 + o, \
643 __C(tc_mem_read_,BYTES)(v, h1, o1 + o)); \
644 }
645 tc_mem_copy_region_N(1)
646 tc_mem_copy_region_N(2)
647 tc_mem_copy_region_N(4)
648 tc_mem_copy_region_N(8)
NetBSD on the FriendlyARM MINI2440