sys/arch/arc/jazz/rd94.h

   1 /*      $NetBSD: rd94.h,v 1.6 2002/12/09 13:36:28 tsutsui Exp $ */
   2 /*      $OpenBSD: pica.h,v 1.4 1996/09/14 15:58:28 pefo Exp $ */
   3
   4 /*
   5  * Copyright (c) 1994, 1995, 1996 Per Fogelstrom
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. All advertising materials mentioning features or use of this software
  16  *    must display the following acknowledgement:
  17  *      This product includes software developed under OpenBSD by
  18  *      Per Fogelstrom.
  19  * 4. The name of the author may not be used to endorse or promote products
  20  *    derived from this software without specific prior written permission.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
  23  * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  26  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  28  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  31  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  32  * SUCH DAMAGE.
  33  *
  34  */
  35 #ifndef _RD94_H_
  36 #define _RD94_H_ 1
  37
  38 /*
  39  * I/O map
  40  */
  41
  42 #define RD94_P_LOCAL_IO_BASE    0x80000000      /* I/O Base address */
  43 #define RD94_V_LOCAL_IO_BASE    0xe0000000
  44 #define RD94_S_LOCAL_IO_BASE    0x00040000      /* Size */
  45 #define RD94SYS RD94_V_LOCAL_IO_BASE
  46
  47 #define RD94_SYS_CONFIG         (RD94SYS+0x000) /* Global config register */
  48 #define RD94_SYS_RFAILADDR      (RD94SYS+0x010) /* Remote failed address */
  49 #define RD94_SYS_MFAILADDR      (RD94SYS+0x018) /* Memory failed address */
  50 #define RD94_SYS_INVALIDADDR    (RD94SYS+0x020) /* Invalid address */
  51 #define RD94_SYS_TL_BASE        (RD94SYS+0x028) /* DMA transl. table base */
  52 #define RD94_SYS_TL_LIMIT       (RD94SYS+0x030) /* DMA transl. table limit */
  53 #define RD94_SYS_TL_IVALID      (RD94SYS+0x038) /* DMA transl. cache inval */
  54 #define RD94_SYS_INTSTAT0       (RD94SYS+0x040) /* Int0 status (DMA?) */
  55 #define RD94_SYS_INTSTAT1       (RD94SYS+0x048) /* Int1 status (LB) */
  56 #define RD94_SYS_INTSTAT2       (RD94SYS+0x050) /* Int2 status (PCI/EISA) */
  57 #define RD94_SYS_INTSTAT3       (RD94SYS+0x058) /* Int3 status (Timer) */
  58 #define RD94_SYS_INTSTAT4       (RD94SYS+0x060) /* Int4 status (IPI) */
  59 #define RD94_SYS_CPUID          (RD94SYS+0x070) /* CPU number */
  60 #define RD94_SYS_NMISRC         (RD94SYS+0x078) /* NMI source */
  61 #define RD94_SYS_EXT_IMASK      (RD94SYS+0x0f8) /* External int enable mask */
  62 #define RD94_SYS_DMA0_REGS      (RD94SYS+0x100) /* DMA ch0 base address */
  63 #define RD94_SYS_DMA1_REGS      (RD94SYS+0x120) /* DMA ch0 base address */
  64 #define RD94_SYS_DMA2_REGS      (RD94SYS+0x140) /* DMA ch0 base address */
  65 #define RD94_SYS_DMA3_REGS      (RD94SYS+0x160) /* DMA ch0 base address */
  66 #define RD94_SYS_IT_VALUE       (RD94SYS+0x1a8) /* Interval timer reload */
  67 #define RD94_SYS_IPI            (RD94SYS+0x1b8) /* IPI register */
  68 #define RD94_SYS_ECCDIAG        (RD94SYS+0x1c8) /* ECC diagnostics */
  69 #define RD94_SYS_PCI_CONFADDR   (RD94SYS+0x518) /* PCI configuration address */
  70 #define RD94_SYS_PCI_CONFDATA   (RD94SYS+0x520) /* PCI configuration data */
  71 #define RD94_SYS_PCI_INTMASK    (RD94SYS+0x530) /* PCI interrupt mask */
  72 #define RD94_SYS_PCI_INTSTAT    (RD94SYS+0x538) /* PCI interrupt status */
  73 #define RD94_SYS_BEEP_DIVISOR   (RD94SYS+0x5A8) /* Beep frequency divisor */
  74 #define RD94_SYS_BEEP_CNTL      (RD94SYS+0x5AC) /* Beep control */
  75 #define RD94_SYS_ERR_STAT       (RD94SYS+0x5BC) /* System error status */
  76
  77 #define RD94LB RD94_V_LOCAL_IO_BASE
  78 #define RD94_SYS_SONIC          (RD94LB+0x1000) /* SONIC base address */
  79 #define RD94_SYS_SCSI0          (RD94LB+0x2000) /* SCSI0 base address */
  80 #define RD94_SYS_SCSI1          (RD94LB+0x3000) /* SCSI1 base address */
  81 #define RD94_SYS_CLOCK          (RD94LB+0x4000) /* Clock base address */
  82 #define RD94_SYS_KBD            (RD94LB+0x5000) /* Keybrd/mouse base address */
  83 #define RD94_SYS_COM1           (RD94LB+0x6000) /* Com port 1 */
  84 #define RD94_SYS_COM2           (RD94LB+0x7000) /* Com port 2 */
  85 #define RD94_SYS_PAR1           (RD94LB+0x8000) /* Parallel port 1 */
  86 #define RD94_SYS_NVRAM          (RD94LB+0x9000) /* Unprotected NV-ram */
  87 #define RD94_SYS_PNVRAM         (RD94LB+0xa000) /* Protected NV-ram */
  88 #define RD94_SYS_NVPROM         (RD94LB+0xb000) /* Read only NV-ram */
  89 #define RD94_SYS_FLOPPY         (RD94LB+0xC000) /* Floppy base address */
  90 #define RD94_SYS_SOUND          (RD94LB+0x10000)/* Sound port */
  91 #define RD94_SYS_THERMOMETER    (RD94LB+0x12000)/* DS1620 thermometer */
  92
  93 #define RD94_SYS_LB_LED         (RD94LB+0xE000) /* LED/self-test register */
  94 #define RD94_SYS_LB_IE1         (RD94LB+0xF000) /* Local bus int enable */
  95 #define RD94_SYS_LB_IE2         (RD94LB+0xF002) /* Local bus int enable */
  96
  97 #define RD94_P_PCI_IO           0x90000000      /* PCI I/O control */
  98 #define RD94_V_PCI_IO           0xe2000000
  99 #define RD94_S_PCI_IO           0x01000000
 100
 101 #define RD94_P_PCI_MEM          0x100000000LL   /* PCI Memory control */
 102 #define RD94_V_PCI_MEM          0xe3000000
 103 #define RD94_S_PCI_MEM          0x40000000
 104
 105 #define RD94_P_EISA_IO          0x90000000      /* EISA I/O control */
 106 #define RD94_V_EISA_IO          0xe2000000
 107 #define RD94_S_EISA_IO          0x01000000
 108
 109 #define RD94_P_EISA_MEM         0x100000000LL   /* EISA Memory control */
 110 #define RD94_V_EISA_MEM         0xe3000000
 111 #define RD94_S_EISA_MEM         0x40000000
 112
 113 #endif  /* _RD94_H_ */