sys/arch/arm/at91/at91aicreg.h

   1 /*      $NetBSD: at91aicreg.h,v 1.2 2008/07/03 01:15:38 matt Exp $      */
   2
   3 /*
   4  * Copyright (c) 2007 Embedtronics Oy
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
  17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  19  * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
  20  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 #ifndef _AT91AICREG_H_
  30 #define _AT91AICREG_H_
  31
  32 #define AT91AIC_BASE    0xFFFFF000UL    /* AIC BUS address              */
  33
  34 #define AIC_NIRQ        32UL            /* number of vectors            */
  35 #define AIC_VEC_VALID(n)        ((n) >= 0 && (n) < AIC_NIRQ)
  36
  37 #define AIC_SMR(vec)    (0x000UL+(vec)*4UL)/* Source Mode Registers     */
  38 #define AIC_SVR(vec)    (0x080UL+(vec)*4UL)/* Source Vectors Regs       */
  39 #define AIC_IVR         0x100UL         /* 100: Interrupt Vector Reg    */
  40 #define AIC_FVR         0x104UL         /* 104: Fast Interrupt Vect Reg */
  41 #define AIC_ISR         0x108UL         /* 108: Interrupt Status Reg    */
  42 #define AIC_IPR         0x10CUL         /* 10c: Interrupt Pending Reg   */
  43 #define AIC_IMR         0x110UL         /* 110: Interrupt Mask Reg      */
  44 #define AIC_CISR        0x114UL         /* 114: Core interrupt Stat Reg */
  45 #define AIC_IECR        0x120UL         /* 120: Interrupt Enable Cmd reg*/
  46 #define AIC_IDCR        0x124UL         /* 124: Interrupt Dis. Cmd Reg  */
  47 #define AIC_ICCR        0x128UL         /* 128: Interrupt Clear Cmd Reg */
  48 #define AIC_ISCR        0x12CUL         /* 12c: Interrupt Set Cmd Reg   */
  49 #define AIC_EOICR       0x130UL         /* 130: End of Interrupt Vec Reg*/
  50 #define AIC_SPU         0x134UL         /* 134: Spurious Int. Vec Reg   */
  51 #define AIC_DCR         0x138UL         /* 138: Debug Control Reg       */
  52 #define AIC_FFER        0x140UL         /* 140: Fast Forcing Enable     */
  53 #define AIC_FFDR        0x144UL         /* 144: Fast Forcing Disable    */
  54 #define AIC_FFSR        0x148UL         /* 148: Fast Forcing Status     */
  55
  56 /* Source Mode Register bits: */
  57 #define AIC_SMR_SRCTYPE         0x60
  58 #define AIC_SMR_SRCTYPE_LVL_LO  0x00
  59 #define AIC_SMR_SRCTYPE_FALLING 0x20
  60 #define AIC_SMR_SRCTYPE_LEVEL   0x00
  61 #define AIC_SMR_SRCTYPE_EDGE    0x20
  62 #define AIC_SMR_SRCTYPE_LVL_HI  0x40
  63 #define AIC_SMR_SRCTYPE_RISING  0x60
  64 #define AIC_SMR_PRIOR           0x7
  65 #define AIC_SMR_PRIOR_SHIFT     0
  66
  67 /* Debug Control Register: */
  68 #define AIC_DEBUG_GMSK          0x2     /* 1= mask all interrupts (?)   */
  69 #define AIC_DEBUG_PROT          0x1     /* 1 = protection mode enabled  */
  70
  71 #endif  // _AT91AICREG_H_
  72