sys/arch/arm/at91/at91pmcreg.h

   1 /*      $Id: at91pmcreg.h,v 1.2 2008/07/03 01:15:38 matt Exp $  */
   2
   3 #ifndef _AT91PMCREG_H_
   4 #define _AT91PMCREG_H_  1
   5
   6 /* Power Management Controller (PMC), at,
   7  * at91rm9200.pdf, page 271 */
   8
   9 #define PMC_NUM_PCLOCKS 8
  10
  11 #define PMC_SCER        0x00U           /* 00: System Clock Enable Reg  */
  12 #define PMC_SCDR        0x04U           /* 04: System Clock Disable Reg */
  13 #define PMC_SCSR        0x08U           /* 08: System Clock Status Reg  */
  14 #define PMC_PCER        0x10U           /* 10: Peripheral Clock Enable  */
  15 #define PMC_PCDR        0x14U           /* 14: Peripheral Clock Disable */
  16 #define PMC_PCSR        0x18U           /* 18: Peripheral Clock Status  */
  17 #define PMC_MOR         0x20U           /* 20: Main Oscillator Reg      */
  18 #define PMC_MCFR        0x24U           /* 24: Main Clock Freq Reg      */
  19 #define PMC_PLLAR       0x28U           /* 28: PLL A Register#define    PMC_*/
  20 #define PMC_PLLBR       0x2CU           /* 2C: PLL B Register           */
  21 #define PMC_MCKR        0x30U           /* 30: Master Clock Register    */
  22 #define PMC_PCK(num)    (0x40U + (num) * 4U)    /* 40: Programmable Clocks      */
  23 #define PMC_IER         0x60U           /* 60: Interrupt Enable Reg     */
  24 #define PMC_IDR         0x64U           /* 64: Interrupt Disable Reg    */
  25 #define PMC_SR          0x68U           /* 68: Status Register          */
  26 #define PMC_IMR         0x6CU           /* 6C: Interrupt Mask Reg       */
  27
  28 /* System Clock Enable Register bits: */
  29 #define PMC_SCSR_PCK3   0x0800U
  30 #define PMC_SCSR_PCK2   0x0400U
  31 #define PMC_SCSR_PCK1   0x0200U
  32 #define PMC_SCSR_PCK0   0x0100U
  33 #define PMC_SCSR_UHP    0x0010U         /* 1 = Enable USB Host Port clks */
  34 #define PMC_SCSR_MCKUDP 0x0004U         /* 1 = enable Master Clock dis  */
  35 #define PMC_SCSR_UDP    0x0002U         /* 1 = enable USB Device Port clk */
  36 #define PMC_SCSR_PCK    0x0001U         /* 1 = enable the processor clk */
  37
  38 /* Main Oscillator Register bits: */
  39 #define PMC_MOR_OSCOUNT 0xFF00U         /* start-up-time / 8            */
  40 #define PMC_MOR_OSCOUNT_SHIFT 8U
  41 #define PMC_MOR_MOSCEN  0x1U            /* 1 = main oscillator enabled  */
  42
  43 /* Main Clock Frequency Register bits: */
  44 #define PMC_MCFR_MAINRDY        0x10000U        /* 1= main clock ready          */
  45 #define PMC_MCFR_MAINF          0x0FFFFU
  46
  47 /* PLL Register bits: */
  48 #define PMC_PLL_MUL             0x07FF0000U
  49 #define PMC_PLL_MUL_SHIFT       16U
  50 #define PMC_PLL_OUT             0x0000C000U
  51 #define PMC_PLL_OUT_80_TO_160   0x00000000U
  52 #define PMC_PLL_OUT_150_TO_240  0x00008000U
  53 #define PMC_PLL_PLLCOUNT        0x00003F00U
  54 #define PMC_PLL_DIV             0x000000FFU
  55 #define PMC_PLL_DIV_SHIFT       0U
  56
  57 /* PLL B Register bits: */
  58 #define PMC_PLLBR_USB_96M       0x10000000U /* 1 = USB clks = PLL B output / 2  */
  59
  60 /* Master Clock Register bits: */
  61 #define PMC_MCKR_MDIV           0x300U
  62 #define PMC_MCKR_MDIV_1         0x000U
  63 #define PMC_MCKR_MDIV_2         0x100U
  64 #define PMC_MCKR_MDIV_3         0x200U
  65 #define PMC_MCKR_MDIV_4         0x300U
  66 #define PMC_MCKR_MDIV_SHIFT     8U
  67
  68 #define PMC_MCKR_PRES           0x01CU
  69 #define PMC_MCKR_PRES_SHIFT     2U
  70 #define PMC_MCKR_PRES_1         (0U<<PMC_MCKR_PRES_SHIFT)
  71 #define PMC_MCKR_PRES_2         (1U<<PMC_MCKR_PRES_SHIFT)
  72 #define PMC_MCKR_PRES_4         (2U<<PMC_MCKR_PRES_SHIFT)
  73 #define PMC_MCKR_PRES_8         (3U<<PMC_MCKR_PRES_SHIFT)
  74 #define PMC_MCKR_PRES_16        (4U<<PMC_MCKR_PRES_SHIFT)
  75 #define PMC_MCKR_PRES_32        (5U<<PMC_MCKR_PRES_SHIFT)
  76 #define PMC_MCKR_PRES_64        (6U<<PMC_MCKR_PRES_SHIFT)
  77
  78 #define PMC_MCKR_CSS            0x003U
  79 #define PMC_MCKR_CSS_SLOW_CLK   0x000U
  80 #define PMC_MCKR_CSS_MAIN_CLK   0x001U
  81 #define PMC_MCKR_CSS_PLLA       0x002U
  82 #define PMC_MCKR_CSS_PLLB       0x003U
  83
  84 /* Programmable Clock Register bits: */
  85 #define PMC_PCK_PRES            PMC_MCKR_PRES
  86 #define PMC_PCK_PRES_SHIFT      PMC_MCKR_PRES_SHIFT
  87 #define PMC_PCK_PRES_1          PMC_MCKR_PRES_1
  88 #define PMC_PCK_PRES_2          PMC_MCKR_PRES_2
  89 #define PMC_PCK_PRES_4          PMC_MCKR_PRES_4
  90 #define PMC_PCK_PRES_8          PMC_MCKR_PRES_8
  91 #define PMC_PCK_PRES_16         PMC_MCKR_PRES_16
  92 #define PMC_PCK_PRES_32         PMC_MCKR_PRES_32
  93 #define PMC_PCK_PRES_64         PMC_MCKR_PRES_64
  94
  95 #define PMC_PCK_CSS             PMC_MCKR_CSS
  96 #define PMC_PCK_CSS_SLOW_CLK    PMC_MCKR_CSS_SLOW_CLK
  97 #define PMC_PCK_CSS_CLKC        PMC_MCKR_CSS_CLKC
  98 #define PMC_PCK_CSS_CLKA        PMC_MCKR_CSS_CLKA
  99 #define PMC_PCK_CSS_CLKB        PMC_MCKR_CSS_CLKB
 100
 101
 102 /* Interrupt Enable Register bits: */
 103 #define PMC_SR_PCK7RDY          0x8000U
 104 #define PMC_SR_PCK6RDY          0x4000U
 105 #define PMC_SR_PCK5RDY          0x2000U
 106 #define PMC_SR_PCK4RDY          0x1000U
 107 #define PMC_SR_PCK3RDY          0x0800U
 108 #define PMC_SR_PCK2RDY          0x0400U
 109 #define PMC_SR_PCK1RDY          0x0200U
 110 #define PMC_SR_PCK0RDY          0x0100U
 111 #define PMC_SR_MCKRDY           0x0008U
 112 #define PMC_SR_LOCKB            0x0004U
 113 #define PMC_SR_LOCKA            0x0002U
 114 #define PMC_SR_MOSCS            0x0001U
 115
 116 #define PMCREG(offset)          *((volatile uint32_t*)(0xfffffc00UL + (offset)))
 117
 118 #endif /* !_AT91PMCREG_H_ */