sys/arch/arm/at91/at91twireg.h

   1 /*      $Id: at91twireg.h,v 1.2 2008/07/03 01:15:38 matt Exp $  */
   2 /*      $NetBSD$        */
   3
   4 /*-
   5  * Copyright (c) 2007 Embedtronics Oy.
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or
   9  * without modification, are permitted provided that the following
  10  * conditions are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above
  14  *    copyright notice, this list of conditions and the following
  15  *    disclaimer in the documentation and/or other materials provided
  16  *    with the distribution.
  17  * 3. All advertising materials mentioning features or use of this
  18  *    software must display the following acknowledgements:
  19  *      This product includes software developed by the Urbana-Champaign
  20  *      Independent Media Center.
  21  *      This product includes software developed by Garrett D'Amore.
  22  * 4. Urbana-Champaign Independent Media Center's name and Garrett
  23  *    D'Amore's name may not be used to endorse or promote products
  24  *    derived from this software without specific prior written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE URBANA-CHAMPAIGN INDEPENDENT
  27  * MEDIA CENTER AND GARRETT D'AMORE ``AS IS'' AND ANY EXPRESS OR
  28  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  29  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  30  * ARE DISCLAIMED.  IN NO EVENT SHALL THE URBANA-CHAMPAIGN INDEPENDENT
  31  * MEDIA CENTER OR GARRETT D'AMORE BE LIABLE FOR ANY DIRECT, INDIRECT,
  32  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  33  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  34  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  35  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  36  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  37  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
  38  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 #ifndef _AT91TWIREG_H_
  42 #define _AT91TWIREG_H_
  43
  44 #define AT91_TWI_SIZE   0x4000U
  45
  46 #define TWI_CR          0x00U   /* 0x00: Control Register               */
  47 #define TWI_MMR         0x04U   /* 0x04: Master Mode Register           */
  48 #define TWI_IADR        0x0CU   /* 0x0C: Internal Address Register      */
  49 #define TWI_CWGR        0x10U   /* 0x10: Clock Waveform Generator Reg   */
  50 #define TWI_SR          0x20U   /* 0x20: Status Register                */
  51 #define TWI_IER         0x24U   /* 0x24: Interrupt Enable Register      */
  52 #define TWI_IDR         0x28U   /* 0x28: Interrupt Disable Register     */
  53 #define TWI_IMR         0x2CU   /* 0x2C: Interrupt Mask Register        */
  54 #define TWI_RHR         0x30U   /* 0x30: Receive Holding Register       */
  55 #define TWI_THR         0x34U   /* 0x34: Transmit Holding Register      */
  56
  57 /* Control Registre bits: */
  58 #define TWI_CR_SWRST    0x80U   /* 1 = do software reset                */
  59 #define TWI_CR_MSDIS    0x08U   /* 1 = disable master mode              */
  60 #define TWI_CR_MSEN     0x04U   /* 1 = enable master mode               */
  61 #define TWI_CR_STOP     0x02U   /* 1 = send a stop condition            */
  62 #define TWI_CR_START    0x01U   /* 1 = send a start condition           */
  63
  64 /* Master Mode Register bits: */
  65 #define TWI_MMR_DADR 0x7F0000U /* device address                        */
  66 #define TWI_MMR_DADR_SHIFT 16U
  67 #define TWI_MMR_MREAD   0x1000U /* 1 = Master read direction (0= write) */
  68 #define TWI_MMR_IADRSZ 0x300U   /* device address size          */
  69 #define TWI_MMR_IADRSZ_SHIFT 8U
  70
  71 /* Clock Waveform Generator Register bits: */
  72 #define TWI_CWGR_CKDIV 0x70000U /* Clock Divider                */
  73 #define TWI_CWGR_CKDIV_SHIFT 16U
  74 #define TWI_CWGR_CHDIV 0xFF00U  /* Clock High Divider           */
  75 #define TWI_CWGR_CHDIV_SHIFT 8U
  76 #define TWI_CWGR_CLDIV 0xFFU    /* Clock Low Divider            */
  77 #define TWI_CWGR_CLDIV_SHIFT 0U
  78
  79
  80 /* Status Register bits: */
  81 #define TWI_SR_NACK     0x100U          /* 1 = not acknowledged         */
  82 #define TWI_SR_UNRE     0x080U          /* 1 = underrun error           */
  83 #define TWI_SR_OVRE     0x040U          /* 1 = overrun error            */
  84 #define TWI_SR_TXRDY    0x004U          /* 1 = transmit holding reg rdy */
  85 #define TWI_SR_RXRDY    0x002U          /* 1 = receive hodling reg rdy  */
  86 #define TWI_SR_TXCOMP   0x001U          /* 1 = transmission completed   */
  87
  88
  89 #endif  /* _AT91TWIREG_H_ */