sys/arch/arm/ep93xx/epgpioreg.h

   1 /*      $NetBSD$        */
   2
   3 /*
   4  * Copyright (c) 2005 HAMAJIMA Katsuomi. All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  */
  27
  28 /*      Cirrus Logic EP9315
  29         GPIO Interface register
  30         http://www.cirrus.com/jp/pubs/manual/EP9315_Users_Guide.pdf     */
  31
  32 #ifndef _EPGPIOREG_H_
  33 #define _EPGPIOREG_H_
  34
  35 /* Port A
  36 7:0     EGPIO[7:0]
  37 6       I2S port 2 SDO2
  38 5       I2S port 1 SDI1
  39 4       I2S port 1 SDO1
  40 3       HDLC clock or TENn
  41 2       DMARQ
  42 1       RTC 32.768kHz reference clock
  43 0       Modem Ring Indicator */
  44 #define EP93XX_GPIO_PADR        0x00    /* Data (R/W) */
  45 #define EP93XX_GPIO_PADDR       0x10    /* Data Direction (R/W) */
  46 #define EP93XX_GPIO_AIntEn      0x9c    /* Interrupt Enable (R/W) */
  47 #define EP93XX_GPIO_AIntType1   0x90    /* Interrupt edge or level (R/W) */
  48 #define EP93XX_GPIO_AIntType2   0x94    /* rising/falling edge, high/low level (R/W) */
  49 #define EP93XX_GPIO_AEOI        0x98    /* clear interrupt (W) */
  50 #define EP93XX_GPIO_ADB         0xa8    /* Interrupt debounce enable (R/W) */
  51 #define EP93XX_GPIO_RawIntStsA  0xa4    /* Raw Interrupt Status (R) */
  52 #define EP93XX_GPIO_IntStsA     0xa0    /* Masked interrupt Status (R) */
  53
  54 /* Port B
  55 7:0     EGPIO[15:8]
  56 7       DASPn
  57 5       I2S port 2 SDI2 */
  58 #define EP93XX_GPIO_PBDR        0x04    /* Data (R/W) */
  59 #define EP93XX_GPIO_PBDDR       0x14    /* Data Direction (R/W) */
  60 #define EP93XX_GPIO_BIntEn      0xb8    /* Interrupt Enable (R/W) */
  61 #define EP93XX_GPIO_BIntType1   0xac    /* Interrupt edge or level (R/W) */
  62 #define EP93XX_GPIO_BIntType2   0xb0    /* rising/falling edge, high/low level (R/W) */
  63 #define EP93XX_GPIO_BEOI        0xb4    /* clear interrupt (W) */
  64 #define EP93XX_GPIO_BDB         0xc4    /* Interrupt debounce enable (R/W) */
  65 #define EP93XX_GPIO_RawIntStsB  0xc0    /* Raw Interrupt Status (R) */
  66 #define EP93XX_GPIO_IntStsB     0xbc    /* Masked interrupt Status (R) */
  67
  68 /* Port C
  69 7:0     ROW[7:0]        Key Matrix row pin */
  70 #define EP93XX_GPIO_PCDR        0x08    /* Data (R/W) */
  71 #define EP93XX_GPIO_PCDDR       0x18    /* Data Direction (R/W) */
  72
  73 /* Port D
  74 7:0     COL[7:0]        Key Matrix column pin */
  75 #define EP93XX_GPIO_PDDR        0x0c    /* Data (R/W) */
  76 #define EP93XX_GPIO_PDDDR       0x1c    /* Data Direction (R/W) */
  77
  78 /* Port E
  79 7:5     IDEDA[2:0]      IDE control pin
  80 4       IDECS1n         IDE control pin
  81 3       IDECS0n         IDE control pin
  82 2       DIORn           IDE control pin
  83 1       RDLED           Red LED pin
  84 0       GRLED           Green LED pin */
  85 #define EP93XX_GPIO_PEDR        0x20    /* Data (R/W) */
  86 #define EP93XX_GPIO_PEDDR       0x24    /* Data Direction (R/W) */
  87
  88 /* Port F
  89 7       VS2             PCMCIA pin
  90 6       READY           PCMCIA pin
  91 5       VS1             PCMCIA pin
  92 4       MCBVD2          PCMCIA pin
  93 3       MCBVD1          PCMCIA pin
  94 2       MCCD2           PCMCIA pin
  95 1       MCCD1           PCMCIA pin
  96 0       WP              PCMCIA pin */
  97 #define EP93XX_GPIO_PFDR        0x30    /* Data (R/W) */
  98 #define EP93XX_GPIO_PFDDR       0x34    /* Data Direction (R/W) */
  99 #define EP93XX_GPIO_FIntEn      0x58    /* Interrupt Enable (R/W) */
 100 #define EP93XX_GPIO_FIntType1   0x4c    /* Interrupt edge or level (R/W) */
 101 #define EP93XX_GPIO_FIntType2   0x50    /* rising/falling edge, high/low level (R/W) */
 102 #define EP93XX_GPIO_FEOI        0x54    /* clear interrupt (W) */
 103 #define EP93XX_GPIO_FDB         0x64    /* Interrupt debounce enable (R/W) */
 104 #define EP93XX_GPIO_RawIntStsF  0x60    /* Raw Interrupt Status (R) */
 105 #define EP93XX_GPIO_IntStsF     0x5c    /* Masked interrupt Status (R) */
 106
 107 /* Port G
 108 7:4     DD[15:12]       IDE data pin
 109 3:2     SLA[1:0]        PCMCIA voltage control pin
 110 1       EEDAT           EEPROM data pin
 111 0       EECLK           EEPROM clock pin */
 112 #define EP93XX_GPIO_PGDR        0x38    /* Data (R/W) */
 113 #define EP93XX_GPIO_PGDDR       0x3c    /* Data Direction (R/W) */
 114
 115 /* Port H
 116 7:0     DD[7:0]         IDE data pin */
 117 #define EP93XX_GPIO_PHDR        0x40    /* Data (R/W) */
 118 #define EP93XX_GPIO_PHDDR       0x44    /* Data Direction (R/W) */
 119
 120 /* EEPROM interface pin drive type (R/W) */
 121 #define EP93XX_GPIO_EEDrive     0xc8
 122 #define  EP93XX_GPIO_DATOD      (1<<1)  /* EEDAT pin */
 123 #define  EP93XX_GPIO_CLKOD      (1<<0)  /* EECLK pin */
 124
 125 /* Interrupt */
 126 #define EP93XX_GPIO0_INTR       19      /* Port F bit 0 */
 127 #define EP93XX_GPIO1_INTR       20      /* Port F bit 1 */
 128 #define EP93XX_GPIO2_INTR       21      /* Port F bit 2 */
 129 #define EP93XX_GPIO3_INTR       22      /* Port F bit 3 */
 130 #define EP93XX_GPIO4_INTR       47      /* Port F bit 4 */
 131 #define EP93XX_GPIO5_INTR       48      /* Port F bit 5 */
 132 #define EP93XX_GPIO6_INTR       49      /* Port F bit 6 */
 133 #define EP93XX_GPIO7_INTR       50      /* Port F bit 7 */
 134 #define EP93XX_GPIO_INTR        59      /* Port A or B */
 135
 136 #endif  /* _EPGPIOREG_H_ */