sys/arch/arm/footbridge/footbridge.c

   1 /*      $NetBSD: footbridge.c,v 1.20 2009/03/14 15:36:02 dsl Exp $      */
   2
   3 /*
   4  * Copyright (c) 1997,1998 Mark Brinicombe.
   5  * Copyright (c) 1997,1998 Causality Limited
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. All advertising materials mentioning features or use of this software
  17  *    must display the following acknowledgement:
  18  *      This product includes software developed by Mark Brinicombe
  19  *      for the NetBSD Project.
  20  * 4. The name of the company nor the name of the author may be used to
  21  *    endorse or promote products derived from this software without specific
  22  *    prior written permission.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
  25  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  26  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  27  * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
  28  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  29  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  32  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  33  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  34  * SUCH DAMAGE.
  35  */
  36
  37 #include <sys/cdefs.h>
  38 __KERNEL_RCSID(0, "$NetBSD: footbridge.c,v 1.20 2009/03/14 15:36:02 dsl Exp $");
  39
  40 #include <sys/param.h>
  41 #include <sys/systm.h>
  42 #include <sys/kernel.h>
  43 #include <sys/conf.h>
  44 #include <sys/malloc.h>
  45 #include <sys/device.h>
  46 #include <uvm/uvm_extern.h>
  47
  48 #include <dev/pci/pcivar.h>
  49 #define _ARM32_BUS_DMA_PRIVATE
  50 #include <machine/bus.h>
  51 #include <machine/intr.h>
  52 #include <machine/bootconfig.h>
  53
  54 #include <arm/cpuconf.h>
  55 #include <arm/cpufunc.h>
  56
  57 #include <arm/footbridge/footbridgevar.h>
  58 #include <arm/footbridge/dc21285reg.h>
  59 #include <arm/footbridge/dc21285mem.h>
  60 #include <arm/footbridge/footbridge.h>
  61
  62 /*
  63  * DC21285 'Footbridge' device
  64  *
  65  * This probes and attaches the footbridge device
  66  * It then configures any children
  67  */
  68
  69 /* Declare prototypes */
  70
  71 static int footbridge_match(device_t parent, cfdata_t cf, void *aux);
  72 static void footbridge_attach(device_t parent, device_t self, void *aux);
  73 static int footbridge_print(void *aux, const char *pnp);
  74 static int footbridge_intr(void *arg);
  75
  76 /* Driver and attach structures */
  77 CFATTACH_DECL_NEW(footbridge, sizeof(struct footbridge_softc),
  78     footbridge_match, footbridge_attach, NULL, NULL);
  79
  80 /* Various bus space tags */
  81 extern struct bus_space footbridge_bs_tag;
  82 extern void footbridge_create_io_bs_tag(bus_space_tag_t t, void *cookie);
  83 extern void footbridge_create_mem_bs_tag(bus_space_tag_t t, void *cookie);
  84 struct bus_space footbridge_csr_tag;
  85 struct bus_space footbridge_pci_io_bs_tag;
  86 struct bus_space footbridge_pci_mem_bs_tag;
  87 extern struct arm32_pci_chipset footbridge_pci_chipset;
  88 extern struct arm32_bus_dma_tag footbridge_pci_bus_dma_tag;
  89 extern struct arm32_dma_range footbridge_dma_ranges[1];
  90
  91 /* Used in footbridge_clock.c */
  92 struct footbridge_softc *clock_sc;
  93
  94 /* Set to non-zero to enable verbose reporting of footbridge system ints */
  95 int footbridge_intr_report = 0;
  96
  97 int footbridge_found;
  98
  99 void
 100 footbridge_pci_bs_tag_init(void)
 101 {
 102         /* Set up the PCI bus tags */
 103         footbridge_create_io_bs_tag(&footbridge_pci_io_bs_tag,
 104             (void *)DC21285_PCI_IO_VBASE);
 105         footbridge_create_mem_bs_tag(&footbridge_pci_mem_bs_tag,
 106             (void *)DC21285_PCI_MEM_BASE);
 107 }
 108
 109 /*
 110  * int footbridge_print(void *aux, const char *name)
 111  *
 112  * print configuration info for children
 113  */
 114
 115 static int
 116 footbridge_print(void *aux, const char *pnp)
 117 {
 118         union footbridge_attach_args *fba = aux;
 119
 120         if (pnp)
 121                 aprint_normal("%s at %s", fba->fba_name, pnp);
 122         return(UNCONF);
 123 }
 124
 125 /*
 126  * int footbridge_match(struct device *parent, struct cfdata *cf, void *aux)
 127  *
 128  * Just return ok for this if it is device 0
 129  */
 130
 131 static int
 132 footbridge_match(device_t parent, cfdata_t cf, void *aux)
 133 {
 134         if (footbridge_found)
 135                 return(0);
 136         return(1);
 137 }
 138
 139
 140 /*
 141  * void footbridge_attach(device_t parent, device_t dev, void *aux)
 142  *
 143  */
 144
 145 static void
 146 footbridge_attach(device_t parent, device_t self, void *aux)
 147 {
 148         struct footbridge_softc *sc = device_private(self);
 149         union footbridge_attach_args fba;
 150         int vendor, device, rev;
 151
 152         /* There can only be 1 footbridge. */
 153         footbridge_found = 1;
 154
 155         clock_sc = sc;
 156
 157         sc->sc_dev = self;
 158         sc->sc_iot = &footbridge_bs_tag;
 159
 160         /* Map the Footbridge */
 161         if (bus_space_map(sc->sc_iot, DC21285_ARMCSR_VBASE,
 162              DC21285_ARMCSR_VSIZE, 0, &sc->sc_ioh))
 163                 panic("%s: Cannot map registers", device_xname(self));
 164
 165         /* Read the ID to make sure it is what we think it is */
 166         vendor = bus_space_read_2(sc->sc_iot, sc->sc_ioh, VENDOR_ID);
 167         device = bus_space_read_2(sc->sc_iot, sc->sc_ioh, DEVICE_ID);
 168         rev = bus_space_read_1(sc->sc_iot, sc->sc_ioh, REVISION);
 169         if (vendor != DC21285_VENDOR_ID && device != DC21285_DEVICE_ID)
 170                 panic("%s: Unrecognised ID", device_xname(self));
 171
 172         aprint_normal(": DC21285 rev %d\n", rev);
 173
 174         /* Disable all interrupts from the footbridge */
 175         bus_space_write_4(sc->sc_iot, sc->sc_ioh, IRQ_ENABLE_CLEAR, 0xffffffff);
 176         bus_space_write_4(sc->sc_iot, sc->sc_ioh, FIQ_ENABLE_CLEAR, 0xffffffff);
 177
 178 /*      bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0x18, 0x40000000);*/
 179
 180         /* Install a generic handler to catch a load of system interrupts */
 181         sc->sc_serr_ih = footbridge_intr_claim(IRQ_SERR, IPL_HIGH,
 182             "serr", footbridge_intr, sc);
 183         sc->sc_sdram_par_ih = footbridge_intr_claim(IRQ_SDRAM_PARITY, IPL_HIGH,
 184             "sdram parity", footbridge_intr, sc);
 185         sc->sc_data_par_ih = footbridge_intr_claim(IRQ_DATA_PARITY, IPL_HIGH,
 186             "data parity", footbridge_intr, sc);
 187         sc->sc_master_abt_ih = footbridge_intr_claim(IRQ_MASTER_ABORT, IPL_HIGH,
 188             "mast abt", footbridge_intr, sc);
 189         sc->sc_target_abt_ih = footbridge_intr_claim(IRQ_TARGET_ABORT, IPL_HIGH,
 190             "targ abt", footbridge_intr, sc);
 191         sc->sc_parity_ih = footbridge_intr_claim(IRQ_PARITY, IPL_HIGH,
 192             "parity", footbridge_intr, sc);
 193
 194         /* Set up the PCI bus tags */
 195         footbridge_create_io_bs_tag(&footbridge_pci_io_bs_tag,
 196             (void *)DC21285_PCI_IO_VBASE);
 197         footbridge_create_mem_bs_tag(&footbridge_pci_mem_bs_tag,
 198             (void *)DC21285_PCI_MEM_BASE);
 199
 200         /* calibrate the delay loop */
 201         calibrate_delay();
 202
 203         /* it seems that the default of the memory being visible from 0 upwards
 204          * on the PCI bus causes issues when DMAing from traditional PC VGA
 205          * address.  This breaks dumping core on cats, as DMAing pages in the
 206          * range 0xb800-0xc000 cause the system to hang.  This suggests that
 207          * the VGA BIOS is taking over those addresses.
 208          * (note that the range 0xb800-c000 is on an S3 card, others may vary
 209          *
 210          * To workaround this the SDRAM window on the PCI bus is shifted
 211          * to 0x20000000, and the DMA range setup to match.
 212          */
 213         {
 214                 /* first calculate the correct base address mask */
 215                 int memory_size = bootconfig.dram[0].pages * PAGE_SIZE;
 216                 uint32_t mask;
 217
 218                 /* window has to be at least 256KB, and up to 256MB */
 219                 for (mask = 0x00040000; mask < 0x10000000; mask <<= 1)
 220                         if (mask >= memory_size)
 221                                 break;
 222                 mask--;
 223                 mask &= SDRAM_MASK_256MB;
 224
 225                 /*
 226                  * configure the mask, the offset into SDRAM and the address
 227                  * SDRAM is exposed on the PCI bus.
 228                  */
 229                 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SDRAM_BA_MASK, mask);
 230                 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SDRAM_BA_OFFSET, 0);
 231                 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SDRAM_MEMORY_ADDR, 0x20000000);
 232
 233                 /* configure the dma range for the footbridge to match */
 234                 footbridge_dma_ranges[0].dr_sysbase = bootconfig.dram[0].address;
 235                 footbridge_dma_ranges[0].dr_busbase = 0x20000000;
 236                 footbridge_dma_ranges[0].dr_len = memory_size;
 237         }
 238
 239         /* Attach the PCI bus */
 240         fba.fba_pba.pba_pc = &footbridge_pci_chipset;
 241         fba.fba_pba.pba_iot = &footbridge_pci_io_bs_tag;
 242         fba.fba_pba.pba_memt = &footbridge_pci_mem_bs_tag;
 243         fba.fba_pba.pba_dmat = &footbridge_pci_bus_dma_tag;
 244         fba.fba_pba.pba_dmat64 = NULL;
 245         fba.fba_pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED;
 246         fba.fba_pba.pba_bus = 0;
 247         fba.fba_pba.pba_bridgetag = NULL;
 248         config_found_ia(self, "pcibus", &fba.fba_pba, pcibusprint);
 249
 250         /* Attach uart device */
 251         fba.fba_fca.fca_name = "fcom";
 252         fba.fba_fca.fca_iot = sc->sc_iot;
 253         fba.fba_fca.fca_ioh = sc->sc_ioh;
 254         fba.fba_fca.fca_rx_irq = IRQ_SERIAL_RX;
 255         fba.fba_fca.fca_tx_irq = IRQ_SERIAL_TX;
 256         config_found_ia(self, "footbridge", &fba.fba_fca, footbridge_print);
 257
 258         /* Setup fast SA110 cache clean area */
 259 #ifdef CPU_SA110
 260         if (cputype == CPU_ID_SA110)
 261                 footbridge_sa110_cc_setup();
 262 #endif  /* CPU_SA110 */
 263
 264 }
 265
 266 /* Generic footbridge interrupt handler */
 267
 268 int
 269 footbridge_intr(void *arg)
 270 {
 271         struct footbridge_softc *sc = arg;
 272         u_int ctrl, intr;
 273
 274         /*
 275          * Read the footbridge control register and check for
 276          * SERR and parity errors
 277          */
 278         ctrl = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SA_CONTROL);
 279         intr = ctrl & (RECEIVED_SERR | SA_SDRAM_PARITY_ERROR |
 280             PCI_SDRAM_PARITY_ERROR | DMA_SDRAM_PARITY_ERROR);
 281         if (intr) {
 282                 /* Report the interrupt if reporting is enabled */
 283                 if (footbridge_intr_report)
 284                         printf("footbridge_intr: ctrl=%08x\n", intr);
 285                 /* Clear the interrupt state */
 286                 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SA_CONTROL,
 287                     ctrl | intr);
 288         }
 289         /*
 290          * Read the PCI status register and check for errors
 291          */
 292         ctrl = bus_space_read_4(sc->sc_iot, sc->sc_ioh, PCI_COMMAND_STATUS_REG);
 293         intr = ctrl & (PCI_STATUS_PARITY_ERROR | PCI_STATUS_MASTER_TARGET_ABORT
 294             | PCI_STATUS_MASTER_ABORT | PCI_STATUS_SPECIAL_ERROR
 295             | PCI_STATUS_PARITY_DETECT);
 296         if (intr) {
 297                 /* Report the interrupt if reporting is enabled */
 298                 if (footbridge_intr_report)
 299                         printf("footbridge_intr: pcistat=%08x\n", intr);
 300                 /* Clear the interrupt state */
 301                 bus_space_write_4(sc->sc_iot, sc->sc_ioh,
 302                     PCI_COMMAND_STATUS_REG, ctrl | intr);
 303         }
 304         return(0);
 305 }
 306
 307 /* End of footbridge.c */