sys/arch/arm/imx/imx31_intr.h

   1 /*      $NetBSD: imx31_intr.h,v 1.2 2008/04/27 18:58:44 matt Exp $      */
   2 /*-
   3  * Copyright (c) 2007 The NetBSD Foundation, Inc.
   4  * All rights reserved.
   5  *
   6  * This code is derived from software contributed to The NetBSD Foundation
   7  * by Matt Thomas.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  19  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  20  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  21  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  28  * POSSIBILITY OF SUCH DAMAGE.
  29  */
  30 #ifndef _ARM_IMX_IMX31_INTR_H_
  31 #define _ARM_IMX_IMX31_INTR_H_
  32
  33 #define IRQ__RSVD0      0
  34 #define IRQ__RSVD1      1
  35 #define IRQ__RSVD2      2
  36 #define IRQ_I2C3        3       /* I2C 3 */
  37 #define IRQ_I2C2        4       /* I2C 2 */
  38 #define IRQ_MPEG4_ENC   5       /* MPEG-4 Encoder */
  39 #define IRQ_RTIC        6       /* RTIC */
  40 #define IRQ_FIR         7       /* Fast Infrared */
  41 #define IRQ_MMSD_HC2    8       /* MultiMedia/Secure Data Host Controller 2 */
  42 #define IRQ_MMSD_HC1    9       /* MultiMedia/Secure Data Host Controller 1 */
  43 #define IRQ_I2C1        10      /* i2c 1 */
  44 #define IRQ_SSI2        11      /* Synchronous Serial Interface 1 */
  45 #define IRQ_SSI1        12      /* Synchronous Serial Interface 2 */
  46 #define IRQ_CSPI2       13      /* Configurable Serial Peripheral Intf 2 */
  47 #define IRQ_CSPI1       14      /* Configurable Serial Peripheral Intf 1 */
  48 #define IRQ_ATA         15      /* Hard Drive (ATA) Controller */
  49 #define IRQ_MBX_RS      16      /* Graphics Accelerator */
  50 #define IRQ_CSPI3       17      /* Configurable Serial Peripheral Intf 3 */
  51 #define IRQ_UART3       18      /* UART3 (rx,tx,mint) */
  52 #define IRQ_I2C_ID      19      /* IC identification */
  53 #define IRQ_SIM1        20      /* Subscriber Identification Module */
  54 #define IRQ_SIM2        21      /* Subscriber Identification Module */
  55 #define IRQ_RNGA        22      /* Random Number Generator Accelerator */
  56 #define IRQ_EVTMON      23      /* event monitor + pmu */
  57 #define IRQ_KPP         24      /* Keyboard Port Port */
  58 #define IRQ_RTC         25      /* Real Time Clock */
  59 #define IRQ_PWM         26      /* Pulse Width Modulator */
  60 #define IRQ_EPIT2       27      /* Enhanced Periodic Timer 2 */
  61 #define IRQ_EPIT1       28      /* Enhanced Periodic Timer 1 */
  62 #define IRQ_GPT         29      /* General Purpose Timer */
  63 #define IRQ_PWRFAIL     30      /* Power Fail */
  64 #define IRQ_CCM_DVFS    31      /* Configurable Serial Peripheral Intf 3 */
  65 #define IRQ_UART2       32      /* UART2 (rx,tx,mint) */
  66 #define IRQ_NANDFC      33      /* NAND Flash Controller */
  67 #define IRQ_SDMA        34      /* Smart Direct Memory Access */
  68 #define IRQ_USB_H1      35      /* USB Host 1 */
  69 #define IRQ_USB_H2      36      /* USB Host 2 */
  70 #define IRQ_USB_OTG     37      /* USB OTG */
  71 #define IRQ__RSVD38     38      /* */
  72 #define IRQ_MS_HC1      39      /* Memory Stick Host Controller 1 */
  73 #define IRQ_MS_HC2      40      /* Memory Stick Host Controller 2 */
  74 #define IRQ_IPU_ERR     41      /* */
  75 #define IRQ_IPU         42      /* */
  76 #define IRQ__RSVD43     43      /* */
  77 #define IRQ__RSVD44     44      /* */
  78 #define IRQ_UART1       45      /* UART1 (rx,tx,mint) */
  79 #define IRQ_UART4       46      /* UART4 (rx,tx,mint) */
  80 #define IRQ_UART5       47      /* UART5 (rx,tx,mint) */
  81 #define IRQ_ECT         48      /*  */
  82 #define IRQ_SCC_SCM     49      /* SCM interrupt */
  83 #define IRQ_SCC_SMN     50      /* SMN interrupt */
  84 #define IRQ_GPIO2       51      /* General Purpose I/O 2 */
  85 #define IRQ_GPIO1       52      /* General Purpose I/O 1 */
  86 #define IRQ_CCM         53      /* Clock Controller */
  87 #define IRQ_PCMCIA      54      /* PCMCIA Controller 3 */
  88 #define IRQ_WDOG        55      /* Watchdog Timer */
  89 #define IRQ_GPIO3       56      /* General Purpose I/O 3 */
  90 #define IRQ__RSVD57     57
  91 #define IRQ_EXT_PWRMGT  58      /* External (power managerment) */
  92 #define IRQ_EXT_TEMP    59      /* External (Temperture) */
  93 #define IRQ_EXT_SENS2   60      /* External (sensor) */
  94 #define IRQ_EXT_SENS1   61      /* External (sensor) */
  95 #define IRQ_EXT_WDOG    62      /* External (WDOG) */
  96 #define IRQ_EXT_TV      63      /* External (TV) 3 */
  97
  98 #ifdef _LOCORE
  99
 100 #define ARM_IRQ_HANDLER _C_LABEL(imx31_irq_handler)
 101
 102 #else
 103
 104 #define AVIC_INTR_SOURCE_NAMES \
 105 {       "reserved 0",   "reserved 1",   "reserved 2",   "i2c #3",       \
 106         "i2c #2",       "mpeg4 enc",    "rtic",         "fir",          \
 107         "mm/sd hc #2",  "mm/sd hc #1",  "i2c #1",       "ssi #2",       \
 108         "ssi #1",       "cspi #2",      "cspi #1",      "ata",          \
 109         "mbx rs",       "cspi #3",      "uart #3",      "i2c id",       \
 110         "sim #1",       "sim #2",       "rnga",         "evtmon",       \
 111         "kpp",          "rtc",          "pwm",          "epit #2",      \
 112         "epit #1",      "gpt",          "pwrfail",      "ccm dvfs",     \
 113         "uart #2",      "nandfc",       "sdma",         "usb hc #1",    \
 114         "usb hc #2",    "usb otg",      "reserved 38",  "ms hc #1",     \
 115         "ms hc#2",      "ipu err",      "ipu",          "reserved 43",  \
 116         "reserved 44",  "uart #1",      "uart #4",      "uart #5",      \
 117         "ect",          "scc scm",      "scc smn",      "gpio #2",      \
 118         "gpio #1",      "ccm",          "pcmcia",       "wdog",         \
 119         "gpio #3",      "reserved 57",  "ext pwrmgt",   "ext temp",     \
 120         "ext sens #2",  "ext sens #1",  "ext wdog",     "ext tv", }
 121
 122 #define PIC_MAXMAXSOURCES       (64+3*32+128)
 123
 124 #include <arm/pic/picvar.h>
 125
 126 int     _splraise(int);
 127 int     _spllower(int);
 128 void    splx(int);
 129 const char *
 130         intr_typename(int);
 131
 132 void imx31_irq_handler(void *);
 133
 134 #endif /* !_LOCORE */
 135
 136 #endif /* _ARM_IMX_IMX31_INTR_H_ */