sys/arch/arm/include/cpuconf.h

   1 /*      $NetBSD: cpuconf.h,v 1.15 2008/10/14 16:01:22 matt Exp $        */
   2
   3 /*
   4  * Copyright (c) 2002 Wasabi Systems, Inc.
   5  * All rights reserved.
   6  *
   7  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. All advertising materials mentioning features or use of this software
  18  *    must display the following acknowledgement:
  19  *      This product includes software developed for the NetBSD Project by
  20  *      Wasabi Systems, Inc.
  21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
  22  *    or promote products derived from this software without specific prior
  23  *    written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
  26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  35  * POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #ifndef _ARM_CPUCONF_H_
  39 #define _ARM_CPUCONF_H_
  40
  41 #if defined(_KERNEL_OPT)
  42 #include "opt_cputypes.h"
  43 #endif /* _KERNEL_OPT */
  44
  45 #if defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270)
  46 #define __CPU_XSCALE_PXA2XX
  47 #endif
  48
  49 #ifdef CPU_XSCALE_PXA2X0
  50 #warning option CPU_XSCALE_PXA2X0 is obsolete. Use CPU_XSCALE_PXA250 and/or CPU_XSCALE_PXA270.
  51 #endif
  52
  53 /*
  54  * IF YOU CHANGE THIS FILE, MAKE SURE TO UPDATE THE DEFINITION OF
  55  * "PMAP_NEEDS_PTE_SYNC" IN <arm/arm32/pmap.h> FOR THE CPU TYPE
  56  * YOU ARE ADDING SUPPORT FOR.
  57  */
  58
  59 #if 0
  60 /*
  61  * Step 1: Count the number of CPU types configured into the kernel.
  62  */
  63 #if defined(_KERNEL_OPT)
  64 #define CPU_NTYPES      (defined(CPU_ARM2) + defined(CPU_ARM250) +      \
  65                          defined(CPU_ARM3) +                            \
  66                          defined(CPU_ARM6) + defined(CPU_ARM7) +        \
  67                          defined(CPU_ARM7TDMI) +                        \
  68                          defined(CPU_ARM8) + defined(CPU_ARM9) +        \
  69                          defined(CPU_ARM9E) +                           \
  70                          defined(CPU_ARM10) +                           \
  71                          defined(CPU_ARM11) +                           \
  72                          defined(CPU_ARM1136) +                         \
  73                          defined(CPU_ARM1176) +                         \
  74                          defined(CPU_SA110) + defined(CPU_SA1100) +     \
  75                          defined(CPU_SA1110) +                          \
  76                          defined(CPU_FA526) +                           \
  77                          defined(CPU_IXP12X0) +                         \
  78                          defined(CPU_XSCALE_80200) +                    \
  79                          defined(CPU_XSCALE_80321) +                    \
  80                          defined(__CPU_XSCALE_PXA2XX) +                 \
  81                          defined(CPU_XSCALE_IXP425))
  82 #else
  83 #define CPU_NTYPES      2
  84 #endif /* _KERNEL_OPT */
  85 #endif
  86
  87 /*
  88  * Step 2: Determine which ARM architecture versions are configured.
  89  */
  90 #if !defined(_KERNEL_OPT) ||                                            \
  91     (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3))
  92 #define ARM_ARCH_2      1
  93 #else
  94 #define ARM_ARCH_2      0
  95 #endif
  96
  97 #if !defined(_KERNEL_OPT) ||                                            \
  98     (defined(CPU_ARM6) || defined(CPU_ARM7))
  99 #define ARM_ARCH_3      1
 100 #else
 101 #define ARM_ARCH_3      0
 102 #endif
 103
 104 #if !defined(_KERNEL_OPT) ||                                            \
 105     (defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \
 106      defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_FA526) || \
 107      defined(CPU_SA1110) || defined(CPU_IXP12X0))
 108 #define ARM_ARCH_4      1
 109 #else
 110 #define ARM_ARCH_4      0
 111 #endif
 112
 113 #if !defined(_KERNEL_OPT) ||                                            \
 114     (defined(CPU_ARM9E) || defined(CPU_ARM10) ||                        \
 115      defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) ||          \
 116      defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425))
 117 #define ARM_ARCH_5      1
 118 #else
 119 #define ARM_ARCH_5      0
 120 #endif
 121
 122 #if defined(CPU_ARM11)
 123 #define ARM_ARCH_6      1
 124 #else
 125 #define ARM_ARCH_6      0
 126 #endif
 127
 128 #define ARM_NARCH       (ARM_ARCH_2 + ARM_ARCH_3 + ARM_ARCH_4 + \
 129                          ARM_ARCH_5 + ARM_ARCH_6)
 130 #if ARM_NARCH == 0
 131 #error ARM_NARCH is 0
 132 #endif
 133
 134 #if ARM_ARCH_5 || ARM_ARCH_6
 135 /*
 136  * We could support Thumb code on v4T, but the lack of clean interworking
 137  * makes that hard.
 138  */
 139 #define THUMB_CODE
 140 #endif
 141
 142 /*
 143  * Step 3: Define which MMU classes are configured:
 144  *
 145  *      ARM_MMU_MEMC            Prehistoric, external memory controller
 146  *                              and MMU for ARMv2 CPUs.
 147  *
 148  *      ARM_MMU_GENERIC         Generic ARM MMU, compatible with ARM6.
 149  *
 150  *      ARM_MMU_SA1             StrongARM SA-1 MMU.  Compatible with generic
 151  *                              ARM MMU, but has no write-through cache mode.
 152  *
 153  *      ARM_MMU_XSCALE          XScale MMU.  Compatible with generic ARM
 154  *                              MMU, but also has several extensions which
 155  *                              require different PTE layout to use.
 156  *
 157  *      ARM_MMU_V6              ARM v6 MMU.  Compatible with generic ARM
 158  *                              MMU, but also has several extensions which
 159  *                              require different PTE layouts to use.
 160  */
 161 #if !defined(_KERNEL_OPT) ||                                            \
 162     (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3))
 163 #define ARM_MMU_MEMC            1
 164 #else
 165 #define ARM_MMU_MEMC            0
 166 #endif
 167
 168 #if !defined(_KERNEL_OPT) ||                                            \
 169     (defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI) || \
 170      defined(CPU_ARM8) || defined(CPU_ARM9) || defined(CPU_ARM9E) ||    \
 171      defined(CPU_ARM10) || defined(CPU_FA526))
 172 #define ARM_MMU_GENERIC         1
 173 #else
 174 #define ARM_MMU_GENERIC         0
 175 #endif
 176
 177 #if !defined(_KERNEL_OPT) ||                                            \
 178     (defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) ||\
 179      defined(CPU_IXP12X0))
 180 #define ARM_MMU_SA1             1
 181 #else
 182 #define ARM_MMU_SA1             0
 183 #endif
 184
 185 #if !defined(_KERNEL_OPT) ||                                            \
 186     (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) ||          \
 187      defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425))
 188 #define ARM_MMU_XSCALE          1
 189 #else
 190 #define ARM_MMU_XSCALE          0
 191 #endif
 192
 193 #if !defined(_KERNEL_OPT) ||                                            \
 194          defined(CPU_ARM11)
 195 #define ARM_MMU_V6              1
 196 #else
 197 #define ARM_MMU_V6              0
 198 #endif
 199
 200 #define ARM_NMMUS               (ARM_MMU_MEMC + ARM_MMU_GENERIC +       \
 201                                  ARM_MMU_SA1 + ARM_MMU_XSCALE + ARM_MMU_V6)
 202 #if ARM_NMMUS == 0
 203 #error ARM_NMMUS is 0
 204 #endif
 205
 206 /*
 207  * Step 4: Define features that may be present on a subset of CPUs
 208  *
 209  *      ARM_XSCALE_PMU          Performance Monitoring Unit on 80200 and 80321
 210  */
 211
 212 #if !defined(_KERNEL_OPT) ||                                            \
 213     (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321))
 214 #define ARM_XSCALE_PMU  1
 215 #else
 216 #define ARM_XSCALE_PMU  0
 217 #endif
 218
 219 #endif /* _ARM_CPUCONF_H_ */