sys/arch/arm/ixp12x0/ixp12x0_comreg.h

   1 /*      $NetBSD: ixp12x0_comreg.h,v 1.7 2003/03/06 06:14:16 igy Exp $ */
   2
   3 /*
   4  * Copyright (c) 2002
   5  *      Ichiro FUKUHARA <ichiro@ichiro.org>.  All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA AND CONTRIBUTORS ``AS IS''
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS
  20  * HEAD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
  21  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  22  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  23  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  24  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  25  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  26  * THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /*
  30  * IXP12X0 UART register
  31  *  UART_SR 0x90003400
  32  *  UART_CR 0x90003800
  33  *  UART_DR 0x90003C00
  34  */
  35
  36 #ifndef _IXP12X0_COMREG_H_
  37 #define _IXP12X0_COMREG_H_
  38
  39 #define IXPCOM_FREQ             (3686400 / 16)
  40 #define IXPCOMSPEED(b)          (IXPCOM_FREQ / (b) - 1)
  41 #define IXPCOMSPEED2BRD(b)      (IXPCOMSPEED(b) << 16)
  42
  43 /* I/O space */
  44 #define IXPCOM_UART_SIZE        0x00004000UL
  45 #define IXPCOM_UART_OFFSET      0x00000000UL
  46 #define IXPCOM_UART_HWBASE      (IXP12X0_SYS_HWBASE + IXPCOM_UART_OFFSET)
  47 /* IXPCOM_UART_VBASE should be used only for console's ioh. */
  48 #define IXPCOM_UART_VBASE       (IXP12X0_SYS_VBASE + IXPCOM_UART_OFFSET)
  49
  50 /* UART control register */
  51 #define IXPCOM_CR       0x00003800UL
  52 #define CR_BRK          0x01    /* Break */
  53 #define CR_PE           0x02    /* Parity enable */
  54 #define CR_OES          0x04    /* Odd/even parity select */
  55 #define CR_SBS          0x08    /* Stop bit select */
  56 #define  SBS_1STOP      (0 << 3)        /*  1 Stop Bit */
  57 #define  SBS_2STOP      (1 << 3)        /*  2 Stop Bit */
  58 #define CR_RIE          0x10    /* Receive FIFO interrupt enable */
  59 #define CR_DSS          0x60    /* Data size select */
  60 #define  DSS_5BIT       (0 << 5)        /*  5Bits */
  61 #define  DSS_6BIT       (1 << 5)        /*  6Bits */
  62 #define  DSS_7BIT       (2 << 5)        /*  7Bits */
  63 #define  DSS_8BIT       (3 << 5)        /*  8Bits */
  64 #define CR_UE           0x80    /* UART Enable */
  65 #define  UE_DISABLE     (0 << 7)        /*  UART Disabled */
  66 #define  UE_ENABLE      (1 << 7)        /*  UART Enabled */
  67 #define CR_XIE          0x100   /* Transmit FIFO interrupt enable */
  68 #define CR_UIS          0x200   /* UART Interrupt Select */
  69 #define CR_BRD          0x03ff0000      /* Baud rate divisor */
  70
  71
  72 /* UART Status register */
  73 #define IXPCOM_SR       0x00003400UL
  74 #define SR_PRE          0x01    /* Parity error */
  75 #define SR_FRE          0x02    /* Framing error */
  76 #define SR_TXR          0x04    /* Transmit FIFO Ready */
  77 #define SR_ROR          0x08    /* Receiver overrun */
  78 #define SR_RXR          0x10    /* Receiver FIFO Ready */
  79 #define SR_TXE          0x20    /* Transmit FIFO Empty */
  80 #define SR_RXF          0x40    /* Receiver FIFO Full */
  81 #define SR_TXF          0x80    /* Transmit FIFO Full */
  82
  83
  84 /* UART data register */
  85 #define IXPCOM_DR       0x00003C00UL
  86 #define DR_PRE          0x100   /* Parity error */
  87 #define DR_FRE          0x200   /* Framing error */
  88 #define DR_ROR          0x400   /* Receiver overrun */
  89
  90 #define IXPCOMSPLRAISED         (~(CR_RIE | CR_XIE))
  91 #define IXPCOMSPLLOWERD         (~0UL);
  92
  93 #endif /* _IXP12X0_COMREG_H_ */