sys/arch/cobalt/stand/boot/pciide.c

   1 /*      $NetBSD: pciide.c,v 1.7 2007/10/17 19:54:09 garbled Exp $       */
   2
   3 /*-
   4  * Copyright (c) 2003 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  17  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  18  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  19  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  20  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  21  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  22  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  23  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  24  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  25  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  26  * POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #include <sys/types.h>
  30 #include <lib/libsa/stand.h>
  31 #include <mips/cpuregs.h>
  32
  33 #include "boot.h"
  34 #include "wdvar.h"
  35
  36 #define COBALT_IO_SPACE_BASE    0x10000000      /* XXX VT82C586 ISA I/O space */
  37
  38 int
  39 pciide_init(struct wdc_channel *chp, u_int *unit)
  40 {
  41         uint32_t cmdreg, ctlreg;
  42         int i, compatchan = 0;
  43
  44         /*
  45          * two channels per chip, two drives per channel
  46          */
  47         compatchan = *unit / PCIIDE_CHANNEL_NDEV;
  48         if (compatchan >= PCIIDE_NUM_CHANNELS)
  49                 return (ENXIO);
  50         *unit %= PCIIDE_CHANNEL_NDEV;
  51
  52         DPRINTF(("[pciide] unit: %d, channel: %d\n", *unit, compatchan));
  53
  54         /*
  55          * XXX map?
  56          */
  57         cmdreg = MIPS_PHYS_TO_KSEG1(COBALT_IO_SPACE_BASE +
  58             PCIIDE_COMPAT_CMD_BASE(compatchan));
  59         ctlreg = MIPS_PHYS_TO_KSEG1(COBALT_IO_SPACE_BASE +
  60             PCIIDE_COMPAT_CTL_BASE(compatchan));
  61
  62         /* set up cmd regsiters */
  63         chp->c_cmdbase = (uint8_t *)cmdreg;
  64         chp->c_data = (uint16_t *)(cmdreg + wd_data);
  65         for (i = 0; i < WDC_NPORTS; i++)
  66                 chp->c_cmdreg[i] = chp->c_cmdbase + i;
  67         /* set up shadow registers */
  68         chp->c_cmdreg[wd_status]   = chp->c_cmdreg[wd_command];
  69         chp->c_cmdreg[wd_features] = chp->c_cmdreg[wd_precomp];
  70         /* set up ctl registers */
  71         chp->c_ctlbase = (uint8_t *)ctlreg;
  72
  73         return 0;
  74 }