1 /* $NetBSD: start.S,v 1.6 2007/10/30 15:07:08 tsutsui Exp $ */
4 * Copyright (c) 2000 The NetBSD Foundation, Inc.
7 * This code is derived from software contributed to The NetBSD Foundation
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
33 #include <mips/cache_r4k.h>
41 la sp, start - CALLFRAME_SIZ
42 sw zero, CALLFRAME_RA(sp) # clear ra for debugger
43 sw zero, CALLFRAME_SP(sp) # clear fp for debugger
44 move s0, a0 # save argc
45 move s1, a1 # save argv
47 jal _C_LABEL(flushcache)
50 la a0, _C_LABEL (edata) # clear BSS
53 jal _C_LABEL(memset) # memset(edata, 0, end - edata)
56 move a0, s0 # restore argc
57 jal _C_LABEL(main) # main(unsigned int)
58 move a1, s1 # restore argv
61 jal _C_LABEL(cpu_reboot) # failed, reboot
67 addu t1, t0, 32*1024 /* flush 32KB */
68 subu t1, t1, 0x100 /* per 256 bytes */
72 cache CACHE_R4K_I | CACHEOP_R4K_INDEX_INV, 0x000(t0)
73 cache CACHE_R4K_I | CACHEOP_R4K_INDEX_INV, 0x020(t0)
74 cache CACHE_R4K_I | CACHEOP_R4K_INDEX_INV, 0x040(t0)
75 cache CACHE_R4K_I | CACHEOP_R4K_INDEX_INV, 0x060(t0)
76 cache CACHE_R4K_I | CACHEOP_R4K_INDEX_INV, 0x080(t0)
77 cache CACHE_R4K_I | CACHEOP_R4K_INDEX_INV, 0x0a0(t0)
78 cache CACHE_R4K_I | CACHEOP_R4K_INDEX_INV, 0x0c0(t0)
79 cache CACHE_R4K_I | CACHEOP_R4K_INDEX_INV, 0x0e0(t0)
82 cache CACHE_R4K_D | CACHEOP_R4K_INDEX_WB_INV, 0x000(t0)
83 cache CACHE_R4K_D | CACHEOP_R4K_INDEX_WB_INV, 0x020(t0)
84 cache CACHE_R4K_D | CACHEOP_R4K_INDEX_WB_INV, 0x040(t0)
85 cache CACHE_R4K_D | CACHEOP_R4K_INDEX_WB_INV, 0x060(t0)
86 cache CACHE_R4K_D | CACHEOP_R4K_INDEX_WB_INV, 0x080(t0)
87 cache CACHE_R4K_D | CACHEOP_R4K_INDEX_WB_INV, 0x0a0(t0)
88 cache CACHE_R4K_D | CACHEOP_R4K_INDEX_WB_INV, 0x0c0(t0)
89 cache CACHE_R4K_D | CACHEOP_R4K_INDEX_WB_INV, 0x0e0(t0)