sys/arch/evbarm/nslu2/nslu2_pci.c

   1 /*      $NetBSD: nslu2_pci.c,v 1.2 2008/04/28 20:23:17 martin Exp $     */
   2
   3 /*-
   4  * Copyright (c) 2006 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by Steve C. Woodford.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31 /*
  32  * Copyright (c) 2003
  33  *      Ichiro FUKUHARA <ichiro@ichiro.org>.
  34  * All rights reserved.
  35  *
  36  * Redistribution and use in source and binary forms, with or without
  37  * modification, are permitted provided that the following conditions
  38  * are met:
  39  * 1. Redistributions of source code must retain the above copyright
  40  *    notice, this list of conditions and the following disclaimer.
  41  * 2. Redistributions in binary form must reproduce the above copyright
  42  *    notice, this list of conditions and the following disclaimer in the
  43  *    documentation and/or other materials provided with the distribution.
  44  *
  45  * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
  46  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  47  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  48  * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
  49  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  50  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  51  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  52  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  53  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  54  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  55  * SUCH DAMAGE.
  56  */
  57
  58 #include <sys/cdefs.h>
  59 __KERNEL_RCSID(0, "$NetBSD: nslu2_pci.c,v 1.2 2008/04/28 20:23:17 martin Exp $");
  60
  61 /*
  62  * Linksys NSLU2 PCI support.
  63  */
  64
  65 #include <sys/param.h>
  66 #include <sys/systm.h>
  67 #include <sys/device.h>
  68
  69 #include <arm/xscale/ixp425reg.h>
  70 #include <arm/xscale/ixp425var.h>
  71
  72 #include <dev/pci/pcivar.h>
  73
  74 #include <evbarm/nslu2/nslu2reg.h>
  75
  76 static int
  77 nslu2_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
  78 {
  79
  80         KASSERT(pa->pa_bus == 0 && pa->pa_device == 1);
  81
  82         switch (pa->pa_function) {
  83         case 0:
  84                 *ihp = PCI_INT_A;
  85                 break;
  86
  87         case 1:
  88                 *ihp = PCI_INT_B;
  89                 break;
  90
  91         case 2:
  92                 *ihp = PCI_INT_C;
  93                 break;
  94
  95         default:
  96                 return (1);
  97         }
  98
  99         return (0);
 100 }
 101
 102 static const char *
 103 nslu2_pci_intr_string(void *v, pci_intr_handle_t ih)
 104 {
 105
 106         switch (ih) {
 107         case PCI_INT_A:
 108                 return ("INTA");
 109
 110         case PCI_INT_B:
 111                 return ("INTB");
 112
 113         case PCI_INT_C:
 114                 return ("INTC");
 115         }
 116
 117         return (NULL);
 118 }
 119
 120 static const struct evcnt *
 121 nslu2_pci_intr_evcnt(void *v, pci_intr_handle_t ih)
 122 {
 123
 124         return (NULL);
 125 }
 126
 127 static void *
 128 nslu2_pci_intr_establish(void *v, pci_intr_handle_t ih, int ipl,
 129     int (*func)(void *), void *arg)
 130 {
 131
 132         return (ixp425_intr_establish(ih, ipl, func, arg));
 133 }
 134
 135 static void
 136 nslu2_pci_intr_disestablish(void *v, void *cookie)
 137 {
 138
 139         ixp425_intr_disestablish(cookie);
 140 }
 141
 142 void
 143 ixp425_md_pci_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev, int pin,
 144     int swiz, int *ilinep)
 145 {
 146
 147         KASSERT(bus == 0 && dev == 1);
 148
 149         *ilinep = ((swiz + pin - 1) & 3);
 150 }
 151
 152 void
 153 ixp425_md_pci_init(struct ixp425_softc *sc)
 154 {
 155         pci_chipset_tag_t pc = &sc->ia_pci_chipset;
 156         u_int32_t reg;
 157
 158         pc->pc_intr_v = sc;
 159         pc->pc_intr_map = nslu2_pci_intr_map;
 160         pc->pc_intr_string = nslu2_pci_intr_string;
 161         pc->pc_intr_evcnt = nslu2_pci_intr_evcnt;
 162         pc->pc_intr_establish = nslu2_pci_intr_establish;
 163         pc->pc_intr_disestablish = nslu2_pci_intr_disestablish;
 164
 165         /* PCI Reset Assert */
 166         reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOUTR);
 167         reg &= ~(1u << GPIO_PCI_RESET);
 168         GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOUTR, reg);
 169
 170         /* PCI Clock Disable */
 171         reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR);
 172         reg &= ~GPCLKR_MUX14;
 173         GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg);
 174
 175         /*
 176          * Set GPIO Direction
 177          *      Output: PCI_CLK, PCI_RESET
 178          *      Input:  PCI_INTA, PCI_INTB, PCI_INTC
 179          */
 180         reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOER);
 181         reg &= ~((1u << GPIO_PCI_CLK) | (1u << GPIO_PCI_RESET));
 182         reg |= (1u << GPIO_PCI_INTA) | (1u << GPIO_PCI_INTB) |
 183             (1u << GPIO_PCI_INTC);
 184         GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOER, reg);
 185
 186         /*
 187          * Set GPIO interrupt type
 188          *      PCI_INT_A, PCI_INTB, PCI_INT_C: Active Low
 189          */
 190         reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTA));
 191         reg &= ~GPIO_TYPE(GPIO_PCI_INTA, GPIO_TYPE_MASK);
 192         reg |= GPIO_TYPE(GPIO_PCI_INTA, GPIO_TYPE_ACT_LOW);
 193         GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTA), reg);
 194
 195         reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTB));
 196         reg &= ~GPIO_TYPE(GPIO_PCI_INTB, GPIO_TYPE_MASK);
 197         reg |= GPIO_TYPE(GPIO_PCI_INTB, GPIO_TYPE_ACT_LOW);
 198         GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTB), reg);
 199
 200         reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTC));
 201         reg &= ~GPIO_TYPE(GPIO_PCI_INTC, GPIO_TYPE_MASK);
 202         reg |= GPIO_TYPE(GPIO_PCI_INTC, GPIO_TYPE_ACT_LOW);
 203         GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTC), reg);
 204
 205         /* Clear ISR */
 206         GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPISR, (1u << GPIO_PCI_INTA) |
 207             (1u << GPIO_PCI_INTB) | (1u << GPIO_PCI_INTC));
 208
 209         /* Wait 1ms to satisfy "minimum reset assertion time" of the PCI spec */
 210         DELAY(1000);
 211         reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR);
 212         reg |= (0xf << GPCLKR_CLK0DC_SHIFT) | (0xf << GPCLKR_CLK0TC_SHIFT);
 213         GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg);
 214
 215         /* PCI Clock Enable */
 216         reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR);
 217         reg |= GPCLKR_MUX14;
 218         GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg);
 219
 220         /*
 221          * Wait 100us to satisfy "minimum reset assertion time from clock stable
 222          * requirement of the PCI spec
 223          */
 224         DELAY(100);
 225         /* PCI Reset deassert */
 226         reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOUTR);
 227         reg |= 1u << GPIO_PCI_RESET;
 228         GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOUTR, reg);
 229
 230         /*
 231          * AHB->PCI address translation
 232          *      PCI Memory Map allocation in 0x48000000 (64MB)
 233          *      see. IXP425_PCI_MEM_HWBASE
 234          */
 235         PCI_CSR_WRITE_4(sc, PCI_PCIMEMBASE, 0x48494a4b);
 236
 237         /*
 238          * PCI->AHB address translation
 239          *      begin at the physical memory start + OFFSET
 240          */
 241 #define AHB_OFFSET      0x10000000UL
 242         reg  = (AHB_OFFSET + 0x00000000) >> 0;
 243         reg |= (AHB_OFFSET + 0x01000000) >> 8;
 244         reg |= (AHB_OFFSET + 0x02000000) >> 16;
 245         reg |= (AHB_OFFSET + 0x03000000) >> 24;
 246         PCI_CSR_WRITE_4(sc, PCI_AHBMEMBASE, reg);
 247
 248         /* Write Mapping registers PCI Configuration Registers */
 249         /* Base Address 0 - 3 */
 250         ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR0, AHB_OFFSET + 0x00000000);
 251         ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR1, AHB_OFFSET + 0x01000000);
 252         ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR2, AHB_OFFSET + 0x02000000);
 253         ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR3, AHB_OFFSET + 0x03000000);
 254
 255         /* Base Address 4 */
 256         ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR4, 0xffffffff);
 257
 258         /* Base Address 5 */
 259         ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR5, 0x00000000);
 260
 261         /* Assert some PCI errors */
 262         PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_AHBE | ISR_PPE | ISR_PFE | ISR_PSE);
 263
 264         /*
 265          * Set up byte lane swapping between little-endian PCI
 266          * and the big-endian AHB bus
 267          */
 268         PCI_CSR_WRITE_4(sc, PCI_CSR, CSR_IC | CSR_ABE | CSR_PDS);
 269
 270         /*
 271          * Enable bus mastering and I/O,memory access
 272          */
 273         ixp425_pci_conf_reg_write(sc, PCI_COMMAND_STATUS_REG,
 274                 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
 275                 PCI_COMMAND_MASTER_ENABLE);
 276
 277         /*
 278          * Wait some more to ensure PCI devices have stabilised.
 279          */
 280         DELAY(50000);
 281 }