sys/arch/evbmips/alchemy/mtx-1.c

   1 /* $NetBSD: mtx-1.c,v 1.2 2006/02/23 04:45:55 gdamore Exp $ */
   2
   3 /*-
   4  * Copyright (c) 2006 Itronix Inc.
   5  * All rights reserved.
   6  *
   7  * Written by Garrett D'Amore for Itronix Inc.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. The name of Itronix Inc. may not be used to endorse
  18  *    or promote products derived from this software without specific
  19  *    prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  23  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  24  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY
  25  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  27  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  28  * ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31  * POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/cdefs.h>
  35 __KERNEL_RCSID(0, "$NetBSD: mtx-1.c,v 1.2 2006/02/23 04:45:55 gdamore Exp $");
  36
  37 #include <sys/param.h>
  38 #include <machine/bus.h>
  39 #include <machine/locore.h>
  40 #include <evbmips/alchemy/obiovar.h>
  41 #include <evbmips/alchemy/board.h>
  42
  43 #define MTX1_RESET      0xE00001C
  44
  45 #define GET16(x)        \
  46         (*((volatile uint16_t *)MIPS_PHYS_TO_KSEG1(x)))
  47 #define PUT16(x, v)     \
  48         (*((volatile uint16_t *)MIPS_PHYS_TO_KSEG1(x)) = (v))
  49
  50 static void mtx1_init(void);
  51 static int mtx1_pci_intr_map(struct pci_attach_args *,
  52                                  pci_intr_handle_t *);
  53 static void mtx1_reboot(void);
  54
  55 static const struct obiodev mtx1_devices[] = {
  56 #if 0
  57         { "aupcmcia", -1, -1 },
  58         { "auaudio", -1, -1 },
  59 #endif
  60         { NULL },
  61 };
  62
  63 static struct alchemy_board mtx1_info = {
  64         "4G Systems MTX-1",
  65         mtx1_devices,
  66         mtx1_init,
  67         mtx1_pci_intr_map,
  68         mtx1_reboot,
  69         NULL,   /* poweroff */
  70 };
  71
  72 const struct alchemy_board *
  73 board_info(void)
  74 {
  75
  76         return &mtx1_info;
  77 }
  78
  79 void
  80 mtx1_init(void)
  81 {
  82
  83         if (MIPS_PRID_COPTS(cpu_id) != MIPS_AU1500)
  84                 panic("mtx-1: CPU not an AU1500!");
  85
  86         /*
  87          * If we had any kind of identification registers, we could
  88          * print them here.  Apparently the MTX-1 doesn't have that
  89          * kind of info.
  90          */
  91
  92         /* leave console and clocks alone -- YAMON should have got it right! */
  93 }
  94
  95 int
  96 mtx1_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
  97 {
  98         /*
  99          * The board has up to 4 adapters, each with two minipci slots,
 100          * giving up to 8 devices.  Each slot 0 is the top, and slot 1
 101          * is the bottom.
 102          *
 103          * As these are mini PCI slots, only 2 interrupt pins can be
 104          * used on each slot.
 105          */
 106         static const int irqmap[8/*device*/][4/*pin*/] = {
 107                 {  1,  2, -1, -1 },     /* IDSEL 0 - Adapter A - Slot 0 */
 108                 {  1,  2, -1, -1 },     /* IDSEL 1 - Adapter A - Slot 1 */
 109                 {  4,  5, -1, -1 },     /* IDSEL 2 - Adapter B - Slot 0 */
 110                 {  5,  4, -1, -1 },     /* IDSEL 3 - Adapter B - Slot 1 */
 111
 112                 {  1,  2, -1, -1 },     /* IDSEL 4 - Adapter C - Slot 0 */
 113                 {  1,  2, -1, -1 },     /* IDSEL 5 - Adapter C - Slot 1 */
 114                 {  4,  5, -1, -1 },     /* IDSEL 6 - Adapter D - Slot 0 */
 115                 {  5,  4, -1, -1 },     /* IDSEL 7 - Adapter D - Slot 1 */
 116         };
 117         int     pin, dev, irq;
 118
 119         /* if interrupt pin not used... */
 120         if ((pin = pa->pa_intrpin) == 0)
 121                 return 1;
 122
 123         if (pin > 4) {
 124                 printf("pci: bad interrupt pin %d\n", pin);
 125                 return 1;
 126         }
 127
 128         pci_decompose_tag(pa->pa_pc, pa->pa_intrtag, NULL, &dev, NULL);
 129         if ((dev < 0) || (dev > 7)) {
 130                 printf("pci: bad device %d\n", dev);
 131                 return 1;
 132         }
 133
 134         if ((irq = irqmap[dev][pin - 1]) == -1) {
 135                 printf("pci: no IRQ routing for device %d pin %d\n", dev, pin);
 136                 return 1;
 137         }
 138
 139         *ihp = irq;
 140         return 0;
 141 }
 142
 143 void
 144 mtx1_reboot(void)
 145 {
 146         /* fyi, this looks like the same as the DBAu1500 reset */
 147         PUT16(MTX1_RESET , 0);
 148         delay(100000);  /* 100 msec */
 149 }