sys/arch/evbmips/alchemy/pb1000reg.h

   1 /*      $NetBSD: pb1000reg.h,v 1.2 2006/06/17 14:42:54 simonb Exp $     */
   2
   3 /*-
   4  * Copyright (c) 2001 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by Jason R. Thorpe.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 /*
  33  * Memory map and register definitions for the Alchemy Semiconductor Pb1000.
  34  */
  35
  36 /* RAM addresses */
  37 #define PB1000_SDRAM_BASE       0x00000000
  38 #define PB1000_SDRAM_SIZE       0x04000000
  39
  40 /* Static RAM */
  41 #define PB1000_SRAM_BASE        0x1c000000
  42 #define PB1000_SRAM_SIZE        0x00040000
  43
  44 /* PCMCIA addresses */
  45 #define PB1000_PCMCIA_CONTROL   0x1e000000
  46 #define PB1000_PCMCIA_DATA      0x1e000004
  47 #define PB1000_PCMCIA_STATUS    0x1e000008
  48
  49 /* CPLD addresses */
  50 #define PB1000_CPLD_AUX0        0x1e00000c
  51 #define PB1000_CPLD_AUX1        0x1e000010
  52 #define PB1000_CPLD_AUX2        0x1e000014
  53
  54 /* Flash addresses */
  55 #define PB1000_FLASH_BASE       0x1f800000
  56 #define PB1000_FLASH_SIZE       0x00800000