sys/arch/evbmips/malta/dev/gtreg.h

   1 /*      $NetBSD: gtreg.h,v 1.1 2002/03/07 14:44:05 simonb Exp $ */
   2
   3 #define GT_REGVAL(x)    *((volatile u_int32_t *) \
   4                             (MIPS_PHYS_TO_KSEG1(MALTA_CORECTRL_BASE + (x))))
   5
   6 /* CPU Configuration Register Map */
   7 #define GT_CPU_INT      0x000
   8 #define GT_MULTIGT      0x120
   9
  10 /* CPU Address Decode Register Map */
  11
  12 /* CPU Error Report Register Map */
  13
  14 /* CPU Sync Barrier Register Map */
  15
  16 /* SDRAM and Device Address Decode Register Map */
  17
  18 /* SDRAM Configuration Register Map */
  19
  20 /* SDRAM Parameters Register Map */
  21
  22 /* ECC Register Map */
  23
  24 /* Device Parameters Register Map */
  25
  26 /* DMA Record Register Map */
  27
  28 /* DMA Arbiter Register Map */
  29
  30 /* Timer/Counter Register Map */
  31 //#define       GT_TC_0         0x850
  32 //#define       GT_TC_1         0x854
  33 //#define       GT_TC_2         0x858
  34 //#define       GT_TC_3         0x85c
  35 //#define       GT_TC_CONTROL   0x864
  36
  37 /* PCI Internal Register Map */
  38 #define GT_PCI0_CFG_ADDR        0xcf8
  39 #define GT_PCI0_CFG_DATA        0xcfc
  40 #define GT_PCI0_INTR_ACK        0xc34
  41
  42 /* Interrupts Register Map */
  43 #define GT_INTR_CAUSE   0xc18
  44 #define  GTIC_INTSUM     0x00000001
  45 #define  GTIC_MEMOUT     0x00000002
  46 #define  GTIC_DMAOUT     0x00000004
  47 #define  GTIC_CPUOUT     0x00000008
  48 #define  GTIC_DMA0COMP   0x00000010
  49 #define  GTIC_DMA1COMP   0x00000020
  50 #define  GTIC_DMA2COMP   0x00000040
  51 #define  GTIC_DMA3COMP   0x00000080
  52 #define  GTIC_T0EXP      0x00000100
  53 #define  GTIC_T1EXP      0x00000200
  54 #define  GTIC_T2EXP      0x00000400
  55 #define  GTIC_T3EXP      0x00000800
  56 #define  GTIC_MASRDERR0  0x00001000
  57 #define  GTIC_SLVWRERR0  0x00002000
  58 #define  GTIC_MASWRERR0  0x00004000
  59 #define  GTIC_SLVRDERR0  0x00008000
  60 #define  GTIC_ADDRERR0   0x00010000
  61 #define  GTIC_MEMERR     0x00020000
  62 #define  GTIC_MASABORT0  0x00040000
  63 #define  GTIC_TARABORT0  0x00080000
  64 #define  GTIC_RETRYCNT0  0x00100000
  65 #define  GTIC_PMCINT_0   0x00200000
  66 #define  GTIC_CPUINT     0x0c300000
  67 #define  GTIC_PCINT      0xc3000000
  68 #define  GTIC_CPUINTSUM  0x40000000
  69 #define  GTIC_PCIINTSUM  0x80000000
  70
  71 /* PCI Configuration Register Map */
  72 //#define       GT_PCICONFIGBASE        0
  73 //#define       GT_PCIDID               BONITO(GT_PCICONFIGBASE + 0x00)
  74 //#define       GT_PCICMD               BONITO(GT_PCICONFIGBASE + 0x04)
  75 //#define       GT_PCICLASS             BONITO(GT_PCICONFIGBASE + 0x08)
  76 //#define       GT_PCILTIMER            BONITO(GT_PCICONFIGBASE + 0x0c)
  77 //#define       GT_PCIBASE0             BONITO(GT_PCICONFIGBASE + 0x10)
  78 //#define       GT_PCIBASE1             BONITO(GT_PCICONFIGBASE + 0x14)
  79 //#define       GT_PCIBASE2             BONITO(GT_PCICONFIGBASE + 0x18)
  80 //#define       GT_PCIEXPRBASE          BONITO(GT_PCICONFIGBASE + 0x30)
  81 //#define       GT_PCIINT               BONITO(GT_PCICONFIGBASE + 0x3c)
  82
  83 /* PCI Configuration, Function 1, Register Map */
  84
  85 /* I2O Support Register Map */