sys/arch/evbmips/malta/malta_intr.c

   1 /*      $NetBSD: malta_intr.c,v 1.18 2008/01/09 20:38:35 wiz Exp $      */
   2
   3 /*
   4  * Copyright 2001, 2002 Wasabi Systems, Inc.
   5  * All rights reserved.
   6  *
   7  * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. All advertising materials mentioning features or use of this software
  18  *    must display the following acknowledgement:
  19  *      This product includes software developed for the NetBSD Project by
  20  *      Wasabi Systems, Inc.
  21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
  22  *    or promote products derived from this software without specific prior
  23  *    written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
  26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  35  * POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 /*
  39  * Platform-specific interrupt support for the MIPS Malta.
  40  */
  41
  42 #include <sys/cdefs.h>
  43 __KERNEL_RCSID(0, "$NetBSD: malta_intr.c,v 1.18 2008/01/09 20:38:35 wiz Exp $");
  44
  45 #include <sys/param.h>
  46 #include <sys/device.h>
  47 #include <sys/kernel.h>
  48 #include <sys/malloc.h>
  49 #include <sys/systm.h>
  50 #include <sys/cpu.h>
  51
  52 #include <mips/locore.h>
  53
  54 #include <evbmips/malta/maltavar.h>
  55 #include <evbmips/malta/pci/pcibvar.h>
  56
  57 #include <dev/ic/mc146818reg.h>         /* for malta_cal_timer() */
  58
  59 #include <dev/isa/isavar.h>
  60 #include <dev/pci/pciidereg.h>
  61
  62 /*
  63  * This is a mask of bits to clear in the SR when we go to a
  64  * given hardware interrupt priority level.
  65  */
  66 const uint32_t ipl_sr_bits[_IPL_N] = {
  67         [IPL_NONE] = 0,
  68         [IPL_SOFTCLOCK] =
  69             MIPS_SOFT_INT_MASK_0,
  70         [IPL_SOFTNET] =
  71             MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1,
  72         [IPL_VM] =
  73             MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
  74             MIPS_INT_MASK_0,
  75         [IPL_SCHED] =
  76             MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
  77             MIPS_INT_MASK_0 |
  78             MIPS_INT_MASK_1 |
  79             MIPS_INT_MASK_2 |
  80             MIPS_INT_MASK_3 |
  81             MIPS_INT_MASK_4 |
  82             MIPS_INT_MASK_5,
  83 };
  84
  85 /*
  86  * This is a mask of bits to clear in the SR when we go to a
  87  * given software interrupt priority level.
  88  * Hardware ipls are port/board specific.
  89  */
  90 const uint32_t mips_ipl_si_to_sr[2] = {
  91         MIPS_SOFT_INT_MASK_0,
  92         MIPS_SOFT_INT_MASK_1, /* XXX is this right with the new softints? */
  93 };
  94
  95 struct malta_cpuintr {
  96         LIST_HEAD(, evbmips_intrhand) cintr_list;
  97         struct evcnt cintr_count;
  98 };
  99 #define NINTRS          5       /* MIPS INT0 - INT4 */
 100
 101 struct malta_cpuintr malta_cpuintrs[NINTRS];
 102 const char *malta_cpuintrnames[NINTRS] = {
 103         "int 0 (piix4)",
 104         "int 1 (smi)",
 105         "int 2 (uart)",
 106         "int 3 (core hi/gt64120)",
 107         "int 4 (core lo)",
 108 };
 109
 110 static int      malta_pci_intr_map(struct pci_attach_args *, pci_intr_handle_t *);
 111 static const char
 112                 *malta_pci_intr_string(void *, pci_intr_handle_t);
 113 static const struct evcnt
 114                 *malta_pci_intr_evcnt(void *, pci_intr_handle_t);
 115 static void     *malta_pci_intr_establish(void *, pci_intr_handle_t, int,
 116                     int (*)(void *), void *);
 117 static void     malta_pci_intr_disestablish(void *, void *);
 118 static void     malta_pci_conf_interrupt(void *, int, int, int, int, int *);
 119 static void     *malta_pciide_compat_intr_establish(void *, struct device *,
 120                     struct pci_attach_args *, int, int (*)(void *), void *);
 121
 122 void
 123 evbmips_intr_init(void)
 124 {
 125         struct malta_config *mcp = &malta_configuration;
 126         int i;
 127
 128         for (i = 0; i < NINTRS; i++) {
 129                 LIST_INIT(&malta_cpuintrs[i].cintr_list);
 130                 evcnt_attach_dynamic(&malta_cpuintrs[i].cintr_count,
 131                     EVCNT_TYPE_INTR, NULL, "mips", malta_cpuintrnames[i]);
 132         }
 133
 134         mcp->mc_pc.pc_intr_v = NULL;
 135         mcp->mc_pc.pc_intr_map = malta_pci_intr_map;
 136         mcp->mc_pc.pc_intr_string = malta_pci_intr_string;
 137         mcp->mc_pc.pc_intr_evcnt = malta_pci_intr_evcnt;
 138         mcp->mc_pc.pc_intr_establish = malta_pci_intr_establish;
 139         mcp->mc_pc.pc_intr_disestablish = malta_pci_intr_disestablish;
 140         mcp->mc_pc.pc_conf_interrupt = malta_pci_conf_interrupt;
 141         mcp->mc_pc.pc_pciide_compat_intr_establish =
 142             malta_pciide_compat_intr_establish;
 143 }
 144
 145 void
 146 malta_cal_timer(bus_space_tag_t st, bus_space_handle_t sh)
 147 {
 148         uint32_t ctrdiff[4], startctr, endctr;
 149         uint8_t regc;
 150         int i;
 151
 152         /* Disable interrupts first. */
 153         bus_space_write_1(st, sh, 0, MC_REGB);
 154         bus_space_write_1(st, sh, 1, MC_REGB_SQWE | MC_REGB_BINARY |
 155             MC_REGB_24HR);
 156
 157         /* Initialize for 16Hz. */
 158         bus_space_write_1(st, sh, 0, MC_REGA);
 159         bus_space_write_1(st, sh, 1, MC_BASE_32_KHz | MC_RATE_16_Hz);
 160
 161         /* Run the loop an extra time to prime the cache. */
 162         for (i = 0; i < 4; i++) {
 163                 // led_display('h', 'z', '0' + i, ' ');
 164
 165                 /* Enable the interrupt. */
 166                 bus_space_write_1(st, sh, 0, MC_REGB);
 167                 bus_space_write_1(st, sh, 1, MC_REGB_PIE | MC_REGB_SQWE |
 168                     MC_REGB_BINARY | MC_REGB_24HR);
 169
 170                 /* Go to REGC. */
 171                 bus_space_write_1(st, sh, 0, MC_REGC);
 172
 173                 /* Wait for it to happen. */
 174                 startctr = mips3_cp0_count_read();
 175                 do {
 176                         regc = bus_space_read_1(st, sh, 1);
 177                         endctr = mips3_cp0_count_read();
 178                 } while ((regc & MC_REGC_IRQF) == 0);
 179
 180                 /* Already ACK'd. */
 181
 182                 /* Disable. */
 183                 bus_space_write_1(st, sh, 0, MC_REGB);
 184                 bus_space_write_1(st, sh, 1, MC_REGB_SQWE | MC_REGB_BINARY |
 185                     MC_REGB_24HR);
 186
 187                 ctrdiff[i] = endctr - startctr;
 188         }
 189
 190         /* Compute the number of cycles per second. */
 191         curcpu()->ci_cpu_freq = ((ctrdiff[2] + ctrdiff[3]) / 2) * 16/*Hz*/;
 192
 193         /* Compute the number of ticks for hz. */
 194         curcpu()->ci_cycles_per_hz = (curcpu()->ci_cpu_freq + hz / 2) / hz;
 195
 196         /* Compute the delay divisor. */
 197         curcpu()->ci_divisor_delay =
 198             ((curcpu()->ci_cpu_freq + 500000) / 1000000);
 199
 200         /*
 201          * Get correct cpu frequency if the CPU runs at twice the
 202          * external/cp0-count frequency.
 203          */
 204         if (mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT)
 205                 curcpu()->ci_cpu_freq *= 2;
 206
 207 #ifdef DEBUG
 208         printf("Timer calibration: %lu cycles/sec [(%u, %u) * 16]\n",
 209             curcpu()->ci_cpu_freq, ctrdiff[2], ctrdiff[3]);
 210 #endif
 211 }
 212
 213 void *
 214 evbmips_intr_establish(int irq, int (*func)(void *), void *arg)
 215 {
 216         struct evbmips_intrhand *ih;
 217         int s;
 218
 219         ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT);
 220         if (ih == NULL)
 221                 return (NULL);
 222
 223         ih->ih_func = func;
 224         ih->ih_arg = arg;
 225
 226         s = splhigh();
 227
 228         /*
 229          * Link it into the tables.
 230          */
 231         LIST_INSERT_HEAD(&malta_cpuintrs[0].cintr_list, ih, ih_q);
 232
 233         /* XXX - should check that MIPS_INT_MASK_0 is set... */
 234
 235         splx(s);
 236
 237         return (ih);
 238 }
 239
 240 void
 241 evbmips_intr_disestablish(void *arg)
 242 {
 243         struct evbmips_intrhand *ih = arg;
 244         int s;
 245
 246         s = splhigh();
 247
 248         /*
 249          * First, remove it from the table.
 250          */
 251         LIST_REMOVE(ih, ih_q);
 252
 253         /* XXX - disable MIPS_INT_MASK_0 if list is empty? */
 254
 255         splx(s);
 256
 257         free(ih, M_DEVBUF);
 258 }
 259
 260 void
 261 evbmips_iointr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
 262 {
 263         struct evbmips_intrhand *ih;
 264
 265         /* Check for error interrupts (SMI, GT64120) */
 266         if (ipending & (MIPS_INT_MASK_1 | MIPS_INT_MASK_3)) {
 267                 if (ipending & MIPS_INT_MASK_1)
 268                         panic("piix4 SMI interrupt");
 269                 if (ipending & MIPS_INT_MASK_3)
 270                         panic("gt64120 error interrupt");
 271         }
 272
 273         /*
 274          * Read the interrupt pending registers, mask them with the
 275          * ones we have enabled, and service them in order of decreasing
 276          * priority.
 277          */
 278         if (ipending & MIPS_INT_MASK_0) {
 279                 /* All interrupts are gated through MIPS HW interrupt 0 */
 280                 malta_cpuintrs[0].cintr_count.ev_count++;
 281                 LIST_FOREACH(ih, &malta_cpuintrs[0].cintr_list, ih_q)
 282                         (*ih->ih_func)(ih->ih_arg);
 283                 cause &= ~MIPS_INT_MASK_0;
 284         }
 285
 286         /* Re-enable anything that we have processed. */
 287         _splset(MIPS_SR_INT_IE | ((status & ~cause) & MIPS_HARD_INT_MASK));
 288 }
 289
 290 /*
 291  * YAMON configures pa_intrline correctly (so far), so we trust it to DTRT
 292  * in the future...
 293  */
 294 #undef YAMON_IRQ_MAP_BAD
 295
 296 /*
 297  * PCI interrupt support
 298  */
 299 static int
 300 malta_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
 301 {
 302 #ifdef YAMON_IRQ_MAP_BAD
 303         static const int pciirqmap[12/*device*/][4/*pin*/] = {
 304                 { -1, -1, -1, 11 },     /* 10: USB */
 305                 { 10, -1, -1, -1 },     /* 11: Ethernet */
 306                 { 11, -1, -1, -1 },     /* 12: Audio */
 307                 { -1, -1, -1, -1 },     /* 13: not used */
 308                 { -1, -1, -1, -1 },     /* 14: not used */
 309                 { -1, -1, -1, -1 },     /* 15: not used */
 310                 { -1, -1, -1, -1 },     /* 16: not used */
 311                 { -1, -1, -1, -1 },     /* 17: Core card(?) */
 312                 { 10, 10, 11, 11 },     /* 18: PCI Slot 1 */
 313                 { 10, 11, 11, 10 },     /* 19: PCI Slot 2 */
 314                 { 11, 11, 10, 10 },     /* 20: PCI Slot 3 */
 315                 { 11, 10, 10, 11 },     /* 21: PCI Slot 4 */
 316         };
 317         int buspin, device, irq;
 318 #else   /* !YAMON_IRQ_MAP_BAD */
 319         int buspin;
 320 #endif  /* !YAMON_IRQ_MAP_BAD */
 321
 322         buspin = pa->pa_intrpin;
 323
 324         if (buspin == 0) {
 325                 /* No IRQ used. */
 326                 return (1);
 327         }
 328
 329         if (buspin > 4) {
 330                 printf("malta_pci_intr_map: bad interrupt pin %d\n", buspin);
 331                 return (1);
 332         }
 333
 334 #ifdef YAMON_IRQ_MAP_BAD
 335         pci_decompose_tag(pa->pa_pc, pa->pa_intrtag, NULL, &device, NULL);
 336
 337         if (device < 10 || device > 21) {
 338                 printf("malta_pci_intr_map: bad device %d\n", device);
 339                 return (1);
 340         }
 341
 342         irq = pciirqmap[device - 10][buspin - 1];
 343         if (irq == -1) {
 344                 printf("malta_pci_intr_map: no mapping for device %d pin %d\n",
 345                     device, buspin);
 346                 return (1);
 347         }
 348
 349         *ihp = irq;
 350 #else   /* !YAMON_IRQ_MAP_BAD */
 351         *ihp = pa->pa_intrline;
 352 #endif  /* !YAMON_IRQ_MAP_BAD */
 353         return (0);
 354 }
 355
 356 static const char *
 357 malta_pci_intr_string(void *v, pci_intr_handle_t irq)
 358 {
 359
 360         return (isa_intr_string(pcib_ic, irq));
 361 }
 362
 363 static const struct evcnt *
 364 malta_pci_intr_evcnt(void *v, pci_intr_handle_t irq)
 365 {
 366
 367         return (isa_intr_evcnt(pcib_ic, irq));
 368 }
 369
 370 static void *
 371 malta_pci_intr_establish(void *v, pci_intr_handle_t irq, int level,
 372     int (*func)(void *), void *arg)
 373 {
 374
 375         return (isa_intr_establish(pcib_ic, irq, IST_LEVEL, level, func, arg));
 376 }
 377
 378 static void
 379 malta_pci_intr_disestablish(void *v, void *arg)
 380 {
 381
 382         return (isa_intr_disestablish(pcib_ic, arg));
 383 }
 384
 385 static void
 386 malta_pci_conf_interrupt(void *v, int bus, int dev, int func, int swiz,
 387     int *iline)
 388 {
 389
 390         /*
 391          * We actually don't need to do anything; everything is handled
 392          * in pci_intr_map().
 393          */
 394         *iline = 0;
 395 }
 396
 397 void *
 398 malta_pciide_compat_intr_establish(void *v, struct device *dev,
 399     struct pci_attach_args *pa, int chan, int (*func)(void *), void *arg)
 400 {
 401         pci_chipset_tag_t pc = pa->pa_pc;
 402         void *cookie;
 403         int bus, irq;
 404
 405         pci_decompose_tag(pc, pa->pa_tag, &bus, NULL, NULL);
 406
 407         /*
 408          * If this isn't PCI bus #0, all bets are off.
 409          */
 410         if (bus != 0)
 411                 return (NULL);
 412
 413         irq = PCIIDE_COMPAT_IRQ(chan);
 414         cookie = isa_intr_establish(pcib_ic, irq, IST_EDGE, IPL_BIO, func, arg);
 415         if (cookie == NULL)
 416                 return (NULL);
 417         printf("%s: %s channel interrupting at %s\n", dev->dv_xname,
 418             PCIIDE_CHANNEL_NAME(chan), malta_pci_intr_string(v, irq));
 419         return (cookie);
 420 }