sys/arch/evbppc/virtex/dev/cdmacreg.h

   1 /*      $NetBSD */
   2
   3 /*
   4  * Copyright (c) 2006 Jachym Holecek
   5  * All rights reserved.
   6  *
   7  * Written for DFC Design, s.r.o.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  *
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  *
  16  * 2. Redistributions in binary form must reproduce the above copyright
  17  *    notice, this list of conditions and the following disclaimer in the
  18  *    documentation and/or other materials provided with the distribution.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  21  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  22  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  23  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  24  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  25  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  26  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  27  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  28  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  29  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 #include <sys/cdefs.h>
  33
  34 #ifndef _VIRTEX_DEV_CDMACREG_H_
  35 #define _VIRTEX_DEV_CDMACREG_H_
  36
  37 /*
  38  * CDMAC registers and data structures. Keep the names fully qualified, users
  39  * need at least CDMAC_STAT bits to manipulate descriptor queues. The offsets
  40  * are multiplied by four compared to Xilinx documentation -- so don't get
  41  * confused, bus space will deal.
  42  *
  43  * The number of channels and interrupt wiring differs per design.
  44  */
  45
  46 /* Status and control register block sizes. */
  47 #define CDMAC_CTRL_SIZE         0x0c
  48 #define CDMAC_STAT_SIZE         0x04
  49
  50 /* Status and control register offsets per channel. */
  51 #define CDMAC_STAT_BASE(n)      (0x80 + (n) * 0x04)
  52 #define CDMAC_CTRL_BASE(n)      (0x00 + (n) * 0x10)
  53
  54 /* Individual engine control registers. */
  55 #define CDMAC_NEXT              0x0000  /* Next descriptor pointer,
  56                                          * 32B aligned, 0x0 = stop */
  57 #define CDMAC_CURADDR           0x0004  /* Address being transferred */
  58 #define CDMAC_CURSIZE           0x0008  /* Remaining length */
  59 #define CDMAC_CURDESC           0x000c  /* Current descriptor pointer */
  60
  61 #define CDMAC_CURSIZE_MASK      0x00ffffff
  62
  63 /* Engine status reg bits. */
  64 #define CDMAC_STAT_ERROR        0x80000000      /* EINVAL -> halt, interrupt */
  65 #define CDMAC_STAT_INTR         0x40000000      /* Interrupt on end of descr */
  66 #define CDMAC_STAT_STOP         0x20000000      /* Stop on end of descr */
  67 #define CDMAC_STAT_DONE         0x10000000      /* Descriptor done */
  68 #define CDMAC_STAT_SOP          0x08000000      /* Start of packet */
  69 #define CDMAC_STAT_EOP          0x04000000      /* End of packet */
  70 #define CDMAC_STAT_BUSY         0x02000000      /* Engine busy */
  71 #define CDMAC_STAT_RESET        0x01000000      /* Channel reset */
  72
  73 #ifdef notdef
  74 /*
  75  * DMA engine timers, 8bit. Rather useless -- we need "interrupt
  76  * if transfer stalls for N cycles", not "fire after N cycles".
  77  * If we ever use this, move definitions to design-specific code
  78  * like we do with STAT.
  79  */
  80 #define CDMAC_TIMER_TX0         0x00a0
  81 #define CDMAC_TIMER_RX0         0x00a4
  82 #define CDMAC_TIMER_TX1         0x00a8
  83 #define CDMAC_TIMER_RX1         0x00ac
  84 #endif /* notdef */
  85
  86 /* Interrupt register (active-high level-sensitive intr). */
  87 #define CDMAC_INTR              0x00bc
  88
  89 #define CDMAC_INTR_MIE          0x80000000      /* Master interrupt enable */
  90 #define CDMAC_INTR_TX0          0x00000001      /* Descriptor interrupts */
  91 #define CDMAC_INTR_RX0          0x00000002
  92 #define CDMAC_INTR_TX1          0x00000004
  93 #define CDMAC_INTR_RX1          0x00000008
  94 #define CDMAC_TIMO_TX0          0x01000000      /* Timer interrupts */
  95 #define CDMAC_TIMO_RX0          0x02000000
  96 #define CDMAC_TIMO_TX1          0x04000000
  97 #define CDMAC_TIMO_RX1          0x08000000
  98
  99 #define CDMAC_CHAN_INTR(n)      (1 << (n))
 100
 101 /*
 102  * Wire data structure of transfer descriptor (shared for Rx/Tx).
 103  */
 104 struct cdmac_descr {
 105         uint32_t        desc_next;      /* Next descriptor */
 106         uint32_t        desc_addr;      /* Payload address */
 107         uint32_t        desc_size;      /* Payload size */
 108
 109         /* Application defined fields, valid in 1st desc on Tx, last on Rx. */
 110         uint32_t        desc_user0;     /* See below */
 111 #define desc_stat       desc_user0
 112
 113         uint32_t        desc_user1;
 114         uint32_t        desc_user2;
 115         uint32_t        desc_user3;
 116         uint32_t        desc_user4;
 117 } __aligned(8) __packed;
 118
 119 #define DMAC_STAT_MASK  0xff000000      /* CDMAC portion of desc_user0 */
 120 #define DMAC_USER_MASK  0x00ffffff      /* User defined part of desc_user0 */
 121
 122 #endif /*_VIRTEX_DEV_CDMACREG_H_*/