1 /* $NetBSD: grf_dvreg.h,v 1.5.66.3 2004/09/21 13:15:14 skrll Exp $ */
4 * Copyright (c) 1990, 1993
5 * The Regents of the University of California. All rights reserved.
7 * This code is derived from software contributed to Berkeley by
8 * the Systems Programming Group of the University of Utah Computer
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. Neither the name of the University nor the names of its contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * from: Utah $Hdr: grf_dvreg.h 1.5 92/01/21$
37 * @(#)grf_dvreg.h 8.1 (Berkeley) 6/10/93
40 * Copyright (c) 1988 University of Utah.
42 * This code is derived from software contributed to Berkeley by
43 * the Systems Programming Group of the University of Utah Computer
46 * Redistribution and use in source and binary forms, with or without
47 * modification, are permitted provided that the following conditions
49 * 1. Redistributions of source code must retain the above copyright
50 * notice, this list of conditions and the following disclaimer.
51 * 2. Redistributions in binary form must reproduce the above copyright
52 * notice, this list of conditions and the following disclaimer in the
53 * documentation and/or other materials provided with the distribution.
54 * 3. All advertising materials mentioning features or use of this software
55 * must display the following acknowledgement:
56 * This product includes software developed by the University of
57 * California, Berkeley and its contributors.
58 * 4. Neither the name of the University nor the names of its contributors
59 * may be used to endorse or promote products derived from this software
60 * without specific prior written permission.
62 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
63 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
64 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
65 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
66 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
67 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
68 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
69 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
70 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
71 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
74 * from: Utah $Hdr: grf_dvreg.h 1.5 92/01/21$
76 * @(#)grf_dvreg.h 8.1 (Berkeley) 6/10/93
79 #include <hp300/dev/iotypes.h> /* XXX */
82 * Map of the DaVinci frame buffer controller chip in memory ...
85 #define db_waitbusy(regaddr) \
86 while (((struct dvboxfb *)(regaddr))->wbusy || \
87 ((struct dvboxfb *)(regaddr))->as_busy) DELAY(100)
100 vu_char reset
; /* reset register 0x01 */
101 u_char fb_address
; /* frame buffer address 0x02 */
102 vu_char interrupt
; /* interrupt register 0x03 */
104 vu_char fbwmsb
; /* frame buffer width MSB 0x05 */
106 vu_char fbwlsb
; /* frame buffer width MSB 0x07 */
108 vu_char fbhmsb
; /* frame buffer height MSB 0x09 */
110 vu_char fbhlsb
; /* frame buffer height MSB 0x0b */
112 vu_char dwmsb
; /* display width MSB 0x0d */
114 vu_char dwlsb
; /* display width MSB 0x0f */
116 vu_char dhmsb
; /* display height MSB 0x11 */
118 vu_char dhlsb
; /* display height MSB 0x13 */
120 vu_char fbid
; /* frame buffer id 0x15 */
122 vu_char fbomsb
; /* frame buffer offset MSB 0x5d */
124 vu_char fbolsb
; /* frame buffer offset LSB 0x5f */
126 vu_char wbusy
; /* Window move in progress 0x4047 */
127 u_char f3
[0x405b-0x4047-1];
128 vu_char as_busy
; /* Scan accessing frame buf. 0x405B */
129 u_char f4
[0x4090-0x405b-1];
130 vu_int fbwen
; /* Frame buffer write enable 0x4090 */
131 u_char f5
[0x409f-0x4090-4];
132 vu_char wmove
; /* Initiate window move. 0x409F */
133 u_char f6
[0x40b3-0x409f-1];
134 vu_char fold
; /* Byte/longword per pixel 0x40B3 */
135 u_char f7
[0x40b7-0x40b3-1];
136 vu_char opwen
; /* Overlay plane write enable 0x40B7 */
137 u_char f8
[0x40bf-0x40b7-1];
138 vu_char drive
; /* Select FB vs. Overlay. 0x40BF */
140 u_char f8a
[0x40cb-0x40bf-1];
141 vu_char zconfig
; /* Z buffer configuration 0x40CB */
142 u_char f8b
[0x40cf-0x40cb-1];
143 vu_char alt_rr
; /* Alternate replacement rule 0x40CF */
144 u_char f8c
[0x40d3-0x40cf-1];
145 vu_char zrr
; /* Z replacement rule 0x40D3 */
147 u_char f9
[0x40d7-0x40d3-1];
148 vu_char en_scan
; /* Enable scan DTACK. 0x40D7 */
149 u_char f10
[0x40ef-0x40d7-1];
150 vu_char rep_rule
; /* Replacement rule 0x40EF */
151 u_char f11
[0x40f2-0x40ef-1];
152 vu_short source_x
; /* Window source X origin 0x40F2 */
153 u_char f12
[0x40f6-0x40f2-2];
154 vu_short source_y
; /* Window source Y origin 0x40F6 */
155 u_char f13
[0x40fa-0x40f6-2];
156 vu_short dest_x
; /* Window dest X origin 0x40FA */
157 u_char f14
[0x40fe -0x40fa-2];
158 vu_short dest_y
; /* Window dest Y origin 0x40FE */
159 u_char f15
[0x4102-0x40fe -2];
160 vu_short wwidth
; /* Window width 0x4102 */
161 u_char f16
[0x4106-0x4102-2];
162 vu_short wheight
; /* Window height 0x4106 */
163 u_char f17
[0x6003-0x4106-2];
164 vu_char cmapbank
; /* Bank select (0 or 1) 0x6003 */
165 u_char f18
[0x6007-0x6003-1];
166 vu_char dispen
; /* Display enable 0x6007 */
168 u_char f18a
[0x600B-0x6007-1];
169 vu_char fbvenp
; /* Frame buffer video enable 0x600B */
170 u_char f18b
[0x6017-0x600B-1];
171 vu_char fbvens
; /* fbvenp blink counterpart 0x6017 */
173 u_char f19
[0x6023-0x6017-1];
174 vu_char vdrive
; /* Video display mode 0x6023 */
175 u_char f20
[0x6083-0x6023-1];
176 vu_char panxh
; /* Pan display in X (high) 0x6083 */
177 u_char f21
[0x6087-0x6083-1];
178 vu_char panxl
; /* Pan display in X (low) 0x6087 */
179 u_char f22
[0x608b-0x6087-1];
180 vu_char panyh
; /* Pan display in Y (high) 0x608B */
181 u_char f23
[0x608f-0x608b-1];
182 vu_char panyl
; /* Pan display in Y (low) 0x608F */
183 u_char f24
[0x6093-0x608f-1];
184 vu_char zoom
; /* Zoom factor 0x6093 */
185 u_char f25
[0x6097-0x6093-1];
186 vu_char pz_trig
; /* Pan & zoom trigger 0x6097 */
187 u_char f26
[0x609b-0x6097-1];
188 vu_char ovly0p
; /* Overlay 0 primary map 0x609B */
189 u_char f27
[0x609f-0x609b-1];
190 vu_char ovly1p
; /* Overlay 1 primary map 0x609F */
191 u_char f28
[0x60a3-0x609f-1];
192 vu_char ovly0s
; /* Overlay 0 secondary map 0x60A3 */
193 u_char f29
[0x60a7-0x60a3-1];
194 vu_char ovly1s
; /* Overlay 1 secondary map 0x60A7 */
195 u_char f30
[0x60ab-0x60a7-1];
196 vu_char opvenp
; /* Overlay video enable 0x60AB */
197 u_char f31
[0x60af-0x60ab-1];
198 vu_char opvens
; /* Overlay blink enable 0x60AF */
199 u_char f32
[0x60b3-0x60af-1];
200 vu_char fv_trig
; /* Trigger control registers 0x60B3 */
201 u_char f33
[0x60b7-0x60b3-1];
202 vu_char cdwidth
; /* Iris cdwidth timing reg. 0x60B7 */
203 u_char f34
[0x60bb-0x60b7-1];
204 vu_char chstart
; /* Iris chstart timing reg. 0x60BB */
205 u_char f35
[0x60bf-0x60bb-1];
206 vu_char cvwidth
; /* Iris cvwidth timing reg. 0x60BF */
207 u_char f36
[0x6100-0x60bf-1];
208 struct rgb rgb
[8]; /* overlay color map */
209 u_char f37
[0x6403-0x6100-sizeof(struct rgb
)*8];
211 u_char f38
[0x6803-0x6403-1];
213 u_char f39
[0x6c03-0x6803-1];
215 u_char f40
[0x7403-0x6c03-1];
217 u_char f41
[0x7803-0x7403-1];
219 u_char f42
[0x7c03-0x7803-1];
221 u_char f43
[0x8012-0x7c03-1];
222 vu_short status1
; /* Master Status register 0x8012 */
223 u_char f44
[0xC226-0x8012-2];
224 vu_short trans
; /* Transparency 0xC226 */
225 u_char f45
[0xC23E -0xC226-2];
226 vu_short pstop
; /* Pace value control 0xc23e */